1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 // Copyright (C) 2008 Juergen Beisert
6 #include <linux/completion.h>
7 #include <linux/delay.h>
8 #include <linux/dmaengine.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/err.h>
11 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/slab.h>
20 #include <linux/spi/spi.h>
21 #include <linux/spi/spi_bitbang.h>
22 #include <linux/types.h>
24 #include <linux/of_device.h>
25 #include <linux/property.h>
27 #include <linux/platform_data/dma-imx.h>
29 #define DRIVER_NAME "spi_imx"
31 static bool use_dma = true;
32 module_param(use_dma, bool, 0644);
33 MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)");
35 #define MXC_RPM_TIMEOUT 2000 /* 2000ms */
37 #define MXC_CSPIRXDATA 0x00
38 #define MXC_CSPITXDATA 0x04
39 #define MXC_CSPICTRL 0x08
40 #define MXC_CSPIINT 0x0c
41 #define MXC_RESET 0x1c
43 /* generic defines to abstract from the different register layouts */
44 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
45 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
46 #define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */
48 /* The maximum bytes that a sdma BD can transfer. */
49 #define MAX_SDMA_BD_BYTES (1 << 15)
50 #define MX51_ECSPI_CTRL_MAX_BURST 512
51 /* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/
52 #define MX53_MAX_TRANSFER_BYTES 512
54 enum spi_imx_devtype {
59 IMX35_CSPI, /* CSPI on all i.mx except above */
60 IMX51_ECSPI, /* ECSPI on i.mx51 */
61 IMX53_ECSPI, /* ECSPI on i.mx53 and later */
66 struct spi_imx_devtype_data {
67 void (*intctrl)(struct spi_imx_data *, int);
68 int (*prepare_message)(struct spi_imx_data *, struct spi_message *);
69 int (*prepare_transfer)(struct spi_imx_data *, struct spi_device *);
70 void (*trigger)(struct spi_imx_data *);
71 int (*rx_available)(struct spi_imx_data *);
72 void (*reset)(struct spi_imx_data *);
73 void (*setup_wml)(struct spi_imx_data *);
74 void (*disable)(struct spi_imx_data *);
75 void (*disable_dma)(struct spi_imx_data *);
78 unsigned int fifo_size;
81 * ERR009165 fixed or not:
82 * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
85 enum spi_imx_devtype devtype;
89 struct spi_bitbang bitbang;
92 struct completion xfer_done;
94 unsigned long base_phys;
98 unsigned long spi_clk;
99 unsigned int spi_bus_clk;
101 unsigned int bits_per_word;
102 unsigned int spi_drctl;
104 unsigned int count, remainder;
105 void (*tx)(struct spi_imx_data *);
106 void (*rx)(struct spi_imx_data *);
109 unsigned int txfifo; /* number of words pushed in tx FIFO */
110 unsigned int dynamic_burst;
115 unsigned int slave_burst;
120 struct completion dma_rx_completion;
121 struct completion dma_tx_completion;
123 const struct spi_imx_devtype_data *devtype_data;
126 static inline int is_imx27_cspi(struct spi_imx_data *d)
128 return d->devtype_data->devtype == IMX27_CSPI;
131 static inline int is_imx35_cspi(struct spi_imx_data *d)
133 return d->devtype_data->devtype == IMX35_CSPI;
136 static inline int is_imx51_ecspi(struct spi_imx_data *d)
138 return d->devtype_data->devtype == IMX51_ECSPI;
141 static inline int is_imx53_ecspi(struct spi_imx_data *d)
143 return d->devtype_data->devtype == IMX53_ECSPI;
146 #define MXC_SPI_BUF_RX(type) \
147 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
149 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
151 if (spi_imx->rx_buf) { \
152 *(type *)spi_imx->rx_buf = val; \
153 spi_imx->rx_buf += sizeof(type); \
156 spi_imx->remainder -= sizeof(type); \
159 #define MXC_SPI_BUF_TX(type) \
160 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
164 if (spi_imx->tx_buf) { \
165 val = *(type *)spi_imx->tx_buf; \
166 spi_imx->tx_buf += sizeof(type); \
169 spi_imx->count -= sizeof(type); \
171 writel(val, spi_imx->base + MXC_CSPITXDATA); \
181 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
182 * (which is currently not the case in this driver)
184 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
185 256, 384, 512, 768, 1024};
188 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
189 unsigned int fspi, unsigned int max, unsigned int *fres)
193 for (i = 2; i < max; i++)
194 if (fspi * mxc_clkdivs[i] >= fin)
197 *fres = fin / mxc_clkdivs[i];
201 /* MX1, MX31, MX35, MX51 CSPI */
202 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
203 unsigned int fspi, unsigned int *fres)
207 for (i = 0; i < 7; i++) {
208 if (fspi * div >= fin)
218 static int spi_imx_bytes_per_word(const int bits_per_word)
220 if (bits_per_word <= 8)
222 else if (bits_per_word <= 16)
228 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
229 struct spi_transfer *transfer)
231 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
233 if (!use_dma || master->fallback)
239 if (spi_imx->slave_mode)
242 if (transfer->len < spi_imx->devtype_data->fifo_size)
245 spi_imx->dynamic_burst = 0;
250 #define MX51_ECSPI_CTRL 0x08
251 #define MX51_ECSPI_CTRL_ENABLE (1 << 0)
252 #define MX51_ECSPI_CTRL_XCH (1 << 2)
253 #define MX51_ECSPI_CTRL_SMC (1 << 3)
254 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
255 #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16)
256 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
257 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
258 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
259 #define MX51_ECSPI_CTRL_BL_OFFSET 20
260 #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20)
262 #define MX51_ECSPI_CONFIG 0x0c
263 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
264 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
265 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
266 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
267 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
269 #define MX51_ECSPI_INT 0x10
270 #define MX51_ECSPI_INT_TEEN (1 << 0)
271 #define MX51_ECSPI_INT_RREN (1 << 3)
272 #define MX51_ECSPI_INT_RDREN (1 << 4)
274 #define MX51_ECSPI_DMA 0x14
275 #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f)
276 #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16)
277 #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24)
279 #define MX51_ECSPI_DMA_TEDEN (1 << 7)
280 #define MX51_ECSPI_DMA_RXDEN (1 << 23)
281 #define MX51_ECSPI_DMA_RXTDEN (1 << 31)
283 #define MX51_ECSPI_STAT 0x18
284 #define MX51_ECSPI_STAT_RR (1 << 3)
286 #define MX51_ECSPI_TESTREG 0x20
287 #define MX51_ECSPI_TESTREG_LBC BIT(31)
289 static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
291 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
292 #ifdef __LITTLE_ENDIAN
293 unsigned int bytes_per_word;
296 if (spi_imx->rx_buf) {
297 #ifdef __LITTLE_ENDIAN
298 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
299 if (bytes_per_word == 1)
300 val = cpu_to_be32(val);
301 else if (bytes_per_word == 2)
302 val = (val << 16) | (val >> 16);
304 *(u32 *)spi_imx->rx_buf = val;
305 spi_imx->rx_buf += sizeof(u32);
308 spi_imx->remainder -= sizeof(u32);
311 static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
316 unaligned = spi_imx->remainder % 4;
319 spi_imx_buf_rx_swap_u32(spi_imx);
323 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
324 spi_imx_buf_rx_u16(spi_imx);
328 val = readl(spi_imx->base + MXC_CSPIRXDATA);
330 while (unaligned--) {
331 if (spi_imx->rx_buf) {
332 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff;
335 spi_imx->remainder--;
339 static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
342 #ifdef __LITTLE_ENDIAN
343 unsigned int bytes_per_word;
346 if (spi_imx->tx_buf) {
347 val = *(u32 *)spi_imx->tx_buf;
348 spi_imx->tx_buf += sizeof(u32);
351 spi_imx->count -= sizeof(u32);
352 #ifdef __LITTLE_ENDIAN
353 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
355 if (bytes_per_word == 1)
356 val = cpu_to_be32(val);
357 else if (bytes_per_word == 2)
358 val = (val << 16) | (val >> 16);
360 writel(val, spi_imx->base + MXC_CSPITXDATA);
363 static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
368 unaligned = spi_imx->count % 4;
371 spi_imx_buf_tx_swap_u32(spi_imx);
375 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
376 spi_imx_buf_tx_u16(spi_imx);
380 while (unaligned--) {
381 if (spi_imx->tx_buf) {
382 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned);
388 writel(val, spi_imx->base + MXC_CSPITXDATA);
391 static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx)
393 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));
395 if (spi_imx->rx_buf) {
396 int n_bytes = spi_imx->slave_burst % sizeof(val);
399 n_bytes = sizeof(val);
401 memcpy(spi_imx->rx_buf,
402 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);
404 spi_imx->rx_buf += n_bytes;
405 spi_imx->slave_burst -= n_bytes;
408 spi_imx->remainder -= sizeof(u32);
411 static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx)
414 int n_bytes = spi_imx->count % sizeof(val);
417 n_bytes = sizeof(val);
419 if (spi_imx->tx_buf) {
420 memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
421 spi_imx->tx_buf, n_bytes);
422 val = cpu_to_be32(val);
423 spi_imx->tx_buf += n_bytes;
426 spi_imx->count -= n_bytes;
428 writel(val, spi_imx->base + MXC_CSPITXDATA);
432 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
433 unsigned int fspi, unsigned int *fres)
436 * there are two 4-bit dividers, the pre-divider divides by
437 * $pre, the post-divider by 2^$post
439 unsigned int pre, post;
440 unsigned int fin = spi_imx->spi_clk;
442 if (unlikely(fspi > fin))
445 post = fls(fin) - fls(fspi);
446 if (fin > fspi << post)
449 /* now we have: (fin <= fspi << post) with post being minimal */
451 post = max(4U, post) - 4;
452 if (unlikely(post > 0xf)) {
453 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
458 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
460 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
461 __func__, fin, fspi, post, pre);
463 /* Resulting frequency for the SCLK line. */
464 *fres = (fin / (pre + 1)) >> post;
466 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
467 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
470 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
474 if (enable & MXC_INT_TE)
475 val |= MX51_ECSPI_INT_TEEN;
477 if (enable & MXC_INT_RR)
478 val |= MX51_ECSPI_INT_RREN;
480 if (enable & MXC_INT_RDR)
481 val |= MX51_ECSPI_INT_RDREN;
483 writel(val, spi_imx->base + MX51_ECSPI_INT);
486 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
490 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
491 reg |= MX51_ECSPI_CTRL_XCH;
492 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
495 static void mx51_disable_dma(struct spi_imx_data *spi_imx)
497 writel(0, spi_imx->base + MX51_ECSPI_DMA);
500 static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
504 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
505 ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
506 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
509 static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
510 struct spi_message *msg)
512 struct spi_device *spi = msg->spi;
513 struct spi_transfer *xfer;
514 u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
515 u32 min_speed_hz = ~0U;
517 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
519 /* set Master or Slave mode */
520 if (spi_imx->slave_mode)
521 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
523 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
526 * Enable SPI_RDY handling (falling edge/level triggered).
528 if (spi->mode & SPI_READY)
529 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
531 /* set chip select to use */
532 ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
535 * The ctrl register must be written first, with the EN bit set other
536 * registers must not be written to.
538 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
540 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
541 if (spi->mode & SPI_LOOP)
542 testreg |= MX51_ECSPI_TESTREG_LBC;
544 testreg &= ~MX51_ECSPI_TESTREG_LBC;
545 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
548 * eCSPI burst completion by Chip Select signal in Slave mode
549 * is not functional for imx53 Soc, config SPI burst completed when
550 * BURST_LENGTH + 1 bits are received
552 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
553 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
555 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
557 if (spi->mode & SPI_CPHA)
558 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
560 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
562 if (spi->mode & SPI_CPOL) {
563 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
564 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
566 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
567 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
570 if (spi->mode & SPI_CS_HIGH)
571 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
573 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
575 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
578 * Wait until the changes in the configuration register CONFIGREG
579 * propagate into the hardware. It takes exactly one tick of the
580 * SCLK clock, but we will wait two SCLK clock just to be sure. The
581 * effect of the delay it takes for the hardware to apply changes
582 * is noticable if the SCLK clock run very slow. In such a case, if
583 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
584 * be asserted before the SCLK polarity changes, which would disrupt
585 * the SPI communication as the device on the other end would consider
586 * the change of SCLK polarity as a clock tick already.
588 * Because spi_imx->spi_bus_clk is only set in bitbang prepare_message
589 * callback, iterate over all the transfers in spi_message, find the
590 * one with lowest bus frequency, and use that bus frequency for the
591 * delay calculation. In case all transfers have speed_hz == 0, then
592 * min_speed_hz is ~0 and the resulting delay is zero.
594 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
597 min_speed_hz = min(xfer->speed_hz, min_speed_hz);
600 delay = (2 * 1000000) / min_speed_hz;
601 if (likely(delay < 10)) /* SCLK is faster than 200 kHz */
603 else /* SCLK is _very_ slow */
604 usleep_range(delay, delay + 10);
609 static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
610 struct spi_device *spi)
612 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
615 /* Clear BL field and set the right value */
616 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
617 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
618 ctrl |= (spi_imx->slave_burst * 8 - 1)
619 << MX51_ECSPI_CTRL_BL_OFFSET;
621 ctrl |= (spi_imx->bits_per_word - 1)
622 << MX51_ECSPI_CTRL_BL_OFFSET;
624 /* set clock speed */
625 ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
626 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET);
627 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk);
628 spi_imx->spi_bus_clk = clk;
631 * ERR009165: work in XHC mode instead of SMC as PIO on the chips
634 if (spi_imx->usedma && spi_imx->devtype_data->tx_glitch_fixed)
635 ctrl |= MX51_ECSPI_CTRL_SMC;
637 ctrl &= ~MX51_ECSPI_CTRL_SMC;
639 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
644 static void mx51_setup_wml(struct spi_imx_data *spi_imx)
648 if (spi_imx->devtype_data->tx_glitch_fixed)
649 tx_wml = spi_imx->wml;
651 * Configure the DMA register: setup the watermark
652 * and enable DMA request.
654 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
655 MX51_ECSPI_DMA_TX_WML(tx_wml) |
656 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
657 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
658 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
661 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
663 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
666 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
668 /* drain receive buffer */
669 while (mx51_ecspi_rx_available(spi_imx))
670 readl(spi_imx->base + MXC_CSPIRXDATA);
673 #define MX31_INTREG_TEEN (1 << 0)
674 #define MX31_INTREG_RREN (1 << 3)
676 #define MX31_CSPICTRL_ENABLE (1 << 0)
677 #define MX31_CSPICTRL_MASTER (1 << 1)
678 #define MX31_CSPICTRL_XCH (1 << 2)
679 #define MX31_CSPICTRL_SMC (1 << 3)
680 #define MX31_CSPICTRL_POL (1 << 4)
681 #define MX31_CSPICTRL_PHA (1 << 5)
682 #define MX31_CSPICTRL_SSCTL (1 << 6)
683 #define MX31_CSPICTRL_SSPOL (1 << 7)
684 #define MX31_CSPICTRL_BC_SHIFT 8
685 #define MX35_CSPICTRL_BL_SHIFT 20
686 #define MX31_CSPICTRL_CS_SHIFT 24
687 #define MX35_CSPICTRL_CS_SHIFT 12
688 #define MX31_CSPICTRL_DR_SHIFT 16
690 #define MX31_CSPI_DMAREG 0x10
691 #define MX31_DMAREG_RH_DEN (1<<4)
692 #define MX31_DMAREG_TH_DEN (1<<1)
694 #define MX31_CSPISTATUS 0x14
695 #define MX31_STATUS_RR (1 << 3)
697 #define MX31_CSPI_TESTREG 0x1C
698 #define MX31_TEST_LBC (1 << 14)
700 /* These functions also work for the i.MX35, but be aware that
701 * the i.MX35 has a slightly different register layout for bits
702 * we do not use here.
704 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
706 unsigned int val = 0;
708 if (enable & MXC_INT_TE)
709 val |= MX31_INTREG_TEEN;
710 if (enable & MXC_INT_RR)
711 val |= MX31_INTREG_RREN;
713 writel(val, spi_imx->base + MXC_CSPIINT);
716 static void mx31_trigger(struct spi_imx_data *spi_imx)
720 reg = readl(spi_imx->base + MXC_CSPICTRL);
721 reg |= MX31_CSPICTRL_XCH;
722 writel(reg, spi_imx->base + MXC_CSPICTRL);
725 static int mx31_prepare_message(struct spi_imx_data *spi_imx,
726 struct spi_message *msg)
731 static int mx31_prepare_transfer(struct spi_imx_data *spi_imx,
732 struct spi_device *spi)
734 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
737 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
738 MX31_CSPICTRL_DR_SHIFT;
739 spi_imx->spi_bus_clk = clk;
741 if (is_imx35_cspi(spi_imx)) {
742 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
743 reg |= MX31_CSPICTRL_SSCTL;
745 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
748 if (spi->mode & SPI_CPHA)
749 reg |= MX31_CSPICTRL_PHA;
750 if (spi->mode & SPI_CPOL)
751 reg |= MX31_CSPICTRL_POL;
752 if (spi->mode & SPI_CS_HIGH)
753 reg |= MX31_CSPICTRL_SSPOL;
755 reg |= (spi->chip_select) <<
756 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
757 MX31_CSPICTRL_CS_SHIFT);
760 reg |= MX31_CSPICTRL_SMC;
762 writel(reg, spi_imx->base + MXC_CSPICTRL);
764 reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
765 if (spi->mode & SPI_LOOP)
766 reg |= MX31_TEST_LBC;
768 reg &= ~MX31_TEST_LBC;
769 writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
771 if (spi_imx->usedma) {
773 * configure DMA requests when RXFIFO is half full and
774 * when TXFIFO is half empty
776 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
777 spi_imx->base + MX31_CSPI_DMAREG);
783 static int mx31_rx_available(struct spi_imx_data *spi_imx)
785 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
788 static void mx31_reset(struct spi_imx_data *spi_imx)
790 /* drain receive buffer */
791 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
792 readl(spi_imx->base + MXC_CSPIRXDATA);
795 #define MX21_INTREG_RR (1 << 4)
796 #define MX21_INTREG_TEEN (1 << 9)
797 #define MX21_INTREG_RREN (1 << 13)
799 #define MX21_CSPICTRL_POL (1 << 5)
800 #define MX21_CSPICTRL_PHA (1 << 6)
801 #define MX21_CSPICTRL_SSPOL (1 << 8)
802 #define MX21_CSPICTRL_XCH (1 << 9)
803 #define MX21_CSPICTRL_ENABLE (1 << 10)
804 #define MX21_CSPICTRL_MASTER (1 << 11)
805 #define MX21_CSPICTRL_DR_SHIFT 14
806 #define MX21_CSPICTRL_CS_SHIFT 19
808 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
810 unsigned int val = 0;
812 if (enable & MXC_INT_TE)
813 val |= MX21_INTREG_TEEN;
814 if (enable & MXC_INT_RR)
815 val |= MX21_INTREG_RREN;
817 writel(val, spi_imx->base + MXC_CSPIINT);
820 static void mx21_trigger(struct spi_imx_data *spi_imx)
824 reg = readl(spi_imx->base + MXC_CSPICTRL);
825 reg |= MX21_CSPICTRL_XCH;
826 writel(reg, spi_imx->base + MXC_CSPICTRL);
829 static int mx21_prepare_message(struct spi_imx_data *spi_imx,
830 struct spi_message *msg)
835 static int mx21_prepare_transfer(struct spi_imx_data *spi_imx,
836 struct spi_device *spi)
838 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
839 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
842 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk)
843 << MX21_CSPICTRL_DR_SHIFT;
844 spi_imx->spi_bus_clk = clk;
846 reg |= spi_imx->bits_per_word - 1;
848 if (spi->mode & SPI_CPHA)
849 reg |= MX21_CSPICTRL_PHA;
850 if (spi->mode & SPI_CPOL)
851 reg |= MX21_CSPICTRL_POL;
852 if (spi->mode & SPI_CS_HIGH)
853 reg |= MX21_CSPICTRL_SSPOL;
855 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT;
857 writel(reg, spi_imx->base + MXC_CSPICTRL);
862 static int mx21_rx_available(struct spi_imx_data *spi_imx)
864 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
867 static void mx21_reset(struct spi_imx_data *spi_imx)
869 writel(1, spi_imx->base + MXC_RESET);
872 #define MX1_INTREG_RR (1 << 3)
873 #define MX1_INTREG_TEEN (1 << 8)
874 #define MX1_INTREG_RREN (1 << 11)
876 #define MX1_CSPICTRL_POL (1 << 4)
877 #define MX1_CSPICTRL_PHA (1 << 5)
878 #define MX1_CSPICTRL_XCH (1 << 8)
879 #define MX1_CSPICTRL_ENABLE (1 << 9)
880 #define MX1_CSPICTRL_MASTER (1 << 10)
881 #define MX1_CSPICTRL_DR_SHIFT 13
883 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
885 unsigned int val = 0;
887 if (enable & MXC_INT_TE)
888 val |= MX1_INTREG_TEEN;
889 if (enable & MXC_INT_RR)
890 val |= MX1_INTREG_RREN;
892 writel(val, spi_imx->base + MXC_CSPIINT);
895 static void mx1_trigger(struct spi_imx_data *spi_imx)
899 reg = readl(spi_imx->base + MXC_CSPICTRL);
900 reg |= MX1_CSPICTRL_XCH;
901 writel(reg, spi_imx->base + MXC_CSPICTRL);
904 static int mx1_prepare_message(struct spi_imx_data *spi_imx,
905 struct spi_message *msg)
910 static int mx1_prepare_transfer(struct spi_imx_data *spi_imx,
911 struct spi_device *spi)
913 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
916 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
917 MX1_CSPICTRL_DR_SHIFT;
918 spi_imx->spi_bus_clk = clk;
920 reg |= spi_imx->bits_per_word - 1;
922 if (spi->mode & SPI_CPHA)
923 reg |= MX1_CSPICTRL_PHA;
924 if (spi->mode & SPI_CPOL)
925 reg |= MX1_CSPICTRL_POL;
927 writel(reg, spi_imx->base + MXC_CSPICTRL);
932 static int mx1_rx_available(struct spi_imx_data *spi_imx)
934 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
937 static void mx1_reset(struct spi_imx_data *spi_imx)
939 writel(1, spi_imx->base + MXC_RESET);
942 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
943 .intctrl = mx1_intctrl,
944 .prepare_message = mx1_prepare_message,
945 .prepare_transfer = mx1_prepare_transfer,
946 .trigger = mx1_trigger,
947 .rx_available = mx1_rx_available,
950 .has_dmamode = false,
951 .dynamic_burst = false,
952 .has_slavemode = false,
953 .devtype = IMX1_CSPI,
956 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
957 .intctrl = mx21_intctrl,
958 .prepare_message = mx21_prepare_message,
959 .prepare_transfer = mx21_prepare_transfer,
960 .trigger = mx21_trigger,
961 .rx_available = mx21_rx_available,
964 .has_dmamode = false,
965 .dynamic_burst = false,
966 .has_slavemode = false,
967 .devtype = IMX21_CSPI,
970 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
971 /* i.mx27 cspi shares the functions with i.mx21 one */
972 .intctrl = mx21_intctrl,
973 .prepare_message = mx21_prepare_message,
974 .prepare_transfer = mx21_prepare_transfer,
975 .trigger = mx21_trigger,
976 .rx_available = mx21_rx_available,
979 .has_dmamode = false,
980 .dynamic_burst = false,
981 .has_slavemode = false,
982 .devtype = IMX27_CSPI,
985 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
986 .intctrl = mx31_intctrl,
987 .prepare_message = mx31_prepare_message,
988 .prepare_transfer = mx31_prepare_transfer,
989 .trigger = mx31_trigger,
990 .rx_available = mx31_rx_available,
993 .has_dmamode = false,
994 .dynamic_burst = false,
995 .has_slavemode = false,
996 .devtype = IMX31_CSPI,
999 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
1000 /* i.mx35 and later cspi shares the functions with i.mx31 one */
1001 .intctrl = mx31_intctrl,
1002 .prepare_message = mx31_prepare_message,
1003 .prepare_transfer = mx31_prepare_transfer,
1004 .trigger = mx31_trigger,
1005 .rx_available = mx31_rx_available,
1006 .reset = mx31_reset,
1008 .has_dmamode = true,
1009 .dynamic_burst = false,
1010 .has_slavemode = false,
1011 .devtype = IMX35_CSPI,
1014 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
1015 .intctrl = mx51_ecspi_intctrl,
1016 .prepare_message = mx51_ecspi_prepare_message,
1017 .prepare_transfer = mx51_ecspi_prepare_transfer,
1018 .trigger = mx51_ecspi_trigger,
1019 .rx_available = mx51_ecspi_rx_available,
1020 .reset = mx51_ecspi_reset,
1021 .setup_wml = mx51_setup_wml,
1022 .disable_dma = mx51_disable_dma,
1024 .has_dmamode = true,
1025 .dynamic_burst = true,
1026 .has_slavemode = true,
1027 .disable = mx51_ecspi_disable,
1028 .devtype = IMX51_ECSPI,
1031 static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
1032 .intctrl = mx51_ecspi_intctrl,
1033 .prepare_message = mx51_ecspi_prepare_message,
1034 .prepare_transfer = mx51_ecspi_prepare_transfer,
1035 .trigger = mx51_ecspi_trigger,
1036 .rx_available = mx51_ecspi_rx_available,
1037 .disable_dma = mx51_disable_dma,
1038 .reset = mx51_ecspi_reset,
1040 .has_dmamode = true,
1041 .has_slavemode = true,
1042 .disable = mx51_ecspi_disable,
1043 .devtype = IMX53_ECSPI,
1046 static struct spi_imx_devtype_data imx6ul_ecspi_devtype_data = {
1047 .intctrl = mx51_ecspi_intctrl,
1048 .prepare_message = mx51_ecspi_prepare_message,
1049 .prepare_transfer = mx51_ecspi_prepare_transfer,
1050 .trigger = mx51_ecspi_trigger,
1051 .rx_available = mx51_ecspi_rx_available,
1052 .reset = mx51_ecspi_reset,
1053 .setup_wml = mx51_setup_wml,
1055 .has_dmamode = true,
1056 .dynamic_burst = true,
1057 .has_slavemode = true,
1058 .tx_glitch_fixed = true,
1059 .disable = mx51_ecspi_disable,
1060 .devtype = IMX51_ECSPI,
1063 static const struct of_device_id spi_imx_dt_ids[] = {
1064 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
1065 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
1066 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
1067 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
1068 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1069 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1070 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1071 { .compatible = "fsl,imx6ul-ecspi", .data = &imx6ul_ecspi_devtype_data, },
1074 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
1076 static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits)
1080 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
1081 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
1082 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET);
1083 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
1086 static void spi_imx_push(struct spi_imx_data *spi_imx)
1088 unsigned int burst_len;
1091 * Reload the FIFO when the remaining bytes to be transferred in the
1092 * current burst is 0. This only applies when bits_per_word is a
1095 if (!spi_imx->remainder) {
1096 if (spi_imx->dynamic_burst) {
1098 /* We need to deal unaligned data first */
1099 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST;
1102 burst_len = MX51_ECSPI_CTRL_MAX_BURST;
1104 spi_imx_set_burst_len(spi_imx, burst_len * 8);
1106 spi_imx->remainder = burst_len;
1108 spi_imx->remainder = spi_imx_bytes_per_word(spi_imx->bits_per_word);
1112 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
1113 if (!spi_imx->count)
1115 if (spi_imx->dynamic_burst &&
1116 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, 4))
1118 spi_imx->tx(spi_imx);
1122 if (!spi_imx->slave_mode)
1123 spi_imx->devtype_data->trigger(spi_imx);
1126 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
1128 struct spi_imx_data *spi_imx = dev_id;
1130 while (spi_imx->txfifo &&
1131 spi_imx->devtype_data->rx_available(spi_imx)) {
1132 spi_imx->rx(spi_imx);
1136 if (spi_imx->count) {
1137 spi_imx_push(spi_imx);
1141 if (spi_imx->txfifo) {
1142 /* No data left to push, but still waiting for rx data,
1143 * enable receive data available interrupt.
1145 spi_imx->devtype_data->intctrl(
1146 spi_imx, MXC_INT_RR);
1150 spi_imx->devtype_data->intctrl(spi_imx, 0);
1151 complete(&spi_imx->xfer_done);
1156 static int spi_imx_dma_configure(struct spi_master *master)
1159 enum dma_slave_buswidth buswidth;
1160 struct dma_slave_config rx = {}, tx = {};
1161 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1163 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
1165 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1168 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1171 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1177 tx.direction = DMA_MEM_TO_DEV;
1178 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
1179 tx.dst_addr_width = buswidth;
1180 tx.dst_maxburst = spi_imx->wml;
1181 ret = dmaengine_slave_config(master->dma_tx, &tx);
1183 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
1187 rx.direction = DMA_DEV_TO_MEM;
1188 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
1189 rx.src_addr_width = buswidth;
1190 rx.src_maxburst = spi_imx->wml;
1191 ret = dmaengine_slave_config(master->dma_rx, &rx);
1193 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
1200 static int spi_imx_setupxfer(struct spi_device *spi,
1201 struct spi_transfer *t)
1203 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1209 if (!spi->max_speed_hz) {
1210 dev_err(&spi->dev, "no speed_hz provided!\n");
1213 dev_dbg(&spi->dev, "using spi->max_speed_hz!\n");
1214 spi_imx->spi_bus_clk = spi->max_speed_hz;
1216 spi_imx->spi_bus_clk = t->speed_hz;
1218 spi_imx->bits_per_word = t->bits_per_word;
1221 * Initialize the functions for transfer. To transfer non byte-aligned
1222 * words, we have to use multiple word-size bursts, we can't use
1223 * dynamic_burst in that case.
1225 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode &&
1226 !(spi->mode & SPI_CS_WORD) &&
1227 (spi_imx->bits_per_word == 8 ||
1228 spi_imx->bits_per_word == 16 ||
1229 spi_imx->bits_per_word == 32)) {
1231 spi_imx->rx = spi_imx_buf_rx_swap;
1232 spi_imx->tx = spi_imx_buf_tx_swap;
1233 spi_imx->dynamic_burst = 1;
1236 if (spi_imx->bits_per_word <= 8) {
1237 spi_imx->rx = spi_imx_buf_rx_u8;
1238 spi_imx->tx = spi_imx_buf_tx_u8;
1239 } else if (spi_imx->bits_per_word <= 16) {
1240 spi_imx->rx = spi_imx_buf_rx_u16;
1241 spi_imx->tx = spi_imx_buf_tx_u16;
1243 spi_imx->rx = spi_imx_buf_rx_u32;
1244 spi_imx->tx = spi_imx_buf_tx_u32;
1246 spi_imx->dynamic_burst = 0;
1249 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
1250 spi_imx->usedma = true;
1252 spi_imx->usedma = false;
1254 if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) {
1255 spi_imx->rx = mx53_ecspi_rx_slave;
1256 spi_imx->tx = mx53_ecspi_tx_slave;
1257 spi_imx->slave_burst = t->len;
1260 spi_imx->devtype_data->prepare_transfer(spi_imx, spi);
1265 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
1267 struct spi_master *master = spi_imx->bitbang.master;
1269 if (master->dma_rx) {
1270 dma_release_channel(master->dma_rx);
1271 master->dma_rx = NULL;
1274 if (master->dma_tx) {
1275 dma_release_channel(master->dma_tx);
1276 master->dma_tx = NULL;
1280 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1281 struct spi_master *master)
1285 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
1287 /* Prepare for TX DMA: */
1288 master->dma_tx = dma_request_chan(dev, "tx");
1289 if (IS_ERR(master->dma_tx)) {
1290 ret = PTR_ERR(master->dma_tx);
1291 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
1292 master->dma_tx = NULL;
1296 /* Prepare for RX : */
1297 master->dma_rx = dma_request_chan(dev, "rx");
1298 if (IS_ERR(master->dma_rx)) {
1299 ret = PTR_ERR(master->dma_rx);
1300 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
1301 master->dma_rx = NULL;
1305 init_completion(&spi_imx->dma_rx_completion);
1306 init_completion(&spi_imx->dma_tx_completion);
1307 master->can_dma = spi_imx_can_dma;
1308 master->max_dma_len = MAX_SDMA_BD_BYTES;
1309 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
1314 spi_imx_sdma_exit(spi_imx);
1318 static void spi_imx_dma_rx_callback(void *cookie)
1320 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1322 complete(&spi_imx->dma_rx_completion);
1325 static void spi_imx_dma_tx_callback(void *cookie)
1327 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1329 complete(&spi_imx->dma_tx_completion);
1332 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1334 unsigned long timeout = 0;
1336 /* Time with actual data transfer and CS change delay related to HW */
1337 timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1339 /* Add extra second for scheduler related activities */
1342 /* Double calculated timeout */
1343 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1346 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1347 struct spi_transfer *transfer)
1349 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1350 unsigned long transfer_timeout;
1351 unsigned long timeout;
1352 struct spi_master *master = spi_imx->bitbang.master;
1353 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1354 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents);
1355 unsigned int bytes_per_word, i;
1358 /* Get the right burst length from the last sg to ensure no tail data */
1359 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
1360 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
1361 if (!(sg_dma_len(last_sg) % (i * bytes_per_word)))
1364 /* Use 1 as wml in case no available burst length got */
1370 ret = spi_imx_dma_configure(master);
1372 goto dma_failure_no_start;
1374 if (!spi_imx->devtype_data->setup_wml) {
1375 dev_err(spi_imx->dev, "No setup_wml()?\n");
1377 goto dma_failure_no_start;
1379 spi_imx->devtype_data->setup_wml(spi_imx);
1382 * The TX DMA setup starts the transfer, so make sure RX is configured
1385 desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
1386 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1387 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1390 goto dma_failure_no_start;
1393 desc_rx->callback = spi_imx_dma_rx_callback;
1394 desc_rx->callback_param = (void *)spi_imx;
1395 dmaengine_submit(desc_rx);
1396 reinit_completion(&spi_imx->dma_rx_completion);
1397 dma_async_issue_pending(master->dma_rx);
1399 desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
1400 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1401 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1403 dmaengine_terminate_all(master->dma_tx);
1404 dmaengine_terminate_all(master->dma_rx);
1408 desc_tx->callback = spi_imx_dma_tx_callback;
1409 desc_tx->callback_param = (void *)spi_imx;
1410 dmaengine_submit(desc_tx);
1411 reinit_completion(&spi_imx->dma_tx_completion);
1412 dma_async_issue_pending(master->dma_tx);
1414 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1416 /* Wait SDMA to finish the data transfer.*/
1417 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1420 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1421 dmaengine_terminate_all(master->dma_tx);
1422 dmaengine_terminate_all(master->dma_rx);
1426 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1429 dev_err(&master->dev, "I/O Error in DMA RX\n");
1430 spi_imx->devtype_data->reset(spi_imx);
1431 dmaengine_terminate_all(master->dma_rx);
1435 return transfer->len;
1436 /* fallback to pio */
1437 dma_failure_no_start:
1438 transfer->error |= SPI_TRANS_FAIL_NO_START;
1442 static int spi_imx_pio_transfer(struct spi_device *spi,
1443 struct spi_transfer *transfer)
1445 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1446 unsigned long transfer_timeout;
1447 unsigned long timeout;
1449 spi_imx->tx_buf = transfer->tx_buf;
1450 spi_imx->rx_buf = transfer->rx_buf;
1451 spi_imx->count = transfer->len;
1452 spi_imx->txfifo = 0;
1453 spi_imx->remainder = 0;
1455 reinit_completion(&spi_imx->xfer_done);
1457 spi_imx_push(spi_imx);
1459 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1461 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1463 timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1466 dev_err(&spi->dev, "I/O Error in PIO\n");
1467 spi_imx->devtype_data->reset(spi_imx);
1471 return transfer->len;
1474 static int spi_imx_pio_transfer_slave(struct spi_device *spi,
1475 struct spi_transfer *transfer)
1477 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1478 int ret = transfer->len;
1480 if (is_imx53_ecspi(spi_imx) &&
1481 transfer->len > MX53_MAX_TRANSFER_BYTES) {
1482 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
1483 MX53_MAX_TRANSFER_BYTES);
1487 spi_imx->tx_buf = transfer->tx_buf;
1488 spi_imx->rx_buf = transfer->rx_buf;
1489 spi_imx->count = transfer->len;
1490 spi_imx->txfifo = 0;
1491 spi_imx->remainder = 0;
1493 reinit_completion(&spi_imx->xfer_done);
1494 spi_imx->slave_aborted = false;
1496 spi_imx_push(spi_imx);
1498 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);
1500 if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
1501 spi_imx->slave_aborted) {
1502 dev_dbg(&spi->dev, "interrupted\n");
1506 /* ecspi has a HW issue when works in Slave mode,
1507 * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
1508 * ECSPI_TXDATA keeps shift out the last word data,
1509 * so we have to disable ECSPI when in slave mode after the
1510 * transfer completes
1512 if (spi_imx->devtype_data->disable)
1513 spi_imx->devtype_data->disable(spi_imx);
1518 static int spi_imx_transfer(struct spi_device *spi,
1519 struct spi_transfer *transfer)
1521 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1523 transfer->effective_speed_hz = spi_imx->spi_bus_clk;
1525 /* flush rxfifo before transfer */
1526 while (spi_imx->devtype_data->rx_available(spi_imx))
1527 readl(spi_imx->base + MXC_CSPIRXDATA);
1529 if (spi_imx->slave_mode)
1530 return spi_imx_pio_transfer_slave(spi, transfer);
1532 if (spi_imx->usedma)
1533 return spi_imx_dma_transfer(spi_imx, transfer);
1535 return spi_imx_pio_transfer(spi, transfer);
1538 static int spi_imx_setup(struct spi_device *spi)
1540 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1541 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1546 static void spi_imx_cleanup(struct spi_device *spi)
1551 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1553 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1556 ret = pm_runtime_get_sync(spi_imx->dev);
1558 pm_runtime_put_noidle(spi_imx->dev);
1559 dev_err(spi_imx->dev, "failed to enable clock\n");
1563 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg);
1565 pm_runtime_mark_last_busy(spi_imx->dev);
1566 pm_runtime_put_autosuspend(spi_imx->dev);
1573 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1575 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1577 pm_runtime_mark_last_busy(spi_imx->dev);
1578 pm_runtime_put_autosuspend(spi_imx->dev);
1582 static int spi_imx_slave_abort(struct spi_master *master)
1584 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1586 spi_imx->slave_aborted = true;
1587 complete(&spi_imx->xfer_done);
1592 static int spi_imx_probe(struct platform_device *pdev)
1594 struct device_node *np = pdev->dev.of_node;
1595 struct spi_master *master;
1596 struct spi_imx_data *spi_imx;
1597 struct resource *res;
1598 int ret, irq, spi_drctl;
1599 const struct spi_imx_devtype_data *devtype_data =
1600 of_device_get_match_data(&pdev->dev);
1604 slave_mode = devtype_data->has_slavemode &&
1605 of_property_read_bool(np, "spi-slave");
1607 master = spi_alloc_slave(&pdev->dev,
1608 sizeof(struct spi_imx_data));
1610 master = spi_alloc_master(&pdev->dev,
1611 sizeof(struct spi_imx_data));
1615 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1616 if ((ret < 0) || (spi_drctl >= 0x3)) {
1617 /* '11' is reserved */
1621 platform_set_drvdata(pdev, master);
1623 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1624 master->bus_num = np ? -1 : pdev->id;
1625 master->use_gpio_descriptors = true;
1627 spi_imx = spi_master_get_devdata(master);
1628 spi_imx->bitbang.master = master;
1629 spi_imx->dev = &pdev->dev;
1630 spi_imx->slave_mode = slave_mode;
1632 spi_imx->devtype_data = devtype_data;
1635 * Get number of chip selects from device properties. This can be
1636 * coming from device tree or boardfiles, if it is not defined,
1637 * a default value of 3 chip selects will be used, as all the legacy
1638 * board files have <= 3 chip selects.
1640 if (!device_property_read_u32(&pdev->dev, "num-cs", &val))
1641 master->num_chipselect = val;
1643 master->num_chipselect = 3;
1645 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1646 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1647 spi_imx->bitbang.master->setup = spi_imx_setup;
1648 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1649 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1650 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1651 spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort;
1652 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
1654 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
1655 is_imx53_ecspi(spi_imx))
1656 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
1658 if (is_imx51_ecspi(spi_imx) &&
1659 device_property_read_u32(&pdev->dev, "cs-gpios", NULL))
1661 * When using HW-CS implementing SPI_CS_WORD can be done by just
1662 * setting the burst length to the word size. This is
1663 * considerably faster than manually controlling the CS.
1665 spi_imx->bitbang.master->mode_bits |= SPI_CS_WORD;
1667 spi_imx->spi_drctl = spi_drctl;
1669 init_completion(&spi_imx->xfer_done);
1671 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1672 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1673 if (IS_ERR(spi_imx->base)) {
1674 ret = PTR_ERR(spi_imx->base);
1675 goto out_master_put;
1677 spi_imx->base_phys = res->start;
1679 irq = platform_get_irq(pdev, 0);
1682 goto out_master_put;
1685 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1686 dev_name(&pdev->dev), spi_imx);
1688 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1689 goto out_master_put;
1692 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1693 if (IS_ERR(spi_imx->clk_ipg)) {
1694 ret = PTR_ERR(spi_imx->clk_ipg);
1695 goto out_master_put;
1698 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1699 if (IS_ERR(spi_imx->clk_per)) {
1700 ret = PTR_ERR(spi_imx->clk_per);
1701 goto out_master_put;
1704 ret = clk_prepare_enable(spi_imx->clk_per);
1706 goto out_master_put;
1708 ret = clk_prepare_enable(spi_imx->clk_ipg);
1712 pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT);
1713 pm_runtime_use_autosuspend(spi_imx->dev);
1714 pm_runtime_get_noresume(spi_imx->dev);
1715 pm_runtime_set_active(spi_imx->dev);
1716 pm_runtime_enable(spi_imx->dev);
1718 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1720 * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1721 * if validated on other chips.
1723 if (spi_imx->devtype_data->has_dmamode) {
1724 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1725 if (ret == -EPROBE_DEFER)
1726 goto out_runtime_pm_put;
1729 dev_dbg(&pdev->dev, "dma setup error %d, use pio\n",
1733 spi_imx->devtype_data->reset(spi_imx);
1735 spi_imx->devtype_data->intctrl(spi_imx, 0);
1737 master->dev.of_node = pdev->dev.of_node;
1738 ret = spi_bitbang_start(&spi_imx->bitbang);
1740 dev_err_probe(&pdev->dev, ret, "bitbang start failed\n");
1741 goto out_bitbang_start;
1744 pm_runtime_mark_last_busy(spi_imx->dev);
1745 pm_runtime_put_autosuspend(spi_imx->dev);
1750 if (spi_imx->devtype_data->has_dmamode)
1751 spi_imx_sdma_exit(spi_imx);
1753 pm_runtime_dont_use_autosuspend(spi_imx->dev);
1754 pm_runtime_set_suspended(&pdev->dev);
1755 pm_runtime_disable(spi_imx->dev);
1757 clk_disable_unprepare(spi_imx->clk_ipg);
1759 clk_disable_unprepare(spi_imx->clk_per);
1761 spi_master_put(master);
1766 static int spi_imx_remove(struct platform_device *pdev)
1768 struct spi_master *master = platform_get_drvdata(pdev);
1769 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1772 spi_bitbang_stop(&spi_imx->bitbang);
1774 ret = pm_runtime_get_sync(spi_imx->dev);
1776 pm_runtime_put_noidle(spi_imx->dev);
1777 dev_err(spi_imx->dev, "failed to enable clock\n");
1781 writel(0, spi_imx->base + MXC_CSPICTRL);
1783 pm_runtime_dont_use_autosuspend(spi_imx->dev);
1784 pm_runtime_put_sync(spi_imx->dev);
1785 pm_runtime_disable(spi_imx->dev);
1787 spi_imx_sdma_exit(spi_imx);
1788 spi_master_put(master);
1793 static int __maybe_unused spi_imx_runtime_resume(struct device *dev)
1795 struct spi_master *master = dev_get_drvdata(dev);
1796 struct spi_imx_data *spi_imx;
1799 spi_imx = spi_master_get_devdata(master);
1801 ret = clk_prepare_enable(spi_imx->clk_per);
1805 ret = clk_prepare_enable(spi_imx->clk_ipg);
1807 clk_disable_unprepare(spi_imx->clk_per);
1814 static int __maybe_unused spi_imx_runtime_suspend(struct device *dev)
1816 struct spi_master *master = dev_get_drvdata(dev);
1817 struct spi_imx_data *spi_imx;
1819 spi_imx = spi_master_get_devdata(master);
1821 clk_disable_unprepare(spi_imx->clk_per);
1822 clk_disable_unprepare(spi_imx->clk_ipg);
1827 static int __maybe_unused spi_imx_suspend(struct device *dev)
1829 pinctrl_pm_select_sleep_state(dev);
1833 static int __maybe_unused spi_imx_resume(struct device *dev)
1835 pinctrl_pm_select_default_state(dev);
1839 static const struct dev_pm_ops imx_spi_pm = {
1840 SET_RUNTIME_PM_OPS(spi_imx_runtime_suspend,
1841 spi_imx_runtime_resume, NULL)
1842 SET_SYSTEM_SLEEP_PM_OPS(spi_imx_suspend, spi_imx_resume)
1845 static struct platform_driver spi_imx_driver = {
1847 .name = DRIVER_NAME,
1848 .of_match_table = spi_imx_dt_ids,
1851 .probe = spi_imx_probe,
1852 .remove = spi_imx_remove,
1854 module_platform_driver(spi_imx_driver);
1856 MODULE_DESCRIPTION("i.MX SPI Controller driver");
1857 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1858 MODULE_LICENSE("GPL");
1859 MODULE_ALIAS("platform:" DRIVER_NAME);