drivers/spi/spi-imx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3 // Copyright (C) 2008 Juergen Beisert
   4
   5 #include <linux/clk.h>
   6 #include <linux/completion.h>
   7 #include <linux/delay.h>
   8 #include <linux/dmaengine.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/err.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/io.h>
  13 #include <linux/irq.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/pinctrl/consumer.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/slab.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/spi/spi_bitbang.h>
  22 #include <linux/types.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/property.h>
  26
  27 #include <linux/platform_data/dma-imx.h>
  28
  29 #define DRIVER_NAME "spi_imx"
  30
  31 static bool use_dma = true;
  32 module_param(use_dma, bool, 0644);
  33 MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)");
  34
  35 #define MXC_RPM_TIMEOUT         2000 /* 2000ms */
  36
  37 #define MXC_CSPIRXDATA          0x00
  38 #define MXC_CSPITXDATA          0x04
  39 #define MXC_CSPICTRL            0x08
  40 #define MXC_CSPIINT             0x0c
  41 #define MXC_RESET               0x1c
  42
  43 /* generic defines to abstract from the different register layouts */
  44 #define MXC_INT_RR      (1 << 0) /* Receive data ready interrupt */
  45 #define MXC_INT_TE      (1 << 1) /* Transmit FIFO empty interrupt */
  46 #define MXC_INT_RDR     BIT(4) /* Receive date threshold interrupt */
  47
  48 /* The maximum bytes that a sdma BD can transfer. */
  49 #define MAX_SDMA_BD_BYTES (1 << 15)
  50 #define MX51_ECSPI_CTRL_MAX_BURST       512
  51 /* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/
  52 #define MX53_MAX_TRANSFER_BYTES         512
  53
  54 enum spi_imx_devtype {
  55         IMX1_CSPI,
  56         IMX21_CSPI,
  57         IMX27_CSPI,
  58         IMX31_CSPI,
  59         IMX35_CSPI,     /* CSPI on all i.mx except above */
  60         IMX51_ECSPI,    /* ECSPI on i.mx51 */
  61         IMX53_ECSPI,    /* ECSPI on i.mx53 and later */
  62 };
  63
  64 struct spi_imx_data;
  65
  66 struct spi_imx_devtype_data {
  67         void (*intctrl)(struct spi_imx_data *, int);
  68         int (*prepare_message)(struct spi_imx_data *, struct spi_message *);
  69         int (*prepare_transfer)(struct spi_imx_data *, struct spi_device *);
  70         void (*trigger)(struct spi_imx_data *);
  71         int (*rx_available)(struct spi_imx_data *);
  72         void (*reset)(struct spi_imx_data *);
  73         void (*setup_wml)(struct spi_imx_data *);
  74         void (*disable)(struct spi_imx_data *);
  75         void (*disable_dma)(struct spi_imx_data *);
  76         bool has_dmamode;
  77         bool has_slavemode;
  78         unsigned int fifo_size;
  79         bool dynamic_burst;
  80         /*
  81          * ERR009165 fixed or not:
  82          * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
  83          */
  84         bool tx_glitch_fixed;
  85         enum spi_imx_devtype devtype;
  86 };
  87
  88 struct spi_imx_data {
  89         struct spi_bitbang bitbang;
  90         struct device *dev;
  91
  92         struct completion xfer_done;
  93         void __iomem *base;
  94         unsigned long base_phys;
  95
  96         struct clk *clk_per;
  97         struct clk *clk_ipg;
  98         unsigned long spi_clk;
  99         unsigned int spi_bus_clk;
 100
 101         unsigned int bits_per_word;
 102         unsigned int spi_drctl;
 103
 104         unsigned int count, remainder;
 105         void (*tx)(struct spi_imx_data *);
 106         void (*rx)(struct spi_imx_data *);
 107         void *rx_buf;
 108         const void *tx_buf;
 109         unsigned int txfifo; /* number of words pushed in tx FIFO */
 110         unsigned int dynamic_burst;
 111
 112         /* Slave mode */
 113         bool slave_mode;
 114         bool slave_aborted;
 115         unsigned int slave_burst;
 116
 117         /* DMA */
 118         bool usedma;
 119         u32 wml;
 120         struct completion dma_rx_completion;
 121         struct completion dma_tx_completion;
 122
 123         const struct spi_imx_devtype_data *devtype_data;
 124 };
 125
 126 static inline int is_imx27_cspi(struct spi_imx_data *d)
 127 {
 128         return d->devtype_data->devtype == IMX27_CSPI;
 129 }
 130
 131 static inline int is_imx35_cspi(struct spi_imx_data *d)
 132 {
 133         return d->devtype_data->devtype == IMX35_CSPI;
 134 }
 135
 136 static inline int is_imx51_ecspi(struct spi_imx_data *d)
 137 {
 138         return d->devtype_data->devtype == IMX51_ECSPI;
 139 }
 140
 141 static inline int is_imx53_ecspi(struct spi_imx_data *d)
 142 {
 143         return d->devtype_data->devtype == IMX53_ECSPI;
 144 }
 145
 146 #define MXC_SPI_BUF_RX(type)                                            \
 147 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx)         \
 148 {                                                                       \
 149         unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);       \
 150                                                                         \
 151         if (spi_imx->rx_buf) {                                          \
 152                 *(type *)spi_imx->rx_buf = val;                         \
 153                 spi_imx->rx_buf += sizeof(type);                        \
 154         }                                                               \
 155                                                                         \
 156         spi_imx->remainder -= sizeof(type);                             \
 157 }
 158
 159 #define MXC_SPI_BUF_TX(type)                                            \
 160 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx)         \
 161 {                                                                       \
 162         type val = 0;                                                   \
 163                                                                         \
 164         if (spi_imx->tx_buf) {                                          \
 165                 val = *(type *)spi_imx->tx_buf;                         \
 166                 spi_imx->tx_buf += sizeof(type);                        \
 167         }                                                               \
 168                                                                         \
 169         spi_imx->count -= sizeof(type);                                 \
 170                                                                         \
 171         writel(val, spi_imx->base + MXC_CSPITXDATA);                    \
 172 }
 173
 174 MXC_SPI_BUF_RX(u8)
 175 MXC_SPI_BUF_TX(u8)
 176 MXC_SPI_BUF_RX(u16)
 177 MXC_SPI_BUF_TX(u16)
 178 MXC_SPI_BUF_RX(u32)
 179 MXC_SPI_BUF_TX(u32)
 180
 181 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
 182  * (which is currently not the case in this driver)
 183  */
 184 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
 185         256, 384, 512, 768, 1024};
 186
 187 /* MX21, MX27 */
 188 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
 189                 unsigned int fspi, unsigned int max, unsigned int *fres)
 190 {
 191         int i;
 192
 193         for (i = 2; i < max; i++)
 194                 if (fspi * mxc_clkdivs[i] >= fin)
 195                         break;
 196
 197         *fres = fin / mxc_clkdivs[i];
 198         return i;
 199 }
 200
 201 /* MX1, MX31, MX35, MX51 CSPI */
 202 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
 203                 unsigned int fspi, unsigned int *fres)
 204 {
 205         int i, div = 4;
 206
 207         for (i = 0; i < 7; i++) {
 208                 if (fspi * div >= fin)
 209                         goto out;
 210                 div <<= 1;
 211         }
 212
 213 out:
 214         *fres = fin / div;
 215         return i;
 216 }
 217
 218 static int spi_imx_bytes_per_word(const int bits_per_word)
 219 {
 220         if (bits_per_word <= 8)
 221                 return 1;
 222         else if (bits_per_word <= 16)
 223                 return 2;
 224         else
 225                 return 4;
 226 }
 227
 228 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
 229                          struct spi_transfer *transfer)
 230 {
 231         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
 232
 233         if (!use_dma || master->fallback)
 234                 return false;
 235
 236         if (!master->dma_rx)
 237                 return false;
 238
 239         if (spi_imx->slave_mode)
 240                 return false;
 241
 242         if (transfer->len < spi_imx->devtype_data->fifo_size)
 243                 return false;
 244
 245         spi_imx->dynamic_burst = 0;
 246
 247         return true;
 248 }
 249
 250 #define MX51_ECSPI_CTRL         0x08
 251 #define MX51_ECSPI_CTRL_ENABLE          (1 <<  0)
 252 #define MX51_ECSPI_CTRL_XCH             (1 <<  2)
 253 #define MX51_ECSPI_CTRL_SMC             (1 << 3)
 254 #define MX51_ECSPI_CTRL_MODE_MASK       (0xf << 4)
 255 #define MX51_ECSPI_CTRL_DRCTL(drctl)    ((drctl) << 16)
 256 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET  8
 257 #define MX51_ECSPI_CTRL_PREDIV_OFFSET   12
 258 #define MX51_ECSPI_CTRL_CS(cs)          ((cs) << 18)
 259 #define MX51_ECSPI_CTRL_BL_OFFSET       20
 260 #define MX51_ECSPI_CTRL_BL_MASK         (0xfff << 20)
 261
 262 #define MX51_ECSPI_CONFIG       0x0c
 263 #define MX51_ECSPI_CONFIG_SCLKPHA(cs)   (1 << ((cs) +  0))
 264 #define MX51_ECSPI_CONFIG_SCLKPOL(cs)   (1 << ((cs) +  4))
 265 #define MX51_ECSPI_CONFIG_SBBCTRL(cs)   (1 << ((cs) +  8))
 266 #define MX51_ECSPI_CONFIG_SSBPOL(cs)    (1 << ((cs) + 12))
 267 #define MX51_ECSPI_CONFIG_SCLKCTL(cs)   (1 << ((cs) + 20))
 268
 269 #define MX51_ECSPI_INT          0x10
 270 #define MX51_ECSPI_INT_TEEN             (1 <<  0)
 271 #define MX51_ECSPI_INT_RREN             (1 <<  3)
 272 #define MX51_ECSPI_INT_RDREN            (1 <<  4)
 273
 274 #define MX51_ECSPI_DMA          0x14
 275 #define MX51_ECSPI_DMA_TX_WML(wml)      ((wml) & 0x3f)
 276 #define MX51_ECSPI_DMA_RX_WML(wml)      (((wml) & 0x3f) << 16)
 277 #define MX51_ECSPI_DMA_RXT_WML(wml)     (((wml) & 0x3f) << 24)
 278
 279 #define MX51_ECSPI_DMA_TEDEN            (1 << 7)
 280 #define MX51_ECSPI_DMA_RXDEN            (1 << 23)
 281 #define MX51_ECSPI_DMA_RXTDEN           (1 << 31)
 282
 283 #define MX51_ECSPI_STAT         0x18
 284 #define MX51_ECSPI_STAT_RR              (1 <<  3)
 285
 286 #define MX51_ECSPI_TESTREG      0x20
 287 #define MX51_ECSPI_TESTREG_LBC  BIT(31)
 288
 289 static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
 290 {
 291         unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
 292 #ifdef __LITTLE_ENDIAN
 293         unsigned int bytes_per_word;
 294 #endif
 295
 296         if (spi_imx->rx_buf) {
 297 #ifdef __LITTLE_ENDIAN
 298                 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
 299                 if (bytes_per_word == 1)
 300                         val = cpu_to_be32(val);
 301                 else if (bytes_per_word == 2)
 302                         val = (val << 16) | (val >> 16);
 303 #endif
 304                 *(u32 *)spi_imx->rx_buf = val;
 305                 spi_imx->rx_buf += sizeof(u32);
 306         }
 307
 308         spi_imx->remainder -= sizeof(u32);
 309 }
 310
 311 static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
 312 {
 313         int unaligned;
 314         u32 val;
 315
 316         unaligned = spi_imx->remainder % 4;
 317
 318         if (!unaligned) {
 319                 spi_imx_buf_rx_swap_u32(spi_imx);
 320                 return;
 321         }
 322
 323         if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
 324                 spi_imx_buf_rx_u16(spi_imx);
 325                 return;
 326         }
 327
 328         val = readl(spi_imx->base + MXC_CSPIRXDATA);
 329
 330         while (unaligned--) {
 331                 if (spi_imx->rx_buf) {
 332                         *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff;
 333                         spi_imx->rx_buf++;
 334                 }
 335                 spi_imx->remainder--;
 336         }
 337 }
 338
 339 static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
 340 {
 341         u32 val = 0;
 342 #ifdef __LITTLE_ENDIAN
 343         unsigned int bytes_per_word;
 344 #endif
 345
 346         if (spi_imx->tx_buf) {
 347                 val = *(u32 *)spi_imx->tx_buf;
 348                 spi_imx->tx_buf += sizeof(u32);
 349         }
 350
 351         spi_imx->count -= sizeof(u32);
 352 #ifdef __LITTLE_ENDIAN
 353         bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
 354
 355         if (bytes_per_word == 1)
 356                 val = cpu_to_be32(val);
 357         else if (bytes_per_word == 2)
 358                 val = (val << 16) | (val >> 16);
 359 #endif
 360         writel(val, spi_imx->base + MXC_CSPITXDATA);
 361 }
 362
 363 static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
 364 {
 365         int unaligned;
 366         u32 val = 0;
 367
 368         unaligned = spi_imx->count % 4;
 369
 370         if (!unaligned) {
 371                 spi_imx_buf_tx_swap_u32(spi_imx);
 372                 return;
 373         }
 374
 375         if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
 376                 spi_imx_buf_tx_u16(spi_imx);
 377                 return;
 378         }
 379
 380         while (unaligned--) {
 381                 if (spi_imx->tx_buf) {
 382                         val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned);
 383                         spi_imx->tx_buf++;
 384                 }
 385                 spi_imx->count--;
 386         }
 387
 388         writel(val, spi_imx->base + MXC_CSPITXDATA);
 389 }
 390
 391 static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx)
 392 {
 393         u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));
 394
 395         if (spi_imx->rx_buf) {
 396                 int n_bytes = spi_imx->slave_burst % sizeof(val);
 397
 398                 if (!n_bytes)
 399                         n_bytes = sizeof(val);
 400
 401                 memcpy(spi_imx->rx_buf,
 402                        ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);
 403
 404                 spi_imx->rx_buf += n_bytes;
 405                 spi_imx->slave_burst -= n_bytes;
 406         }
 407
 408         spi_imx->remainder -= sizeof(u32);
 409 }
 410
 411 static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx)
 412 {
 413         u32 val = 0;
 414         int n_bytes = spi_imx->count % sizeof(val);
 415
 416         if (!n_bytes)
 417                 n_bytes = sizeof(val);
 418
 419         if (spi_imx->tx_buf) {
 420                 memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
 421                        spi_imx->tx_buf, n_bytes);
 422                 val = cpu_to_be32(val);
 423                 spi_imx->tx_buf += n_bytes;
 424         }
 425
 426         spi_imx->count -= n_bytes;
 427
 428         writel(val, spi_imx->base + MXC_CSPITXDATA);
 429 }
 430
 431 /* MX51 eCSPI */
 432 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
 433                                       unsigned int fspi, unsigned int *fres)
 434 {
 435         /*
 436          * there are two 4-bit dividers, the pre-divider divides by
 437          * $pre, the post-divider by 2^$post
 438          */
 439         unsigned int pre, post;
 440         unsigned int fin = spi_imx->spi_clk;
 441
 442         if (unlikely(fspi > fin))
 443                 return 0;
 444
 445         post = fls(fin) - fls(fspi);
 446         if (fin > fspi << post)
 447                 post++;
 448
 449         /* now we have: (fin <= fspi << post) with post being minimal */
 450
 451         post = max(4U, post) - 4;
 452         if (unlikely(post > 0xf)) {
 453                 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
 454                                 fspi, fin);
 455                 return 0xff;
 456         }
 457
 458         pre = DIV_ROUND_UP(fin, fspi << post) - 1;
 459
 460         dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
 461                         __func__, fin, fspi, post, pre);
 462
 463         /* Resulting frequency for the SCLK line. */
 464         *fres = (fin / (pre + 1)) >> post;
 465
 466         return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
 467                 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
 468 }
 469
 470 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
 471 {
 472         unsigned val = 0;
 473
 474         if (enable & MXC_INT_TE)
 475                 val |= MX51_ECSPI_INT_TEEN;
 476
 477         if (enable & MXC_INT_RR)
 478                 val |= MX51_ECSPI_INT_RREN;
 479
 480         if (enable & MXC_INT_RDR)
 481                 val |= MX51_ECSPI_INT_RDREN;
 482
 483         writel(val, spi_imx->base + MX51_ECSPI_INT);
 484 }
 485
 486 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
 487 {
 488         u32 reg;
 489
 490         reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
 491         reg |= MX51_ECSPI_CTRL_XCH;
 492         writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
 493 }
 494
 495 static void mx51_disable_dma(struct spi_imx_data *spi_imx)
 496 {
 497         writel(0, spi_imx->base + MX51_ECSPI_DMA);
 498 }
 499
 500 static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
 501 {
 502         u32 ctrl;
 503
 504         ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
 505         ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
 506         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 507 }
 508
 509 static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
 510                                       struct spi_message *msg)
 511 {
 512         struct spi_device *spi = msg->spi;
 513         struct spi_transfer *xfer;
 514         u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
 515         u32 min_speed_hz = ~0U;
 516         u32 testreg, delay;
 517         u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
 518
 519         /* set Master or Slave mode */
 520         if (spi_imx->slave_mode)
 521                 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
 522         else
 523                 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
 524
 525         /*
 526          * Enable SPI_RDY handling (falling edge/level triggered).
 527          */
 528         if (spi->mode & SPI_READY)
 529                 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
 530
 531         /* set chip select to use */
 532         ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
 533
 534         /*
 535          * The ctrl register must be written first, with the EN bit set other
 536          * registers must not be written to.
 537          */
 538         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 539
 540         testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
 541         if (spi->mode & SPI_LOOP)
 542                 testreg |= MX51_ECSPI_TESTREG_LBC;
 543         else
 544                 testreg &= ~MX51_ECSPI_TESTREG_LBC;
 545         writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
 546
 547         /*
 548          * eCSPI burst completion by Chip Select signal in Slave mode
 549          * is not functional for imx53 Soc, config SPI burst completed when
 550          * BURST_LENGTH + 1 bits are received
 551          */
 552         if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
 553                 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
 554         else
 555                 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
 556
 557         if (spi->mode & SPI_CPHA)
 558                 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
 559         else
 560                 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
 561
 562         if (spi->mode & SPI_CPOL) {
 563                 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
 564                 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
 565         } else {
 566                 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
 567                 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
 568         }
 569
 570         if (spi->mode & SPI_CS_HIGH)
 571                 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
 572         else
 573                 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
 574
 575         writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
 576
 577         /*
 578          * Wait until the changes in the configuration register CONFIGREG
 579          * propagate into the hardware. It takes exactly one tick of the
 580          * SCLK clock, but we will wait two SCLK clock just to be sure. The
 581          * effect of the delay it takes for the hardware to apply changes
 582          * is noticable if the SCLK clock run very slow. In such a case, if
 583          * the polarity of SCLK should be inverted, the GPIO ChipSelect might
 584          * be asserted before the SCLK polarity changes, which would disrupt
 585          * the SPI communication as the device on the other end would consider
 586          * the change of SCLK polarity as a clock tick already.
 587          *
 588          * Because spi_imx->spi_bus_clk is only set in bitbang prepare_message
 589          * callback, iterate over all the transfers in spi_message, find the
 590          * one with lowest bus frequency, and use that bus frequency for the
 591          * delay calculation. In case all transfers have speed_hz == 0, then
 592          * min_speed_hz is ~0 and the resulting delay is zero.
 593          */
 594         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 595                 if (!xfer->speed_hz)
 596                         continue;
 597                 min_speed_hz = min(xfer->speed_hz, min_speed_hz);
 598         }
 599
 600         delay = (2 * 1000000) / min_speed_hz;
 601         if (likely(delay < 10)) /* SCLK is faster than 200 kHz */
 602                 udelay(delay);
 603         else                    /* SCLK is _very_ slow */
 604                 usleep_range(delay, delay + 10);
 605
 606         return 0;
 607 }
 608
 609 static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
 610                                        struct spi_device *spi)
 611 {
 612         u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
 613         u32 clk;
 614
 615         /* Clear BL field and set the right value */
 616         ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
 617         if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
 618                 ctrl |= (spi_imx->slave_burst * 8 - 1)
 619                         << MX51_ECSPI_CTRL_BL_OFFSET;
 620         else
 621                 ctrl |= (spi_imx->bits_per_word - 1)
 622                         << MX51_ECSPI_CTRL_BL_OFFSET;
 623
 624         /* set clock speed */
 625         ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
 626                   0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET);
 627         ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk);
 628         spi_imx->spi_bus_clk = clk;
 629
 630         /*
 631          * ERR009165: work in XHC mode instead of SMC as PIO on the chips
 632          * before i.mx6ul.
 633          */
 634         if (spi_imx->usedma && spi_imx->devtype_data->tx_glitch_fixed)
 635                 ctrl |= MX51_ECSPI_CTRL_SMC;
 636         else
 637                 ctrl &= ~MX51_ECSPI_CTRL_SMC;
 638
 639         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 640
 641         return 0;
 642 }
 643
 644 static void mx51_setup_wml(struct spi_imx_data *spi_imx)
 645 {
 646         u32 tx_wml = 0;
 647
 648         if (spi_imx->devtype_data->tx_glitch_fixed)
 649                 tx_wml = spi_imx->wml;
 650         /*
 651          * Configure the DMA register: setup the watermark
 652          * and enable DMA request.
 653          */
 654         writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
 655                 MX51_ECSPI_DMA_TX_WML(tx_wml) |
 656                 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
 657                 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
 658                 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
 659 }
 660
 661 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
 662 {
 663         return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
 664 }
 665
 666 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
 667 {
 668         /* drain receive buffer */
 669         while (mx51_ecspi_rx_available(spi_imx))
 670                 readl(spi_imx->base + MXC_CSPIRXDATA);
 671 }
 672
 673 #define MX31_INTREG_TEEN        (1 << 0)
 674 #define MX31_INTREG_RREN        (1 << 3)
 675
 676 #define MX31_CSPICTRL_ENABLE    (1 << 0)
 677 #define MX31_CSPICTRL_MASTER    (1 << 1)
 678 #define MX31_CSPICTRL_XCH       (1 << 2)
 679 #define MX31_CSPICTRL_SMC       (1 << 3)
 680 #define MX31_CSPICTRL_POL       (1 << 4)
 681 #define MX31_CSPICTRL_PHA       (1 << 5)
 682 #define MX31_CSPICTRL_SSCTL     (1 << 6)
 683 #define MX31_CSPICTRL_SSPOL     (1 << 7)
 684 #define MX31_CSPICTRL_BC_SHIFT  8
 685 #define MX35_CSPICTRL_BL_SHIFT  20
 686 #define MX31_CSPICTRL_CS_SHIFT  24
 687 #define MX35_CSPICTRL_CS_SHIFT  12
 688 #define MX31_CSPICTRL_DR_SHIFT  16
 689
 690 #define MX31_CSPI_DMAREG        0x10
 691 #define MX31_DMAREG_RH_DEN      (1<<4)
 692 #define MX31_DMAREG_TH_DEN      (1<<1)
 693
 694 #define MX31_CSPISTATUS         0x14
 695 #define MX31_STATUS_RR          (1 << 3)
 696
 697 #define MX31_CSPI_TESTREG       0x1C
 698 #define MX31_TEST_LBC           (1 << 14)
 699
 700 /* These functions also work for the i.MX35, but be aware that
 701  * the i.MX35 has a slightly different register layout for bits
 702  * we do not use here.
 703  */
 704 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
 705 {
 706         unsigned int val = 0;
 707
 708         if (enable & MXC_INT_TE)
 709                 val |= MX31_INTREG_TEEN;
 710         if (enable & MXC_INT_RR)
 711                 val |= MX31_INTREG_RREN;
 712
 713         writel(val, spi_imx->base + MXC_CSPIINT);
 714 }
 715
 716 static void mx31_trigger(struct spi_imx_data *spi_imx)
 717 {
 718         unsigned int reg;
 719
 720         reg = readl(spi_imx->base + MXC_CSPICTRL);
 721         reg |= MX31_CSPICTRL_XCH;
 722         writel(reg, spi_imx->base + MXC_CSPICTRL);
 723 }
 724
 725 static int mx31_prepare_message(struct spi_imx_data *spi_imx,
 726                                 struct spi_message *msg)
 727 {
 728         return 0;
 729 }
 730
 731 static int mx31_prepare_transfer(struct spi_imx_data *spi_imx,
 732                                  struct spi_device *spi)
 733 {
 734         unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
 735         unsigned int clk;
 736
 737         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
 738                 MX31_CSPICTRL_DR_SHIFT;
 739         spi_imx->spi_bus_clk = clk;
 740
 741         if (is_imx35_cspi(spi_imx)) {
 742                 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
 743                 reg |= MX31_CSPICTRL_SSCTL;
 744         } else {
 745                 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
 746         }
 747
 748         if (spi->mode & SPI_CPHA)
 749                 reg |= MX31_CSPICTRL_PHA;
 750         if (spi->mode & SPI_CPOL)
 751                 reg |= MX31_CSPICTRL_POL;
 752         if (spi->mode & SPI_CS_HIGH)
 753                 reg |= MX31_CSPICTRL_SSPOL;
 754         if (!spi->cs_gpiod)
 755                 reg |= (spi->chip_select) <<
 756                         (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
 757                                                   MX31_CSPICTRL_CS_SHIFT);
 758
 759         if (spi_imx->usedma)
 760                 reg |= MX31_CSPICTRL_SMC;
 761
 762         writel(reg, spi_imx->base + MXC_CSPICTRL);
 763
 764         reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
 765         if (spi->mode & SPI_LOOP)
 766                 reg |= MX31_TEST_LBC;
 767         else
 768                 reg &= ~MX31_TEST_LBC;
 769         writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
 770
 771         if (spi_imx->usedma) {
 772                 /*
 773                  * configure DMA requests when RXFIFO is half full and
 774                  * when TXFIFO is half empty
 775                  */
 776                 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
 777                         spi_imx->base + MX31_CSPI_DMAREG);
 778         }
 779
 780         return 0;
 781 }
 782
 783 static int mx31_rx_available(struct spi_imx_data *spi_imx)
 784 {
 785         return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
 786 }
 787
 788 static void mx31_reset(struct spi_imx_data *spi_imx)
 789 {
 790         /* drain receive buffer */
 791         while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
 792                 readl(spi_imx->base + MXC_CSPIRXDATA);
 793 }
 794
 795 #define MX21_INTREG_RR          (1 << 4)
 796 #define MX21_INTREG_TEEN        (1 << 9)
 797 #define MX21_INTREG_RREN        (1 << 13)
 798
 799 #define MX21_CSPICTRL_POL       (1 << 5)
 800 #define MX21_CSPICTRL_PHA       (1 << 6)
 801 #define MX21_CSPICTRL_SSPOL     (1 << 8)
 802 #define MX21_CSPICTRL_XCH       (1 << 9)
 803 #define MX21_CSPICTRL_ENABLE    (1 << 10)
 804 #define MX21_CSPICTRL_MASTER    (1 << 11)
 805 #define MX21_CSPICTRL_DR_SHIFT  14
 806 #define MX21_CSPICTRL_CS_SHIFT  19
 807
 808 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
 809 {
 810         unsigned int val = 0;
 811
 812         if (enable & MXC_INT_TE)
 813                 val |= MX21_INTREG_TEEN;
 814         if (enable & MXC_INT_RR)
 815                 val |= MX21_INTREG_RREN;
 816
 817         writel(val, spi_imx->base + MXC_CSPIINT);
 818 }
 819
 820 static void mx21_trigger(struct spi_imx_data *spi_imx)
 821 {
 822         unsigned int reg;
 823
 824         reg = readl(spi_imx->base + MXC_CSPICTRL);
 825         reg |= MX21_CSPICTRL_XCH;
 826         writel(reg, spi_imx->base + MXC_CSPICTRL);
 827 }
 828
 829 static int mx21_prepare_message(struct spi_imx_data *spi_imx,
 830                                 struct spi_message *msg)
 831 {
 832         return 0;
 833 }
 834
 835 static int mx21_prepare_transfer(struct spi_imx_data *spi_imx,
 836                                  struct spi_device *spi)
 837 {
 838         unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
 839         unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
 840         unsigned int clk;
 841
 842         reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk)
 843                 << MX21_CSPICTRL_DR_SHIFT;
 844         spi_imx->spi_bus_clk = clk;
 845
 846         reg |= spi_imx->bits_per_word - 1;
 847
 848         if (spi->mode & SPI_CPHA)
 849                 reg |= MX21_CSPICTRL_PHA;
 850         if (spi->mode & SPI_CPOL)
 851                 reg |= MX21_CSPICTRL_POL;
 852         if (spi->mode & SPI_CS_HIGH)
 853                 reg |= MX21_CSPICTRL_SSPOL;
 854         if (!spi->cs_gpiod)
 855                 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT;
 856
 857         writel(reg, spi_imx->base + MXC_CSPICTRL);
 858
 859         return 0;
 860 }
 861
 862 static int mx21_rx_available(struct spi_imx_data *spi_imx)
 863 {
 864         return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
 865 }
 866
 867 static void mx21_reset(struct spi_imx_data *spi_imx)
 868 {
 869         writel(1, spi_imx->base + MXC_RESET);
 870 }
 871
 872 #define MX1_INTREG_RR           (1 << 3)
 873 #define MX1_INTREG_TEEN         (1 << 8)
 874 #define MX1_INTREG_RREN         (1 << 11)
 875
 876 #define MX1_CSPICTRL_POL        (1 << 4)
 877 #define MX1_CSPICTRL_PHA        (1 << 5)
 878 #define MX1_CSPICTRL_XCH        (1 << 8)
 879 #define MX1_CSPICTRL_ENABLE     (1 << 9)
 880 #define MX1_CSPICTRL_MASTER     (1 << 10)
 881 #define MX1_CSPICTRL_DR_SHIFT   13
 882
 883 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
 884 {
 885         unsigned int val = 0;
 886
 887         if (enable & MXC_INT_TE)
 888                 val |= MX1_INTREG_TEEN;
 889         if (enable & MXC_INT_RR)
 890                 val |= MX1_INTREG_RREN;
 891
 892         writel(val, spi_imx->base + MXC_CSPIINT);
 893 }
 894
 895 static void mx1_trigger(struct spi_imx_data *spi_imx)
 896 {
 897         unsigned int reg;
 898
 899         reg = readl(spi_imx->base + MXC_CSPICTRL);
 900         reg |= MX1_CSPICTRL_XCH;
 901         writel(reg, spi_imx->base + MXC_CSPICTRL);
 902 }
 903
 904 static int mx1_prepare_message(struct spi_imx_data *spi_imx,
 905                                struct spi_message *msg)
 906 {
 907         return 0;
 908 }
 909
 910 static int mx1_prepare_transfer(struct spi_imx_data *spi_imx,
 911                                 struct spi_device *spi)
 912 {
 913         unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
 914         unsigned int clk;
 915
 916         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
 917                 MX1_CSPICTRL_DR_SHIFT;
 918         spi_imx->spi_bus_clk = clk;
 919
 920         reg |= spi_imx->bits_per_word - 1;
 921
 922         if (spi->mode & SPI_CPHA)
 923                 reg |= MX1_CSPICTRL_PHA;
 924         if (spi->mode & SPI_CPOL)
 925                 reg |= MX1_CSPICTRL_POL;
 926
 927         writel(reg, spi_imx->base + MXC_CSPICTRL);
 928
 929         return 0;
 930 }
 931
 932 static int mx1_rx_available(struct spi_imx_data *spi_imx)
 933 {
 934         return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
 935 }
 936
 937 static void mx1_reset(struct spi_imx_data *spi_imx)
 938 {
 939         writel(1, spi_imx->base + MXC_RESET);
 940 }
 941
 942 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
 943         .intctrl = mx1_intctrl,
 944         .prepare_message = mx1_prepare_message,
 945         .prepare_transfer = mx1_prepare_transfer,
 946         .trigger = mx1_trigger,
 947         .rx_available = mx1_rx_available,
 948         .reset = mx1_reset,
 949         .fifo_size = 8,
 950         .has_dmamode = false,
 951         .dynamic_burst = false,
 952         .has_slavemode = false,
 953         .devtype = IMX1_CSPI,
 954 };
 955
 956 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
 957         .intctrl = mx21_intctrl,
 958         .prepare_message = mx21_prepare_message,
 959         .prepare_transfer = mx21_prepare_transfer,
 960         .trigger = mx21_trigger,
 961         .rx_available = mx21_rx_available,
 962         .reset = mx21_reset,
 963         .fifo_size = 8,
 964         .has_dmamode = false,
 965         .dynamic_burst = false,
 966         .has_slavemode = false,
 967         .devtype = IMX21_CSPI,
 968 };
 969
 970 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
 971         /* i.mx27 cspi shares the functions with i.mx21 one */
 972         .intctrl = mx21_intctrl,
 973         .prepare_message = mx21_prepare_message,
 974         .prepare_transfer = mx21_prepare_transfer,
 975         .trigger = mx21_trigger,
 976         .rx_available = mx21_rx_available,
 977         .reset = mx21_reset,
 978         .fifo_size = 8,
 979         .has_dmamode = false,
 980         .dynamic_burst = false,
 981         .has_slavemode = false,
 982         .devtype = IMX27_CSPI,
 983 };
 984
 985 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
 986         .intctrl = mx31_intctrl,
 987         .prepare_message = mx31_prepare_message,
 988         .prepare_transfer = mx31_prepare_transfer,
 989         .trigger = mx31_trigger,
 990         .rx_available = mx31_rx_available,
 991         .reset = mx31_reset,
 992         .fifo_size = 8,
 993         .has_dmamode = false,
 994         .dynamic_burst = false,
 995         .has_slavemode = false,
 996         .devtype = IMX31_CSPI,
 997 };
 998
 999 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
1000         /* i.mx35 and later cspi shares the functions with i.mx31 one */
1001         .intctrl = mx31_intctrl,
1002         .prepare_message = mx31_prepare_message,
1003         .prepare_transfer = mx31_prepare_transfer,
1004         .trigger = mx31_trigger,
1005         .rx_available = mx31_rx_available,
1006         .reset = mx31_reset,
1007         .fifo_size = 8,
1008         .has_dmamode = true,
1009         .dynamic_burst = false,
1010         .has_slavemode = false,
1011         .devtype = IMX35_CSPI,
1012 };
1013
1014 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
1015         .intctrl = mx51_ecspi_intctrl,
1016         .prepare_message = mx51_ecspi_prepare_message,
1017         .prepare_transfer = mx51_ecspi_prepare_transfer,
1018         .trigger = mx51_ecspi_trigger,
1019         .rx_available = mx51_ecspi_rx_available,
1020         .reset = mx51_ecspi_reset,
1021         .setup_wml = mx51_setup_wml,
1022         .disable_dma = mx51_disable_dma,
1023         .fifo_size = 64,
1024         .has_dmamode = true,
1025         .dynamic_burst = true,
1026         .has_slavemode = true,
1027         .disable = mx51_ecspi_disable,
1028         .devtype = IMX51_ECSPI,
1029 };
1030
1031 static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
1032         .intctrl = mx51_ecspi_intctrl,
1033         .prepare_message = mx51_ecspi_prepare_message,
1034         .prepare_transfer = mx51_ecspi_prepare_transfer,
1035         .trigger = mx51_ecspi_trigger,
1036         .rx_available = mx51_ecspi_rx_available,
1037         .disable_dma = mx51_disable_dma,
1038         .reset = mx51_ecspi_reset,
1039         .fifo_size = 64,
1040         .has_dmamode = true,
1041         .has_slavemode = true,
1042         .disable = mx51_ecspi_disable,
1043         .devtype = IMX53_ECSPI,
1044 };
1045
1046 static struct spi_imx_devtype_data imx6ul_ecspi_devtype_data = {
1047         .intctrl = mx51_ecspi_intctrl,
1048         .prepare_message = mx51_ecspi_prepare_message,
1049         .prepare_transfer = mx51_ecspi_prepare_transfer,
1050         .trigger = mx51_ecspi_trigger,
1051         .rx_available = mx51_ecspi_rx_available,
1052         .reset = mx51_ecspi_reset,
1053         .setup_wml = mx51_setup_wml,
1054         .fifo_size = 64,
1055         .has_dmamode = true,
1056         .dynamic_burst = true,
1057         .has_slavemode = true,
1058         .tx_glitch_fixed = true,
1059         .disable = mx51_ecspi_disable,
1060         .devtype = IMX51_ECSPI,
1061 };
1062
1063 static const struct of_device_id spi_imx_dt_ids[] = {
1064         { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
1065         { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
1066         { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
1067         { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
1068         { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1069         { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1070         { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1071         { .compatible = "fsl,imx6ul-ecspi", .data = &imx6ul_ecspi_devtype_data, },
1072         { /* sentinel */ }
1073 };
1074 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
1075
1076 static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits)
1077 {
1078         u32 ctrl;
1079
1080         ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
1081         ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
1082         ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET);
1083         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
1084 }
1085
1086 static void spi_imx_push(struct spi_imx_data *spi_imx)
1087 {
1088         unsigned int burst_len;
1089
1090         /*
1091          * Reload the FIFO when the remaining bytes to be transferred in the
1092          * current burst is 0. This only applies when bits_per_word is a
1093          * multiple of 8.
1094          */
1095         if (!spi_imx->remainder) {
1096                 if (spi_imx->dynamic_burst) {
1097
1098                         /* We need to deal unaligned data first */
1099                         burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST;
1100
1101                         if (!burst_len)
1102                                 burst_len = MX51_ECSPI_CTRL_MAX_BURST;
1103
1104                         spi_imx_set_burst_len(spi_imx, burst_len * 8);
1105
1106                         spi_imx->remainder = burst_len;
1107                 } else {
1108                         spi_imx->remainder = spi_imx_bytes_per_word(spi_imx->bits_per_word);
1109                 }
1110         }
1111
1112         while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
1113                 if (!spi_imx->count)
1114                         break;
1115                 if (spi_imx->dynamic_burst &&
1116                     spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, 4))
1117                         break;
1118                 spi_imx->tx(spi_imx);
1119                 spi_imx->txfifo++;
1120         }
1121
1122         if (!spi_imx->slave_mode)
1123                 spi_imx->devtype_data->trigger(spi_imx);
1124 }
1125
1126 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
1127 {
1128         struct spi_imx_data *spi_imx = dev_id;
1129
1130         while (spi_imx->txfifo &&
1131                spi_imx->devtype_data->rx_available(spi_imx)) {
1132                 spi_imx->rx(spi_imx);
1133                 spi_imx->txfifo--;
1134         }
1135
1136         if (spi_imx->count) {
1137                 spi_imx_push(spi_imx);
1138                 return IRQ_HANDLED;
1139         }
1140
1141         if (spi_imx->txfifo) {
1142                 /* No data left to push, but still waiting for rx data,
1143                  * enable receive data available interrupt.
1144                  */
1145                 spi_imx->devtype_data->intctrl(
1146                                 spi_imx, MXC_INT_RR);
1147                 return IRQ_HANDLED;
1148         }
1149
1150         spi_imx->devtype_data->intctrl(spi_imx, 0);
1151         complete(&spi_imx->xfer_done);
1152
1153         return IRQ_HANDLED;
1154 }
1155
1156 static int spi_imx_dma_configure(struct spi_master *master)
1157 {
1158         int ret;
1159         enum dma_slave_buswidth buswidth;
1160         struct dma_slave_config rx = {}, tx = {};
1161         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1162
1163         switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
1164         case 4:
1165                 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1166                 break;
1167         case 2:
1168                 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1169                 break;
1170         case 1:
1171                 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1172                 break;
1173         default:
1174                 return -EINVAL;
1175         }
1176
1177         tx.direction = DMA_MEM_TO_DEV;
1178         tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
1179         tx.dst_addr_width = buswidth;
1180         tx.dst_maxburst = spi_imx->wml;
1181         ret = dmaengine_slave_config(master->dma_tx, &tx);
1182         if (ret) {
1183                 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
1184                 return ret;
1185         }
1186
1187         rx.direction = DMA_DEV_TO_MEM;
1188         rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
1189         rx.src_addr_width = buswidth;
1190         rx.src_maxburst = spi_imx->wml;
1191         ret = dmaengine_slave_config(master->dma_rx, &rx);
1192         if (ret) {
1193                 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
1194                 return ret;
1195         }
1196
1197         return 0;
1198 }
1199
1200 static int spi_imx_setupxfer(struct spi_device *spi,
1201                                  struct spi_transfer *t)
1202 {
1203         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1204
1205         if (!t)
1206                 return 0;
1207
1208         if (!t->speed_hz) {
1209                 if (!spi->max_speed_hz) {
1210                         dev_err(&spi->dev, "no speed_hz provided!\n");
1211                         return -EINVAL;
1212                 }
1213                 dev_dbg(&spi->dev, "using spi->max_speed_hz!\n");
1214                 spi_imx->spi_bus_clk = spi->max_speed_hz;
1215         } else
1216                 spi_imx->spi_bus_clk = t->speed_hz;
1217
1218         spi_imx->bits_per_word = t->bits_per_word;
1219
1220         /*
1221          * Initialize the functions for transfer. To transfer non byte-aligned
1222          * words, we have to use multiple word-size bursts, we can't use
1223          * dynamic_burst in that case.
1224          */
1225         if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode &&
1226             !(spi->mode & SPI_CS_WORD) &&
1227             (spi_imx->bits_per_word == 8 ||
1228             spi_imx->bits_per_word == 16 ||
1229             spi_imx->bits_per_word == 32)) {
1230
1231                 spi_imx->rx = spi_imx_buf_rx_swap;
1232                 spi_imx->tx = spi_imx_buf_tx_swap;
1233                 spi_imx->dynamic_burst = 1;
1234
1235         } else {
1236                 if (spi_imx->bits_per_word <= 8) {
1237                         spi_imx->rx = spi_imx_buf_rx_u8;
1238                         spi_imx->tx = spi_imx_buf_tx_u8;
1239                 } else if (spi_imx->bits_per_word <= 16) {
1240                         spi_imx->rx = spi_imx_buf_rx_u16;
1241                         spi_imx->tx = spi_imx_buf_tx_u16;
1242                 } else {
1243                         spi_imx->rx = spi_imx_buf_rx_u32;
1244                         spi_imx->tx = spi_imx_buf_tx_u32;
1245                 }
1246                 spi_imx->dynamic_burst = 0;
1247         }
1248
1249         if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
1250                 spi_imx->usedma = true;
1251         else
1252                 spi_imx->usedma = false;
1253
1254         if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) {
1255                 spi_imx->rx = mx53_ecspi_rx_slave;
1256                 spi_imx->tx = mx53_ecspi_tx_slave;
1257                 spi_imx->slave_burst = t->len;
1258         }
1259
1260         spi_imx->devtype_data->prepare_transfer(spi_imx, spi);
1261
1262         return 0;
1263 }
1264
1265 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
1266 {
1267         struct spi_master *master = spi_imx->bitbang.master;
1268
1269         if (master->dma_rx) {
1270                 dma_release_channel(master->dma_rx);
1271                 master->dma_rx = NULL;
1272         }
1273
1274         if (master->dma_tx) {
1275                 dma_release_channel(master->dma_tx);
1276                 master->dma_tx = NULL;
1277         }
1278 }
1279
1280 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1281                              struct spi_master *master)
1282 {
1283         int ret;
1284
1285         spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
1286
1287         /* Prepare for TX DMA: */
1288         master->dma_tx = dma_request_chan(dev, "tx");
1289         if (IS_ERR(master->dma_tx)) {
1290                 ret = PTR_ERR(master->dma_tx);
1291                 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
1292                 master->dma_tx = NULL;
1293                 goto err;
1294         }
1295
1296         /* Prepare for RX : */
1297         master->dma_rx = dma_request_chan(dev, "rx");
1298         if (IS_ERR(master->dma_rx)) {
1299                 ret = PTR_ERR(master->dma_rx);
1300                 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
1301                 master->dma_rx = NULL;
1302                 goto err;
1303         }
1304
1305         init_completion(&spi_imx->dma_rx_completion);
1306         init_completion(&spi_imx->dma_tx_completion);
1307         master->can_dma = spi_imx_can_dma;
1308         master->max_dma_len = MAX_SDMA_BD_BYTES;
1309         spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
1310                                          SPI_MASTER_MUST_TX;
1311
1312         return 0;
1313 err:
1314         spi_imx_sdma_exit(spi_imx);
1315         return ret;
1316 }
1317
1318 static void spi_imx_dma_rx_callback(void *cookie)
1319 {
1320         struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1321
1322         complete(&spi_imx->dma_rx_completion);
1323 }
1324
1325 static void spi_imx_dma_tx_callback(void *cookie)
1326 {
1327         struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1328
1329         complete(&spi_imx->dma_tx_completion);
1330 }
1331
1332 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1333 {
1334         unsigned long timeout = 0;
1335
1336         /* Time with actual data transfer and CS change delay related to HW */
1337         timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1338
1339         /* Add extra second for scheduler related activities */
1340         timeout += 1;
1341
1342         /* Double calculated timeout */
1343         return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1344 }
1345
1346 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1347                                 struct spi_transfer *transfer)
1348 {
1349         struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1350         unsigned long transfer_timeout;
1351         unsigned long timeout;
1352         struct spi_master *master = spi_imx->bitbang.master;
1353         struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1354         struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents);
1355         unsigned int bytes_per_word, i;
1356         int ret;
1357
1358         /* Get the right burst length from the last sg to ensure no tail data */
1359         bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
1360         for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
1361                 if (!(sg_dma_len(last_sg) % (i * bytes_per_word)))
1362                         break;
1363         }
1364         /* Use 1 as wml in case no available burst length got */
1365         if (i == 0)
1366                 i = 1;
1367
1368         spi_imx->wml =  i;
1369
1370         ret = spi_imx_dma_configure(master);
1371         if (ret)
1372                 goto dma_failure_no_start;
1373
1374         if (!spi_imx->devtype_data->setup_wml) {
1375                 dev_err(spi_imx->dev, "No setup_wml()?\n");
1376                 ret = -EINVAL;
1377                 goto dma_failure_no_start;
1378         }
1379         spi_imx->devtype_data->setup_wml(spi_imx);
1380
1381         /*
1382          * The TX DMA setup starts the transfer, so make sure RX is configured
1383          * before TX.
1384          */
1385         desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
1386                                 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1387                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1388         if (!desc_rx) {
1389                 ret = -EINVAL;
1390                 goto dma_failure_no_start;
1391         }
1392
1393         desc_rx->callback = spi_imx_dma_rx_callback;
1394         desc_rx->callback_param = (void *)spi_imx;
1395         dmaengine_submit(desc_rx);
1396         reinit_completion(&spi_imx->dma_rx_completion);
1397         dma_async_issue_pending(master->dma_rx);
1398
1399         desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
1400                                 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1401                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1402         if (!desc_tx) {
1403                 dmaengine_terminate_all(master->dma_tx);
1404                 dmaengine_terminate_all(master->dma_rx);
1405                 return -EINVAL;
1406         }
1407
1408         desc_tx->callback = spi_imx_dma_tx_callback;
1409         desc_tx->callback_param = (void *)spi_imx;
1410         dmaengine_submit(desc_tx);
1411         reinit_completion(&spi_imx->dma_tx_completion);
1412         dma_async_issue_pending(master->dma_tx);
1413
1414         transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1415
1416         /* Wait SDMA to finish the data transfer.*/
1417         timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1418                                                 transfer_timeout);
1419         if (!timeout) {
1420                 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1421                 dmaengine_terminate_all(master->dma_tx);
1422                 dmaengine_terminate_all(master->dma_rx);
1423                 return -ETIMEDOUT;
1424         }
1425
1426         timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1427                                               transfer_timeout);
1428         if (!timeout) {
1429                 dev_err(&master->dev, "I/O Error in DMA RX\n");
1430                 spi_imx->devtype_data->reset(spi_imx);
1431                 dmaengine_terminate_all(master->dma_rx);
1432                 return -ETIMEDOUT;
1433         }
1434
1435         return transfer->len;
1436 /* fallback to pio */
1437 dma_failure_no_start:
1438         transfer->error |= SPI_TRANS_FAIL_NO_START;
1439         return ret;
1440 }
1441
1442 static int spi_imx_pio_transfer(struct spi_device *spi,
1443                                 struct spi_transfer *transfer)
1444 {
1445         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1446         unsigned long transfer_timeout;
1447         unsigned long timeout;
1448
1449         spi_imx->tx_buf = transfer->tx_buf;
1450         spi_imx->rx_buf = transfer->rx_buf;
1451         spi_imx->count = transfer->len;
1452         spi_imx->txfifo = 0;
1453         spi_imx->remainder = 0;
1454
1455         reinit_completion(&spi_imx->xfer_done);
1456
1457         spi_imx_push(spi_imx);
1458
1459         spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1460
1461         transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1462
1463         timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1464                                               transfer_timeout);
1465         if (!timeout) {
1466                 dev_err(&spi->dev, "I/O Error in PIO\n");
1467                 spi_imx->devtype_data->reset(spi_imx);
1468                 return -ETIMEDOUT;
1469         }
1470
1471         return transfer->len;
1472 }
1473
1474 static int spi_imx_pio_transfer_slave(struct spi_device *spi,
1475                                       struct spi_transfer *transfer)
1476 {
1477         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1478         int ret = transfer->len;
1479
1480         if (is_imx53_ecspi(spi_imx) &&
1481             transfer->len > MX53_MAX_TRANSFER_BYTES) {
1482                 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
1483                         MX53_MAX_TRANSFER_BYTES);
1484                 return -EMSGSIZE;
1485         }
1486
1487         spi_imx->tx_buf = transfer->tx_buf;
1488         spi_imx->rx_buf = transfer->rx_buf;
1489         spi_imx->count = transfer->len;
1490         spi_imx->txfifo = 0;
1491         spi_imx->remainder = 0;
1492
1493         reinit_completion(&spi_imx->xfer_done);
1494         spi_imx->slave_aborted = false;
1495
1496         spi_imx_push(spi_imx);
1497
1498         spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);
1499
1500         if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
1501             spi_imx->slave_aborted) {
1502                 dev_dbg(&spi->dev, "interrupted\n");
1503                 ret = -EINTR;
1504         }
1505
1506         /* ecspi has a HW issue when works in Slave mode,
1507          * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
1508          * ECSPI_TXDATA keeps shift out the last word data,
1509          * so we have to disable ECSPI when in slave mode after the
1510          * transfer completes
1511          */
1512         if (spi_imx->devtype_data->disable)
1513                 spi_imx->devtype_data->disable(spi_imx);
1514
1515         return ret;
1516 }
1517
1518 static int spi_imx_transfer(struct spi_device *spi,
1519                                 struct spi_transfer *transfer)
1520 {
1521         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1522
1523         transfer->effective_speed_hz = spi_imx->spi_bus_clk;
1524
1525         /* flush rxfifo before transfer */
1526         while (spi_imx->devtype_data->rx_available(spi_imx))
1527                 readl(spi_imx->base + MXC_CSPIRXDATA);
1528
1529         if (spi_imx->slave_mode)
1530                 return spi_imx_pio_transfer_slave(spi, transfer);
1531
1532         if (spi_imx->usedma)
1533                 return spi_imx_dma_transfer(spi_imx, transfer);
1534
1535         return spi_imx_pio_transfer(spi, transfer);
1536 }
1537
1538 static int spi_imx_setup(struct spi_device *spi)
1539 {
1540         dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1541                  spi->mode, spi->bits_per_word, spi->max_speed_hz);
1542
1543         return 0;
1544 }
1545
1546 static void spi_imx_cleanup(struct spi_device *spi)
1547 {
1548 }
1549
1550 static int
1551 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1552 {
1553         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1554         int ret;
1555
1556         ret = pm_runtime_get_sync(spi_imx->dev);
1557         if (ret < 0) {
1558                 pm_runtime_put_noidle(spi_imx->dev);
1559                 dev_err(spi_imx->dev, "failed to enable clock\n");
1560                 return ret;
1561         }
1562
1563         ret = spi_imx->devtype_data->prepare_message(spi_imx, msg);
1564         if (ret) {
1565                 pm_runtime_mark_last_busy(spi_imx->dev);
1566                 pm_runtime_put_autosuspend(spi_imx->dev);
1567         }
1568
1569         return ret;
1570 }
1571
1572 static int
1573 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1574 {
1575         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1576
1577         pm_runtime_mark_last_busy(spi_imx->dev);
1578         pm_runtime_put_autosuspend(spi_imx->dev);
1579         return 0;
1580 }
1581
1582 static int spi_imx_slave_abort(struct spi_master *master)
1583 {
1584         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1585
1586         spi_imx->slave_aborted = true;
1587         complete(&spi_imx->xfer_done);
1588
1589         return 0;
1590 }
1591
1592 static int spi_imx_probe(struct platform_device *pdev)
1593 {
1594         struct device_node *np = pdev->dev.of_node;
1595         struct spi_master *master;
1596         struct spi_imx_data *spi_imx;
1597         struct resource *res;
1598         int ret, irq, spi_drctl;
1599         const struct spi_imx_devtype_data *devtype_data =
1600                         of_device_get_match_data(&pdev->dev);
1601         bool slave_mode;
1602         u32 val;
1603
1604         slave_mode = devtype_data->has_slavemode &&
1605                         of_property_read_bool(np, "spi-slave");
1606         if (slave_mode)
1607                 master = spi_alloc_slave(&pdev->dev,
1608                                          sizeof(struct spi_imx_data));
1609         else
1610                 master = spi_alloc_master(&pdev->dev,
1611                                           sizeof(struct spi_imx_data));
1612         if (!master)
1613                 return -ENOMEM;
1614
1615         ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1616         if ((ret < 0) || (spi_drctl >= 0x3)) {
1617                 /* '11' is reserved */
1618                 spi_drctl = 0;
1619         }
1620
1621         platform_set_drvdata(pdev, master);
1622
1623         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1624         master->bus_num = np ? -1 : pdev->id;
1625         master->use_gpio_descriptors = true;
1626
1627         spi_imx = spi_master_get_devdata(master);
1628         spi_imx->bitbang.master = master;
1629         spi_imx->dev = &pdev->dev;
1630         spi_imx->slave_mode = slave_mode;
1631
1632         spi_imx->devtype_data = devtype_data;
1633
1634         /*
1635          * Get number of chip selects from device properties. This can be
1636          * coming from device tree or boardfiles, if it is not defined,
1637          * a default value of 3 chip selects will be used, as all the legacy
1638          * board files have <= 3 chip selects.
1639          */
1640         if (!device_property_read_u32(&pdev->dev, "num-cs", &val))
1641                 master->num_chipselect = val;
1642         else
1643                 master->num_chipselect = 3;
1644
1645         spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1646         spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1647         spi_imx->bitbang.master->setup = spi_imx_setup;
1648         spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1649         spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1650         spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1651         spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort;
1652         spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
1653                                              | SPI_NO_CS;
1654         if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
1655             is_imx53_ecspi(spi_imx))
1656                 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
1657
1658         if (is_imx51_ecspi(spi_imx) &&
1659             device_property_read_u32(&pdev->dev, "cs-gpios", NULL))
1660                 /*
1661                  * When using HW-CS implementing SPI_CS_WORD can be done by just
1662                  * setting the burst length to the word size. This is
1663                  * considerably faster than manually controlling the CS.
1664                  */
1665                 spi_imx->bitbang.master->mode_bits |= SPI_CS_WORD;
1666
1667         spi_imx->spi_drctl = spi_drctl;
1668
1669         init_completion(&spi_imx->xfer_done);
1670
1671         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1672         spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1673         if (IS_ERR(spi_imx->base)) {
1674                 ret = PTR_ERR(spi_imx->base);
1675                 goto out_master_put;
1676         }
1677         spi_imx->base_phys = res->start;
1678
1679         irq = platform_get_irq(pdev, 0);
1680         if (irq < 0) {
1681                 ret = irq;
1682                 goto out_master_put;
1683         }
1684
1685         ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1686                                dev_name(&pdev->dev), spi_imx);
1687         if (ret) {
1688                 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1689                 goto out_master_put;
1690         }
1691
1692         spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1693         if (IS_ERR(spi_imx->clk_ipg)) {
1694                 ret = PTR_ERR(spi_imx->clk_ipg);
1695                 goto out_master_put;
1696         }
1697
1698         spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1699         if (IS_ERR(spi_imx->clk_per)) {
1700                 ret = PTR_ERR(spi_imx->clk_per);
1701                 goto out_master_put;
1702         }
1703
1704         ret = clk_prepare_enable(spi_imx->clk_per);
1705         if (ret)
1706                 goto out_master_put;
1707
1708         ret = clk_prepare_enable(spi_imx->clk_ipg);
1709         if (ret)
1710                 goto out_put_per;
1711
1712         pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT);
1713         pm_runtime_use_autosuspend(spi_imx->dev);
1714         pm_runtime_get_noresume(spi_imx->dev);
1715         pm_runtime_set_active(spi_imx->dev);
1716         pm_runtime_enable(spi_imx->dev);
1717
1718         spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1719         /*
1720          * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1721          * if validated on other chips.
1722          */
1723         if (spi_imx->devtype_data->has_dmamode) {
1724                 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1725                 if (ret == -EPROBE_DEFER)
1726                         goto out_runtime_pm_put;
1727
1728                 if (ret < 0)
1729                         dev_dbg(&pdev->dev, "dma setup error %d, use pio\n",
1730                                 ret);
1731         }
1732
1733         spi_imx->devtype_data->reset(spi_imx);
1734
1735         spi_imx->devtype_data->intctrl(spi_imx, 0);
1736
1737         master->dev.of_node = pdev->dev.of_node;
1738         ret = spi_bitbang_start(&spi_imx->bitbang);
1739         if (ret) {
1740                 dev_err_probe(&pdev->dev, ret, "bitbang start failed\n");
1741                 goto out_bitbang_start;
1742         }
1743
1744         pm_runtime_mark_last_busy(spi_imx->dev);
1745         pm_runtime_put_autosuspend(spi_imx->dev);
1746
1747         return ret;
1748
1749 out_bitbang_start:
1750         if (spi_imx->devtype_data->has_dmamode)
1751                 spi_imx_sdma_exit(spi_imx);
1752 out_runtime_pm_put:
1753         pm_runtime_dont_use_autosuspend(spi_imx->dev);
1754         pm_runtime_set_suspended(&pdev->dev);
1755         pm_runtime_disable(spi_imx->dev);
1756
1757         clk_disable_unprepare(spi_imx->clk_ipg);
1758 out_put_per:
1759         clk_disable_unprepare(spi_imx->clk_per);
1760 out_master_put:
1761         spi_master_put(master);
1762
1763         return ret;
1764 }
1765
1766 static int spi_imx_remove(struct platform_device *pdev)
1767 {
1768         struct spi_master *master = platform_get_drvdata(pdev);
1769         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1770         int ret;
1771
1772         spi_bitbang_stop(&spi_imx->bitbang);
1773
1774         ret = pm_runtime_get_sync(spi_imx->dev);
1775         if (ret < 0) {
1776                 pm_runtime_put_noidle(spi_imx->dev);
1777                 dev_err(spi_imx->dev, "failed to enable clock\n");
1778                 return ret;
1779         }
1780
1781         writel(0, spi_imx->base + MXC_CSPICTRL);
1782
1783         pm_runtime_dont_use_autosuspend(spi_imx->dev);
1784         pm_runtime_put_sync(spi_imx->dev);
1785         pm_runtime_disable(spi_imx->dev);
1786
1787         spi_imx_sdma_exit(spi_imx);
1788         spi_master_put(master);
1789
1790         return 0;
1791 }
1792
1793 static int __maybe_unused spi_imx_runtime_resume(struct device *dev)
1794 {
1795         struct spi_master *master = dev_get_drvdata(dev);
1796         struct spi_imx_data *spi_imx;
1797         int ret;
1798
1799         spi_imx = spi_master_get_devdata(master);
1800
1801         ret = clk_prepare_enable(spi_imx->clk_per);
1802         if (ret)
1803                 return ret;
1804
1805         ret = clk_prepare_enable(spi_imx->clk_ipg);
1806         if (ret) {
1807                 clk_disable_unprepare(spi_imx->clk_per);
1808                 return ret;
1809         }
1810
1811         return 0;
1812 }
1813
1814 static int __maybe_unused spi_imx_runtime_suspend(struct device *dev)
1815 {
1816         struct spi_master *master = dev_get_drvdata(dev);
1817         struct spi_imx_data *spi_imx;
1818
1819         spi_imx = spi_master_get_devdata(master);
1820
1821         clk_disable_unprepare(spi_imx->clk_per);
1822         clk_disable_unprepare(spi_imx->clk_ipg);
1823
1824         return 0;
1825 }
1826
1827 static int __maybe_unused spi_imx_suspend(struct device *dev)
1828 {
1829         pinctrl_pm_select_sleep_state(dev);
1830         return 0;
1831 }
1832
1833 static int __maybe_unused spi_imx_resume(struct device *dev)
1834 {
1835         pinctrl_pm_select_default_state(dev);
1836         return 0;
1837 }
1838
1839 static const struct dev_pm_ops imx_spi_pm = {
1840         SET_RUNTIME_PM_OPS(spi_imx_runtime_suspend,
1841                                 spi_imx_runtime_resume, NULL)
1842         SET_SYSTEM_SLEEP_PM_OPS(spi_imx_suspend, spi_imx_resume)
1843 };
1844
1845 static struct platform_driver spi_imx_driver = {
1846         .driver = {
1847                    .name = DRIVER_NAME,
1848                    .of_match_table = spi_imx_dt_ids,
1849                    .pm = &imx_spi_pm,
1850         },
1851         .probe = spi_imx_probe,
1852         .remove = spi_imx_remove,
1853 };
1854 module_platform_driver(spi_imx_driver);
1855
1856 MODULE_DESCRIPTION("i.MX SPI Controller driver");
1857 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1858 MODULE_LICENSE("GPL");
1859 MODULE_ALIAS("platform:" DRIVER_NAME);