1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
5 #include <linux/dmaengine.h>
6 #include <linux/dma-mapping.h>
7 #include <linux/dma/qcom-gpi-dma.h>
8 #include <linux/interrupt.h>
10 #include <linux/log2.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_opp.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/soc/qcom/geni-se.h>
16 #include <linux/spi/spi.h>
17 #include <linux/spinlock.h>
19 /* SPI SE specific registers and respective register fields */
20 #define SE_SPI_CPHA 0x224
23 #define SE_SPI_LOOPBACK 0x22c
24 #define LOOPBACK_ENABLE 0x1
25 #define NORMAL_MODE 0x0
26 #define LOOPBACK_MSK GENMASK(1, 0)
28 #define SE_SPI_CPOL 0x230
31 #define SE_SPI_DEMUX_OUTPUT_INV 0x24c
32 #define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0)
34 #define SE_SPI_DEMUX_SEL 0x250
35 #define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0)
37 #define SE_SPI_TRANS_CFG 0x25c
38 #define CS_TOGGLE BIT(1)
40 #define SE_SPI_WORD_LEN 0x268
41 #define WORD_LEN_MSK GENMASK(9, 0)
42 #define MIN_WORD_LEN 4
44 #define SE_SPI_TX_TRANS_LEN 0x26c
45 #define SE_SPI_RX_TRANS_LEN 0x270
46 #define TRANS_LEN_MSK GENMASK(23, 0)
48 #define SE_SPI_PRE_POST_CMD_DLY 0x274
50 #define SE_SPI_DELAY_COUNTERS 0x278
51 #define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0)
52 #define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10)
53 #define SPI_CS_CLK_DELAY_SHFT 10
55 /* M_CMD OP codes for SPI */
59 #define SPI_CS_ASSERT 8
60 #define SPI_CS_DEASSERT 9
61 #define SPI_SCK_ONLY 10
62 /* M_CMD params for SPI */
63 #define SPI_PRE_CMD_DELAY BIT(0)
64 #define TIMESTAMP_BEFORE BIT(1)
65 #define FRAGMENTATION BIT(2)
66 #define TIMESTAMP_AFTER BIT(3)
67 #define POST_CMD_DELAY BIT(4)
69 #define GSI_LOOPBACK_EN BIT(0)
70 #define GSI_CS_TOGGLE BIT(3)
71 #define GSI_CPHA BIT(4)
72 #define GSI_CPOL BIT(5)
74 struct spi_geni_master {
81 unsigned long cur_speed_hz;
82 unsigned long cur_sclk_hz;
83 unsigned int cur_bits_per_word;
84 unsigned int tx_rem_bytes;
85 unsigned int rx_rem_bytes;
86 const struct spi_transfer *cur_xfer;
87 struct completion cs_done;
88 struct completion cancel_done;
89 struct completion abort_done;
90 struct completion tx_reset_done;
91 struct completion rx_reset_done;
92 unsigned int oversampling;
102 static int get_spi_clk_cfg(unsigned int speed_hz,
103 struct spi_geni_master *mas,
104 unsigned int *clk_idx,
105 unsigned int *clk_div)
107 unsigned long sclk_freq;
108 unsigned int actual_hz;
111 ret = geni_se_clk_freq_match(&mas->se,
112 speed_hz * mas->oversampling,
113 clk_idx, &sclk_freq, false);
115 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n",
120 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz);
121 actual_hz = sclk_freq / (mas->oversampling * *clk_div);
123 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz,
124 actual_hz, sclk_freq, *clk_idx, *clk_div);
125 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq);
127 dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret);
129 mas->cur_sclk_hz = sclk_freq;
134 static void handle_se_timeout(struct spi_master *spi,
135 struct spi_message *msg)
137 struct spi_geni_master *mas = spi_master_get_devdata(spi);
138 unsigned long time_left;
139 struct geni_se *se = &mas->se;
140 const struct spi_transfer *xfer;
142 spin_lock_irq(&mas->lock);
143 reinit_completion(&mas->cancel_done);
144 if (mas->cur_xfer_mode == GENI_SE_FIFO)
145 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
147 xfer = mas->cur_xfer;
148 mas->cur_xfer = NULL;
149 geni_se_cancel_m_cmd(se);
150 spin_unlock_irq(&mas->lock);
152 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ);
156 spin_lock_irq(&mas->lock);
157 reinit_completion(&mas->abort_done);
158 geni_se_abort_m_cmd(se);
159 spin_unlock_irq(&mas->lock);
161 time_left = wait_for_completion_timeout(&mas->abort_done, HZ);
163 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n");
166 * No need for a lock since SPI core has a lock and we never
167 * access this from an interrupt.
169 mas->abort_failed = true;
173 if (mas->cur_xfer_mode == GENI_SE_DMA) {
176 spin_lock_irq(&mas->lock);
177 reinit_completion(&mas->tx_reset_done);
178 writel(1, se->base + SE_DMA_TX_FSM_RST);
179 spin_unlock_irq(&mas->lock);
180 time_left = wait_for_completion_timeout(&mas->tx_reset_done, HZ);
182 dev_err(mas->dev, "DMA TX RESET failed\n");
185 spin_lock_irq(&mas->lock);
186 reinit_completion(&mas->rx_reset_done);
187 writel(1, se->base + SE_DMA_RX_FSM_RST);
188 spin_unlock_irq(&mas->lock);
189 time_left = wait_for_completion_timeout(&mas->rx_reset_done, HZ);
191 dev_err(mas->dev, "DMA RX RESET failed\n");
195 * This can happen if a timeout happened and we had to wait
196 * for lock in this function because isr was holding the lock
197 * and handling transfer completion at that time.
199 dev_warn(mas->dev, "Cancel/Abort on completed SPI transfer\n");
204 static void handle_gpi_timeout(struct spi_master *spi, struct spi_message *msg)
206 struct spi_geni_master *mas = spi_master_get_devdata(spi);
208 dmaengine_terminate_sync(mas->tx);
209 dmaengine_terminate_sync(mas->rx);
212 static void spi_geni_handle_err(struct spi_master *spi, struct spi_message *msg)
214 struct spi_geni_master *mas = spi_master_get_devdata(spi);
216 switch (mas->cur_xfer_mode) {
219 handle_se_timeout(spi, msg);
222 handle_gpi_timeout(spi, msg);
225 dev_err(mas->dev, "Abort on Mode:%d not supported", mas->cur_xfer_mode);
229 static bool spi_geni_is_abort_still_pending(struct spi_geni_master *mas)
231 struct geni_se *se = &mas->se;
234 if (!mas->abort_failed)
238 * The only known case where a transfer times out and then a cancel
239 * times out then an abort times out is if something is blocking our
240 * interrupt handler from running. Avoid starting any new transfers
241 * until that sorts itself out.
243 spin_lock_irq(&mas->lock);
244 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
245 m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN);
246 spin_unlock_irq(&mas->lock);
248 if (m_irq & m_irq_en) {
249 dev_err(mas->dev, "Interrupts pending after abort: %#010x\n",
255 * If we're here the problem resolved itself so no need to check more
256 * on future transfers.
258 mas->abort_failed = false;
263 static void spi_geni_set_cs(struct spi_device *slv, bool set_flag)
265 struct spi_geni_master *mas = spi_master_get_devdata(slv->master);
266 struct spi_master *spi = dev_get_drvdata(mas->dev);
267 struct geni_se *se = &mas->se;
268 unsigned long time_left;
270 if (!(slv->mode & SPI_CS_HIGH))
271 set_flag = !set_flag;
273 if (set_flag == mas->cs_flag)
276 pm_runtime_get_sync(mas->dev);
278 if (spi_geni_is_abort_still_pending(mas)) {
279 dev_err(mas->dev, "Can't set chip select\n");
283 spin_lock_irq(&mas->lock);
285 dev_err(mas->dev, "Can't set CS when prev xfer running\n");
286 spin_unlock_irq(&mas->lock);
290 mas->cs_flag = set_flag;
291 /* set xfer_mode to FIFO to complete cs_done in isr */
292 mas->cur_xfer_mode = GENI_SE_FIFO;
293 geni_se_select_mode(se, mas->cur_xfer_mode);
295 reinit_completion(&mas->cs_done);
297 geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0);
299 geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0);
300 spin_unlock_irq(&mas->lock);
302 time_left = wait_for_completion_timeout(&mas->cs_done, HZ);
304 dev_warn(mas->dev, "Timeout setting chip select\n");
305 handle_se_timeout(spi, NULL);
309 pm_runtime_put(mas->dev);
312 static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode,
313 unsigned int bits_per_word)
315 unsigned int pack_words;
316 bool msb_first = (mode & SPI_LSB_FIRST) ? false : true;
317 struct geni_se *se = &mas->se;
321 * If bits_per_word isn't a byte aligned value, set the packing to be
322 * 1 SPI word per FIFO word.
324 if (!(mas->fifo_width_bits % bits_per_word))
325 pack_words = mas->fifo_width_bits / bits_per_word;
328 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first,
330 word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK;
331 writel(word_len, se->base + SE_SPI_WORD_LEN);
334 static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas,
335 unsigned long clk_hz)
337 u32 clk_sel, m_clk_cfg, idx, div;
338 struct geni_se *se = &mas->se;
341 if (clk_hz == mas->cur_speed_hz)
344 ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div);
346 dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret);
351 * SPI core clock gets configured with the requested frequency
352 * or the frequency closer to the requested frequency.
353 * For that reason requested frequency is stored in the
354 * cur_speed_hz and referred in the consecutive transfer instead
355 * of calling clk_get_rate() API.
357 mas->cur_speed_hz = clk_hz;
359 clk_sel = idx & CLK_SEL_MSK;
360 m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN;
361 writel(clk_sel, se->base + SE_GENI_CLK_SEL);
362 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
364 /* Set BW quota for CPU as driver supports FIFO mode only. */
365 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz);
366 ret = geni_icc_set_bw(se);
373 static int setup_fifo_params(struct spi_device *spi_slv,
374 struct spi_master *spi)
376 struct spi_geni_master *mas = spi_master_get_devdata(spi);
377 struct geni_se *se = &mas->se;
378 u32 loopback_cfg = 0, cpol = 0, cpha = 0, demux_output_inv = 0;
381 if (mas->last_mode != spi_slv->mode) {
382 if (spi_slv->mode & SPI_LOOP)
383 loopback_cfg = LOOPBACK_ENABLE;
385 if (spi_slv->mode & SPI_CPOL)
388 if (spi_slv->mode & SPI_CPHA)
391 if (spi_slv->mode & SPI_CS_HIGH)
392 demux_output_inv = BIT(spi_get_chipselect(spi_slv, 0));
394 demux_sel = spi_get_chipselect(spi_slv, 0);
395 mas->cur_bits_per_word = spi_slv->bits_per_word;
397 spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word);
398 writel(loopback_cfg, se->base + SE_SPI_LOOPBACK);
399 writel(demux_sel, se->base + SE_SPI_DEMUX_SEL);
400 writel(cpha, se->base + SE_SPI_CPHA);
401 writel(cpol, se->base + SE_SPI_CPOL);
402 writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV);
404 mas->last_mode = spi_slv->mode;
407 return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz);
411 spi_gsi_callback_result(void *cb, const struct dmaengine_result *result)
413 struct spi_master *spi = cb;
415 spi->cur_msg->status = -EIO;
416 if (result->result != DMA_TRANS_NOERROR) {
417 dev_err(&spi->dev, "DMA txn failed: %d\n", result->result);
418 spi_finalize_current_transfer(spi);
422 if (!result->residue) {
423 spi->cur_msg->status = 0;
424 dev_dbg(&spi->dev, "DMA txn completed\n");
426 dev_err(&spi->dev, "DMA xfer has pending: %d\n", result->residue);
429 spi_finalize_current_transfer(spi);
432 static int setup_gsi_xfer(struct spi_transfer *xfer, struct spi_geni_master *mas,
433 struct spi_device *spi_slv, struct spi_master *spi)
435 unsigned long flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
436 struct dma_slave_config config = {};
437 struct gpi_spi_config peripheral = {};
438 struct dma_async_tx_descriptor *tx_desc, *rx_desc;
441 config.peripheral_config = &peripheral;
442 config.peripheral_size = sizeof(peripheral);
443 peripheral.set_config = true;
445 if (xfer->bits_per_word != mas->cur_bits_per_word ||
446 xfer->speed_hz != mas->cur_speed_hz) {
447 mas->cur_bits_per_word = xfer->bits_per_word;
448 mas->cur_speed_hz = xfer->speed_hz;
451 if (xfer->tx_buf && xfer->rx_buf) {
452 peripheral.cmd = SPI_DUPLEX;
453 } else if (xfer->tx_buf) {
454 peripheral.cmd = SPI_TX;
455 peripheral.rx_len = 0;
456 } else if (xfer->rx_buf) {
457 peripheral.cmd = SPI_RX;
458 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) {
459 peripheral.rx_len = ((xfer->len << 3) / mas->cur_bits_per_word);
461 int bytes_per_word = (mas->cur_bits_per_word / BITS_PER_BYTE) + 1;
463 peripheral.rx_len = (xfer->len / bytes_per_word);
467 peripheral.loopback_en = !!(spi_slv->mode & SPI_LOOP);
468 peripheral.clock_pol_high = !!(spi_slv->mode & SPI_CPOL);
469 peripheral.data_pol_high = !!(spi_slv->mode & SPI_CPHA);
470 peripheral.cs = spi_get_chipselect(spi_slv, 0);
471 peripheral.pack_en = true;
472 peripheral.word_len = xfer->bits_per_word - MIN_WORD_LEN;
474 ret = get_spi_clk_cfg(mas->cur_speed_hz, mas,
475 &peripheral.clk_src, &peripheral.clk_div);
477 dev_err(mas->dev, "Err in get_spi_clk_cfg() :%d\n", ret);
481 if (!xfer->cs_change) {
482 if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers))
483 peripheral.fragmentation = FRAGMENTATION;
486 if (peripheral.cmd & SPI_RX) {
487 dmaengine_slave_config(mas->rx, &config);
488 rx_desc = dmaengine_prep_slave_sg(mas->rx, xfer->rx_sg.sgl, xfer->rx_sg.nents,
489 DMA_DEV_TO_MEM, flags);
491 dev_err(mas->dev, "Err setting up rx desc\n");
497 * Prepare the TX always, even for RX or tx_buf being null, we would
498 * need TX to be prepared per GSI spec
500 dmaengine_slave_config(mas->tx, &config);
501 tx_desc = dmaengine_prep_slave_sg(mas->tx, xfer->tx_sg.sgl, xfer->tx_sg.nents,
502 DMA_MEM_TO_DEV, flags);
504 dev_err(mas->dev, "Err setting up tx desc\n");
508 tx_desc->callback_result = spi_gsi_callback_result;
509 tx_desc->callback_param = spi;
511 if (peripheral.cmd & SPI_RX)
512 dmaengine_submit(rx_desc);
513 dmaengine_submit(tx_desc);
515 if (peripheral.cmd & SPI_RX)
516 dma_async_issue_pending(mas->rx);
518 dma_async_issue_pending(mas->tx);
522 static u32 get_xfer_len_in_words(struct spi_transfer *xfer,
523 struct spi_geni_master *mas)
527 if (!(mas->cur_bits_per_word % MIN_WORD_LEN))
528 len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word;
530 len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1);
531 len &= TRANS_LEN_MSK;
536 static bool geni_can_dma(struct spi_controller *ctlr,
537 struct spi_device *slv, struct spi_transfer *xfer)
539 struct spi_geni_master *mas = spi_master_get_devdata(slv->master);
542 if (mas->cur_xfer_mode == GENI_GPI_DMA)
545 len = get_xfer_len_in_words(xfer, mas);
546 fifo_size = mas->tx_fifo_depth * mas->fifo_width_bits / mas->cur_bits_per_word;
554 static int spi_geni_prepare_message(struct spi_master *spi,
555 struct spi_message *spi_msg)
557 struct spi_geni_master *mas = spi_master_get_devdata(spi);
560 switch (mas->cur_xfer_mode) {
563 if (spi_geni_is_abort_still_pending(mas))
565 ret = setup_fifo_params(spi_msg->spi, spi);
567 dev_err(mas->dev, "Couldn't select mode %d\n", ret);
571 /* nothing to do for GPI DMA */
575 dev_err(mas->dev, "Mode not supported %d", mas->cur_xfer_mode);
579 static int spi_geni_grab_gpi_chan(struct spi_geni_master *mas)
583 mas->tx = dma_request_chan(mas->dev, "tx");
584 if (IS_ERR(mas->tx)) {
585 ret = dev_err_probe(mas->dev, PTR_ERR(mas->tx),
586 "Failed to get tx DMA ch\n");
590 mas->rx = dma_request_chan(mas->dev, "rx");
591 if (IS_ERR(mas->rx)) {
592 ret = dev_err_probe(mas->dev, PTR_ERR(mas->rx),
593 "Failed to get rx DMA ch\n");
601 dma_release_channel(mas->tx);
607 static void spi_geni_release_dma_chan(struct spi_geni_master *mas)
610 dma_release_channel(mas->rx);
615 dma_release_channel(mas->tx);
620 static int spi_geni_init(struct spi_geni_master *mas)
622 struct geni_se *se = &mas->se;
623 unsigned int proto, major, minor, ver;
624 u32 spi_tx_cfg, fifo_disable;
627 pm_runtime_get_sync(mas->dev);
629 proto = geni_se_read_proto(se);
630 if (proto != GENI_SE_SPI) {
631 dev_err(mas->dev, "Invalid proto %d\n", proto);
634 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se);
636 /* Width of Tx and Rx FIFO is same */
637 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se);
640 * Hardware programming guide suggests to configure
641 * RX FIFO RFR level to fifo_depth-2.
643 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2);
644 /* Transmit an entire FIFO worth of data per IRQ */
646 ver = geni_se_get_qup_hw_version(se);
647 major = GENI_SE_VERSION_MAJOR(ver);
648 minor = GENI_SE_VERSION_MINOR(ver);
650 if (major == 1 && minor == 0)
651 mas->oversampling = 2;
653 mas->oversampling = 1;
655 fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE;
656 switch (fifo_disable) {
658 ret = spi_geni_grab_gpi_chan(mas);
659 if (!ret) { /* success case */
660 mas->cur_xfer_mode = GENI_GPI_DMA;
661 geni_se_select_mode(se, GENI_GPI_DMA);
662 dev_dbg(mas->dev, "Using GPI DMA mode for SPI\n");
664 } else if (ret == -EPROBE_DEFER) {
668 * in case of failure to get gpi dma channel, we can still do the
669 * FIFO mode, so fallthrough
671 dev_warn(mas->dev, "FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode\n");
675 mas->cur_xfer_mode = GENI_SE_FIFO;
676 geni_se_select_mode(se, GENI_SE_FIFO);
681 /* We always control CS manually */
682 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);
683 spi_tx_cfg &= ~CS_TOGGLE;
684 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);
687 pm_runtime_put(mas->dev);
691 static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas)
694 * Calculate how many bytes we'll put in each FIFO word. If the
695 * transfer words don't pack cleanly into a FIFO word we'll just put
696 * one transfer word in each FIFO word. If they do pack we'll pack 'em.
698 if (mas->fifo_width_bits % mas->cur_bits_per_word)
699 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word,
702 return mas->fifo_width_bits / BITS_PER_BYTE;
705 static bool geni_spi_handle_tx(struct spi_geni_master *mas)
707 struct geni_se *se = &mas->se;
708 unsigned int max_bytes;
710 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
713 /* Stop the watermark IRQ if nothing to send */
714 if (!mas->cur_xfer) {
715 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
719 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word;
720 if (mas->tx_rem_bytes < max_bytes)
721 max_bytes = mas->tx_rem_bytes;
723 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes;
724 while (i < max_bytes) {
726 unsigned int bytes_to_write;
728 u8 *fifo_byte = (u8 *)&fifo_word;
730 bytes_to_write = min(bytes_per_fifo_word, max_bytes - i);
731 for (j = 0; j < bytes_to_write; j++)
732 fifo_byte[j] = tx_buf[i++];
733 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1);
735 mas->tx_rem_bytes -= max_bytes;
736 if (!mas->tx_rem_bytes) {
737 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
743 static void geni_spi_handle_rx(struct spi_geni_master *mas)
745 struct geni_se *se = &mas->se;
747 unsigned int rx_bytes;
748 unsigned int rx_last_byte_valid;
750 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
753 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS);
754 rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word;
755 if (rx_fifo_status & RX_LAST) {
756 rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK;
757 rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT;
758 if (rx_last_byte_valid && rx_last_byte_valid < 4)
759 rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid;
762 /* Clear out the FIFO and bail if nowhere to put it */
763 if (!mas->cur_xfer) {
764 for (i = 0; i < DIV_ROUND_UP(rx_bytes, bytes_per_fifo_word); i++)
765 readl(se->base + SE_GENI_RX_FIFOn);
769 if (mas->rx_rem_bytes < rx_bytes)
770 rx_bytes = mas->rx_rem_bytes;
772 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes;
773 while (i < rx_bytes) {
775 u8 *fifo_byte = (u8 *)&fifo_word;
776 unsigned int bytes_to_read;
779 bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i);
780 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1);
781 for (j = 0; j < bytes_to_read; j++)
782 rx_buf[i++] = fifo_byte[j];
784 mas->rx_rem_bytes -= rx_bytes;
787 static int setup_se_xfer(struct spi_transfer *xfer,
788 struct spi_geni_master *mas,
789 u16 mode, struct spi_master *spi)
793 struct geni_se *se = &mas->se;
797 * Ensure that our interrupt handler isn't still running from some
798 * prior command before we start messing with the hardware behind
799 * its back. We don't need to _keep_ the lock here since we're only
800 * worried about racing with out interrupt handler. The SPI core
801 * already handles making sure that we're not trying to do two
802 * transfers at once or setting a chip select and doing a transfer
805 * NOTE: we actually _can't_ hold the lock here because possibly we
806 * might call clk_set_rate() which needs to be able to sleep.
808 spin_lock_irq(&mas->lock);
809 spin_unlock_irq(&mas->lock);
811 if (xfer->bits_per_word != mas->cur_bits_per_word) {
812 spi_setup_word_len(mas, mode, xfer->bits_per_word);
813 mas->cur_bits_per_word = xfer->bits_per_word;
816 /* Speed and bits per word can be overridden per transfer */
817 ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz);
821 mas->tx_rem_bytes = 0;
822 mas->rx_rem_bytes = 0;
824 len = get_xfer_len_in_words(xfer, mas);
826 mas->cur_xfer = xfer;
828 m_cmd |= SPI_TX_ONLY;
829 mas->tx_rem_bytes = xfer->len;
830 writel(len, se->base + SE_SPI_TX_TRANS_LEN);
834 m_cmd |= SPI_RX_ONLY;
835 writel(len, se->base + SE_SPI_RX_TRANS_LEN);
836 mas->rx_rem_bytes = xfer->len;
840 * Select DMA mode if sgt are present; and with only 1 entry
841 * This is not a serious limitation because the xfer buffers are
842 * expected to fit into in 1 entry almost always, and if any
843 * doesn't for any reason we fall back to FIFO mode anyway
845 if (!xfer->tx_sg.nents && !xfer->rx_sg.nents)
846 mas->cur_xfer_mode = GENI_SE_FIFO;
847 else if (xfer->tx_sg.nents > 1 || xfer->rx_sg.nents > 1) {
848 dev_warn_once(mas->dev, "Doing FIFO, cannot handle tx_nents-%d, rx_nents-%d\n",
849 xfer->tx_sg.nents, xfer->rx_sg.nents);
850 mas->cur_xfer_mode = GENI_SE_FIFO;
852 mas->cur_xfer_mode = GENI_SE_DMA;
853 geni_se_select_mode(se, mas->cur_xfer_mode);
856 * Lock around right before we start the transfer since our
857 * interrupt could come in at any time now.
859 spin_lock_irq(&mas->lock);
860 geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION);
862 if (mas->cur_xfer_mode == GENI_SE_DMA) {
863 if (m_cmd & SPI_RX_ONLY)
864 geni_se_rx_init_dma(se, sg_dma_address(xfer->rx_sg.sgl),
865 sg_dma_len(xfer->rx_sg.sgl));
866 if (m_cmd & SPI_TX_ONLY)
867 geni_se_tx_init_dma(se, sg_dma_address(xfer->tx_sg.sgl),
868 sg_dma_len(xfer->tx_sg.sgl));
869 } else if (m_cmd & SPI_TX_ONLY) {
870 if (geni_spi_handle_tx(mas))
871 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG);
874 spin_unlock_irq(&mas->lock);
878 static int spi_geni_transfer_one(struct spi_master *spi,
879 struct spi_device *slv,
880 struct spi_transfer *xfer)
882 struct spi_geni_master *mas = spi_master_get_devdata(spi);
885 if (spi_geni_is_abort_still_pending(mas))
888 /* Terminate and return success for 0 byte length transfer */
892 if (mas->cur_xfer_mode == GENI_SE_FIFO || mas->cur_xfer_mode == GENI_SE_DMA) {
893 ret = setup_se_xfer(xfer, mas, slv->mode, spi);
894 /* SPI framework expects +ve ret code to wait for transfer complete */
899 return setup_gsi_xfer(xfer, mas, slv, spi);
902 static irqreturn_t geni_spi_isr(int irq, void *data)
904 struct spi_master *spi = data;
905 struct spi_geni_master *mas = spi_master_get_devdata(spi);
906 struct geni_se *se = &mas->se;
909 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
913 if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |
914 M_RX_FIFO_RD_ERR_EN | M_RX_FIFO_WR_ERR_EN |
915 M_TX_FIFO_RD_ERR_EN | M_TX_FIFO_WR_ERR_EN))
916 dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq);
918 spin_lock(&mas->lock);
920 if (mas->cur_xfer_mode == GENI_SE_FIFO) {
921 if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN))
922 geni_spi_handle_rx(mas);
924 if (m_irq & M_TX_FIFO_WATERMARK_EN)
925 geni_spi_handle_tx(mas);
927 if (m_irq & M_CMD_DONE_EN) {
929 spi_finalize_current_transfer(spi);
930 mas->cur_xfer = NULL;
932 * If this happens, then a CMD_DONE came before all the
933 * Tx buffer bytes were sent out. This is unusual, log
934 * this condition and disable the WM interrupt to
935 * prevent the system from stalling due an interrupt
938 * If this happens when all Rx bytes haven't been
939 * received, log the condition. The only known time
940 * this can happen is if bits_per_word != 8 and some
941 * registers that expect xfer lengths in num spi_words
942 * weren't written correctly.
944 if (mas->tx_rem_bytes) {
945 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
946 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n",
947 mas->tx_rem_bytes, mas->cur_bits_per_word);
949 if (mas->rx_rem_bytes)
950 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n",
951 mas->rx_rem_bytes, mas->cur_bits_per_word);
953 complete(&mas->cs_done);
956 } else if (mas->cur_xfer_mode == GENI_SE_DMA) {
957 const struct spi_transfer *xfer = mas->cur_xfer;
958 u32 dma_tx_status = readl_relaxed(se->base + SE_DMA_TX_IRQ_STAT);
959 u32 dma_rx_status = readl_relaxed(se->base + SE_DMA_RX_IRQ_STAT);
962 writel(dma_tx_status, se->base + SE_DMA_TX_IRQ_CLR);
964 writel(dma_rx_status, se->base + SE_DMA_RX_IRQ_CLR);
965 if (dma_tx_status & TX_DMA_DONE)
966 mas->tx_rem_bytes = 0;
967 if (dma_rx_status & RX_DMA_DONE)
968 mas->rx_rem_bytes = 0;
969 if (dma_tx_status & TX_RESET_DONE)
970 complete(&mas->tx_reset_done);
971 if (dma_rx_status & RX_RESET_DONE)
972 complete(&mas->rx_reset_done);
973 if (!mas->tx_rem_bytes && !mas->rx_rem_bytes && xfer) {
974 spi_finalize_current_transfer(spi);
975 mas->cur_xfer = NULL;
979 if (m_irq & M_CMD_CANCEL_EN)
980 complete(&mas->cancel_done);
981 if (m_irq & M_CMD_ABORT_EN)
982 complete(&mas->abort_done);
985 * It's safe or a good idea to Ack all of our interrupts at the end
986 * of the function. Specifically:
987 * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and
988 * clearing Acks. Clearing at the end relies on nobody else having
989 * started a new transfer yet or else we could be clearing _their_
990 * done bit, but everyone grabs the spinlock before starting a new
992 * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear
993 * to be "latched level" interrupts so it's important to clear them
994 * _after_ you've handled the condition and always safe to do so
995 * since they'll re-assert if they're still happening.
997 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR);
999 spin_unlock(&mas->lock);
1004 static int spi_geni_probe(struct platform_device *pdev)
1007 struct spi_master *spi;
1008 struct spi_geni_master *mas;
1011 struct device *dev = &pdev->dev;
1013 irq = platform_get_irq(pdev, 0);
1017 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
1019 return dev_err_probe(dev, ret, "could not set DMA mask\n");
1021 base = devm_platform_ioremap_resource(pdev, 0);
1023 return PTR_ERR(base);
1025 clk = devm_clk_get(dev, "se");
1027 return PTR_ERR(clk);
1029 spi = devm_spi_alloc_master(dev, sizeof(*mas));
1033 platform_set_drvdata(pdev, spi);
1034 mas = spi_master_get_devdata(spi);
1038 mas->se.wrapper = dev_get_drvdata(dev->parent);
1039 mas->se.base = base;
1042 ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
1045 /* OPP table is optional */
1046 ret = devm_pm_opp_of_add_table(&pdev->dev);
1047 if (ret && ret != -ENODEV) {
1048 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1053 spi->dev.of_node = dev->of_node;
1054 spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH;
1055 spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1056 spi->num_chipselect = 4;
1057 spi->max_speed_hz = 50000000;
1058 spi->max_dma_len = 0xffff0; /* 24 bits for tx/rx dma length */
1059 spi->prepare_message = spi_geni_prepare_message;
1060 spi->transfer_one = spi_geni_transfer_one;
1061 spi->can_dma = geni_can_dma;
1062 spi->dma_map_dev = dev->parent;
1063 spi->auto_runtime_pm = true;
1064 spi->handle_err = spi_geni_handle_err;
1065 spi->use_gpio_descriptors = true;
1067 init_completion(&mas->cs_done);
1068 init_completion(&mas->cancel_done);
1069 init_completion(&mas->abort_done);
1070 init_completion(&mas->tx_reset_done);
1071 init_completion(&mas->rx_reset_done);
1072 spin_lock_init(&mas->lock);
1073 pm_runtime_use_autosuspend(&pdev->dev);
1074 pm_runtime_set_autosuspend_delay(&pdev->dev, 250);
1075 pm_runtime_enable(dev);
1077 ret = geni_icc_get(&mas->se, NULL);
1079 goto spi_geni_probe_runtime_disable;
1080 /* Set the bus quota to a reasonable value for register access */
1081 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ);
1082 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1084 ret = geni_icc_set_bw(&mas->se);
1086 goto spi_geni_probe_runtime_disable;
1088 ret = spi_geni_init(mas);
1090 goto spi_geni_probe_runtime_disable;
1093 * check the mode supported and set_cs for fifo mode only
1094 * for dma (gsi) mode, the gsi will set cs based on params passed in
1097 if (mas->cur_xfer_mode == GENI_SE_FIFO)
1098 spi->set_cs = spi_geni_set_cs;
1100 ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi);
1102 goto spi_geni_release_dma;
1104 ret = spi_register_master(spi);
1106 goto spi_geni_probe_free_irq;
1109 spi_geni_probe_free_irq:
1110 free_irq(mas->irq, spi);
1111 spi_geni_release_dma:
1112 spi_geni_release_dma_chan(mas);
1113 spi_geni_probe_runtime_disable:
1114 pm_runtime_disable(dev);
1118 static void spi_geni_remove(struct platform_device *pdev)
1120 struct spi_master *spi = platform_get_drvdata(pdev);
1121 struct spi_geni_master *mas = spi_master_get_devdata(spi);
1123 /* Unregister _before_ disabling pm_runtime() so we stop transfers */
1124 spi_unregister_master(spi);
1126 spi_geni_release_dma_chan(mas);
1128 free_irq(mas->irq, spi);
1129 pm_runtime_disable(&pdev->dev);
1132 static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
1134 struct spi_master *spi = dev_get_drvdata(dev);
1135 struct spi_geni_master *mas = spi_master_get_devdata(spi);
1138 /* Drop the performance state vote */
1139 dev_pm_opp_set_rate(dev, 0);
1141 ret = geni_se_resources_off(&mas->se);
1145 return geni_icc_disable(&mas->se);
1148 static int __maybe_unused spi_geni_runtime_resume(struct device *dev)
1150 struct spi_master *spi = dev_get_drvdata(dev);
1151 struct spi_geni_master *mas = spi_master_get_devdata(spi);
1154 ret = geni_icc_enable(&mas->se);
1158 ret = geni_se_resources_on(&mas->se);
1162 return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz);
1165 static int __maybe_unused spi_geni_suspend(struct device *dev)
1167 struct spi_master *spi = dev_get_drvdata(dev);
1170 ret = spi_master_suspend(spi);
1174 ret = pm_runtime_force_suspend(dev);
1176 spi_master_resume(spi);
1181 static int __maybe_unused spi_geni_resume(struct device *dev)
1183 struct spi_master *spi = dev_get_drvdata(dev);
1186 ret = pm_runtime_force_resume(dev);
1190 ret = spi_master_resume(spi);
1192 pm_runtime_force_suspend(dev);
1197 static const struct dev_pm_ops spi_geni_pm_ops = {
1198 SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend,
1199 spi_geni_runtime_resume, NULL)
1200 SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume)
1203 static const struct of_device_id spi_geni_dt_match[] = {
1204 { .compatible = "qcom,geni-spi" },
1207 MODULE_DEVICE_TABLE(of, spi_geni_dt_match);
1209 static struct platform_driver spi_geni_driver = {
1210 .probe = spi_geni_probe,
1211 .remove_new = spi_geni_remove,
1214 .pm = &spi_geni_pm_ops,
1215 .of_match_table = spi_geni_dt_match,
1218 module_platform_driver(spi_geni_driver);
1220 MODULE_DESCRIPTION("SPI driver for GENI based QUP cores");
1221 MODULE_LICENSE("GPL v2");