drivers/spi/spi-fsl-spi.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Freescale SPI controller driver.
   4  *
   5  * Maintainer: Kumar Gala
   6  *
   7  * Copyright (C) 2006 Polycom, Inc.
   8  * Copyright 2010 Freescale Semiconductor, Inc.
   9  *
  10  * CPM SPI and QE buffer descriptors mode support:
  11  * Copyright (c) 2009  MontaVista Software, Inc.
  12  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
  13  *
  14  * GRLIB support:
  15  * Copyright (c) 2012 Aeroflex Gaisler AB.
  16  * Author: Andreas Larsson <andreas@gaisler.com>
  17  */
  18 #include <linux/delay.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/fsl_devices.h>
  21 #include <linux/gpio.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/module.h>
  27 #include <linux/mutex.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_gpio.h>
  32 #include <linux/of_platform.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/spi/spi.h>
  35 #include <linux/spi/spi_bitbang.h>
  36 #include <linux/types.h>
  37
  38 #ifdef CONFIG_FSL_SOC
  39 #include <sysdev/fsl_soc.h>
  40 #endif
  41
  42 /* Specific to the MPC8306/MPC8309 */
  43 #define IMMR_SPI_CS_OFFSET 0x14c
  44 #define SPI_BOOT_SEL_BIT   0x80000000
  45
  46 #include "spi-fsl-lib.h"
  47 #include "spi-fsl-cpm.h"
  48 #include "spi-fsl-spi.h"
  49
  50 #define TYPE_FSL        0
  51 #define TYPE_GRLIB      1
  52
  53 struct fsl_spi_match_data {
  54         int type;
  55 };
  56
  57 static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
  58         .type = TYPE_FSL,
  59 };
  60
  61 static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
  62         .type = TYPE_GRLIB,
  63 };
  64
  65 static const struct of_device_id of_fsl_spi_match[] = {
  66         {
  67                 .compatible = "fsl,spi",
  68                 .data = &of_fsl_spi_fsl_config,
  69         },
  70         {
  71                 .compatible = "aeroflexgaisler,spictrl",
  72                 .data = &of_fsl_spi_grlib_config,
  73         },
  74         {}
  75 };
  76 MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
  77
  78 static int fsl_spi_get_type(struct device *dev)
  79 {
  80         const struct of_device_id *match;
  81
  82         if (dev->of_node) {
  83                 match = of_match_node(of_fsl_spi_match, dev->of_node);
  84                 if (match && match->data)
  85                         return ((struct fsl_spi_match_data *)match->data)->type;
  86         }
  87         return TYPE_FSL;
  88 }
  89
  90 static void fsl_spi_change_mode(struct spi_device *spi)
  91 {
  92         struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
  93         struct spi_mpc8xxx_cs *cs = spi->controller_state;
  94         struct fsl_spi_reg *reg_base = mspi->reg_base;
  95         __be32 __iomem *mode = &reg_base->mode;
  96         unsigned long flags;
  97
  98         if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
  99                 return;
 100
 101         /* Turn off IRQs locally to minimize time that SPI is disabled. */
 102         local_irq_save(flags);
 103
 104         /* Turn off SPI unit prior changing mode */
 105         mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
 106
 107         /* When in CPM mode, we need to reinit tx and rx. */
 108         if (mspi->flags & SPI_CPM_MODE) {
 109                 fsl_spi_cpm_reinit_txrx(mspi);
 110         }
 111         mpc8xxx_spi_write_reg(mode, cs->hw_mode);
 112         local_irq_restore(flags);
 113 }
 114
 115 static void fsl_spi_chipselect(struct spi_device *spi, int value)
 116 {
 117         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 118         struct fsl_spi_platform_data *pdata;
 119         bool pol = spi->mode & SPI_CS_HIGH;
 120         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 121
 122         pdata = spi->dev.parent->parent->platform_data;
 123
 124         if (value == BITBANG_CS_INACTIVE) {
 125                 if (pdata->cs_control)
 126                         pdata->cs_control(spi, !pol);
 127         }
 128
 129         if (value == BITBANG_CS_ACTIVE) {
 130                 mpc8xxx_spi->rx_shift = cs->rx_shift;
 131                 mpc8xxx_spi->tx_shift = cs->tx_shift;
 132                 mpc8xxx_spi->get_rx = cs->get_rx;
 133                 mpc8xxx_spi->get_tx = cs->get_tx;
 134
 135                 fsl_spi_change_mode(spi);
 136
 137                 if (pdata->cs_control)
 138                         pdata->cs_control(spi, pol);
 139         }
 140 }
 141
 142 static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
 143                                       int bits_per_word, int msb_first)
 144 {
 145         *rx_shift = 0;
 146         *tx_shift = 0;
 147         if (msb_first) {
 148                 if (bits_per_word <= 8) {
 149                         *rx_shift = 16;
 150                         *tx_shift = 24;
 151                 } else if (bits_per_word <= 16) {
 152                         *rx_shift = 16;
 153                         *tx_shift = 16;
 154                 }
 155         } else {
 156                 if (bits_per_word <= 8)
 157                         *rx_shift = 8;
 158         }
 159 }
 160
 161 static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
 162                                      int bits_per_word, int msb_first)
 163 {
 164         *rx_shift = 0;
 165         *tx_shift = 0;
 166         if (bits_per_word <= 16) {
 167                 if (msb_first) {
 168                         *rx_shift = 16; /* LSB in bit 16 */
 169                         *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */
 170                 } else {
 171                         *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */
 172                 }
 173         }
 174 }
 175
 176 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
 177                                 struct spi_device *spi,
 178                                 struct mpc8xxx_spi *mpc8xxx_spi,
 179                                 int bits_per_word)
 180 {
 181         cs->rx_shift = 0;
 182         cs->tx_shift = 0;
 183         if (bits_per_word <= 8) {
 184                 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
 185                 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
 186         } else if (bits_per_word <= 16) {
 187                 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
 188                 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
 189         } else if (bits_per_word <= 32) {
 190                 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
 191                 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
 192         } else
 193                 return -EINVAL;
 194
 195         if (mpc8xxx_spi->set_shifts)
 196                 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
 197                                         bits_per_word,
 198                                         !(spi->mode & SPI_LSB_FIRST));
 199
 200         mpc8xxx_spi->rx_shift = cs->rx_shift;
 201         mpc8xxx_spi->tx_shift = cs->tx_shift;
 202         mpc8xxx_spi->get_rx = cs->get_rx;
 203         mpc8xxx_spi->get_tx = cs->get_tx;
 204
 205         return bits_per_word;
 206 }
 207
 208 static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
 209                                 struct spi_device *spi,
 210                                 int bits_per_word)
 211 {
 212         /* QE uses Little Endian for words > 8
 213          * so transform all words > 8 into 8 bits
 214          * Unfortnatly that doesn't work for LSB so
 215          * reject these for now */
 216         /* Note: 32 bits word, LSB works iff
 217          * tfcr/rfcr is set to CPMFCR_GBL */
 218         if (spi->mode & SPI_LSB_FIRST &&
 219             bits_per_word > 8)
 220                 return -EINVAL;
 221         if (bits_per_word > 8)
 222                 return 8; /* pretend its 8 bits */
 223         return bits_per_word;
 224 }
 225
 226 static int fsl_spi_setup_transfer(struct spi_device *spi,
 227                                         struct spi_transfer *t)
 228 {
 229         struct mpc8xxx_spi *mpc8xxx_spi;
 230         int bits_per_word = 0;
 231         u8 pm;
 232         u32 hz = 0;
 233         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 234
 235         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 236
 237         if (t) {
 238                 bits_per_word = t->bits_per_word;
 239                 hz = t->speed_hz;
 240         }
 241
 242         /* spi_transfer level calls that work per-word */
 243         if (!bits_per_word)
 244                 bits_per_word = spi->bits_per_word;
 245
 246         if (!hz)
 247                 hz = spi->max_speed_hz;
 248
 249         if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
 250                 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
 251                                                            mpc8xxx_spi,
 252                                                            bits_per_word);
 253         else if (mpc8xxx_spi->flags & SPI_QE)
 254                 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
 255                                                           bits_per_word);
 256
 257         if (bits_per_word < 0)
 258                 return bits_per_word;
 259
 260         if (bits_per_word == 32)
 261                 bits_per_word = 0;
 262         else
 263                 bits_per_word = bits_per_word - 1;
 264
 265         /* mask out bits we are going to set */
 266         cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
 267                                   | SPMODE_PM(0xF));
 268
 269         cs->hw_mode |= SPMODE_LEN(bits_per_word);
 270
 271         if ((mpc8xxx_spi->spibrg / hz) > 64) {
 272                 cs->hw_mode |= SPMODE_DIV16;
 273                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
 274                 WARN_ONCE(pm > 16,
 275                           "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n",
 276                           dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024);
 277                 if (pm > 16)
 278                         pm = 16;
 279         } else {
 280                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
 281         }
 282         if (pm)
 283                 pm--;
 284
 285         cs->hw_mode |= SPMODE_PM(pm);
 286
 287         fsl_spi_change_mode(spi);
 288         return 0;
 289 }
 290
 291 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
 292                                 struct spi_transfer *t, unsigned int len)
 293 {
 294         u32 word;
 295         struct fsl_spi_reg *reg_base = mspi->reg_base;
 296
 297         mspi->count = len;
 298
 299         /* enable rx ints */
 300         mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
 301
 302         /* transmit word */
 303         word = mspi->get_tx(mspi);
 304         mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 305
 306         return 0;
 307 }
 308
 309 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
 310                             bool is_dma_mapped)
 311 {
 312         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 313         struct fsl_spi_reg *reg_base;
 314         unsigned int len = t->len;
 315         u8 bits_per_word;
 316         int ret;
 317
 318         reg_base = mpc8xxx_spi->reg_base;
 319         bits_per_word = spi->bits_per_word;
 320         if (t->bits_per_word)
 321                 bits_per_word = t->bits_per_word;
 322
 323         if (bits_per_word > 8) {
 324                 /* invalid length? */
 325                 if (len & 1)
 326                         return -EINVAL;
 327                 len /= 2;
 328         }
 329         if (bits_per_word > 16) {
 330                 /* invalid length? */
 331                 if (len & 1)
 332                         return -EINVAL;
 333                 len /= 2;
 334         }
 335
 336         mpc8xxx_spi->tx = t->tx_buf;
 337         mpc8xxx_spi->rx = t->rx_buf;
 338
 339         reinit_completion(&mpc8xxx_spi->done);
 340
 341         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 342                 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
 343         else
 344                 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
 345         if (ret)
 346                 return ret;
 347
 348         wait_for_completion(&mpc8xxx_spi->done);
 349
 350         /* disable rx ints */
 351         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 352
 353         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 354                 fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
 355
 356         return mpc8xxx_spi->count;
 357 }
 358
 359 static int fsl_spi_do_one_msg(struct spi_master *master,
 360                               struct spi_message *m)
 361 {
 362         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 363         struct spi_device *spi = m->spi;
 364         struct spi_transfer *t, *first;
 365         unsigned int cs_change;
 366         const int nsecs = 50;
 367         int status, last_bpw;
 368
 369         /*
 370          * In CPU mode, optimize large byte transfers to use larger
 371          * bits_per_word values to reduce number of interrupts taken.
 372          */
 373         if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
 374                 list_for_each_entry(t, &m->transfers, transfer_list) {
 375                         if (t->len < 256 || t->bits_per_word != 8)
 376                                 continue;
 377                         if ((t->len & 3) == 0)
 378                                 t->bits_per_word = 32;
 379                         else if ((t->len & 1) == 0)
 380                                 t->bits_per_word = 16;
 381                 }
 382         }
 383
 384         /* Don't allow changes if CS is active */
 385         cs_change = 1;
 386         list_for_each_entry(t, &m->transfers, transfer_list) {
 387                 if (cs_change)
 388                         first = t;
 389                 cs_change = t->cs_change;
 390                 if (first->speed_hz != t->speed_hz) {
 391                         dev_err(&spi->dev,
 392                                 "speed_hz cannot change while CS is active\n");
 393                         return -EINVAL;
 394                 }
 395         }
 396
 397         last_bpw = -1;
 398         cs_change = 1;
 399         status = -EINVAL;
 400         list_for_each_entry(t, &m->transfers, transfer_list) {
 401                 if (cs_change || last_bpw != t->bits_per_word)
 402                         status = fsl_spi_setup_transfer(spi, t);
 403                 if (status < 0)
 404                         break;
 405                 last_bpw = t->bits_per_word;
 406
 407                 if (cs_change) {
 408                         fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
 409                         ndelay(nsecs);
 410                 }
 411                 cs_change = t->cs_change;
 412                 if (t->len)
 413                         status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
 414                 if (status) {
 415                         status = -EMSGSIZE;
 416                         break;
 417                 }
 418                 m->actual_length += t->len;
 419
 420                 if (t->delay_usecs)
 421                         udelay(t->delay_usecs);
 422
 423                 if (cs_change) {
 424                         ndelay(nsecs);
 425                         fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 426                         ndelay(nsecs);
 427                 }
 428         }
 429
 430         m->status = status;
 431
 432         if (status || !cs_change) {
 433                 ndelay(nsecs);
 434                 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 435         }
 436
 437         fsl_spi_setup_transfer(spi, NULL);
 438         spi_finalize_current_message(master);
 439         return 0;
 440 }
 441
 442 static int fsl_spi_setup(struct spi_device *spi)
 443 {
 444         struct mpc8xxx_spi *mpc8xxx_spi;
 445         struct fsl_spi_reg *reg_base;
 446         int retval;
 447         u32 hw_mode;
 448         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
 449
 450         if (!spi->max_speed_hz)
 451                 return -EINVAL;
 452
 453         if (!cs) {
 454                 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 455                 if (!cs)
 456                         return -ENOMEM;
 457                 spi_set_ctldata(spi, cs);
 458         }
 459         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 460
 461         reg_base = mpc8xxx_spi->reg_base;
 462
 463         hw_mode = cs->hw_mode; /* Save original settings */
 464         cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
 465         /* mask out bits we are going to set */
 466         cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
 467                          | SPMODE_REV | SPMODE_LOOP);
 468
 469         if (spi->mode & SPI_CPHA)
 470                 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
 471         if (spi->mode & SPI_CPOL)
 472                 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
 473         if (!(spi->mode & SPI_LSB_FIRST))
 474                 cs->hw_mode |= SPMODE_REV;
 475         if (spi->mode & SPI_LOOP)
 476                 cs->hw_mode |= SPMODE_LOOP;
 477
 478         retval = fsl_spi_setup_transfer(spi, NULL);
 479         if (retval < 0) {
 480                 cs->hw_mode = hw_mode; /* Restore settings */
 481                 return retval;
 482         }
 483
 484         if (mpc8xxx_spi->type == TYPE_GRLIB) {
 485                 if (gpio_is_valid(spi->cs_gpio)) {
 486                         int desel;
 487
 488                         retval = gpio_request(spi->cs_gpio,
 489                                               dev_name(&spi->dev));
 490                         if (retval)
 491                                 return retval;
 492
 493                         desel = !(spi->mode & SPI_CS_HIGH);
 494                         retval = gpio_direction_output(spi->cs_gpio, desel);
 495                         if (retval) {
 496                                 gpio_free(spi->cs_gpio);
 497                                 return retval;
 498                         }
 499                 } else if (spi->cs_gpio != -ENOENT) {
 500                         if (spi->cs_gpio < 0)
 501                                 return spi->cs_gpio;
 502                         return -EINVAL;
 503                 }
 504                 /* When spi->cs_gpio == -ENOENT, a hole in the phandle list
 505                  * indicates to use native chipselect if present, or allow for
 506                  * an always selected chip
 507                  */
 508         }
 509
 510         /* Initialize chipselect - might be active for SPI_CS_HIGH mode */
 511         fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 512
 513         return 0;
 514 }
 515
 516 static void fsl_spi_cleanup(struct spi_device *spi)
 517 {
 518         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 519         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
 520
 521         if (mpc8xxx_spi->type == TYPE_GRLIB && gpio_is_valid(spi->cs_gpio))
 522                 gpio_free(spi->cs_gpio);
 523
 524         kfree(cs);
 525         spi_set_ctldata(spi, NULL);
 526 }
 527
 528 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
 529 {
 530         struct fsl_spi_reg *reg_base = mspi->reg_base;
 531
 532         /* We need handle RX first */
 533         if (events & SPIE_NE) {
 534                 u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
 535
 536                 if (mspi->rx)
 537                         mspi->get_rx(rx_data, mspi);
 538         }
 539
 540         if ((events & SPIE_NF) == 0)
 541                 /* spin until TX is done */
 542                 while (((events =
 543                         mpc8xxx_spi_read_reg(&reg_base->event)) &
 544                                                 SPIE_NF) == 0)
 545                         cpu_relax();
 546
 547         /* Clear the events */
 548         mpc8xxx_spi_write_reg(&reg_base->event, events);
 549
 550         mspi->count -= 1;
 551         if (mspi->count) {
 552                 u32 word = mspi->get_tx(mspi);
 553
 554                 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 555         } else {
 556                 complete(&mspi->done);
 557         }
 558 }
 559
 560 static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
 561 {
 562         struct mpc8xxx_spi *mspi = context_data;
 563         irqreturn_t ret = IRQ_NONE;
 564         u32 events;
 565         struct fsl_spi_reg *reg_base = mspi->reg_base;
 566
 567         /* Get interrupt events(tx/rx) */
 568         events = mpc8xxx_spi_read_reg(&reg_base->event);
 569         if (events)
 570                 ret = IRQ_HANDLED;
 571
 572         dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
 573
 574         if (mspi->flags & SPI_CPM_MODE)
 575                 fsl_spi_cpm_irq(mspi, events);
 576         else
 577                 fsl_spi_cpu_irq(mspi, events);
 578
 579         return ret;
 580 }
 581
 582 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
 583 {
 584         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 585         struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
 586         u32 slvsel;
 587         u16 cs = spi->chip_select;
 588
 589         if (gpio_is_valid(spi->cs_gpio)) {
 590                 gpio_set_value(spi->cs_gpio, on);
 591         } else if (cs < mpc8xxx_spi->native_chipselects) {
 592                 slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);
 593                 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
 594                 mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel);
 595         }
 596 }
 597
 598 static void fsl_spi_grlib_probe(struct device *dev)
 599 {
 600         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 601         struct spi_master *master = dev_get_drvdata(dev);
 602         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 603         struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
 604         int mbits;
 605         u32 capabilities;
 606
 607         capabilities = mpc8xxx_spi_read_reg(&reg_base->cap);
 608
 609         mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
 610         mbits = SPCAP_MAXWLEN(capabilities);
 611         if (mbits)
 612                 mpc8xxx_spi->max_bits_per_word = mbits + 1;
 613
 614         mpc8xxx_spi->native_chipselects = 0;
 615         if (SPCAP_SSEN(capabilities)) {
 616                 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
 617                 mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff);
 618         }
 619         master->num_chipselect = mpc8xxx_spi->native_chipselects;
 620         pdata->cs_control = fsl_spi_grlib_cs_control;
 621 }
 622
 623 static struct spi_master * fsl_spi_probe(struct device *dev,
 624                 struct resource *mem, unsigned int irq)
 625 {
 626         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 627         struct spi_master *master;
 628         struct mpc8xxx_spi *mpc8xxx_spi;
 629         struct fsl_spi_reg *reg_base;
 630         u32 regval;
 631         int ret = 0;
 632
 633         master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
 634         if (master == NULL) {
 635                 ret = -ENOMEM;
 636                 goto err;
 637         }
 638
 639         dev_set_drvdata(dev, master);
 640
 641         mpc8xxx_spi_probe(dev, mem, irq);
 642
 643         master->setup = fsl_spi_setup;
 644         master->cleanup = fsl_spi_cleanup;
 645         master->transfer_one_message = fsl_spi_do_one_msg;
 646
 647         mpc8xxx_spi = spi_master_get_devdata(master);
 648         mpc8xxx_spi->max_bits_per_word = 32;
 649         mpc8xxx_spi->type = fsl_spi_get_type(dev);
 650
 651         ret = fsl_spi_cpm_init(mpc8xxx_spi);
 652         if (ret)
 653                 goto err_cpm_init;
 654
 655         mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
 656         if (IS_ERR(mpc8xxx_spi->reg_base)) {
 657                 ret = PTR_ERR(mpc8xxx_spi->reg_base);
 658                 goto err_probe;
 659         }
 660
 661         if (mpc8xxx_spi->type == TYPE_GRLIB)
 662                 fsl_spi_grlib_probe(dev);
 663
 664         master->bits_per_word_mask =
 665                 (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
 666                 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
 667
 668         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
 669                 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
 670
 671         if (mpc8xxx_spi->set_shifts)
 672                 /* 8 bits per word and MSB first */
 673                 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
 674                                         &mpc8xxx_spi->tx_shift, 8, 1);
 675
 676         /* Register for SPI Interrupt */
 677         ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq,
 678                                0, "fsl_spi", mpc8xxx_spi);
 679
 680         if (ret != 0)
 681                 goto err_probe;
 682
 683         reg_base = mpc8xxx_spi->reg_base;
 684
 685         /* SPI controller initializations */
 686         mpc8xxx_spi_write_reg(&reg_base->mode, 0);
 687         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 688         mpc8xxx_spi_write_reg(&reg_base->command, 0);
 689         mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
 690
 691         /* Enable SPI interface */
 692         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 693         if (mpc8xxx_spi->max_bits_per_word < 8) {
 694                 regval &= ~SPMODE_LEN(0xF);
 695                 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
 696         }
 697         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
 698                 regval |= SPMODE_OP;
 699
 700         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
 701
 702         ret = devm_spi_register_master(dev, master);
 703         if (ret < 0)
 704                 goto err_probe;
 705
 706         dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
 707                  mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
 708
 709         return master;
 710
 711 err_probe:
 712         fsl_spi_cpm_free(mpc8xxx_spi);
 713 err_cpm_init:
 714         spi_master_put(master);
 715 err:
 716         return ERR_PTR(ret);
 717 }
 718
 719 static void fsl_spi_cs_control(struct spi_device *spi, bool on)
 720 {
 721         struct device *dev = spi->dev.parent->parent;
 722         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 723         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 724         u16 cs = spi->chip_select;
 725
 726         if (cs < pinfo->ngpios) {
 727                 int gpio = pinfo->gpios[cs];
 728                 bool alow = pinfo->alow_flags[cs];
 729
 730                 gpio_set_value(gpio, on ^ alow);
 731         } else {
 732                 if (WARN_ON_ONCE(cs > pinfo->ngpios || !pinfo->immr_spi_cs))
 733                         return;
 734                 iowrite32be(on ? SPI_BOOT_SEL_BIT : 0, pinfo->immr_spi_cs);
 735         }
 736 }
 737
 738 static int of_fsl_spi_get_chipselects(struct device *dev)
 739 {
 740         struct device_node *np = dev->of_node;
 741         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 742         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 743         bool spisel_boot = IS_ENABLED(CONFIG_FSL_SOC) &&
 744                 of_property_read_bool(np, "fsl,spisel_boot");
 745         int ngpios;
 746         int i = 0;
 747         int ret;
 748
 749         ngpios = of_gpio_count(np);
 750         ngpios = max(ngpios, 0);
 751         if (ngpios == 0 && !spisel_boot) {
 752                 /*
 753                  * SPI w/o chip-select line. One SPI device is still permitted
 754                  * though.
 755                  */
 756                 pdata->max_chipselect = 1;
 757                 return 0;
 758         }
 759
 760         pinfo->ngpios = ngpios;
 761         pinfo->gpios = kmalloc_array(ngpios, sizeof(*pinfo->gpios),
 762                                      GFP_KERNEL);
 763         if (!pinfo->gpios)
 764                 return -ENOMEM;
 765         memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
 766
 767         pinfo->alow_flags = kcalloc(ngpios, sizeof(*pinfo->alow_flags),
 768                                     GFP_KERNEL);
 769         if (!pinfo->alow_flags) {
 770                 ret = -ENOMEM;
 771                 goto err_alloc_flags;
 772         }
 773
 774         for (; i < ngpios; i++) {
 775                 int gpio;
 776                 enum of_gpio_flags flags;
 777
 778                 gpio = of_get_gpio_flags(np, i, &flags);
 779                 if (!gpio_is_valid(gpio)) {
 780                         dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
 781                         ret = gpio;
 782                         goto err_loop;
 783                 }
 784
 785                 ret = gpio_request(gpio, dev_name(dev));
 786                 if (ret) {
 787                         dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
 788                         goto err_loop;
 789                 }
 790
 791                 pinfo->gpios[i] = gpio;
 792                 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
 793
 794                 ret = gpio_direction_output(pinfo->gpios[i],
 795                                             pinfo->alow_flags[i]);
 796                 if (ret) {
 797                         dev_err(dev,
 798                                 "can't set output direction for gpio #%d: %d\n",
 799                                 i, ret);
 800                         goto err_loop;
 801                 }
 802         }
 803
 804 #if IS_ENABLED(CONFIG_FSL_SOC)
 805         if (spisel_boot) {
 806                 pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4);
 807                 if (!pinfo->immr_spi_cs) {
 808                         ret = -ENOMEM;
 809                         i = ngpios - 1;
 810                         goto err_loop;
 811                 }
 812         }
 813 #endif
 814
 815         pdata->max_chipselect = ngpios + spisel_boot;
 816         pdata->cs_control = fsl_spi_cs_control;
 817
 818         return 0;
 819
 820 err_loop:
 821         while (i >= 0) {
 822                 if (gpio_is_valid(pinfo->gpios[i]))
 823                         gpio_free(pinfo->gpios[i]);
 824                 i--;
 825         }
 826
 827         kfree(pinfo->alow_flags);
 828         pinfo->alow_flags = NULL;
 829 err_alloc_flags:
 830         kfree(pinfo->gpios);
 831         pinfo->gpios = NULL;
 832         return ret;
 833 }
 834
 835 static int of_fsl_spi_free_chipselects(struct device *dev)
 836 {
 837         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 838         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 839         int i;
 840
 841         if (!pinfo->gpios)
 842                 return 0;
 843
 844         for (i = 0; i < pdata->max_chipselect; i++) {
 845                 if (gpio_is_valid(pinfo->gpios[i]))
 846                         gpio_free(pinfo->gpios[i]);
 847         }
 848
 849         kfree(pinfo->gpios);
 850         kfree(pinfo->alow_flags);
 851         return 0;
 852 }
 853
 854 static int of_fsl_spi_probe(struct platform_device *ofdev)
 855 {
 856         struct device *dev = &ofdev->dev;
 857         struct device_node *np = ofdev->dev.of_node;
 858         struct spi_master *master;
 859         struct resource mem;
 860         int irq = 0, type;
 861         int ret = -ENOMEM;
 862
 863         ret = of_mpc8xxx_spi_probe(ofdev);
 864         if (ret)
 865                 return ret;
 866
 867         type = fsl_spi_get_type(&ofdev->dev);
 868         if (type == TYPE_FSL) {
 869                 ret = of_fsl_spi_get_chipselects(dev);
 870                 if (ret)
 871                         goto err;
 872         }
 873
 874         ret = of_address_to_resource(np, 0, &mem);
 875         if (ret)
 876                 goto err;
 877
 878         irq = irq_of_parse_and_map(np, 0);
 879         if (!irq) {
 880                 ret = -EINVAL;
 881                 goto err;
 882         }
 883
 884         master = fsl_spi_probe(dev, &mem, irq);
 885         if (IS_ERR(master)) {
 886                 ret = PTR_ERR(master);
 887                 goto err;
 888         }
 889
 890         return 0;
 891
 892 err:
 893         irq_dispose_mapping(irq);
 894         if (type == TYPE_FSL)
 895                 of_fsl_spi_free_chipselects(dev);
 896         return ret;
 897 }
 898
 899 static int of_fsl_spi_remove(struct platform_device *ofdev)
 900 {
 901         struct spi_master *master = platform_get_drvdata(ofdev);
 902         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 903
 904         fsl_spi_cpm_free(mpc8xxx_spi);
 905         if (mpc8xxx_spi->type == TYPE_FSL)
 906                 of_fsl_spi_free_chipselects(&ofdev->dev);
 907         return 0;
 908 }
 909
 910 static struct platform_driver of_fsl_spi_driver = {
 911         .driver = {
 912                 .name = "fsl_spi",
 913                 .of_match_table = of_fsl_spi_match,
 914         },
 915         .probe          = of_fsl_spi_probe,
 916         .remove         = of_fsl_spi_remove,
 917 };
 918
 919 #ifdef CONFIG_MPC832x_RDB
 920 /*
 921  * XXX XXX XXX
 922  * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
 923  * only. The driver should go away soon, since newer MPC8323E-RDB's device
 924  * tree can work with OpenFirmware driver. But for now we support old trees
 925  * as well.
 926  */
 927 static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
 928 {
 929         struct resource *mem;
 930         int irq;
 931         struct spi_master *master;
 932
 933         if (!dev_get_platdata(&pdev->dev))
 934                 return -EINVAL;
 935
 936         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 937         if (!mem)
 938                 return -EINVAL;
 939
 940         irq = platform_get_irq(pdev, 0);
 941         if (irq <= 0)
 942                 return -EINVAL;
 943
 944         master = fsl_spi_probe(&pdev->dev, mem, irq);
 945         return PTR_ERR_OR_ZERO(master);
 946 }
 947
 948 static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
 949 {
 950         struct spi_master *master = platform_get_drvdata(pdev);
 951         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 952
 953         fsl_spi_cpm_free(mpc8xxx_spi);
 954
 955         return 0;
 956 }
 957
 958 MODULE_ALIAS("platform:mpc8xxx_spi");
 959 static struct platform_driver mpc8xxx_spi_driver = {
 960         .probe = plat_mpc8xxx_spi_probe,
 961         .remove = plat_mpc8xxx_spi_remove,
 962         .driver = {
 963                 .name = "mpc8xxx_spi",
 964         },
 965 };
 966
 967 static bool legacy_driver_failed;
 968
 969 static void __init legacy_driver_register(void)
 970 {
 971         legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
 972 }
 973
 974 static void __exit legacy_driver_unregister(void)
 975 {
 976         if (legacy_driver_failed)
 977                 return;
 978         platform_driver_unregister(&mpc8xxx_spi_driver);
 979 }
 980 #else
 981 static void __init legacy_driver_register(void) {}
 982 static void __exit legacy_driver_unregister(void) {}
 983 #endif /* CONFIG_MPC832x_RDB */
 984
 985 static int __init fsl_spi_init(void)
 986 {
 987         legacy_driver_register();
 988         return platform_driver_register(&of_fsl_spi_driver);
 989 }
 990 module_init(fsl_spi_init);
 991
 992 static void __exit fsl_spi_exit(void)
 993 {
 994         platform_driver_unregister(&of_fsl_spi_driver);
 995         legacy_driver_unregister();
 996 }
 997 module_exit(fsl_spi_exit);
 998
 999 MODULE_AUTHOR("Kumar Gala");
1000 MODULE_DESCRIPTION("Simple Freescale SPI Driver");
1001 MODULE_LICENSE("GPL");