drivers/spi/spi-fsl-lpspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Freescale i.MX7ULP LPSPI driver
   4 //
   5 // Copyright 2016 Freescale Semiconductor, Inc.
   6 // Copyright 2018 NXP Semiconductors
   7
   8 #include <linux/clk.h>
   9 #include <linux/completion.h>
  10 #include <linux/delay.h>
  11 #include <linux/dmaengine.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/err.h>
  14 #include <linux/gpio.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/irq.h>
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_gpio.h>
  23 #include <linux/pinctrl/consumer.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/platform_data/dma-imx.h>
  26 #include <linux/platform_data/spi-imx.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/slab.h>
  29 #include <linux/spi/spi.h>
  30 #include <linux/spi/spi_bitbang.h>
  31 #include <linux/types.h>
  32
  33 #define DRIVER_NAME "fsl_lpspi"
  34
  35 #define FSL_LPSPI_RPM_TIMEOUT 50 /* 50ms */
  36
  37 /* The maximum bytes that edma can transfer once.*/
  38 #define FSL_LPSPI_MAX_EDMA_BYTES  ((1 << 15) - 1)
  39
  40 /* i.MX7ULP LPSPI registers */
  41 #define IMX7ULP_VERID   0x0
  42 #define IMX7ULP_PARAM   0x4
  43 #define IMX7ULP_CR      0x10
  44 #define IMX7ULP_SR      0x14
  45 #define IMX7ULP_IER     0x18
  46 #define IMX7ULP_DER     0x1c
  47 #define IMX7ULP_CFGR0   0x20
  48 #define IMX7ULP_CFGR1   0x24
  49 #define IMX7ULP_DMR0    0x30
  50 #define IMX7ULP_DMR1    0x34
  51 #define IMX7ULP_CCR     0x40
  52 #define IMX7ULP_FCR     0x58
  53 #define IMX7ULP_FSR     0x5c
  54 #define IMX7ULP_TCR     0x60
  55 #define IMX7ULP_TDR     0x64
  56 #define IMX7ULP_RSR     0x70
  57 #define IMX7ULP_RDR     0x74
  58
  59 /* General control register field define */
  60 #define CR_RRF          BIT(9)
  61 #define CR_RTF          BIT(8)
  62 #define CR_RST          BIT(1)
  63 #define CR_MEN          BIT(0)
  64 #define SR_MBF          BIT(24)
  65 #define SR_TCF          BIT(10)
  66 #define SR_FCF          BIT(9)
  67 #define SR_RDF          BIT(1)
  68 #define SR_TDF          BIT(0)
  69 #define IER_TCIE        BIT(10)
  70 #define IER_FCIE        BIT(9)
  71 #define IER_RDIE        BIT(1)
  72 #define IER_TDIE        BIT(0)
  73 #define DER_RDDE        BIT(1)
  74 #define DER_TDDE        BIT(0)
  75 #define CFGR1_PCSCFG    BIT(27)
  76 #define CFGR1_PINCFG    (BIT(24)|BIT(25))
  77 #define CFGR1_PCSPOL    BIT(8)
  78 #define CFGR1_NOSTALL   BIT(3)
  79 #define CFGR1_MASTER    BIT(0)
  80 #define FSR_TXCOUNT     (0xFF)
  81 #define RSR_RXEMPTY     BIT(1)
  82 #define TCR_CPOL        BIT(31)
  83 #define TCR_CPHA        BIT(30)
  84 #define TCR_CONT        BIT(21)
  85 #define TCR_CONTC       BIT(20)
  86 #define TCR_RXMSK       BIT(19)
  87 #define TCR_TXMSK       BIT(18)
  88
  89 struct lpspi_config {
  90         u8 bpw;
  91         u8 chip_select;
  92         u8 prescale;
  93         u16 mode;
  94         u32 speed_hz;
  95 };
  96
  97 struct fsl_lpspi_data {
  98         struct device *dev;
  99         void __iomem *base;
 100         unsigned long base_phys;
 101         struct clk *clk_ipg;
 102         struct clk *clk_per;
 103         bool is_slave;
 104         bool is_first_byte;
 105
 106         void *rx_buf;
 107         const void *tx_buf;
 108         void (*tx)(struct fsl_lpspi_data *);
 109         void (*rx)(struct fsl_lpspi_data *);
 110
 111         u32 remain;
 112         u8 watermark;
 113         u8 txfifosize;
 114         u8 rxfifosize;
 115
 116         struct lpspi_config config;
 117         struct completion xfer_done;
 118
 119         bool slave_aborted;
 120
 121         /* DMA */
 122         bool usedma;
 123         struct completion dma_rx_completion;
 124         struct completion dma_tx_completion;
 125
 126         int chipselect[];
 127 };
 128
 129 static const struct of_device_id fsl_lpspi_dt_ids[] = {
 130         { .compatible = "fsl,imx7ulp-spi", },
 131         { /* sentinel */ }
 132 };
 133 MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);
 134
 135 #define LPSPI_BUF_RX(type)                                              \
 136 static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi)   \
 137 {                                                                       \
 138         unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR);        \
 139                                                                         \
 140         if (fsl_lpspi->rx_buf) {                                        \
 141                 *(type *)fsl_lpspi->rx_buf = val;                       \
 142                 fsl_lpspi->rx_buf += sizeof(type);                      \
 143         }                                                               \
 144 }
 145
 146 #define LPSPI_BUF_TX(type)                                              \
 147 static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi)   \
 148 {                                                                       \
 149         type val = 0;                                                   \
 150                                                                         \
 151         if (fsl_lpspi->tx_buf) {                                        \
 152                 val = *(type *)fsl_lpspi->tx_buf;                       \
 153                 fsl_lpspi->tx_buf += sizeof(type);                      \
 154         }                                                               \
 155                                                                         \
 156         fsl_lpspi->remain -= sizeof(type);                              \
 157         writel(val, fsl_lpspi->base + IMX7ULP_TDR);                     \
 158 }
 159
 160 LPSPI_BUF_RX(u8)
 161 LPSPI_BUF_TX(u8)
 162 LPSPI_BUF_RX(u16)
 163 LPSPI_BUF_TX(u16)
 164 LPSPI_BUF_RX(u32)
 165 LPSPI_BUF_TX(u32)
 166
 167 static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
 168                               unsigned int enable)
 169 {
 170         writel(enable, fsl_lpspi->base + IMX7ULP_IER);
 171 }
 172
 173 static int fsl_lpspi_bytes_per_word(const int bpw)
 174 {
 175         return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
 176 }
 177
 178 static bool fsl_lpspi_can_dma(struct spi_controller *controller,
 179                               struct spi_device *spi,
 180                               struct spi_transfer *transfer)
 181 {
 182         unsigned int bytes_per_word;
 183
 184         if (!controller->dma_rx)
 185                 return false;
 186
 187         bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word);
 188
 189         switch (bytes_per_word)
 190         {
 191                 case 1:
 192                 case 2:
 193                 case 4:
 194                         break;
 195                 default:
 196                         return false;
 197         }
 198
 199         return true;
 200 }
 201
 202 static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
 203 {
 204         struct fsl_lpspi_data *fsl_lpspi =
 205                                 spi_controller_get_devdata(controller);
 206         int ret;
 207
 208         ret = pm_runtime_get_sync(fsl_lpspi->dev);
 209         if (ret < 0) {
 210                 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
 211                 return ret;
 212         }
 213
 214         return 0;
 215 }
 216
 217 static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
 218 {
 219         struct fsl_lpspi_data *fsl_lpspi =
 220                                 spi_controller_get_devdata(controller);
 221
 222         pm_runtime_mark_last_busy(fsl_lpspi->dev);
 223         pm_runtime_put_autosuspend(fsl_lpspi->dev);
 224
 225         return 0;
 226 }
 227
 228 static int fsl_lpspi_prepare_message(struct spi_controller *controller,
 229                                      struct spi_message *msg)
 230 {
 231         struct fsl_lpspi_data *fsl_lpspi =
 232                                         spi_controller_get_devdata(controller);
 233         struct spi_device *spi = msg->spi;
 234         int gpio = fsl_lpspi->chipselect[spi->chip_select];
 235
 236         if (gpio_is_valid(gpio))
 237                 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
 238
 239         return 0;
 240 }
 241
 242 static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
 243 {
 244         u8 txfifo_cnt;
 245         u32 temp;
 246
 247         txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
 248
 249         while (txfifo_cnt < fsl_lpspi->txfifosize) {
 250                 if (!fsl_lpspi->remain)
 251                         break;
 252                 fsl_lpspi->tx(fsl_lpspi);
 253                 txfifo_cnt++;
 254         }
 255
 256         if (txfifo_cnt < fsl_lpspi->txfifosize) {
 257                 if (!fsl_lpspi->is_slave) {
 258                         temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
 259                         temp &= ~TCR_CONTC;
 260                         writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
 261                 }
 262
 263                 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
 264         } else
 265                 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
 266 }
 267
 268 static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
 269 {
 270         while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
 271                 fsl_lpspi->rx(fsl_lpspi);
 272 }
 273
 274 static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi)
 275 {
 276         u32 temp = 0;
 277
 278         temp |= fsl_lpspi->config.bpw - 1;
 279         temp |= (fsl_lpspi->config.mode & 0x3) << 30;
 280         if (!fsl_lpspi->is_slave) {
 281                 temp |= fsl_lpspi->config.prescale << 27;
 282                 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;
 283
 284                 /*
 285                  * Set TCR_CONT will keep SS asserted after current transfer.
 286                  * For the first transfer, clear TCR_CONTC to assert SS.
 287                  * For subsequent transfer, set TCR_CONTC to keep SS asserted.
 288                  */
 289                 if (!fsl_lpspi->usedma) {
 290                         temp |= TCR_CONT;
 291                         if (fsl_lpspi->is_first_byte)
 292                                 temp &= ~TCR_CONTC;
 293                         else
 294                                 temp |= TCR_CONTC;
 295                 }
 296         }
 297         writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
 298
 299         dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
 300 }
 301
 302 static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
 303 {
 304         u32 temp;
 305
 306         if (!fsl_lpspi->usedma)
 307                 temp = fsl_lpspi->watermark >> 1 |
 308                        (fsl_lpspi->watermark >> 1) << 16;
 309         else
 310                 temp = fsl_lpspi->watermark >> 1;
 311
 312         writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
 313
 314         dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
 315 }
 316
 317 static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
 318 {
 319         struct lpspi_config config = fsl_lpspi->config;
 320         unsigned int perclk_rate, scldiv;
 321         u8 prescale;
 322
 323         perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
 324
 325         if (config.speed_hz > perclk_rate / 2) {
 326                 dev_err(fsl_lpspi->dev,
 327                       "per-clk should be at least two times of transfer speed");
 328                 return -EINVAL;
 329         }
 330
 331         for (prescale = 0; prescale < 8; prescale++) {
 332                 scldiv = perclk_rate / config.speed_hz / (1 << prescale) - 2;
 333                 if (scldiv < 256) {
 334                         fsl_lpspi->config.prescale = prescale;
 335                         break;
 336                 }
 337         }
 338
 339         if (scldiv >= 256)
 340                 return -EINVAL;
 341
 342         writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16),
 343                                         fsl_lpspi->base + IMX7ULP_CCR);
 344
 345         dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale=%d, scldiv=%d\n",
 346                 perclk_rate, config.speed_hz, prescale, scldiv);
 347
 348         return 0;
 349 }
 350
 351 static int fsl_lpspi_dma_configure(struct spi_controller *controller)
 352 {
 353         int ret;
 354         enum dma_slave_buswidth buswidth;
 355         struct dma_slave_config rx = {}, tx = {};
 356         struct fsl_lpspi_data *fsl_lpspi =
 357                                 spi_controller_get_devdata(controller);
 358
 359         switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) {
 360         case 4:
 361                 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
 362                 break;
 363         case 2:
 364                 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
 365                 break;
 366         case 1:
 367                 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
 368                 break;
 369         default:
 370                 return -EINVAL;
 371         }
 372
 373         tx.direction = DMA_MEM_TO_DEV;
 374         tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR;
 375         tx.dst_addr_width = buswidth;
 376         tx.dst_maxburst = 1;
 377         ret = dmaengine_slave_config(controller->dma_tx, &tx);
 378         if (ret) {
 379                 dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n",
 380                         ret);
 381                 return ret;
 382         }
 383
 384         rx.direction = DMA_DEV_TO_MEM;
 385         rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR;
 386         rx.src_addr_width = buswidth;
 387         rx.src_maxburst = 1;
 388         ret = dmaengine_slave_config(controller->dma_rx, &rx);
 389         if (ret) {
 390                 dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n",
 391                         ret);
 392                 return ret;
 393         }
 394
 395         return 0;
 396 }
 397
 398 static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
 399 {
 400         u32 temp;
 401         int ret;
 402
 403         if (!fsl_lpspi->is_slave) {
 404                 ret = fsl_lpspi_set_bitrate(fsl_lpspi);
 405                 if (ret)
 406                         return ret;
 407         }
 408
 409         fsl_lpspi_set_watermark(fsl_lpspi);
 410
 411         if (!fsl_lpspi->is_slave)
 412                 temp = CFGR1_MASTER;
 413         else
 414                 temp = CFGR1_PINCFG;
 415         if (fsl_lpspi->config.mode & SPI_CS_HIGH)
 416                 temp |= CFGR1_PCSPOL;
 417         writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
 418
 419         temp = readl(fsl_lpspi->base + IMX7ULP_CR);
 420         temp |= CR_RRF | CR_RTF | CR_MEN;
 421         writel(temp, fsl_lpspi->base + IMX7ULP_CR);
 422
 423         temp = 0;
 424         if (fsl_lpspi->usedma)
 425                 temp = DER_TDDE | DER_RDDE;
 426         writel(temp, fsl_lpspi->base + IMX7ULP_DER);
 427
 428         return 0;
 429 }
 430
 431 static int fsl_lpspi_setup_transfer(struct spi_controller *controller,
 432                                      struct spi_device *spi,
 433                                      struct spi_transfer *t)
 434 {
 435         struct fsl_lpspi_data *fsl_lpspi =
 436                                 spi_controller_get_devdata(spi->controller);
 437
 438         if (t == NULL)
 439                 return -EINVAL;
 440
 441         fsl_lpspi->config.mode = spi->mode;
 442         fsl_lpspi->config.bpw = t->bits_per_word;
 443         fsl_lpspi->config.speed_hz = t->speed_hz;
 444         fsl_lpspi->config.chip_select = spi->chip_select;
 445
 446         if (!fsl_lpspi->config.speed_hz)
 447                 fsl_lpspi->config.speed_hz = spi->max_speed_hz;
 448         if (!fsl_lpspi->config.bpw)
 449                 fsl_lpspi->config.bpw = spi->bits_per_word;
 450
 451         /* Initialize the functions for transfer */
 452         if (fsl_lpspi->config.bpw <= 8) {
 453                 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
 454                 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
 455         } else if (fsl_lpspi->config.bpw <= 16) {
 456                 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
 457                 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
 458         } else {
 459                 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
 460                 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
 461         }
 462
 463         if (t->len <= fsl_lpspi->txfifosize)
 464                 fsl_lpspi->watermark = t->len;
 465         else
 466                 fsl_lpspi->watermark = fsl_lpspi->txfifosize;
 467
 468         if (fsl_lpspi_can_dma(controller, spi, t))
 469                 fsl_lpspi->usedma = true;
 470         else
 471                 fsl_lpspi->usedma = false;
 472
 473         return fsl_lpspi_config(fsl_lpspi);
 474 }
 475
 476 static int fsl_lpspi_slave_abort(struct spi_controller *controller)
 477 {
 478         struct fsl_lpspi_data *fsl_lpspi =
 479                                 spi_controller_get_devdata(controller);
 480
 481         fsl_lpspi->slave_aborted = true;
 482         if (!fsl_lpspi->usedma)
 483                 complete(&fsl_lpspi->xfer_done);
 484         else {
 485                 complete(&fsl_lpspi->dma_tx_completion);
 486                 complete(&fsl_lpspi->dma_rx_completion);
 487         }
 488
 489         return 0;
 490 }
 491
 492 static int fsl_lpspi_wait_for_completion(struct spi_controller *controller)
 493 {
 494         struct fsl_lpspi_data *fsl_lpspi =
 495                                 spi_controller_get_devdata(controller);
 496
 497         if (fsl_lpspi->is_slave) {
 498                 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) ||
 499                         fsl_lpspi->slave_aborted) {
 500                         dev_dbg(fsl_lpspi->dev, "interrupted\n");
 501                         return -EINTR;
 502                 }
 503         } else {
 504                 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
 505                         dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
 506                         return -ETIMEDOUT;
 507                 }
 508         }
 509
 510         return 0;
 511 }
 512
 513 static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
 514 {
 515         u32 temp;
 516
 517         if (!fsl_lpspi->usedma) {
 518                 /* Disable all interrupt */
 519                 fsl_lpspi_intctrl(fsl_lpspi, 0);
 520         }
 521
 522         /* W1C for all flags in SR */
 523         temp = 0x3F << 8;
 524         writel(temp, fsl_lpspi->base + IMX7ULP_SR);
 525
 526         /* Clear FIFO and disable module */
 527         temp = CR_RRF | CR_RTF;
 528         writel(temp, fsl_lpspi->base + IMX7ULP_CR);
 529
 530         return 0;
 531 }
 532
 533 static void fsl_lpspi_dma_rx_callback(void *cookie)
 534 {
 535         struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
 536
 537         complete(&fsl_lpspi->dma_rx_completion);
 538 }
 539
 540 static void fsl_lpspi_dma_tx_callback(void *cookie)
 541 {
 542         struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
 543
 544         complete(&fsl_lpspi->dma_tx_completion);
 545 }
 546
 547 static int fsl_lpspi_calculate_timeout(struct fsl_lpspi_data *fsl_lpspi,
 548                                        int size)
 549 {
 550         unsigned long timeout = 0;
 551
 552         /* Time with actual data transfer and CS change delay related to HW */
 553         timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz;
 554
 555         /* Add extra second for scheduler related activities */
 556         timeout += 1;
 557
 558         /* Double calculated timeout */
 559         return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
 560 }
 561
 562 static int fsl_lpspi_dma_transfer(struct spi_controller *controller,
 563                                 struct fsl_lpspi_data *fsl_lpspi,
 564                                 struct spi_transfer *transfer)
 565 {
 566         struct dma_async_tx_descriptor *desc_tx, *desc_rx;
 567         unsigned long transfer_timeout;
 568         unsigned long timeout;
 569         struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
 570         int ret;
 571
 572         ret = fsl_lpspi_dma_configure(controller);
 573         if (ret)
 574                 return ret;
 575
 576         desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
 577                                 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
 578                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 579         if (!desc_rx)
 580                 return -EINVAL;
 581
 582         desc_rx->callback = fsl_lpspi_dma_rx_callback;
 583         desc_rx->callback_param = (void *)fsl_lpspi;
 584         dmaengine_submit(desc_rx);
 585         reinit_completion(&fsl_lpspi->dma_rx_completion);
 586         dma_async_issue_pending(controller->dma_rx);
 587
 588         desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
 589                                 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
 590                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 591         if (!desc_tx) {
 592                 dmaengine_terminate_all(controller->dma_tx);
 593                 return -EINVAL;
 594         }
 595
 596         desc_tx->callback = fsl_lpspi_dma_tx_callback;
 597         desc_tx->callback_param = (void *)fsl_lpspi;
 598         dmaengine_submit(desc_tx);
 599         reinit_completion(&fsl_lpspi->dma_tx_completion);
 600         dma_async_issue_pending(controller->dma_tx);
 601
 602         fsl_lpspi->slave_aborted = false;
 603
 604         if (!fsl_lpspi->is_slave) {
 605                 transfer_timeout = fsl_lpspi_calculate_timeout(fsl_lpspi,
 606                                                                transfer->len);
 607
 608                 /* Wait eDMA to finish the data transfer.*/
 609                 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion,
 610                                                       transfer_timeout);
 611                 if (!timeout) {
 612                         dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n");
 613                         dmaengine_terminate_all(controller->dma_tx);
 614                         dmaengine_terminate_all(controller->dma_rx);
 615                         fsl_lpspi_reset(fsl_lpspi);
 616                         return -ETIMEDOUT;
 617                 }
 618
 619                 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion,
 620                                                       transfer_timeout);
 621                 if (!timeout) {
 622                         dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n");
 623                         dmaengine_terminate_all(controller->dma_tx);
 624                         dmaengine_terminate_all(controller->dma_rx);
 625                         fsl_lpspi_reset(fsl_lpspi);
 626                         return -ETIMEDOUT;
 627                 }
 628         } else {
 629                 if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) ||
 630                         fsl_lpspi->slave_aborted) {
 631                         dev_dbg(fsl_lpspi->dev,
 632                                 "I/O Error in DMA TX interrupted\n");
 633                         dmaengine_terminate_all(controller->dma_tx);
 634                         dmaengine_terminate_all(controller->dma_rx);
 635                         fsl_lpspi_reset(fsl_lpspi);
 636                         return -EINTR;
 637                 }
 638
 639                 if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) ||
 640                         fsl_lpspi->slave_aborted) {
 641                         dev_dbg(fsl_lpspi->dev,
 642                                 "I/O Error in DMA RX interrupted\n");
 643                         dmaengine_terminate_all(controller->dma_tx);
 644                         dmaengine_terminate_all(controller->dma_rx);
 645                         fsl_lpspi_reset(fsl_lpspi);
 646                         return -EINTR;
 647                 }
 648         }
 649
 650         fsl_lpspi_reset(fsl_lpspi);
 651
 652         return 0;
 653 }
 654
 655 static void fsl_lpspi_dma_exit(struct spi_controller *controller)
 656 {
 657         if (controller->dma_rx) {
 658                 dma_release_channel(controller->dma_rx);
 659                 controller->dma_rx = NULL;
 660         }
 661
 662         if (controller->dma_tx) {
 663                 dma_release_channel(controller->dma_tx);
 664                 controller->dma_tx = NULL;
 665         }
 666 }
 667
 668 static int fsl_lpspi_dma_init(struct device *dev,
 669                               struct fsl_lpspi_data *fsl_lpspi,
 670                               struct spi_controller *controller)
 671 {
 672         int ret;
 673
 674         /* Prepare for TX DMA: */
 675         controller->dma_tx = dma_request_chan(dev, "tx");
 676         if (IS_ERR(controller->dma_tx)) {
 677                 ret = PTR_ERR(controller->dma_tx);
 678                 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
 679                 controller->dma_tx = NULL;
 680                 goto err;
 681         }
 682
 683         /* Prepare for RX DMA: */
 684         controller->dma_rx = dma_request_chan(dev, "rx");
 685         if (IS_ERR(controller->dma_rx)) {
 686                 ret = PTR_ERR(controller->dma_rx);
 687                 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
 688                 controller->dma_rx = NULL;
 689                 goto err;
 690         }
 691
 692         init_completion(&fsl_lpspi->dma_rx_completion);
 693         init_completion(&fsl_lpspi->dma_tx_completion);
 694         controller->can_dma = fsl_lpspi_can_dma;
 695         controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES;
 696
 697         return 0;
 698 err:
 699         fsl_lpspi_dma_exit(controller);
 700         return ret;
 701 }
 702
 703 static int fsl_lpspi_pio_transfer(struct spi_controller *controller,
 704                                   struct spi_transfer *t)
 705 {
 706         struct fsl_lpspi_data *fsl_lpspi =
 707                                 spi_controller_get_devdata(controller);
 708         int ret;
 709
 710         fsl_lpspi->tx_buf = t->tx_buf;
 711         fsl_lpspi->rx_buf = t->rx_buf;
 712         fsl_lpspi->remain = t->len;
 713
 714         reinit_completion(&fsl_lpspi->xfer_done);
 715         fsl_lpspi->slave_aborted = false;
 716
 717         fsl_lpspi_write_tx_fifo(fsl_lpspi);
 718
 719         ret = fsl_lpspi_wait_for_completion(controller);
 720         if (ret)
 721                 return ret;
 722
 723         fsl_lpspi_reset(fsl_lpspi);
 724
 725         return 0;
 726 }
 727
 728 static int fsl_lpspi_transfer_one(struct spi_controller *controller,
 729                                   struct spi_device *spi,
 730                                   struct spi_transfer *t)
 731 {
 732         struct fsl_lpspi_data *fsl_lpspi =
 733                                         spi_controller_get_devdata(controller);
 734         int ret;
 735
 736         fsl_lpspi->is_first_byte = true;
 737         ret = fsl_lpspi_setup_transfer(controller, spi, t);
 738         if (ret < 0)
 739                 return ret;
 740
 741         fsl_lpspi_set_cmd(fsl_lpspi);
 742         fsl_lpspi->is_first_byte = false;
 743
 744         if (fsl_lpspi->usedma)
 745                 ret = fsl_lpspi_dma_transfer(controller, fsl_lpspi, t);
 746         else
 747                 ret = fsl_lpspi_pio_transfer(controller, t);
 748         if (ret < 0)
 749                 return ret;
 750
 751         return 0;
 752 }
 753
 754 static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
 755 {
 756         u32 temp_SR, temp_IER;
 757         struct fsl_lpspi_data *fsl_lpspi = dev_id;
 758
 759         temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
 760         fsl_lpspi_intctrl(fsl_lpspi, 0);
 761         temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);
 762
 763         fsl_lpspi_read_rx_fifo(fsl_lpspi);
 764
 765         if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) {
 766                 fsl_lpspi_write_tx_fifo(fsl_lpspi);
 767                 return IRQ_HANDLED;
 768         }
 769
 770         if (temp_SR & SR_MBF ||
 771             readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) {
 772                 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
 773                 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
 774                 return IRQ_HANDLED;
 775         }
 776
 777         if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) {
 778                 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
 779                 complete(&fsl_lpspi->xfer_done);
 780                 return IRQ_HANDLED;
 781         }
 782
 783         return IRQ_NONE;
 784 }
 785
 786 #ifdef CONFIG_PM
 787 static int fsl_lpspi_runtime_resume(struct device *dev)
 788 {
 789         struct spi_controller *controller = dev_get_drvdata(dev);
 790         struct fsl_lpspi_data *fsl_lpspi;
 791         int ret;
 792
 793         fsl_lpspi = spi_controller_get_devdata(controller);
 794
 795         ret = clk_prepare_enable(fsl_lpspi->clk_per);
 796         if (ret)
 797                 return ret;
 798
 799         ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
 800         if (ret) {
 801                 clk_disable_unprepare(fsl_lpspi->clk_per);
 802                 return ret;
 803         }
 804
 805         return 0;
 806 }
 807
 808 static int fsl_lpspi_runtime_suspend(struct device *dev)
 809 {
 810         struct spi_controller *controller = dev_get_drvdata(dev);
 811         struct fsl_lpspi_data *fsl_lpspi;
 812
 813         fsl_lpspi = spi_controller_get_devdata(controller);
 814
 815         clk_disable_unprepare(fsl_lpspi->clk_per);
 816         clk_disable_unprepare(fsl_lpspi->clk_ipg);
 817
 818         return 0;
 819 }
 820 #endif
 821
 822 static int fsl_lpspi_init_rpm(struct fsl_lpspi_data *fsl_lpspi)
 823 {
 824         struct device *dev = fsl_lpspi->dev;
 825
 826         pm_runtime_enable(dev);
 827         pm_runtime_set_autosuspend_delay(dev, FSL_LPSPI_RPM_TIMEOUT);
 828         pm_runtime_use_autosuspend(dev);
 829
 830         return 0;
 831 }
 832
 833 static int fsl_lpspi_probe(struct platform_device *pdev)
 834 {
 835         struct device_node *np = pdev->dev.of_node;
 836         struct fsl_lpspi_data *fsl_lpspi;
 837         struct spi_controller *controller;
 838         struct spi_imx_master *lpspi_platform_info =
 839                 dev_get_platdata(&pdev->dev);
 840         struct resource *res;
 841         int i, ret, irq;
 842         u32 temp;
 843         bool is_slave;
 844
 845         is_slave = of_property_read_bool((&pdev->dev)->of_node, "spi-slave");
 846         if (is_slave)
 847                 controller = spi_alloc_slave(&pdev->dev,
 848                                         sizeof(struct fsl_lpspi_data));
 849         else
 850                 controller = spi_alloc_master(&pdev->dev,
 851                                         sizeof(struct fsl_lpspi_data));
 852
 853         if (!controller)
 854                 return -ENOMEM;
 855
 856         platform_set_drvdata(pdev, controller);
 857
 858         fsl_lpspi = spi_controller_get_devdata(controller);
 859         fsl_lpspi->dev = &pdev->dev;
 860         fsl_lpspi->is_slave = is_slave;
 861
 862         controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
 863         controller->transfer_one = fsl_lpspi_transfer_one;
 864         controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
 865         controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
 866         controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 867         controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
 868         controller->dev.of_node = pdev->dev.of_node;
 869         controller->bus_num = pdev->id;
 870         controller->slave_abort = fsl_lpspi_slave_abort;
 871
 872         ret = devm_spi_register_controller(&pdev->dev, controller);
 873         if (ret < 0) {
 874                 dev_err(&pdev->dev, "spi_register_controller error.\n");
 875                 goto out_controller_put;
 876         }
 877
 878         if (!fsl_lpspi->is_slave) {
 879                 for (i = 0; i < controller->num_chipselect; i++) {
 880                         int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
 881
 882                         if (!gpio_is_valid(cs_gpio) && lpspi_platform_info)
 883                                 cs_gpio = lpspi_platform_info->chipselect[i];
 884
 885                         fsl_lpspi->chipselect[i] = cs_gpio;
 886                         if (!gpio_is_valid(cs_gpio))
 887                                 continue;
 888
 889                         ret = devm_gpio_request(&pdev->dev,
 890                                                 fsl_lpspi->chipselect[i],
 891                                                 DRIVER_NAME);
 892                         if (ret) {
 893                                 dev_err(&pdev->dev, "can't get cs gpios\n");
 894                                 goto out_controller_put;
 895                         }
 896                 }
 897                 controller->cs_gpios = fsl_lpspi->chipselect;
 898                 controller->prepare_message = fsl_lpspi_prepare_message;
 899         }
 900
 901         init_completion(&fsl_lpspi->xfer_done);
 902
 903         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 904         fsl_lpspi->base = devm_ioremap_resource(&pdev->dev, res);
 905         if (IS_ERR(fsl_lpspi->base)) {
 906                 ret = PTR_ERR(fsl_lpspi->base);
 907                 goto out_controller_put;
 908         }
 909         fsl_lpspi->base_phys = res->start;
 910
 911         irq = platform_get_irq(pdev, 0);
 912         if (irq < 0) {
 913                 ret = irq;
 914                 goto out_controller_put;
 915         }
 916
 917         ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0,
 918                                dev_name(&pdev->dev), fsl_lpspi);
 919         if (ret) {
 920                 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
 921                 goto out_controller_put;
 922         }
 923
 924         fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per");
 925         if (IS_ERR(fsl_lpspi->clk_per)) {
 926                 ret = PTR_ERR(fsl_lpspi->clk_per);
 927                 goto out_controller_put;
 928         }
 929
 930         fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
 931         if (IS_ERR(fsl_lpspi->clk_ipg)) {
 932                 ret = PTR_ERR(fsl_lpspi->clk_ipg);
 933                 goto out_controller_put;
 934         }
 935
 936         /* enable the clock */
 937         ret = fsl_lpspi_init_rpm(fsl_lpspi);
 938         if (ret)
 939                 goto out_controller_put;
 940
 941         ret = pm_runtime_get_sync(fsl_lpspi->dev);
 942         if (ret < 0) {
 943                 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
 944                 goto out_controller_put;
 945         }
 946
 947         temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
 948         fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
 949         fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
 950
 951         ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller);
 952         if (ret == -EPROBE_DEFER)
 953                 goto out_controller_put;
 954
 955         if (ret < 0)
 956                 dev_err(&pdev->dev, "dma setup error %d, use pio\n", ret);
 957
 958         return 0;
 959
 960 out_controller_put:
 961         spi_controller_put(controller);
 962
 963         return ret;
 964 }
 965
 966 static int fsl_lpspi_remove(struct platform_device *pdev)
 967 {
 968         struct spi_controller *controller = platform_get_drvdata(pdev);
 969         struct fsl_lpspi_data *fsl_lpspi =
 970                                 spi_controller_get_devdata(controller);
 971
 972         pm_runtime_disable(fsl_lpspi->dev);
 973
 974         spi_master_put(controller);
 975
 976         return 0;
 977 }
 978
 979 #ifdef CONFIG_PM_SLEEP
 980 static int fsl_lpspi_suspend(struct device *dev)
 981 {
 982         int ret;
 983
 984         pinctrl_pm_select_sleep_state(dev);
 985         ret = pm_runtime_force_suspend(dev);
 986         return ret;
 987 }
 988
 989 static int fsl_lpspi_resume(struct device *dev)
 990 {
 991         int ret;
 992
 993         ret = pm_runtime_force_resume(dev);
 994         if (ret) {
 995                 dev_err(dev, "Error in resume: %d\n", ret);
 996                 return ret;
 997         }
 998
 999         pinctrl_pm_select_default_state(dev);
1000
1001         return 0;
1002 }
1003 #endif /* CONFIG_PM_SLEEP */
1004
1005 static const struct dev_pm_ops fsl_lpspi_pm_ops = {
1006         SET_RUNTIME_PM_OPS(fsl_lpspi_runtime_suspend,
1007                                 fsl_lpspi_runtime_resume, NULL)
1008         SET_SYSTEM_SLEEP_PM_OPS(fsl_lpspi_suspend, fsl_lpspi_resume)
1009 };
1010
1011 static struct platform_driver fsl_lpspi_driver = {
1012         .driver = {
1013                 .name = DRIVER_NAME,
1014                 .of_match_table = fsl_lpspi_dt_ids,
1015                 .pm = &fsl_lpspi_pm_ops,
1016         },
1017         .probe = fsl_lpspi_probe,
1018         .remove = fsl_lpspi_remove,
1019 };
1020 module_platform_driver(fsl_lpspi_driver);
1021
1022 MODULE_DESCRIPTION("LPSPI Controller driver");
1023 MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
1024 MODULE_LICENSE("GPL");