drivers/spi/spi-fsl-lpspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Freescale i.MX7ULP LPSPI driver
   4 //
   5 // Copyright 2016 Freescale Semiconductor, Inc.
   6 // Copyright 2018 NXP Semiconductors
   7
   8 #include <linux/clk.h>
   9 #include <linux/completion.h>
  10 #include <linux/delay.h>
  11 #include <linux/dmaengine.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/err.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/irq.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/pinctrl/consumer.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/platform_data/dma-imx.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/slab.h>
  26 #include <linux/spi/spi.h>
  27 #include <linux/spi/spi_bitbang.h>
  28 #include <linux/types.h>
  29
  30 #define DRIVER_NAME "fsl_lpspi"
  31
  32 #define FSL_LPSPI_RPM_TIMEOUT 50 /* 50ms */
  33
  34 /* The maximum bytes that edma can transfer once.*/
  35 #define FSL_LPSPI_MAX_EDMA_BYTES  ((1 << 15) - 1)
  36
  37 /* i.MX7ULP LPSPI registers */
  38 #define IMX7ULP_VERID   0x0
  39 #define IMX7ULP_PARAM   0x4
  40 #define IMX7ULP_CR      0x10
  41 #define IMX7ULP_SR      0x14
  42 #define IMX7ULP_IER     0x18
  43 #define IMX7ULP_DER     0x1c
  44 #define IMX7ULP_CFGR0   0x20
  45 #define IMX7ULP_CFGR1   0x24
  46 #define IMX7ULP_DMR0    0x30
  47 #define IMX7ULP_DMR1    0x34
  48 #define IMX7ULP_CCR     0x40
  49 #define IMX7ULP_FCR     0x58
  50 #define IMX7ULP_FSR     0x5c
  51 #define IMX7ULP_TCR     0x60
  52 #define IMX7ULP_TDR     0x64
  53 #define IMX7ULP_RSR     0x70
  54 #define IMX7ULP_RDR     0x74
  55
  56 /* General control register field define */
  57 #define CR_RRF          BIT(9)
  58 #define CR_RTF          BIT(8)
  59 #define CR_RST          BIT(1)
  60 #define CR_MEN          BIT(0)
  61 #define SR_MBF          BIT(24)
  62 #define SR_TCF          BIT(10)
  63 #define SR_FCF          BIT(9)
  64 #define SR_RDF          BIT(1)
  65 #define SR_TDF          BIT(0)
  66 #define IER_TCIE        BIT(10)
  67 #define IER_FCIE        BIT(9)
  68 #define IER_RDIE        BIT(1)
  69 #define IER_TDIE        BIT(0)
  70 #define DER_RDDE        BIT(1)
  71 #define DER_TDDE        BIT(0)
  72 #define CFGR1_PCSCFG    BIT(27)
  73 #define CFGR1_PINCFG    (BIT(24)|BIT(25))
  74 #define CFGR1_PCSPOL    BIT(8)
  75 #define CFGR1_NOSTALL   BIT(3)
  76 #define CFGR1_MASTER    BIT(0)
  77 #define FSR_TXCOUNT     (0xFF)
  78 #define RSR_RXEMPTY     BIT(1)
  79 #define TCR_CPOL        BIT(31)
  80 #define TCR_CPHA        BIT(30)
  81 #define TCR_CONT        BIT(21)
  82 #define TCR_CONTC       BIT(20)
  83 #define TCR_RXMSK       BIT(19)
  84 #define TCR_TXMSK       BIT(18)
  85
  86 struct lpspi_config {
  87         u8 bpw;
  88         u8 chip_select;
  89         u8 prescale;
  90         u16 mode;
  91         u32 speed_hz;
  92 };
  93
  94 struct fsl_lpspi_data {
  95         struct device *dev;
  96         void __iomem *base;
  97         unsigned long base_phys;
  98         struct clk *clk_ipg;
  99         struct clk *clk_per;
 100         bool is_slave;
 101         bool is_first_byte;
 102
 103         void *rx_buf;
 104         const void *tx_buf;
 105         void (*tx)(struct fsl_lpspi_data *);
 106         void (*rx)(struct fsl_lpspi_data *);
 107
 108         u32 remain;
 109         u8 watermark;
 110         u8 txfifosize;
 111         u8 rxfifosize;
 112
 113         struct lpspi_config config;
 114         struct completion xfer_done;
 115
 116         bool slave_aborted;
 117
 118         /* DMA */
 119         bool usedma;
 120         struct completion dma_rx_completion;
 121         struct completion dma_tx_completion;
 122 };
 123
 124 static const struct of_device_id fsl_lpspi_dt_ids[] = {
 125         { .compatible = "fsl,imx7ulp-spi", },
 126         { /* sentinel */ }
 127 };
 128 MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);
 129
 130 #define LPSPI_BUF_RX(type)                                              \
 131 static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi)   \
 132 {                                                                       \
 133         unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR);        \
 134                                                                         \
 135         if (fsl_lpspi->rx_buf) {                                        \
 136                 *(type *)fsl_lpspi->rx_buf = val;                       \
 137                 fsl_lpspi->rx_buf += sizeof(type);                      \
 138         }                                                               \
 139 }
 140
 141 #define LPSPI_BUF_TX(type)                                              \
 142 static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi)   \
 143 {                                                                       \
 144         type val = 0;                                                   \
 145                                                                         \
 146         if (fsl_lpspi->tx_buf) {                                        \
 147                 val = *(type *)fsl_lpspi->tx_buf;                       \
 148                 fsl_lpspi->tx_buf += sizeof(type);                      \
 149         }                                                               \
 150                                                                         \
 151         fsl_lpspi->remain -= sizeof(type);                              \
 152         writel(val, fsl_lpspi->base + IMX7ULP_TDR);                     \
 153 }
 154
 155 LPSPI_BUF_RX(u8)
 156 LPSPI_BUF_TX(u8)
 157 LPSPI_BUF_RX(u16)
 158 LPSPI_BUF_TX(u16)
 159 LPSPI_BUF_RX(u32)
 160 LPSPI_BUF_TX(u32)
 161
 162 static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
 163                               unsigned int enable)
 164 {
 165         writel(enable, fsl_lpspi->base + IMX7ULP_IER);
 166 }
 167
 168 static int fsl_lpspi_bytes_per_word(const int bpw)
 169 {
 170         return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
 171 }
 172
 173 static bool fsl_lpspi_can_dma(struct spi_controller *controller,
 174                               struct spi_device *spi,
 175                               struct spi_transfer *transfer)
 176 {
 177         unsigned int bytes_per_word;
 178
 179         if (!controller->dma_rx)
 180                 return false;
 181
 182         bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word);
 183
 184         switch (bytes_per_word) {
 185         case 1:
 186         case 2:
 187         case 4:
 188                 break;
 189         default:
 190                 return false;
 191         }
 192
 193         return true;
 194 }
 195
 196 static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
 197 {
 198         struct fsl_lpspi_data *fsl_lpspi =
 199                                 spi_controller_get_devdata(controller);
 200         int ret;
 201
 202         ret = pm_runtime_get_sync(fsl_lpspi->dev);
 203         if (ret < 0) {
 204                 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
 205                 return ret;
 206         }
 207
 208         return 0;
 209 }
 210
 211 static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
 212 {
 213         struct fsl_lpspi_data *fsl_lpspi =
 214                                 spi_controller_get_devdata(controller);
 215
 216         pm_runtime_mark_last_busy(fsl_lpspi->dev);
 217         pm_runtime_put_autosuspend(fsl_lpspi->dev);
 218
 219         return 0;
 220 }
 221
 222 static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
 223 {
 224         u8 txfifo_cnt;
 225         u32 temp;
 226
 227         txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
 228
 229         while (txfifo_cnt < fsl_lpspi->txfifosize) {
 230                 if (!fsl_lpspi->remain)
 231                         break;
 232                 fsl_lpspi->tx(fsl_lpspi);
 233                 txfifo_cnt++;
 234         }
 235
 236         if (txfifo_cnt < fsl_lpspi->txfifosize) {
 237                 if (!fsl_lpspi->is_slave) {
 238                         temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
 239                         temp &= ~TCR_CONTC;
 240                         writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
 241                 }
 242
 243                 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
 244         } else
 245                 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
 246 }
 247
 248 static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
 249 {
 250         while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
 251                 fsl_lpspi->rx(fsl_lpspi);
 252 }
 253
 254 static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi)
 255 {
 256         u32 temp = 0;
 257
 258         temp |= fsl_lpspi->config.bpw - 1;
 259         temp |= (fsl_lpspi->config.mode & 0x3) << 30;
 260         if (!fsl_lpspi->is_slave) {
 261                 temp |= fsl_lpspi->config.prescale << 27;
 262                 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;
 263
 264                 /*
 265                  * Set TCR_CONT will keep SS asserted after current transfer.
 266                  * For the first transfer, clear TCR_CONTC to assert SS.
 267                  * For subsequent transfer, set TCR_CONTC to keep SS asserted.
 268                  */
 269                 if (!fsl_lpspi->usedma) {
 270                         temp |= TCR_CONT;
 271                         if (fsl_lpspi->is_first_byte)
 272                                 temp &= ~TCR_CONTC;
 273                         else
 274                                 temp |= TCR_CONTC;
 275                 }
 276         }
 277         writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
 278
 279         dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
 280 }
 281
 282 static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
 283 {
 284         u32 temp;
 285
 286         if (!fsl_lpspi->usedma)
 287                 temp = fsl_lpspi->watermark >> 1 |
 288                        (fsl_lpspi->watermark >> 1) << 16;
 289         else
 290                 temp = fsl_lpspi->watermark >> 1;
 291
 292         writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
 293
 294         dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
 295 }
 296
 297 static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
 298 {
 299         struct lpspi_config config = fsl_lpspi->config;
 300         unsigned int perclk_rate, scldiv;
 301         u8 prescale;
 302
 303         perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
 304
 305         if (config.speed_hz > perclk_rate / 2) {
 306                 dev_err(fsl_lpspi->dev,
 307                       "per-clk should be at least two times of transfer speed");
 308                 return -EINVAL;
 309         }
 310
 311         for (prescale = 0; prescale < 8; prescale++) {
 312                 scldiv = perclk_rate / config.speed_hz / (1 << prescale) - 2;
 313                 if (scldiv < 256) {
 314                         fsl_lpspi->config.prescale = prescale;
 315                         break;
 316                 }
 317         }
 318
 319         if (scldiv >= 256)
 320                 return -EINVAL;
 321
 322         writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16),
 323                                         fsl_lpspi->base + IMX7ULP_CCR);
 324
 325         dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale=%d, scldiv=%d\n",
 326                 perclk_rate, config.speed_hz, prescale, scldiv);
 327
 328         return 0;
 329 }
 330
 331 static int fsl_lpspi_dma_configure(struct spi_controller *controller)
 332 {
 333         int ret;
 334         enum dma_slave_buswidth buswidth;
 335         struct dma_slave_config rx = {}, tx = {};
 336         struct fsl_lpspi_data *fsl_lpspi =
 337                                 spi_controller_get_devdata(controller);
 338
 339         switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) {
 340         case 4:
 341                 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
 342                 break;
 343         case 2:
 344                 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
 345                 break;
 346         case 1:
 347                 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
 348                 break;
 349         default:
 350                 return -EINVAL;
 351         }
 352
 353         tx.direction = DMA_MEM_TO_DEV;
 354         tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR;
 355         tx.dst_addr_width = buswidth;
 356         tx.dst_maxburst = 1;
 357         ret = dmaengine_slave_config(controller->dma_tx, &tx);
 358         if (ret) {
 359                 dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n",
 360                         ret);
 361                 return ret;
 362         }
 363
 364         rx.direction = DMA_DEV_TO_MEM;
 365         rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR;
 366         rx.src_addr_width = buswidth;
 367         rx.src_maxburst = 1;
 368         ret = dmaengine_slave_config(controller->dma_rx, &rx);
 369         if (ret) {
 370                 dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n",
 371                         ret);
 372                 return ret;
 373         }
 374
 375         return 0;
 376 }
 377
 378 static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
 379 {
 380         u32 temp;
 381         int ret;
 382
 383         if (!fsl_lpspi->is_slave) {
 384                 ret = fsl_lpspi_set_bitrate(fsl_lpspi);
 385                 if (ret)
 386                         return ret;
 387         }
 388
 389         fsl_lpspi_set_watermark(fsl_lpspi);
 390
 391         if (!fsl_lpspi->is_slave)
 392                 temp = CFGR1_MASTER;
 393         else
 394                 temp = CFGR1_PINCFG;
 395         if (fsl_lpspi->config.mode & SPI_CS_HIGH)
 396                 temp |= CFGR1_PCSPOL;
 397         writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
 398
 399         temp = readl(fsl_lpspi->base + IMX7ULP_CR);
 400         temp |= CR_RRF | CR_RTF | CR_MEN;
 401         writel(temp, fsl_lpspi->base + IMX7ULP_CR);
 402
 403         temp = 0;
 404         if (fsl_lpspi->usedma)
 405                 temp = DER_TDDE | DER_RDDE;
 406         writel(temp, fsl_lpspi->base + IMX7ULP_DER);
 407
 408         return 0;
 409 }
 410
 411 static int fsl_lpspi_setup_transfer(struct spi_controller *controller,
 412                                      struct spi_device *spi,
 413                                      struct spi_transfer *t)
 414 {
 415         struct fsl_lpspi_data *fsl_lpspi =
 416                                 spi_controller_get_devdata(spi->controller);
 417
 418         if (t == NULL)
 419                 return -EINVAL;
 420
 421         fsl_lpspi->config.mode = spi->mode;
 422         fsl_lpspi->config.bpw = t->bits_per_word;
 423         fsl_lpspi->config.speed_hz = t->speed_hz;
 424         fsl_lpspi->config.chip_select = spi->chip_select;
 425
 426         if (!fsl_lpspi->config.speed_hz)
 427                 fsl_lpspi->config.speed_hz = spi->max_speed_hz;
 428         if (!fsl_lpspi->config.bpw)
 429                 fsl_lpspi->config.bpw = spi->bits_per_word;
 430
 431         /* Initialize the functions for transfer */
 432         if (fsl_lpspi->config.bpw <= 8) {
 433                 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
 434                 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
 435         } else if (fsl_lpspi->config.bpw <= 16) {
 436                 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
 437                 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
 438         } else {
 439                 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
 440                 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
 441         }
 442
 443         if (t->len <= fsl_lpspi->txfifosize)
 444                 fsl_lpspi->watermark = t->len;
 445         else
 446                 fsl_lpspi->watermark = fsl_lpspi->txfifosize;
 447
 448         if (fsl_lpspi_can_dma(controller, spi, t))
 449                 fsl_lpspi->usedma = true;
 450         else
 451                 fsl_lpspi->usedma = false;
 452
 453         return fsl_lpspi_config(fsl_lpspi);
 454 }
 455
 456 static int fsl_lpspi_slave_abort(struct spi_controller *controller)
 457 {
 458         struct fsl_lpspi_data *fsl_lpspi =
 459                                 spi_controller_get_devdata(controller);
 460
 461         fsl_lpspi->slave_aborted = true;
 462         if (!fsl_lpspi->usedma)
 463                 complete(&fsl_lpspi->xfer_done);
 464         else {
 465                 complete(&fsl_lpspi->dma_tx_completion);
 466                 complete(&fsl_lpspi->dma_rx_completion);
 467         }
 468
 469         return 0;
 470 }
 471
 472 static int fsl_lpspi_wait_for_completion(struct spi_controller *controller)
 473 {
 474         struct fsl_lpspi_data *fsl_lpspi =
 475                                 spi_controller_get_devdata(controller);
 476
 477         if (fsl_lpspi->is_slave) {
 478                 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) ||
 479                         fsl_lpspi->slave_aborted) {
 480                         dev_dbg(fsl_lpspi->dev, "interrupted\n");
 481                         return -EINTR;
 482                 }
 483         } else {
 484                 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
 485                         dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
 486                         return -ETIMEDOUT;
 487                 }
 488         }
 489
 490         return 0;
 491 }
 492
 493 static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
 494 {
 495         u32 temp;
 496
 497         if (!fsl_lpspi->usedma) {
 498                 /* Disable all interrupt */
 499                 fsl_lpspi_intctrl(fsl_lpspi, 0);
 500         }
 501
 502         /* W1C for all flags in SR */
 503         temp = 0x3F << 8;
 504         writel(temp, fsl_lpspi->base + IMX7ULP_SR);
 505
 506         /* Clear FIFO and disable module */
 507         temp = CR_RRF | CR_RTF;
 508         writel(temp, fsl_lpspi->base + IMX7ULP_CR);
 509
 510         return 0;
 511 }
 512
 513 static void fsl_lpspi_dma_rx_callback(void *cookie)
 514 {
 515         struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
 516
 517         complete(&fsl_lpspi->dma_rx_completion);
 518 }
 519
 520 static void fsl_lpspi_dma_tx_callback(void *cookie)
 521 {
 522         struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
 523
 524         complete(&fsl_lpspi->dma_tx_completion);
 525 }
 526
 527 static int fsl_lpspi_calculate_timeout(struct fsl_lpspi_data *fsl_lpspi,
 528                                        int size)
 529 {
 530         unsigned long timeout = 0;
 531
 532         /* Time with actual data transfer and CS change delay related to HW */
 533         timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz;
 534
 535         /* Add extra second for scheduler related activities */
 536         timeout += 1;
 537
 538         /* Double calculated timeout */
 539         return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
 540 }
 541
 542 static int fsl_lpspi_dma_transfer(struct spi_controller *controller,
 543                                 struct fsl_lpspi_data *fsl_lpspi,
 544                                 struct spi_transfer *transfer)
 545 {
 546         struct dma_async_tx_descriptor *desc_tx, *desc_rx;
 547         unsigned long transfer_timeout;
 548         unsigned long timeout;
 549         struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
 550         int ret;
 551
 552         ret = fsl_lpspi_dma_configure(controller);
 553         if (ret)
 554                 return ret;
 555
 556         desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
 557                                 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
 558                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 559         if (!desc_rx)
 560                 return -EINVAL;
 561
 562         desc_rx->callback = fsl_lpspi_dma_rx_callback;
 563         desc_rx->callback_param = (void *)fsl_lpspi;
 564         dmaengine_submit(desc_rx);
 565         reinit_completion(&fsl_lpspi->dma_rx_completion);
 566         dma_async_issue_pending(controller->dma_rx);
 567
 568         desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
 569                                 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
 570                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 571         if (!desc_tx) {
 572                 dmaengine_terminate_all(controller->dma_tx);
 573                 return -EINVAL;
 574         }
 575
 576         desc_tx->callback = fsl_lpspi_dma_tx_callback;
 577         desc_tx->callback_param = (void *)fsl_lpspi;
 578         dmaengine_submit(desc_tx);
 579         reinit_completion(&fsl_lpspi->dma_tx_completion);
 580         dma_async_issue_pending(controller->dma_tx);
 581
 582         fsl_lpspi->slave_aborted = false;
 583
 584         if (!fsl_lpspi->is_slave) {
 585                 transfer_timeout = fsl_lpspi_calculate_timeout(fsl_lpspi,
 586                                                                transfer->len);
 587
 588                 /* Wait eDMA to finish the data transfer.*/
 589                 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion,
 590                                                       transfer_timeout);
 591                 if (!timeout) {
 592                         dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n");
 593                         dmaengine_terminate_all(controller->dma_tx);
 594                         dmaengine_terminate_all(controller->dma_rx);
 595                         fsl_lpspi_reset(fsl_lpspi);
 596                         return -ETIMEDOUT;
 597                 }
 598
 599                 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion,
 600                                                       transfer_timeout);
 601                 if (!timeout) {
 602                         dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n");
 603                         dmaengine_terminate_all(controller->dma_tx);
 604                         dmaengine_terminate_all(controller->dma_rx);
 605                         fsl_lpspi_reset(fsl_lpspi);
 606                         return -ETIMEDOUT;
 607                 }
 608         } else {
 609                 if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) ||
 610                         fsl_lpspi->slave_aborted) {
 611                         dev_dbg(fsl_lpspi->dev,
 612                                 "I/O Error in DMA TX interrupted\n");
 613                         dmaengine_terminate_all(controller->dma_tx);
 614                         dmaengine_terminate_all(controller->dma_rx);
 615                         fsl_lpspi_reset(fsl_lpspi);
 616                         return -EINTR;
 617                 }
 618
 619                 if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) ||
 620                         fsl_lpspi->slave_aborted) {
 621                         dev_dbg(fsl_lpspi->dev,
 622                                 "I/O Error in DMA RX interrupted\n");
 623                         dmaengine_terminate_all(controller->dma_tx);
 624                         dmaengine_terminate_all(controller->dma_rx);
 625                         fsl_lpspi_reset(fsl_lpspi);
 626                         return -EINTR;
 627                 }
 628         }
 629
 630         fsl_lpspi_reset(fsl_lpspi);
 631
 632         return 0;
 633 }
 634
 635 static void fsl_lpspi_dma_exit(struct spi_controller *controller)
 636 {
 637         if (controller->dma_rx) {
 638                 dma_release_channel(controller->dma_rx);
 639                 controller->dma_rx = NULL;
 640         }
 641
 642         if (controller->dma_tx) {
 643                 dma_release_channel(controller->dma_tx);
 644                 controller->dma_tx = NULL;
 645         }
 646 }
 647
 648 static int fsl_lpspi_dma_init(struct device *dev,
 649                               struct fsl_lpspi_data *fsl_lpspi,
 650                               struct spi_controller *controller)
 651 {
 652         int ret;
 653
 654         /* Prepare for TX DMA: */
 655         controller->dma_tx = dma_request_chan(dev, "tx");
 656         if (IS_ERR(controller->dma_tx)) {
 657                 ret = PTR_ERR(controller->dma_tx);
 658                 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
 659                 controller->dma_tx = NULL;
 660                 goto err;
 661         }
 662
 663         /* Prepare for RX DMA: */
 664         controller->dma_rx = dma_request_chan(dev, "rx");
 665         if (IS_ERR(controller->dma_rx)) {
 666                 ret = PTR_ERR(controller->dma_rx);
 667                 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
 668                 controller->dma_rx = NULL;
 669                 goto err;
 670         }
 671
 672         init_completion(&fsl_lpspi->dma_rx_completion);
 673         init_completion(&fsl_lpspi->dma_tx_completion);
 674         controller->can_dma = fsl_lpspi_can_dma;
 675         controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES;
 676
 677         return 0;
 678 err:
 679         fsl_lpspi_dma_exit(controller);
 680         return ret;
 681 }
 682
 683 static int fsl_lpspi_pio_transfer(struct spi_controller *controller,
 684                                   struct spi_transfer *t)
 685 {
 686         struct fsl_lpspi_data *fsl_lpspi =
 687                                 spi_controller_get_devdata(controller);
 688         int ret;
 689
 690         fsl_lpspi->tx_buf = t->tx_buf;
 691         fsl_lpspi->rx_buf = t->rx_buf;
 692         fsl_lpspi->remain = t->len;
 693
 694         reinit_completion(&fsl_lpspi->xfer_done);
 695         fsl_lpspi->slave_aborted = false;
 696
 697         fsl_lpspi_write_tx_fifo(fsl_lpspi);
 698
 699         ret = fsl_lpspi_wait_for_completion(controller);
 700         if (ret)
 701                 return ret;
 702
 703         fsl_lpspi_reset(fsl_lpspi);
 704
 705         return 0;
 706 }
 707
 708 static int fsl_lpspi_transfer_one(struct spi_controller *controller,
 709                                   struct spi_device *spi,
 710                                   struct spi_transfer *t)
 711 {
 712         struct fsl_lpspi_data *fsl_lpspi =
 713                                         spi_controller_get_devdata(controller);
 714         int ret;
 715
 716         fsl_lpspi->is_first_byte = true;
 717         ret = fsl_lpspi_setup_transfer(controller, spi, t);
 718         if (ret < 0)
 719                 return ret;
 720
 721         fsl_lpspi_set_cmd(fsl_lpspi);
 722         fsl_lpspi->is_first_byte = false;
 723
 724         if (fsl_lpspi->usedma)
 725                 ret = fsl_lpspi_dma_transfer(controller, fsl_lpspi, t);
 726         else
 727                 ret = fsl_lpspi_pio_transfer(controller, t);
 728         if (ret < 0)
 729                 return ret;
 730
 731         return 0;
 732 }
 733
 734 static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
 735 {
 736         u32 temp_SR, temp_IER;
 737         struct fsl_lpspi_data *fsl_lpspi = dev_id;
 738
 739         temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
 740         fsl_lpspi_intctrl(fsl_lpspi, 0);
 741         temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);
 742
 743         fsl_lpspi_read_rx_fifo(fsl_lpspi);
 744
 745         if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) {
 746                 fsl_lpspi_write_tx_fifo(fsl_lpspi);
 747                 return IRQ_HANDLED;
 748         }
 749
 750         if (temp_SR & SR_MBF ||
 751             readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) {
 752                 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
 753                 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
 754                 return IRQ_HANDLED;
 755         }
 756
 757         if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) {
 758                 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
 759                 complete(&fsl_lpspi->xfer_done);
 760                 return IRQ_HANDLED;
 761         }
 762
 763         return IRQ_NONE;
 764 }
 765
 766 #ifdef CONFIG_PM
 767 static int fsl_lpspi_runtime_resume(struct device *dev)
 768 {
 769         struct spi_controller *controller = dev_get_drvdata(dev);
 770         struct fsl_lpspi_data *fsl_lpspi;
 771         int ret;
 772
 773         fsl_lpspi = spi_controller_get_devdata(controller);
 774
 775         ret = clk_prepare_enable(fsl_lpspi->clk_per);
 776         if (ret)
 777                 return ret;
 778
 779         ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
 780         if (ret) {
 781                 clk_disable_unprepare(fsl_lpspi->clk_per);
 782                 return ret;
 783         }
 784
 785         return 0;
 786 }
 787
 788 static int fsl_lpspi_runtime_suspend(struct device *dev)
 789 {
 790         struct spi_controller *controller = dev_get_drvdata(dev);
 791         struct fsl_lpspi_data *fsl_lpspi;
 792
 793         fsl_lpspi = spi_controller_get_devdata(controller);
 794
 795         clk_disable_unprepare(fsl_lpspi->clk_per);
 796         clk_disable_unprepare(fsl_lpspi->clk_ipg);
 797
 798         return 0;
 799 }
 800 #endif
 801
 802 static int fsl_lpspi_init_rpm(struct fsl_lpspi_data *fsl_lpspi)
 803 {
 804         struct device *dev = fsl_lpspi->dev;
 805
 806         pm_runtime_enable(dev);
 807         pm_runtime_set_autosuspend_delay(dev, FSL_LPSPI_RPM_TIMEOUT);
 808         pm_runtime_use_autosuspend(dev);
 809
 810         return 0;
 811 }
 812
 813 static int fsl_lpspi_probe(struct platform_device *pdev)
 814 {
 815         struct fsl_lpspi_data *fsl_lpspi;
 816         struct spi_controller *controller;
 817         struct resource *res;
 818         int ret, irq;
 819         u32 temp;
 820         bool is_slave;
 821
 822         is_slave = of_property_read_bool((&pdev->dev)->of_node, "spi-slave");
 823         if (is_slave)
 824                 controller = spi_alloc_slave(&pdev->dev,
 825                                         sizeof(struct fsl_lpspi_data));
 826         else
 827                 controller = spi_alloc_master(&pdev->dev,
 828                                         sizeof(struct fsl_lpspi_data));
 829
 830         if (!controller)
 831                 return -ENOMEM;
 832
 833         platform_set_drvdata(pdev, controller);
 834
 835         fsl_lpspi = spi_controller_get_devdata(controller);
 836         fsl_lpspi->dev = &pdev->dev;
 837         fsl_lpspi->is_slave = is_slave;
 838
 839         controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
 840         controller->transfer_one = fsl_lpspi_transfer_one;
 841         controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
 842         controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
 843         controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 844         controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
 845         controller->dev.of_node = pdev->dev.of_node;
 846         controller->bus_num = pdev->id;
 847         controller->slave_abort = fsl_lpspi_slave_abort;
 848         if (!fsl_lpspi->is_slave)
 849                 controller->use_gpio_descriptors = true;
 850
 851         init_completion(&fsl_lpspi->xfer_done);
 852
 853         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 854         fsl_lpspi->base = devm_ioremap_resource(&pdev->dev, res);
 855         if (IS_ERR(fsl_lpspi->base)) {
 856                 ret = PTR_ERR(fsl_lpspi->base);
 857                 goto out_controller_put;
 858         }
 859         fsl_lpspi->base_phys = res->start;
 860
 861         irq = platform_get_irq(pdev, 0);
 862         if (irq < 0) {
 863                 ret = irq;
 864                 goto out_controller_put;
 865         }
 866
 867         ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0,
 868                                dev_name(&pdev->dev), fsl_lpspi);
 869         if (ret) {
 870                 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
 871                 goto out_controller_put;
 872         }
 873
 874         fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per");
 875         if (IS_ERR(fsl_lpspi->clk_per)) {
 876                 ret = PTR_ERR(fsl_lpspi->clk_per);
 877                 goto out_controller_put;
 878         }
 879
 880         fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
 881         if (IS_ERR(fsl_lpspi->clk_ipg)) {
 882                 ret = PTR_ERR(fsl_lpspi->clk_ipg);
 883                 goto out_controller_put;
 884         }
 885
 886         /* enable the clock */
 887         ret = fsl_lpspi_init_rpm(fsl_lpspi);
 888         if (ret)
 889                 goto out_controller_put;
 890
 891         ret = pm_runtime_get_sync(fsl_lpspi->dev);
 892         if (ret < 0) {
 893                 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
 894                 goto out_pm_get;
 895         }
 896
 897         temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
 898         fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
 899         fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
 900
 901         ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller);
 902         if (ret == -EPROBE_DEFER)
 903                 goto out_pm_get;
 904
 905         if (ret < 0)
 906                 dev_err(&pdev->dev, "dma setup error %d, use pio\n", ret);
 907
 908         ret = devm_spi_register_controller(&pdev->dev, controller);
 909         if (ret < 0) {
 910                 dev_err(&pdev->dev, "spi_register_controller error.\n");
 911                 goto out_pm_get;
 912         }
 913
 914         pm_runtime_mark_last_busy(fsl_lpspi->dev);
 915         pm_runtime_put_autosuspend(fsl_lpspi->dev);
 916
 917         return 0;
 918
 919 out_pm_get:
 920         pm_runtime_dont_use_autosuspend(fsl_lpspi->dev);
 921         pm_runtime_put_sync(fsl_lpspi->dev);
 922         pm_runtime_disable(fsl_lpspi->dev);
 923 out_controller_put:
 924         spi_controller_put(controller);
 925
 926         return ret;
 927 }
 928
 929 static int fsl_lpspi_remove(struct platform_device *pdev)
 930 {
 931         struct spi_controller *controller = platform_get_drvdata(pdev);
 932         struct fsl_lpspi_data *fsl_lpspi =
 933                                 spi_controller_get_devdata(controller);
 934
 935         pm_runtime_disable(fsl_lpspi->dev);
 936
 937         spi_master_put(controller);
 938
 939         return 0;
 940 }
 941
 942 #ifdef CONFIG_PM_SLEEP
 943 static int fsl_lpspi_suspend(struct device *dev)
 944 {
 945         int ret;
 946
 947         pinctrl_pm_select_sleep_state(dev);
 948         ret = pm_runtime_force_suspend(dev);
 949         return ret;
 950 }
 951
 952 static int fsl_lpspi_resume(struct device *dev)
 953 {
 954         int ret;
 955
 956         ret = pm_runtime_force_resume(dev);
 957         if (ret) {
 958                 dev_err(dev, "Error in resume: %d\n", ret);
 959                 return ret;
 960         }
 961
 962         pinctrl_pm_select_default_state(dev);
 963
 964         return 0;
 965 }
 966 #endif /* CONFIG_PM_SLEEP */
 967
 968 static const struct dev_pm_ops fsl_lpspi_pm_ops = {
 969         SET_RUNTIME_PM_OPS(fsl_lpspi_runtime_suspend,
 970                                 fsl_lpspi_runtime_resume, NULL)
 971         SET_SYSTEM_SLEEP_PM_OPS(fsl_lpspi_suspend, fsl_lpspi_resume)
 972 };
 973
 974 static struct platform_driver fsl_lpspi_driver = {
 975         .driver = {
 976                 .name = DRIVER_NAME,
 977                 .of_match_table = fsl_lpspi_dt_ids,
 978                 .pm = &fsl_lpspi_pm_ops,
 979         },
 980         .probe = fsl_lpspi_probe,
 981         .remove = fsl_lpspi_remove,
 982 };
 983 module_platform_driver(fsl_lpspi_driver);
 984
 985 MODULE_DESCRIPTION("LPSPI Controller driver");
 986 MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
 987 MODULE_LICENSE("GPL");