1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef DW_SPI_HEADER_H
3 #define DW_SPI_HEADER_H
5 #include <linux/completion.h>
6 #include <linux/debugfs.h>
7 #include <linux/irqreturn.h>
9 #include <linux/scatterlist.h>
11 /* Register offsets */
12 #define DW_SPI_CTRLR0 0x00
13 #define DW_SPI_CTRLR1 0x04
14 #define DW_SPI_SSIENR 0x08
15 #define DW_SPI_MWCR 0x0c
16 #define DW_SPI_SER 0x10
17 #define DW_SPI_BAUDR 0x14
18 #define DW_SPI_TXFTLR 0x18
19 #define DW_SPI_RXFTLR 0x1c
20 #define DW_SPI_TXFLR 0x20
21 #define DW_SPI_RXFLR 0x24
22 #define DW_SPI_SR 0x28
23 #define DW_SPI_IMR 0x2c
24 #define DW_SPI_ISR 0x30
25 #define DW_SPI_RISR 0x34
26 #define DW_SPI_TXOICR 0x38
27 #define DW_SPI_RXOICR 0x3c
28 #define DW_SPI_RXUICR 0x40
29 #define DW_SPI_MSTICR 0x44
30 #define DW_SPI_ICR 0x48
31 #define DW_SPI_DMACR 0x4c
32 #define DW_SPI_DMATDLR 0x50
33 #define DW_SPI_DMARDLR 0x54
34 #define DW_SPI_IDR 0x58
35 #define DW_SPI_VERSION 0x5c
36 #define DW_SPI_DR 0x60
37 #define DW_SPI_CS_OVERRIDE 0xf4
39 /* Bit fields in CTRLR0 */
40 #define SPI_DFS_OFFSET 0
42 #define SPI_FRF_OFFSET 4
43 #define SPI_FRF_SPI 0x0
44 #define SPI_FRF_SSP 0x1
45 #define SPI_FRF_MICROWIRE 0x2
46 #define SPI_FRF_RESV 0x3
48 #define SPI_MODE_OFFSET 6
49 #define SPI_SCPH_OFFSET 6
50 #define SPI_SCOL_OFFSET 7
52 #define SPI_TMOD_OFFSET 8
53 #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
54 #define SPI_TMOD_TR 0x0 /* xmit & recv */
55 #define SPI_TMOD_TO 0x1 /* xmit only */
56 #define SPI_TMOD_RO 0x2 /* recv only */
57 #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
59 #define SPI_SLVOE_OFFSET 10
60 #define SPI_SRL_OFFSET 11
61 #define SPI_CFS_OFFSET 12
63 /* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */
64 #define DWC_SSI_CTRLR0_SRL_OFFSET 13
65 #define DWC_SSI_CTRLR0_TMOD_OFFSET 10
66 #define DWC_SSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
67 #define DWC_SSI_CTRLR0_SCPOL_OFFSET 9
68 #define DWC_SSI_CTRLR0_SCPH_OFFSET 8
69 #define DWC_SSI_CTRLR0_FRF_OFFSET 6
70 #define DWC_SSI_CTRLR0_DFS_OFFSET 0
72 /* Bit fields in SR, 7 bits */
73 #define SR_MASK 0x7f /* cover 7 bits */
74 #define SR_BUSY (1 << 0)
75 #define SR_TF_NOT_FULL (1 << 1)
76 #define SR_TF_EMPT (1 << 2)
77 #define SR_RF_NOT_EMPT (1 << 3)
78 #define SR_RF_FULL (1 << 4)
79 #define SR_TX_ERR (1 << 5)
80 #define SR_DCOL (1 << 6)
82 /* Bit fields in ISR, IMR, RISR, 7 bits */
83 #define SPI_INT_TXEI (1 << 0)
84 #define SPI_INT_TXOI (1 << 1)
85 #define SPI_INT_RXUI (1 << 2)
86 #define SPI_INT_RXOI (1 << 3)
87 #define SPI_INT_RXFI (1 << 4)
88 #define SPI_INT_MSTI (1 << 5)
90 /* Bit fields in DMACR */
91 #define SPI_DMA_RDMAE (1 << 0)
92 #define SPI_DMA_TDMAE (1 << 1)
94 /* TX RX interrupt level threshold, max can be 256 */
95 #define SPI_INT_THRESHOLD 32
104 struct dw_spi_dma_ops {
105 int (*dma_init)(struct device *dev, struct dw_spi *dws);
106 void (*dma_exit)(struct dw_spi *dws);
107 int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
108 bool (*can_dma)(struct spi_controller *master, struct spi_device *spi,
109 struct spi_transfer *xfer);
110 int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
111 void (*dma_stop)(struct dw_spi *dws);
115 struct spi_controller *master;
116 enum dw_ssi_type type;
121 u32 fifo_len; /* depth of the FIFO buffer */
122 u32 max_freq; /* max bus freq supported */
125 u32 reg_io_width; /* DR I/O width in bytes */
127 u16 num_cs; /* supported slave numbers */
128 void (*set_cs)(struct spi_device *spi, bool enable);
129 u32 (*update_cr0)(struct spi_controller *master, struct spi_device *spi,
130 struct spi_transfer *transfer);
132 /* Current message transfer state info */
140 u8 n_bytes; /* current is a 1/2 bytes op */
141 irqreturn_t (*transfer_handler)(struct dw_spi *dws);
142 u32 current_freq; /* frequency in hz */
145 struct dma_chan *txchan;
147 struct dma_chan *rxchan;
149 unsigned long dma_chan_busy;
150 dma_addr_t dma_addr; /* phy address of the Data register */
151 const struct dw_spi_dma_ops *dma_ops;
152 struct completion dma_completion;
154 #ifdef CONFIG_DEBUG_FS
155 struct dentry *debugfs;
156 struct debugfs_regset32 regset;
160 static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
162 return __raw_readl(dws->regs + offset);
165 static inline u16 dw_readw(struct dw_spi *dws, u32 offset)
167 return __raw_readw(dws->regs + offset);
170 static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
172 __raw_writel(val, dws->regs + offset);
175 static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)
177 __raw_writew(val, dws->regs + offset);
180 static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
182 switch (dws->reg_io_width) {
184 return dw_readw(dws, offset);
187 return dw_readl(dws, offset);
191 static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
193 switch (dws->reg_io_width) {
195 dw_writew(dws, offset, val);
199 dw_writel(dws, offset, val);
204 static inline void spi_enable_chip(struct dw_spi *dws, int enable)
206 dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
209 static inline void spi_set_clk(struct dw_spi *dws, u16 div)
211 dw_writel(dws, DW_SPI_BAUDR, div);
214 /* Disable IRQ bits */
215 static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
219 new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
220 dw_writel(dws, DW_SPI_IMR, new_mask);
223 /* Enable IRQ bits */
224 static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
228 new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
229 dw_writel(dws, DW_SPI_IMR, new_mask);
233 * This does disable the SPI controller, interrupts, and re-enable the
234 * controller back. Transmit and receive FIFO buffers are cleared when the
235 * device is disabled.
237 static inline void spi_reset_chip(struct dw_spi *dws)
239 spi_enable_chip(dws, 0);
240 spi_mask_intr(dws, 0xff);
241 spi_enable_chip(dws, 1);
244 static inline void spi_shutdown_chip(struct dw_spi *dws)
246 spi_enable_chip(dws, 0);
250 extern void dw_spi_set_cs(struct spi_device *spi, bool enable);
251 extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
252 extern void dw_spi_remove_host(struct dw_spi *dws);
253 extern int dw_spi_suspend_host(struct dw_spi *dws);
254 extern int dw_spi_resume_host(struct dw_spi *dws);
255 extern u32 dw_spi_update_cr0(struct spi_controller *master,
256 struct spi_device *spi,
257 struct spi_transfer *transfer);
258 extern u32 dw_spi_update_cr0_v1_01a(struct spi_controller *master,
259 struct spi_device *spi,
260 struct spi_transfer *transfer);
262 #ifdef CONFIG_SPI_DW_DMA
264 extern void dw_spi_dma_setup_mfld(struct dw_spi *dws);
265 extern void dw_spi_dma_setup_generic(struct dw_spi *dws);
269 static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {}
270 static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {}
272 #endif /* !CONFIG_SPI_DW_DMA */
274 #endif /* DW_SPI_HEADER_H */