drivers/spi/spi-dw.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Designware SPI core controller driver (refer pxa2xx_spi.c)
   4  *
   5  * Copyright (c) 2009, Intel Corporation.
   6  */
   7
   8 #include <linux/dma-mapping.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/module.h>
  11 #include <linux/highmem.h>
  12 #include <linux/delay.h>
  13 #include <linux/slab.h>
  14 #include <linux/spi/spi.h>
  15
  16 #include "spi-dw.h"
  17
  18 #ifdef CONFIG_DEBUG_FS
  19 #include <linux/debugfs.h>
  20 #endif
  21
  22 /* Slave spi_dev related */
  23 struct chip_data {
  24         u8 tmode;               /* TR/TO/RO/EEPROM */
  25         u8 type;                /* SPI/SSP/MicroWire */
  26
  27         u8 poll_mode;           /* 1 means use poll mode */
  28
  29         u16 clk_div;            /* baud rate divider */
  30         u32 speed_hz;           /* baud rate */
  31         void (*cs_control)(u32 command);
  32 };
  33
  34 #ifdef CONFIG_DEBUG_FS
  35 #define SPI_REGS_BUFSIZE        1024
  36 static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
  37                 size_t count, loff_t *ppos)
  38 {
  39         struct dw_spi *dws = file->private_data;
  40         char *buf;
  41         u32 len = 0;
  42         ssize_t ret;
  43
  44         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
  45         if (!buf)
  46                 return 0;
  47
  48         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  49                         "%s registers:\n", dev_name(&dws->master->dev));
  50         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  51                         "=================================\n");
  52         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  53                         "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
  54         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  55                         "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
  56         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  57                         "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
  58         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  59                         "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
  60         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  61                         "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
  62         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  63                         "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
  64         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  65                         "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
  66         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  67                         "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
  68         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  69                         "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
  70         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  71                         "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
  72         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  73                         "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
  74         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  75                         "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
  76         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  77                         "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
  78         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  79                         "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
  80         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  81                         "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
  82         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  83                         "=================================\n");
  84
  85         ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
  86         kfree(buf);
  87         return ret;
  88 }
  89
  90 static const struct file_operations dw_spi_regs_ops = {
  91         .owner          = THIS_MODULE,
  92         .open           = simple_open,
  93         .read           = dw_spi_show_regs,
  94         .llseek         = default_llseek,
  95 };
  96
  97 static int dw_spi_debugfs_init(struct dw_spi *dws)
  98 {
  99         char name[32];
 100
 101         snprintf(name, 32, "dw_spi%d", dws->master->bus_num);
 102         dws->debugfs = debugfs_create_dir(name, NULL);
 103         if (!dws->debugfs)
 104                 return -ENOMEM;
 105
 106         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 107                 dws->debugfs, (void *)dws, &dw_spi_regs_ops);
 108         return 0;
 109 }
 110
 111 static void dw_spi_debugfs_remove(struct dw_spi *dws)
 112 {
 113         debugfs_remove_recursive(dws->debugfs);
 114 }
 115
 116 #else
 117 static inline int dw_spi_debugfs_init(struct dw_spi *dws)
 118 {
 119         return 0;
 120 }
 121
 122 static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
 123 {
 124 }
 125 #endif /* CONFIG_DEBUG_FS */
 126
 127 void dw_spi_set_cs(struct spi_device *spi, bool enable)
 128 {
 129         struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
 130         struct chip_data *chip = spi_get_ctldata(spi);
 131
 132         /* Chip select logic is inverted from spi_set_cs() */
 133         if (chip && chip->cs_control)
 134                 chip->cs_control(!enable);
 135
 136         if (!enable)
 137                 dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
 138         else if (dws->cs_override)
 139                 dw_writel(dws, DW_SPI_SER, 0);
 140 }
 141 EXPORT_SYMBOL_GPL(dw_spi_set_cs);
 142
 143 /* Return the max entries we can fill into tx fifo */
 144 static inline u32 tx_max(struct dw_spi *dws)
 145 {
 146         u32 tx_left, tx_room, rxtx_gap;
 147
 148         tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
 149         tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
 150
 151         /*
 152          * Another concern is about the tx/rx mismatch, we
 153          * though to use (dws->fifo_len - rxflr - txflr) as
 154          * one maximum value for tx, but it doesn't cover the
 155          * data which is out of tx/rx fifo and inside the
 156          * shift registers. So a control from sw point of
 157          * view is taken.
 158          */
 159         rxtx_gap =  ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
 160                         / dws->n_bytes;
 161
 162         return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
 163 }
 164
 165 /* Return the max entries we should read out of rx fifo */
 166 static inline u32 rx_max(struct dw_spi *dws)
 167 {
 168         u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
 169
 170         return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
 171 }
 172
 173 static void dw_writer(struct dw_spi *dws)
 174 {
 175         u32 max;
 176         u16 txw = 0;
 177
 178         spin_lock(&dws->buf_lock);
 179         max = tx_max(dws);
 180         while (max--) {
 181                 /* Set the tx word if the transfer's original "tx" is not null */
 182                 if (dws->tx_end - dws->len) {
 183                         if (dws->n_bytes == 1)
 184                                 txw = *(u8 *)(dws->tx);
 185                         else
 186                                 txw = *(u16 *)(dws->tx);
 187                 }
 188                 dw_write_io_reg(dws, DW_SPI_DR, txw);
 189                 dws->tx += dws->n_bytes;
 190         }
 191         spin_unlock(&dws->buf_lock);
 192 }
 193
 194 static void dw_reader(struct dw_spi *dws)
 195 {
 196         u32 max;
 197         u16 rxw;
 198
 199         spin_lock(&dws->buf_lock);
 200         max = rx_max(dws);
 201         while (max--) {
 202                 rxw = dw_read_io_reg(dws, DW_SPI_DR);
 203                 /* Care rx only if the transfer's original "rx" is not null */
 204                 if (dws->rx_end - dws->len) {
 205                         if (dws->n_bytes == 1)
 206                                 *(u8 *)(dws->rx) = rxw;
 207                         else
 208                                 *(u16 *)(dws->rx) = rxw;
 209                 }
 210                 dws->rx += dws->n_bytes;
 211         }
 212         spin_unlock(&dws->buf_lock);
 213 }
 214
 215 static void int_error_stop(struct dw_spi *dws, const char *msg)
 216 {
 217         spi_reset_chip(dws);
 218
 219         dev_err(&dws->master->dev, "%s\n", msg);
 220         dws->master->cur_msg->status = -EIO;
 221         spi_finalize_current_transfer(dws->master);
 222 }
 223
 224 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
 225 {
 226         u16 irq_status = dw_readl(dws, DW_SPI_ISR);
 227
 228         /* Error handling */
 229         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
 230                 dw_readl(dws, DW_SPI_ICR);
 231                 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
 232                 return IRQ_HANDLED;
 233         }
 234
 235         dw_reader(dws);
 236         if (dws->rx_end == dws->rx) {
 237                 spi_mask_intr(dws, SPI_INT_TXEI);
 238                 spi_finalize_current_transfer(dws->master);
 239                 return IRQ_HANDLED;
 240         }
 241         if (irq_status & SPI_INT_TXEI) {
 242                 spi_mask_intr(dws, SPI_INT_TXEI);
 243                 dw_writer(dws);
 244                 /* Enable TX irq always, it will be disabled when RX finished */
 245                 spi_umask_intr(dws, SPI_INT_TXEI);
 246         }
 247
 248         return IRQ_HANDLED;
 249 }
 250
 251 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
 252 {
 253         struct spi_controller *master = dev_id;
 254         struct dw_spi *dws = spi_controller_get_devdata(master);
 255         u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;
 256
 257         if (!irq_status)
 258                 return IRQ_NONE;
 259
 260         if (!master->cur_msg) {
 261                 spi_mask_intr(dws, SPI_INT_TXEI);
 262                 return IRQ_HANDLED;
 263         }
 264
 265         return dws->transfer_handler(dws);
 266 }
 267
 268 /* Must be called inside pump_transfers() */
 269 static int poll_transfer(struct dw_spi *dws)
 270 {
 271         do {
 272                 dw_writer(dws);
 273                 dw_reader(dws);
 274                 cpu_relax();
 275         } while (dws->rx_end > dws->rx);
 276
 277         return 0;
 278 }
 279
 280 static int dw_spi_transfer_one(struct spi_controller *master,
 281                 struct spi_device *spi, struct spi_transfer *transfer)
 282 {
 283         struct dw_spi *dws = spi_controller_get_devdata(master);
 284         struct chip_data *chip = spi_get_ctldata(spi);
 285         unsigned long flags;
 286         u8 imask = 0;
 287         u16 txlevel = 0;
 288         u32 cr0;
 289         int ret;
 290
 291         dws->dma_mapped = 0;
 292         spin_lock_irqsave(&dws->buf_lock, flags);
 293         dws->tx = (void *)transfer->tx_buf;
 294         dws->tx_end = dws->tx + transfer->len;
 295         dws->rx = transfer->rx_buf;
 296         dws->rx_end = dws->rx + transfer->len;
 297         dws->len = transfer->len;
 298         spin_unlock_irqrestore(&dws->buf_lock, flags);
 299
 300         /* Ensure dw->rx and dw->rx_end are visible */
 301         smp_mb();
 302
 303         spi_enable_chip(dws, 0);
 304
 305         /* Handle per transfer options for bpw and speed */
 306         if (transfer->speed_hz != dws->current_freq) {
 307                 if (transfer->speed_hz != chip->speed_hz) {
 308                         /* clk_div doesn't support odd number */
 309                         chip->clk_div = (DIV_ROUND_UP(dws->max_freq, transfer->speed_hz) + 1) & 0xfffe;
 310                         chip->speed_hz = transfer->speed_hz;
 311                 }
 312                 dws->current_freq = transfer->speed_hz;
 313                 spi_set_clk(dws, chip->clk_div);
 314         }
 315
 316         dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
 317         dws->dma_width = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
 318
 319         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
 320         cr0 = (transfer->bits_per_word - 1)
 321                 | (chip->type << SPI_FRF_OFFSET)
 322                 | ((((spi->mode & SPI_CPOL) ? 1 : 0) << SPI_SCOL_OFFSET) |
 323                         (((spi->mode & SPI_CPHA) ? 1 : 0) << SPI_SCPH_OFFSET) |
 324                         (((spi->mode & SPI_LOOP) ? 1 : 0) << SPI_SRL_OFFSET))
 325                 | (chip->tmode << SPI_TMOD_OFFSET);
 326
 327         /*
 328          * Adjust transfer mode if necessary. Requires platform dependent
 329          * chipselect mechanism.
 330          */
 331         if (chip->cs_control) {
 332                 if (dws->rx && dws->tx)
 333                         chip->tmode = SPI_TMOD_TR;
 334                 else if (dws->rx)
 335                         chip->tmode = SPI_TMOD_RO;
 336                 else
 337                         chip->tmode = SPI_TMOD_TO;
 338
 339                 cr0 &= ~SPI_TMOD_MASK;
 340                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
 341         }
 342
 343         dw_writel(dws, DW_SPI_CTRL0, cr0);
 344
 345         /* Check if current transfer is a DMA transaction */
 346         if (master->can_dma && master->can_dma(master, spi, transfer))
 347                 dws->dma_mapped = master->cur_msg_mapped;
 348
 349         /* For poll mode just disable all interrupts */
 350         spi_mask_intr(dws, 0xff);
 351
 352         /*
 353          * Interrupt mode
 354          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
 355          */
 356         if (dws->dma_mapped) {
 357                 ret = dws->dma_ops->dma_setup(dws, transfer);
 358                 if (ret < 0) {
 359                         spi_enable_chip(dws, 1);
 360                         return ret;
 361                 }
 362         } else if (!chip->poll_mode) {
 363                 txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
 364                 dw_writel(dws, DW_SPI_TXFLTR, txlevel);
 365
 366                 /* Set the interrupt mask */
 367                 imask |= SPI_INT_TXEI | SPI_INT_TXOI |
 368                          SPI_INT_RXUI | SPI_INT_RXOI;
 369                 spi_umask_intr(dws, imask);
 370
 371                 dws->transfer_handler = interrupt_transfer;
 372         }
 373
 374         spi_enable_chip(dws, 1);
 375
 376         if (dws->dma_mapped) {
 377                 ret = dws->dma_ops->dma_transfer(dws, transfer);
 378                 if (ret < 0)
 379                         return ret;
 380         }
 381
 382         if (chip->poll_mode)
 383                 return poll_transfer(dws);
 384
 385         return 1;
 386 }
 387
 388 static void dw_spi_handle_err(struct spi_controller *master,
 389                 struct spi_message *msg)
 390 {
 391         struct dw_spi *dws = spi_controller_get_devdata(master);
 392
 393         if (dws->dma_mapped)
 394                 dws->dma_ops->dma_stop(dws);
 395
 396         spi_reset_chip(dws);
 397 }
 398
 399 /* This may be called twice for each spi dev */
 400 static int dw_spi_setup(struct spi_device *spi)
 401 {
 402         struct dw_spi_chip *chip_info = NULL;
 403         struct chip_data *chip;
 404
 405         /* Only alloc on first setup */
 406         chip = spi_get_ctldata(spi);
 407         if (!chip) {
 408                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 409                 if (!chip)
 410                         return -ENOMEM;
 411                 spi_set_ctldata(spi, chip);
 412         }
 413
 414         /*
 415          * Protocol drivers may change the chip settings, so...
 416          * if chip_info exists, use it
 417          */
 418         chip_info = spi->controller_data;
 419
 420         /* chip_info doesn't always exist */
 421         if (chip_info) {
 422                 if (chip_info->cs_control)
 423                         chip->cs_control = chip_info->cs_control;
 424
 425                 chip->poll_mode = chip_info->poll_mode;
 426                 chip->type = chip_info->type;
 427         }
 428
 429         chip->tmode = SPI_TMOD_TR;
 430
 431         return 0;
 432 }
 433
 434 static void dw_spi_cleanup(struct spi_device *spi)
 435 {
 436         struct chip_data *chip = spi_get_ctldata(spi);
 437
 438         kfree(chip);
 439         spi_set_ctldata(spi, NULL);
 440 }
 441
 442 /* Restart the controller, disable all interrupts, clean rx fifo */
 443 static void spi_hw_init(struct device *dev, struct dw_spi *dws)
 444 {
 445         spi_reset_chip(dws);
 446
 447         /*
 448          * Try to detect the FIFO depth if not set by interface driver,
 449          * the depth could be from 2 to 256 from HW spec
 450          */
 451         if (!dws->fifo_len) {
 452                 u32 fifo;
 453
 454                 for (fifo = 1; fifo < 256; fifo++) {
 455                         dw_writel(dws, DW_SPI_TXFLTR, fifo);
 456                         if (fifo != dw_readl(dws, DW_SPI_TXFLTR))
 457                                 break;
 458                 }
 459                 dw_writel(dws, DW_SPI_TXFLTR, 0);
 460
 461                 dws->fifo_len = (fifo == 1) ? 0 : fifo;
 462                 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
 463         }
 464
 465         /* enable HW fixup for explicit CS deselect for Amazon's alpine chip */
 466         if (dws->cs_override)
 467                 dw_writel(dws, DW_SPI_CS_OVERRIDE, 0xF);
 468 }
 469
 470 int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
 471 {
 472         struct spi_controller *master;
 473         int ret;
 474
 475         BUG_ON(dws == NULL);
 476
 477         master = spi_alloc_master(dev, 0);
 478         if (!master)
 479                 return -ENOMEM;
 480
 481         dws->master = master;
 482         dws->type = SSI_MOTO_SPI;
 483         dws->dma_inited = 0;
 484         dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
 485         spin_lock_init(&dws->buf_lock);
 486
 487         spi_controller_set_devdata(master, dws);
 488
 489         ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev),
 490                           master);
 491         if (ret < 0) {
 492                 dev_err(dev, "can not get IRQ\n");
 493                 goto err_free_master;
 494         }
 495
 496         master->use_gpio_descriptors = true;
 497         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
 498         master->bits_per_word_mask =  SPI_BPW_RANGE_MASK(4, 16);
 499         master->bus_num = dws->bus_num;
 500         master->num_chipselect = dws->num_cs;
 501         master->setup = dw_spi_setup;
 502         master->cleanup = dw_spi_cleanup;
 503         master->set_cs = dw_spi_set_cs;
 504         master->transfer_one = dw_spi_transfer_one;
 505         master->handle_err = dw_spi_handle_err;
 506         master->max_speed_hz = dws->max_freq;
 507         master->dev.of_node = dev->of_node;
 508         master->dev.fwnode = dev->fwnode;
 509         master->flags = SPI_MASTER_GPIO_SS;
 510         master->auto_runtime_pm = true;
 511
 512         if (dws->set_cs)
 513                 master->set_cs = dws->set_cs;
 514
 515         /* Basic HW init */
 516         spi_hw_init(dev, dws);
 517
 518         if (dws->dma_ops && dws->dma_ops->dma_init) {
 519                 ret = dws->dma_ops->dma_init(dws);
 520                 if (ret) {
 521                         dev_warn(dev, "DMA init failed\n");
 522                         dws->dma_inited = 0;
 523                 } else {
 524                         master->can_dma = dws->dma_ops->can_dma;
 525                 }
 526         }
 527
 528         ret = devm_spi_register_controller(dev, master);
 529         if (ret) {
 530                 dev_err(&master->dev, "problem registering spi master\n");
 531                 goto err_dma_exit;
 532         }
 533
 534         dw_spi_debugfs_init(dws);
 535         return 0;
 536
 537 err_dma_exit:
 538         if (dws->dma_ops && dws->dma_ops->dma_exit)
 539                 dws->dma_ops->dma_exit(dws);
 540         spi_enable_chip(dws, 0);
 541         free_irq(dws->irq, master);
 542 err_free_master:
 543         spi_controller_put(master);
 544         return ret;
 545 }
 546 EXPORT_SYMBOL_GPL(dw_spi_add_host);
 547
 548 void dw_spi_remove_host(struct dw_spi *dws)
 549 {
 550         dw_spi_debugfs_remove(dws);
 551
 552         if (dws->dma_ops && dws->dma_ops->dma_exit)
 553                 dws->dma_ops->dma_exit(dws);
 554
 555         spi_shutdown_chip(dws);
 556
 557         free_irq(dws->irq, dws->master);
 558 }
 559 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
 560
 561 int dw_spi_suspend_host(struct dw_spi *dws)
 562 {
 563         int ret;
 564
 565         ret = spi_controller_suspend(dws->master);
 566         if (ret)
 567                 return ret;
 568
 569         spi_shutdown_chip(dws);
 570         return 0;
 571 }
 572 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
 573
 574 int dw_spi_resume_host(struct dw_spi *dws)
 575 {
 576         spi_hw_init(&dws->master->dev, dws);
 577         return spi_controller_resume(dws->master);
 578 }
 579 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
 580
 581 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
 582 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
 583 MODULE_LICENSE("GPL v2");