2 * Memory-mapped interface driver for DW SPI Core
4 * Copyright (c) 2010, Octasic semiconductor.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
11 #include <linux/clk.h>
12 #include <linux/err.h>
13 #include <linux/interrupt.h>
14 #include <linux/platform_device.h>
15 #include <linux/slab.h>
16 #include <linux/spi/spi.h>
17 #include <linux/scatterlist.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/module.h>
21 #include <linux/of_platform.h>
22 #include <linux/acpi.h>
23 #include <linux/property.h>
24 #include <linux/regmap.h>
28 #define DRIVER_NAME "dw_spi_mmio"
37 #define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
38 #define OCELOT_IF_SI_OWNER_OFFSET 4
39 #define JAGUAR2_IF_SI_OWNER_OFFSET 6
40 #define MSCC_IF_SI_OWNER_MASK GENMASK(1, 0)
41 #define MSCC_IF_SI_OWNER_SISL 0
42 #define MSCC_IF_SI_OWNER_SIBM 1
43 #define MSCC_IF_SI_OWNER_SIMC 2
45 #define MSCC_SPI_MST_SW_MODE 0x14
46 #define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
47 #define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) (x << 5)
50 struct regmap *syscon;
51 void __iomem *spi_mst;
55 * The Designware SPI controller (referred to as master in the documentation)
56 * automatically deasserts chip select when the tx fifo is empty. The chip
57 * selects then needs to be either driven as GPIOs or, for the first 4 using the
58 * the SPI boot controller registers. the final chip select is an OR gate
59 * between the Designware SPI controller and the SPI boot controller.
61 static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
63 struct dw_spi *dws = spi_master_get_devdata(spi->master);
64 struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
65 struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
66 u32 cs = spi->chip_select;
69 u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;
72 sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));
74 writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
77 dw_spi_set_cs(spi, enable);
80 static int dw_spi_mscc_init(struct platform_device *pdev,
81 struct dw_spi_mmio *dwsmmio,
82 const char *cpu_syscon, u32 if_si_owner_offset)
84 struct dw_spi_mscc *dwsmscc;
87 dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
91 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
92 dwsmscc->spi_mst = devm_ioremap_resource(&pdev->dev, res);
93 if (IS_ERR(dwsmscc->spi_mst)) {
94 dev_err(&pdev->dev, "SPI_MST region map failed\n");
95 return PTR_ERR(dwsmscc->spi_mst);
98 dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);
99 if (IS_ERR(dwsmscc->syscon))
100 return PTR_ERR(dwsmscc->syscon);
102 /* Deassert all CS */
103 writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
105 /* Select the owner of the SI interface */
106 regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
107 MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
108 MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);
110 dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
111 dwsmmio->priv = dwsmscc;
116 static int dw_spi_mscc_ocelot_init(struct platform_device *pdev,
117 struct dw_spi_mmio *dwsmmio)
119 return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",
120 OCELOT_IF_SI_OWNER_OFFSET);
123 static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
124 struct dw_spi_mmio *dwsmmio)
126 return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",
127 JAGUAR2_IF_SI_OWNER_OFFSET);
130 static int dw_spi_alpine_init(struct platform_device *pdev,
131 struct dw_spi_mmio *dwsmmio)
133 dwsmmio->dws.cs_override = 1;
138 static int dw_spi_mmio_probe(struct platform_device *pdev)
140 int (*init_func)(struct platform_device *pdev,
141 struct dw_spi_mmio *dwsmmio);
142 struct dw_spi_mmio *dwsmmio;
144 struct resource *mem;
148 dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
155 /* Get basic io resource and map it */
156 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
157 dws->regs = devm_ioremap_resource(&pdev->dev, mem);
158 if (IS_ERR(dws->regs)) {
159 dev_err(&pdev->dev, "SPI region map failed\n");
160 return PTR_ERR(dws->regs);
163 dws->irq = platform_get_irq(pdev, 0);
165 dev_err(&pdev->dev, "no irq resource?\n");
166 return dws->irq; /* -ENXIO */
169 dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
170 if (IS_ERR(dwsmmio->clk))
171 return PTR_ERR(dwsmmio->clk);
172 ret = clk_prepare_enable(dwsmmio->clk);
176 /* Optional clock needed to access the registers */
177 dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk");
178 if (IS_ERR(dwsmmio->pclk))
179 return PTR_ERR(dwsmmio->pclk);
180 ret = clk_prepare_enable(dwsmmio->pclk);
184 dws->bus_num = pdev->id;
186 dws->max_freq = clk_get_rate(dwsmmio->clk);
188 device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width);
192 device_property_read_u32(&pdev->dev, "num-cs", &num_cs);
194 dws->num_cs = num_cs;
196 init_func = device_get_match_data(&pdev->dev);
198 ret = init_func(pdev, dwsmmio);
203 ret = dw_spi_add_host(&pdev->dev, dws);
207 platform_set_drvdata(pdev, dwsmmio);
211 clk_disable_unprepare(dwsmmio->pclk);
213 clk_disable_unprepare(dwsmmio->clk);
217 static int dw_spi_mmio_remove(struct platform_device *pdev)
219 struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);
221 dw_spi_remove_host(&dwsmmio->dws);
222 clk_disable_unprepare(dwsmmio->pclk);
223 clk_disable_unprepare(dwsmmio->clk);
228 static const struct of_device_id dw_spi_mmio_of_match[] = {
229 { .compatible = "snps,dw-apb-ssi", },
230 { .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
231 { .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
232 { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
233 { /* end of table */}
235 MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
237 static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
241 MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);
243 static struct platform_driver dw_spi_mmio_driver = {
244 .probe = dw_spi_mmio_probe,
245 .remove = dw_spi_mmio_remove,
248 .of_match_table = dw_spi_mmio_of_match,
249 .acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match),
252 module_platform_driver(dw_spi_mmio_driver);
254 MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
255 MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
256 MODULE_LICENSE("GPL v2");