1 // SPDX-License-Identifier: GPL-2.0-only
3 * Special handling for DW DMA core
5 * Copyright (c) 2009, 2014 Intel Corporation.
8 #include <linux/completion.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/dmaengine.h>
11 #include <linux/irqreturn.h>
12 #include <linux/jiffies.h>
13 #include <linux/pci.h>
14 #include <linux/platform_data/dma-dw.h>
15 #include <linux/spi/spi.h>
16 #include <linux/types.h>
20 #define WAIT_RETRIES 5
22 #define RX_BURST_LEVEL 16
24 #define TX_BURST_LEVEL 16
26 static bool dw_spi_dma_chan_filter(struct dma_chan *chan, void *param)
28 struct dw_dma_slave *s = param;
30 if (s->dma_dev != chan->device->dev)
37 static void dw_spi_dma_maxburst_init(struct dw_spi *dws)
39 struct dma_slave_caps caps;
40 u32 max_burst, def_burst;
43 def_burst = dws->fifo_len / 2;
45 ret = dma_get_slave_caps(dws->rxchan, &caps);
46 if (!ret && caps.max_burst)
47 max_burst = caps.max_burst;
49 max_burst = RX_BURST_LEVEL;
51 dws->rxburst = min(max_burst, def_burst);
53 ret = dma_get_slave_caps(dws->txchan, &caps);
54 if (!ret && caps.max_burst)
55 max_burst = caps.max_burst;
57 max_burst = TX_BURST_LEVEL;
59 dws->txburst = min(max_burst, def_burst);
62 static int dw_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws)
64 struct dw_dma_slave dma_tx = { .dst_id = 1 }, *tx = &dma_tx;
65 struct dw_dma_slave dma_rx = { .src_id = 0 }, *rx = &dma_rx;
66 struct pci_dev *dma_dev;
70 * Get pci device for DMA controller, currently it could only
71 * be the DMA controller of Medfield
73 dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
78 dma_cap_set(DMA_SLAVE, mask);
80 /* 1. Init rx channel */
81 rx->dma_dev = &dma_dev->dev;
82 dws->rxchan = dma_request_channel(mask, dw_spi_dma_chan_filter, rx);
86 /* 2. Init tx channel */
87 tx->dma_dev = &dma_dev->dev;
88 dws->txchan = dma_request_channel(mask, dw_spi_dma_chan_filter, tx);
92 dws->master->dma_rx = dws->rxchan;
93 dws->master->dma_tx = dws->txchan;
95 init_completion(&dws->dma_completion);
97 dw_spi_dma_maxburst_init(dws);
102 dma_release_channel(dws->rxchan);
108 static int dw_spi_dma_init_generic(struct device *dev, struct dw_spi *dws)
110 dws->rxchan = dma_request_slave_channel(dev, "rx");
114 dws->txchan = dma_request_slave_channel(dev, "tx");
116 dma_release_channel(dws->rxchan);
121 dws->master->dma_rx = dws->rxchan;
122 dws->master->dma_tx = dws->txchan;
124 init_completion(&dws->dma_completion);
126 dw_spi_dma_maxburst_init(dws);
131 static void dw_spi_dma_exit(struct dw_spi *dws)
134 dmaengine_terminate_sync(dws->txchan);
135 dma_release_channel(dws->txchan);
139 dmaengine_terminate_sync(dws->rxchan);
140 dma_release_channel(dws->rxchan);
143 dw_writel(dws, DW_SPI_DMACR, 0);
146 static irqreturn_t dw_spi_dma_transfer_handler(struct dw_spi *dws)
148 u16 irq_status = dw_readl(dws, DW_SPI_ISR);
153 dw_readl(dws, DW_SPI_ICR);
156 dev_err(&dws->master->dev, "%s: FIFO overrun/underrun\n", __func__);
157 dws->master->cur_msg->status = -EIO;
158 complete(&dws->dma_completion);
162 static bool dw_spi_can_dma(struct spi_controller *master,
163 struct spi_device *spi, struct spi_transfer *xfer)
165 struct dw_spi *dws = spi_controller_get_devdata(master);
167 return xfer->len > dws->fifo_len;
170 static enum dma_slave_buswidth dw_spi_dma_convert_width(u8 n_bytes)
173 return DMA_SLAVE_BUSWIDTH_1_BYTE;
174 else if (n_bytes == 2)
175 return DMA_SLAVE_BUSWIDTH_2_BYTES;
177 return DMA_SLAVE_BUSWIDTH_UNDEFINED;
180 static int dw_spi_dma_wait(struct dw_spi *dws, struct spi_transfer *xfer)
182 unsigned long long ms;
184 ms = xfer->len * MSEC_PER_SEC * BITS_PER_BYTE;
185 do_div(ms, xfer->effective_speed_hz);
191 ms = wait_for_completion_timeout(&dws->dma_completion,
192 msecs_to_jiffies(ms));
195 dev_err(&dws->master->cur_msg->spi->dev,
196 "DMA transaction timed out\n");
203 static inline bool dw_spi_dma_tx_busy(struct dw_spi *dws)
205 return !(dw_readl(dws, DW_SPI_SR) & SR_TF_EMPT);
208 static int dw_spi_dma_wait_tx_done(struct dw_spi *dws,
209 struct spi_transfer *xfer)
211 int retry = WAIT_RETRIES;
212 struct spi_delay delay;
215 nents = dw_readl(dws, DW_SPI_TXFLR);
216 delay.unit = SPI_DELAY_UNIT_SCK;
217 delay.value = nents * dws->n_bytes * BITS_PER_BYTE;
219 while (dw_spi_dma_tx_busy(dws) && retry--)
220 spi_delay_exec(&delay, xfer);
223 dev_err(&dws->master->dev, "Tx hanged up\n");
231 * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
232 * channel will clear a corresponding bit.
234 static void dw_spi_dma_tx_done(void *arg)
236 struct dw_spi *dws = arg;
238 clear_bit(TX_BUSY, &dws->dma_chan_busy);
239 if (test_bit(RX_BUSY, &dws->dma_chan_busy))
242 dw_writel(dws, DW_SPI_DMACR, 0);
243 complete(&dws->dma_completion);
246 static struct dma_async_tx_descriptor *
247 dw_spi_dma_prepare_tx(struct dw_spi *dws, struct spi_transfer *xfer)
249 struct dma_slave_config txconf;
250 struct dma_async_tx_descriptor *txdesc;
255 memset(&txconf, 0, sizeof(txconf));
256 txconf.direction = DMA_MEM_TO_DEV;
257 txconf.dst_addr = dws->dma_addr;
258 txconf.dst_maxburst = dws->txburst;
259 txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
260 txconf.dst_addr_width = dw_spi_dma_convert_width(dws->n_bytes);
261 txconf.device_fc = false;
263 dmaengine_slave_config(dws->txchan, &txconf);
265 txdesc = dmaengine_prep_slave_sg(dws->txchan,
269 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
273 txdesc->callback = dw_spi_dma_tx_done;
274 txdesc->callback_param = dws;
279 static inline bool dw_spi_dma_rx_busy(struct dw_spi *dws)
281 return !!(dw_readl(dws, DW_SPI_SR) & SR_RF_NOT_EMPT);
284 static int dw_spi_dma_wait_rx_done(struct dw_spi *dws)
286 int retry = WAIT_RETRIES;
287 struct spi_delay delay;
288 unsigned long ns, us;
292 * It's unlikely that DMA engine is still doing the data fetching, but
293 * if it's let's give it some reasonable time. The timeout calculation
294 * is based on the synchronous APB/SSI reference clock rate, on a
295 * number of data entries left in the Rx FIFO, times a number of clock
296 * periods normally needed for a single APB read/write transaction
297 * without PREADY signal utilized (which is true for the DW APB SSI
300 nents = dw_readl(dws, DW_SPI_RXFLR);
301 ns = 4U * NSEC_PER_SEC / dws->max_freq * nents;
302 if (ns <= NSEC_PER_USEC) {
303 delay.unit = SPI_DELAY_UNIT_NSECS;
306 us = DIV_ROUND_UP(ns, NSEC_PER_USEC);
307 delay.unit = SPI_DELAY_UNIT_USECS;
308 delay.value = clamp_val(us, 0, USHRT_MAX);
311 while (dw_spi_dma_rx_busy(dws) && retry--)
312 spi_delay_exec(&delay, NULL);
315 dev_err(&dws->master->dev, "Rx hanged up\n");
323 * dws->dma_chan_busy is set before the dma transfer starts, callback for rx
324 * channel will clear a corresponding bit.
326 static void dw_spi_dma_rx_done(void *arg)
328 struct dw_spi *dws = arg;
330 clear_bit(RX_BUSY, &dws->dma_chan_busy);
331 if (test_bit(TX_BUSY, &dws->dma_chan_busy))
334 dw_writel(dws, DW_SPI_DMACR, 0);
335 complete(&dws->dma_completion);
338 static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
339 struct spi_transfer *xfer)
341 struct dma_slave_config rxconf;
342 struct dma_async_tx_descriptor *rxdesc;
347 memset(&rxconf, 0, sizeof(rxconf));
348 rxconf.direction = DMA_DEV_TO_MEM;
349 rxconf.src_addr = dws->dma_addr;
350 rxconf.src_maxburst = dws->rxburst;
351 rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
352 rxconf.src_addr_width = dw_spi_dma_convert_width(dws->n_bytes);
353 rxconf.device_fc = false;
355 dmaengine_slave_config(dws->rxchan, &rxconf);
357 rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
361 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
365 rxdesc->callback = dw_spi_dma_rx_done;
366 rxdesc->callback_param = dws;
371 static int dw_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
373 u16 imr = 0, dma_ctrl = 0;
376 * Having a Rx DMA channel serviced with higher priority than a Tx DMA
377 * channel might not be enough to provide a well balanced DMA-based
378 * SPI transfer interface. There might still be moments when the Tx DMA
379 * channel is occasionally handled faster than the Rx DMA channel.
380 * That in its turn will eventually cause the SPI Rx FIFO overflow if
381 * SPI bus speed is high enough to fill the SPI Rx FIFO in before it's
382 * cleared by the Rx DMA channel. In order to fix the problem the Tx
383 * DMA activity is intentionally slowed down by limiting the SPI Tx
384 * FIFO depth with a value twice bigger than the Tx burst length
385 * calculated earlier by the dw_spi_dma_maxburst_init() method.
387 dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1);
388 dw_writel(dws, DW_SPI_DMATDLR, dws->txburst);
391 dma_ctrl |= SPI_DMA_TDMAE;
393 dma_ctrl |= SPI_DMA_RDMAE;
394 dw_writel(dws, DW_SPI_DMACR, dma_ctrl);
396 /* Set the interrupt mask */
400 imr |= SPI_INT_RXUI | SPI_INT_RXOI;
401 spi_umask_intr(dws, imr);
403 reinit_completion(&dws->dma_completion);
405 dws->transfer_handler = dw_spi_dma_transfer_handler;
410 static int dw_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer)
412 struct dma_async_tx_descriptor *txdesc, *rxdesc;
415 /* Prepare the TX dma transfer */
416 txdesc = dw_spi_dma_prepare_tx(dws, xfer);
418 /* Prepare the RX dma transfer */
419 rxdesc = dw_spi_dma_prepare_rx(dws, xfer);
421 /* rx must be started before tx due to spi instinct */
423 set_bit(RX_BUSY, &dws->dma_chan_busy);
424 dmaengine_submit(rxdesc);
425 dma_async_issue_pending(dws->rxchan);
429 set_bit(TX_BUSY, &dws->dma_chan_busy);
430 dmaengine_submit(txdesc);
431 dma_async_issue_pending(dws->txchan);
434 ret = dw_spi_dma_wait(dws, xfer);
438 if (txdesc && dws->master->cur_msg->status == -EINPROGRESS) {
439 ret = dw_spi_dma_wait_tx_done(dws, xfer);
444 if (rxdesc && dws->master->cur_msg->status == -EINPROGRESS)
445 ret = dw_spi_dma_wait_rx_done(dws);
450 static void dw_spi_dma_stop(struct dw_spi *dws)
452 if (test_bit(TX_BUSY, &dws->dma_chan_busy)) {
453 dmaengine_terminate_sync(dws->txchan);
454 clear_bit(TX_BUSY, &dws->dma_chan_busy);
456 if (test_bit(RX_BUSY, &dws->dma_chan_busy)) {
457 dmaengine_terminate_sync(dws->rxchan);
458 clear_bit(RX_BUSY, &dws->dma_chan_busy);
461 dw_writel(dws, DW_SPI_DMACR, 0);
464 static const struct dw_spi_dma_ops dw_spi_dma_mfld_ops = {
465 .dma_init = dw_spi_dma_init_mfld,
466 .dma_exit = dw_spi_dma_exit,
467 .dma_setup = dw_spi_dma_setup,
468 .can_dma = dw_spi_can_dma,
469 .dma_transfer = dw_spi_dma_transfer,
470 .dma_stop = dw_spi_dma_stop,
473 void dw_spi_dma_setup_mfld(struct dw_spi *dws)
475 dws->dma_ops = &dw_spi_dma_mfld_ops;
477 EXPORT_SYMBOL_GPL(dw_spi_dma_setup_mfld);
479 static const struct dw_spi_dma_ops dw_spi_dma_generic_ops = {
480 .dma_init = dw_spi_dma_init_generic,
481 .dma_exit = dw_spi_dma_exit,
482 .dma_setup = dw_spi_dma_setup,
483 .can_dma = dw_spi_can_dma,
484 .dma_transfer = dw_spi_dma_transfer,
485 .dma_stop = dw_spi_dma_stop,
488 void dw_spi_dma_setup_generic(struct dw_spi *dws)
490 dws->dma_ops = &dw_spi_dma_generic_ops;
492 EXPORT_SYMBOL_GPL(dw_spi_dma_setup_generic);