drivers/spi/spi-dw-dma.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Special handling for DW DMA core
   4  *
   5  * Copyright (c) 2009, 2014 Intel Corporation.
   6  */
   7
   8 #include <linux/completion.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/dmaengine.h>
  11 #include <linux/irqreturn.h>
  12 #include <linux/jiffies.h>
  13 #include <linux/pci.h>
  14 #include <linux/platform_data/dma-dw.h>
  15 #include <linux/spi/spi.h>
  16 #include <linux/types.h>
  17
  18 #include "spi-dw.h"
  19
  20 #define RX_BUSY         0
  21 #define RX_BURST_LEVEL  16
  22 #define TX_BUSY         1
  23 #define TX_BURST_LEVEL  16
  24
  25 static bool dw_spi_dma_chan_filter(struct dma_chan *chan, void *param)
  26 {
  27         struct dw_dma_slave *s = param;
  28
  29         if (s->dma_dev != chan->device->dev)
  30                 return false;
  31
  32         chan->private = s;
  33         return true;
  34 }
  35
  36 static void dw_spi_dma_maxburst_init(struct dw_spi *dws)
  37 {
  38         struct dma_slave_caps caps;
  39         u32 max_burst, def_burst;
  40         int ret;
  41
  42         def_burst = dws->fifo_len / 2;
  43
  44         ret = dma_get_slave_caps(dws->rxchan, &caps);
  45         if (!ret && caps.max_burst)
  46                 max_burst = caps.max_burst;
  47         else
  48                 max_burst = RX_BURST_LEVEL;
  49
  50         dws->rxburst = min(max_burst, def_burst);
  51         dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1);
  52
  53         ret = dma_get_slave_caps(dws->txchan, &caps);
  54         if (!ret && caps.max_burst)
  55                 max_burst = caps.max_burst;
  56         else
  57                 max_burst = TX_BURST_LEVEL;
  58
  59         /*
  60          * Having a Rx DMA channel serviced with higher priority than a Tx DMA
  61          * channel might not be enough to provide a well balanced DMA-based
  62          * SPI transfer interface. There might still be moments when the Tx DMA
  63          * channel is occasionally handled faster than the Rx DMA channel.
  64          * That in its turn will eventually cause the SPI Rx FIFO overflow if
  65          * SPI bus speed is high enough to fill the SPI Rx FIFO in before it's
  66          * cleared by the Rx DMA channel. In order to fix the problem the Tx
  67          * DMA activity is intentionally slowed down by limiting the SPI Tx
  68          * FIFO depth with a value twice bigger than the Tx burst length.
  69          */
  70         dws->txburst = min(max_burst, def_burst);
  71         dw_writel(dws, DW_SPI_DMATDLR, dws->txburst);
  72 }
  73
  74 static void dw_spi_dma_sg_burst_init(struct dw_spi *dws)
  75 {
  76         struct dma_slave_caps tx = {0}, rx = {0};
  77
  78         dma_get_slave_caps(dws->txchan, &tx);
  79         dma_get_slave_caps(dws->rxchan, &rx);
  80
  81         if (tx.max_sg_burst > 0 && rx.max_sg_burst > 0)
  82                 dws->dma_sg_burst = min(tx.max_sg_burst, rx.max_sg_burst);
  83         else if (tx.max_sg_burst > 0)
  84                 dws->dma_sg_burst = tx.max_sg_burst;
  85         else if (rx.max_sg_burst > 0)
  86                 dws->dma_sg_burst = rx.max_sg_burst;
  87         else
  88                 dws->dma_sg_burst = 0;
  89 }
  90
  91 static int dw_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws)
  92 {
  93         struct dw_dma_slave dma_tx = { .dst_id = 1 }, *tx = &dma_tx;
  94         struct dw_dma_slave dma_rx = { .src_id = 0 }, *rx = &dma_rx;
  95         struct pci_dev *dma_dev;
  96         dma_cap_mask_t mask;
  97
  98         /*
  99          * Get pci device for DMA controller, currently it could only
 100          * be the DMA controller of Medfield
 101          */
 102         dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
 103         if (!dma_dev)
 104                 return -ENODEV;
 105
 106         dma_cap_zero(mask);
 107         dma_cap_set(DMA_SLAVE, mask);
 108
 109         /* 1. Init rx channel */
 110         rx->dma_dev = &dma_dev->dev;
 111         dws->rxchan = dma_request_channel(mask, dw_spi_dma_chan_filter, rx);
 112         if (!dws->rxchan)
 113                 goto err_exit;
 114
 115         /* 2. Init tx channel */
 116         tx->dma_dev = &dma_dev->dev;
 117         dws->txchan = dma_request_channel(mask, dw_spi_dma_chan_filter, tx);
 118         if (!dws->txchan)
 119                 goto free_rxchan;
 120
 121         dws->master->dma_rx = dws->rxchan;
 122         dws->master->dma_tx = dws->txchan;
 123
 124         init_completion(&dws->dma_completion);
 125
 126         dw_spi_dma_maxburst_init(dws);
 127
 128         dw_spi_dma_sg_burst_init(dws);
 129
 130         return 0;
 131
 132 free_rxchan:
 133         dma_release_channel(dws->rxchan);
 134         dws->rxchan = NULL;
 135 err_exit:
 136         return -EBUSY;
 137 }
 138
 139 static int dw_spi_dma_init_generic(struct device *dev, struct dw_spi *dws)
 140 {
 141         dws->rxchan = dma_request_slave_channel(dev, "rx");
 142         if (!dws->rxchan)
 143                 return -ENODEV;
 144
 145         dws->txchan = dma_request_slave_channel(dev, "tx");
 146         if (!dws->txchan) {
 147                 dma_release_channel(dws->rxchan);
 148                 dws->rxchan = NULL;
 149                 return -ENODEV;
 150         }
 151
 152         dws->master->dma_rx = dws->rxchan;
 153         dws->master->dma_tx = dws->txchan;
 154
 155         init_completion(&dws->dma_completion);
 156
 157         dw_spi_dma_maxburst_init(dws);
 158
 159         dw_spi_dma_sg_burst_init(dws);
 160
 161         return 0;
 162 }
 163
 164 static void dw_spi_dma_exit(struct dw_spi *dws)
 165 {
 166         if (dws->txchan) {
 167                 dmaengine_terminate_sync(dws->txchan);
 168                 dma_release_channel(dws->txchan);
 169         }
 170
 171         if (dws->rxchan) {
 172                 dmaengine_terminate_sync(dws->rxchan);
 173                 dma_release_channel(dws->rxchan);
 174         }
 175 }
 176
 177 static irqreturn_t dw_spi_dma_transfer_handler(struct dw_spi *dws)
 178 {
 179         u16 irq_status = dw_readl(dws, DW_SPI_ISR);
 180
 181         if (!irq_status)
 182                 return IRQ_NONE;
 183
 184         dw_readl(dws, DW_SPI_ICR);
 185         spi_reset_chip(dws);
 186
 187         dev_err(&dws->master->dev, "%s: FIFO overrun/underrun\n", __func__);
 188         dws->master->cur_msg->status = -EIO;
 189         complete(&dws->dma_completion);
 190         return IRQ_HANDLED;
 191 }
 192
 193 static bool dw_spi_can_dma(struct spi_controller *master,
 194                            struct spi_device *spi, struct spi_transfer *xfer)
 195 {
 196         struct dw_spi *dws = spi_controller_get_devdata(master);
 197
 198         return xfer->len > dws->fifo_len;
 199 }
 200
 201 static enum dma_slave_buswidth dw_spi_dma_convert_width(u8 n_bytes)
 202 {
 203         if (n_bytes == 1)
 204                 return DMA_SLAVE_BUSWIDTH_1_BYTE;
 205         else if (n_bytes == 2)
 206                 return DMA_SLAVE_BUSWIDTH_2_BYTES;
 207
 208         return DMA_SLAVE_BUSWIDTH_UNDEFINED;
 209 }
 210
 211 static int dw_spi_dma_wait(struct dw_spi *dws, unsigned int len, u32 speed)
 212 {
 213         unsigned long long ms;
 214
 215         ms = len * MSEC_PER_SEC * BITS_PER_BYTE;
 216         do_div(ms, speed);
 217         ms += ms + 200;
 218
 219         if (ms > UINT_MAX)
 220                 ms = UINT_MAX;
 221
 222         ms = wait_for_completion_timeout(&dws->dma_completion,
 223                                          msecs_to_jiffies(ms));
 224
 225         if (ms == 0) {
 226                 dev_err(&dws->master->cur_msg->spi->dev,
 227                         "DMA transaction timed out\n");
 228                 return -ETIMEDOUT;
 229         }
 230
 231         return 0;
 232 }
 233
 234 static inline bool dw_spi_dma_tx_busy(struct dw_spi *dws)
 235 {
 236         return !(dw_readl(dws, DW_SPI_SR) & SR_TF_EMPT);
 237 }
 238
 239 static int dw_spi_dma_wait_tx_done(struct dw_spi *dws,
 240                                    struct spi_transfer *xfer)
 241 {
 242         int retry = SPI_WAIT_RETRIES;
 243         struct spi_delay delay;
 244         u32 nents;
 245
 246         nents = dw_readl(dws, DW_SPI_TXFLR);
 247         delay.unit = SPI_DELAY_UNIT_SCK;
 248         delay.value = nents * dws->n_bytes * BITS_PER_BYTE;
 249
 250         while (dw_spi_dma_tx_busy(dws) && retry--)
 251                 spi_delay_exec(&delay, xfer);
 252
 253         if (retry < 0) {
 254                 dev_err(&dws->master->dev, "Tx hanged up\n");
 255                 return -EIO;
 256         }
 257
 258         return 0;
 259 }
 260
 261 /*
 262  * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
 263  * channel will clear a corresponding bit.
 264  */
 265 static void dw_spi_dma_tx_done(void *arg)
 266 {
 267         struct dw_spi *dws = arg;
 268
 269         clear_bit(TX_BUSY, &dws->dma_chan_busy);
 270         if (test_bit(RX_BUSY, &dws->dma_chan_busy))
 271                 return;
 272
 273         complete(&dws->dma_completion);
 274 }
 275
 276 static int dw_spi_dma_config_tx(struct dw_spi *dws)
 277 {
 278         struct dma_slave_config txconf;
 279
 280         memset(&txconf, 0, sizeof(txconf));
 281         txconf.direction = DMA_MEM_TO_DEV;
 282         txconf.dst_addr = dws->dma_addr;
 283         txconf.dst_maxburst = dws->txburst;
 284         txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 285         txconf.dst_addr_width = dw_spi_dma_convert_width(dws->n_bytes);
 286         txconf.device_fc = false;
 287
 288         return dmaengine_slave_config(dws->txchan, &txconf);
 289 }
 290
 291 static int dw_spi_dma_submit_tx(struct dw_spi *dws, struct scatterlist *sgl,
 292                                 unsigned int nents)
 293 {
 294         struct dma_async_tx_descriptor *txdesc;
 295         dma_cookie_t cookie;
 296         int ret;
 297
 298         txdesc = dmaengine_prep_slave_sg(dws->txchan, sgl, nents,
 299                                          DMA_MEM_TO_DEV,
 300                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 301         if (!txdesc)
 302                 return -ENOMEM;
 303
 304         txdesc->callback = dw_spi_dma_tx_done;
 305         txdesc->callback_param = dws;
 306
 307         cookie = dmaengine_submit(txdesc);
 308         ret = dma_submit_error(cookie);
 309         if (ret) {
 310                 dmaengine_terminate_sync(dws->txchan);
 311                 return ret;
 312         }
 313
 314         set_bit(TX_BUSY, &dws->dma_chan_busy);
 315
 316         return 0;
 317 }
 318
 319 static inline bool dw_spi_dma_rx_busy(struct dw_spi *dws)
 320 {
 321         return !!(dw_readl(dws, DW_SPI_SR) & SR_RF_NOT_EMPT);
 322 }
 323
 324 static int dw_spi_dma_wait_rx_done(struct dw_spi *dws)
 325 {
 326         int retry = SPI_WAIT_RETRIES;
 327         struct spi_delay delay;
 328         unsigned long ns, us;
 329         u32 nents;
 330
 331         /*
 332          * It's unlikely that DMA engine is still doing the data fetching, but
 333          * if it's let's give it some reasonable time. The timeout calculation
 334          * is based on the synchronous APB/SSI reference clock rate, on a
 335          * number of data entries left in the Rx FIFO, times a number of clock
 336          * periods normally needed for a single APB read/write transaction
 337          * without PREADY signal utilized (which is true for the DW APB SSI
 338          * controller).
 339          */
 340         nents = dw_readl(dws, DW_SPI_RXFLR);
 341         ns = 4U * NSEC_PER_SEC / dws->max_freq * nents;
 342         if (ns <= NSEC_PER_USEC) {
 343                 delay.unit = SPI_DELAY_UNIT_NSECS;
 344                 delay.value = ns;
 345         } else {
 346                 us = DIV_ROUND_UP(ns, NSEC_PER_USEC);
 347                 delay.unit = SPI_DELAY_UNIT_USECS;
 348                 delay.value = clamp_val(us, 0, USHRT_MAX);
 349         }
 350
 351         while (dw_spi_dma_rx_busy(dws) && retry--)
 352                 spi_delay_exec(&delay, NULL);
 353
 354         if (retry < 0) {
 355                 dev_err(&dws->master->dev, "Rx hanged up\n");
 356                 return -EIO;
 357         }
 358
 359         return 0;
 360 }
 361
 362 /*
 363  * dws->dma_chan_busy is set before the dma transfer starts, callback for rx
 364  * channel will clear a corresponding bit.
 365  */
 366 static void dw_spi_dma_rx_done(void *arg)
 367 {
 368         struct dw_spi *dws = arg;
 369
 370         clear_bit(RX_BUSY, &dws->dma_chan_busy);
 371         if (test_bit(TX_BUSY, &dws->dma_chan_busy))
 372                 return;
 373
 374         complete(&dws->dma_completion);
 375 }
 376
 377 static int dw_spi_dma_config_rx(struct dw_spi *dws)
 378 {
 379         struct dma_slave_config rxconf;
 380
 381         memset(&rxconf, 0, sizeof(rxconf));
 382         rxconf.direction = DMA_DEV_TO_MEM;
 383         rxconf.src_addr = dws->dma_addr;
 384         rxconf.src_maxburst = dws->rxburst;
 385         rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 386         rxconf.src_addr_width = dw_spi_dma_convert_width(dws->n_bytes);
 387         rxconf.device_fc = false;
 388
 389         return dmaengine_slave_config(dws->rxchan, &rxconf);
 390 }
 391
 392 static int dw_spi_dma_submit_rx(struct dw_spi *dws, struct scatterlist *sgl,
 393                                 unsigned int nents)
 394 {
 395         struct dma_async_tx_descriptor *rxdesc;
 396         dma_cookie_t cookie;
 397         int ret;
 398
 399         rxdesc = dmaengine_prep_slave_sg(dws->rxchan, sgl, nents,
 400                                          DMA_DEV_TO_MEM,
 401                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 402         if (!rxdesc)
 403                 return -ENOMEM;
 404
 405         rxdesc->callback = dw_spi_dma_rx_done;
 406         rxdesc->callback_param = dws;
 407
 408         cookie = dmaengine_submit(rxdesc);
 409         ret = dma_submit_error(cookie);
 410         if (ret) {
 411                 dmaengine_terminate_sync(dws->rxchan);
 412                 return ret;
 413         }
 414
 415         set_bit(RX_BUSY, &dws->dma_chan_busy);
 416
 417         return 0;
 418 }
 419
 420 static int dw_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
 421 {
 422         u16 imr, dma_ctrl;
 423         int ret;
 424
 425         if (!xfer->tx_buf)
 426                 return -EINVAL;
 427
 428         /* Setup DMA channels */
 429         ret = dw_spi_dma_config_tx(dws);
 430         if (ret)
 431                 return ret;
 432
 433         if (xfer->rx_buf) {
 434                 ret = dw_spi_dma_config_rx(dws);
 435                 if (ret)
 436                         return ret;
 437         }
 438
 439         /* Set the DMA handshaking interface */
 440         dma_ctrl = SPI_DMA_TDMAE;
 441         if (xfer->rx_buf)
 442                 dma_ctrl |= SPI_DMA_RDMAE;
 443         dw_writel(dws, DW_SPI_DMACR, dma_ctrl);
 444
 445         /* Set the interrupt mask */
 446         imr = SPI_INT_TXOI;
 447         if (xfer->rx_buf)
 448                 imr |= SPI_INT_RXUI | SPI_INT_RXOI;
 449         spi_umask_intr(dws, imr);
 450
 451         reinit_completion(&dws->dma_completion);
 452
 453         dws->transfer_handler = dw_spi_dma_transfer_handler;
 454
 455         return 0;
 456 }
 457
 458 static int dw_spi_dma_transfer_all(struct dw_spi *dws,
 459                                    struct spi_transfer *xfer)
 460 {
 461         int ret;
 462
 463         /* Submit the DMA Tx transfer */
 464         ret = dw_spi_dma_submit_tx(dws, xfer->tx_sg.sgl, xfer->tx_sg.nents);
 465         if (ret)
 466                 goto err_clear_dmac;
 467
 468         /* Submit the DMA Rx transfer if required */
 469         if (xfer->rx_buf) {
 470                 ret = dw_spi_dma_submit_rx(dws, xfer->rx_sg.sgl,
 471                                            xfer->rx_sg.nents);
 472                 if (ret)
 473                         goto err_clear_dmac;
 474
 475                 /* rx must be started before tx due to spi instinct */
 476                 dma_async_issue_pending(dws->rxchan);
 477         }
 478
 479         dma_async_issue_pending(dws->txchan);
 480
 481         ret = dw_spi_dma_wait(dws, xfer->len, xfer->effective_speed_hz);
 482
 483 err_clear_dmac:
 484         dw_writel(dws, DW_SPI_DMACR, 0);
 485
 486         return ret;
 487 }
 488
 489 /*
 490  * In case if at least one of the requested DMA channels doesn't support the
 491  * hardware accelerated SG list entries traverse, the DMA driver will most
 492  * likely work that around by performing the IRQ-based SG list entries
 493  * resubmission. That might and will cause a problem if the DMA Tx channel is
 494  * recharged and re-executed before the Rx DMA channel. Due to
 495  * non-deterministic IRQ-handler execution latency the DMA Tx channel will
 496  * start pushing data to the SPI bus before the Rx DMA channel is even
 497  * reinitialized with the next inbound SG list entry. By doing so the DMA Tx
 498  * channel will implicitly start filling the DW APB SSI Rx FIFO up, which while
 499  * the DMA Rx channel being recharged and re-executed will eventually be
 500  * overflown.
 501  *
 502  * In order to solve the problem we have to feed the DMA engine with SG list
 503  * entries one-by-one. It shall keep the DW APB SSI Tx and Rx FIFOs
 504  * synchronized and prevent the Rx FIFO overflow. Since in general the tx_sg
 505  * and rx_sg lists may have different number of entries of different lengths
 506  * (though total length should match) let's virtually split the SG-lists to the
 507  * set of DMA transfers, which length is a minimum of the ordered SG-entries
 508  * lengths. An ASCII-sketch of the implemented algo is following:
 509  *                  xfer->len
 510  *                |___________|
 511  * tx_sg list:    |___|____|__|
 512  * rx_sg list:    |_|____|____|
 513  * DMA transfers: |_|_|__|_|__|
 514  *
 515  * Note in order to have this workaround solving the denoted problem the DMA
 516  * engine driver should properly initialize the max_sg_burst capability and set
 517  * the DMA device max segment size parameter with maximum data block size the
 518  * DMA engine supports.
 519  */
 520
 521 static int dw_spi_dma_transfer_one(struct dw_spi *dws,
 522                                    struct spi_transfer *xfer)
 523 {
 524         struct scatterlist *tx_sg = NULL, *rx_sg = NULL, tx_tmp, rx_tmp;
 525         unsigned int tx_len = 0, rx_len = 0;
 526         unsigned int base, len;
 527         int ret;
 528
 529         sg_init_table(&tx_tmp, 1);
 530         sg_init_table(&rx_tmp, 1);
 531
 532         for (base = 0, len = 0; base < xfer->len; base += len) {
 533                 /* Fetch next Tx DMA data chunk */
 534                 if (!tx_len) {
 535                         tx_sg = !tx_sg ? &xfer->tx_sg.sgl[0] : sg_next(tx_sg);
 536                         sg_dma_address(&tx_tmp) = sg_dma_address(tx_sg);
 537                         tx_len = sg_dma_len(tx_sg);
 538                 }
 539
 540                 /* Fetch next Rx DMA data chunk */
 541                 if (!rx_len) {
 542                         rx_sg = !rx_sg ? &xfer->rx_sg.sgl[0] : sg_next(rx_sg);
 543                         sg_dma_address(&rx_tmp) = sg_dma_address(rx_sg);
 544                         rx_len = sg_dma_len(rx_sg);
 545                 }
 546
 547                 len = min(tx_len, rx_len);
 548
 549                 sg_dma_len(&tx_tmp) = len;
 550                 sg_dma_len(&rx_tmp) = len;
 551
 552                 /* Submit DMA Tx transfer */
 553                 ret = dw_spi_dma_submit_tx(dws, &tx_tmp, 1);
 554                 if (ret)
 555                         break;
 556
 557                 /* Submit DMA Rx transfer */
 558                 ret = dw_spi_dma_submit_rx(dws, &rx_tmp, 1);
 559                 if (ret)
 560                         break;
 561
 562                 /* Rx must be started before Tx due to SPI instinct */
 563                 dma_async_issue_pending(dws->rxchan);
 564
 565                 dma_async_issue_pending(dws->txchan);
 566
 567                 /*
 568                  * Here we only need to wait for the DMA transfer to be
 569                  * finished since SPI controller is kept enabled during the
 570                  * procedure this loop implements and there is no risk to lose
 571                  * data left in the Tx/Rx FIFOs.
 572                  */
 573                 ret = dw_spi_dma_wait(dws, len, xfer->effective_speed_hz);
 574                 if (ret)
 575                         break;
 576
 577                 reinit_completion(&dws->dma_completion);
 578
 579                 sg_dma_address(&tx_tmp) += len;
 580                 sg_dma_address(&rx_tmp) += len;
 581                 tx_len -= len;
 582                 rx_len -= len;
 583         }
 584
 585         dw_writel(dws, DW_SPI_DMACR, 0);
 586
 587         return ret;
 588 }
 589
 590 static int dw_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer)
 591 {
 592         unsigned int nents;
 593         int ret;
 594
 595         nents = max(xfer->tx_sg.nents, xfer->rx_sg.nents);
 596
 597         /*
 598          * Execute normal DMA-based transfer (which submits the Rx and Tx SG
 599          * lists directly to the DMA engine at once) if either full hardware
 600          * accelerated SG list traverse is supported by both channels, or the
 601          * Tx-only SPI transfer is requested, or the DMA engine is capable to
 602          * handle both SG lists on hardware accelerated basis.
 603          */
 604         if (!dws->dma_sg_burst || !xfer->rx_buf || nents <= dws->dma_sg_burst)
 605                 ret = dw_spi_dma_transfer_all(dws, xfer);
 606         else
 607                 ret = dw_spi_dma_transfer_one(dws, xfer);
 608         if (ret)
 609                 return ret;
 610
 611         if (dws->master->cur_msg->status == -EINPROGRESS) {
 612                 ret = dw_spi_dma_wait_tx_done(dws, xfer);
 613                 if (ret)
 614                         return ret;
 615         }
 616
 617         if (xfer->rx_buf && dws->master->cur_msg->status == -EINPROGRESS)
 618                 ret = dw_spi_dma_wait_rx_done(dws);
 619
 620         return ret;
 621 }
 622
 623 static void dw_spi_dma_stop(struct dw_spi *dws)
 624 {
 625         if (test_bit(TX_BUSY, &dws->dma_chan_busy)) {
 626                 dmaengine_terminate_sync(dws->txchan);
 627                 clear_bit(TX_BUSY, &dws->dma_chan_busy);
 628         }
 629         if (test_bit(RX_BUSY, &dws->dma_chan_busy)) {
 630                 dmaengine_terminate_sync(dws->rxchan);
 631                 clear_bit(RX_BUSY, &dws->dma_chan_busy);
 632         }
 633 }
 634
 635 static const struct dw_spi_dma_ops dw_spi_dma_mfld_ops = {
 636         .dma_init       = dw_spi_dma_init_mfld,
 637         .dma_exit       = dw_spi_dma_exit,
 638         .dma_setup      = dw_spi_dma_setup,
 639         .can_dma        = dw_spi_can_dma,
 640         .dma_transfer   = dw_spi_dma_transfer,
 641         .dma_stop       = dw_spi_dma_stop,
 642 };
 643
 644 void dw_spi_dma_setup_mfld(struct dw_spi *dws)
 645 {
 646         dws->dma_ops = &dw_spi_dma_mfld_ops;
 647 }
 648 EXPORT_SYMBOL_GPL(dw_spi_dma_setup_mfld);
 649
 650 static const struct dw_spi_dma_ops dw_spi_dma_generic_ops = {
 651         .dma_init       = dw_spi_dma_init_generic,
 652         .dma_exit       = dw_spi_dma_exit,
 653         .dma_setup      = dw_spi_dma_setup,
 654         .can_dma        = dw_spi_can_dma,
 655         .dma_transfer   = dw_spi_dma_transfer,
 656         .dma_stop       = dw_spi_dma_stop,
 657 };
 658
 659 void dw_spi_dma_setup_generic(struct dw_spi *dws)
 660 {
 661         dws->dma_ops = &dw_spi_dma_generic_ops;
 662 }
 663 EXPORT_SYMBOL_GPL(dw_spi_dma_setup_generic);