1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for the Diolan DLN-2 USB-SPI adapter
5 * Copyright (c) 2014 Intel Corporation
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 #include <linux/mfd/dln2.h>
12 #include <linux/spi/spi.h>
13 #include <linux/pm_runtime.h>
14 #include <asm/unaligned.h>
16 #define DLN2_SPI_MODULE_ID 0x02
17 #define DLN2_SPI_CMD(cmd) DLN2_CMD(cmd, DLN2_SPI_MODULE_ID)
20 #define DLN2_SPI_GET_PORT_COUNT DLN2_SPI_CMD(0x00)
21 #define DLN2_SPI_ENABLE DLN2_SPI_CMD(0x11)
22 #define DLN2_SPI_DISABLE DLN2_SPI_CMD(0x12)
23 #define DLN2_SPI_IS_ENABLED DLN2_SPI_CMD(0x13)
24 #define DLN2_SPI_SET_MODE DLN2_SPI_CMD(0x14)
25 #define DLN2_SPI_GET_MODE DLN2_SPI_CMD(0x15)
26 #define DLN2_SPI_SET_FRAME_SIZE DLN2_SPI_CMD(0x16)
27 #define DLN2_SPI_GET_FRAME_SIZE DLN2_SPI_CMD(0x17)
28 #define DLN2_SPI_SET_FREQUENCY DLN2_SPI_CMD(0x18)
29 #define DLN2_SPI_GET_FREQUENCY DLN2_SPI_CMD(0x19)
30 #define DLN2_SPI_READ_WRITE DLN2_SPI_CMD(0x1A)
31 #define DLN2_SPI_READ DLN2_SPI_CMD(0x1B)
32 #define DLN2_SPI_WRITE DLN2_SPI_CMD(0x1C)
33 #define DLN2_SPI_SET_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x20)
34 #define DLN2_SPI_GET_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x21)
35 #define DLN2_SPI_SET_DELAY_AFTER_SS DLN2_SPI_CMD(0x22)
36 #define DLN2_SPI_GET_DELAY_AFTER_SS DLN2_SPI_CMD(0x23)
37 #define DLN2_SPI_SET_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x24)
38 #define DLN2_SPI_GET_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x25)
39 #define DLN2_SPI_SET_SS DLN2_SPI_CMD(0x26)
40 #define DLN2_SPI_GET_SS DLN2_SPI_CMD(0x27)
41 #define DLN2_SPI_RELEASE_SS DLN2_SPI_CMD(0x28)
42 #define DLN2_SPI_SS_VARIABLE_ENABLE DLN2_SPI_CMD(0x2B)
43 #define DLN2_SPI_SS_VARIABLE_DISABLE DLN2_SPI_CMD(0x2C)
44 #define DLN2_SPI_SS_VARIABLE_IS_ENABLED DLN2_SPI_CMD(0x2D)
45 #define DLN2_SPI_SS_AAT_ENABLE DLN2_SPI_CMD(0x2E)
46 #define DLN2_SPI_SS_AAT_DISABLE DLN2_SPI_CMD(0x2F)
47 #define DLN2_SPI_SS_AAT_IS_ENABLED DLN2_SPI_CMD(0x30)
48 #define DLN2_SPI_SS_BETWEEN_FRAMES_ENABLE DLN2_SPI_CMD(0x31)
49 #define DLN2_SPI_SS_BETWEEN_FRAMES_DISABLE DLN2_SPI_CMD(0x32)
50 #define DLN2_SPI_SS_BETWEEN_FRAMES_IS_ENABLED DLN2_SPI_CMD(0x33)
51 #define DLN2_SPI_SET_CPHA DLN2_SPI_CMD(0x34)
52 #define DLN2_SPI_GET_CPHA DLN2_SPI_CMD(0x35)
53 #define DLN2_SPI_SET_CPOL DLN2_SPI_CMD(0x36)
54 #define DLN2_SPI_GET_CPOL DLN2_SPI_CMD(0x37)
55 #define DLN2_SPI_SS_MULTI_ENABLE DLN2_SPI_CMD(0x38)
56 #define DLN2_SPI_SS_MULTI_DISABLE DLN2_SPI_CMD(0x39)
57 #define DLN2_SPI_SS_MULTI_IS_ENABLED DLN2_SPI_CMD(0x3A)
58 #define DLN2_SPI_GET_SUPPORTED_MODES DLN2_SPI_CMD(0x40)
59 #define DLN2_SPI_GET_SUPPORTED_CPHA_VALUES DLN2_SPI_CMD(0x41)
60 #define DLN2_SPI_GET_SUPPORTED_CPOL_VALUES DLN2_SPI_CMD(0x42)
61 #define DLN2_SPI_GET_SUPPORTED_FRAME_SIZES DLN2_SPI_CMD(0x43)
62 #define DLN2_SPI_GET_SS_COUNT DLN2_SPI_CMD(0x44)
63 #define DLN2_SPI_GET_MIN_FREQUENCY DLN2_SPI_CMD(0x45)
64 #define DLN2_SPI_GET_MAX_FREQUENCY DLN2_SPI_CMD(0x46)
65 #define DLN2_SPI_GET_MIN_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x47)
66 #define DLN2_SPI_GET_MAX_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x48)
67 #define DLN2_SPI_GET_MIN_DELAY_AFTER_SS DLN2_SPI_CMD(0x49)
68 #define DLN2_SPI_GET_MAX_DELAY_AFTER_SS DLN2_SPI_CMD(0x4A)
69 #define DLN2_SPI_GET_MIN_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x4B)
70 #define DLN2_SPI_GET_MAX_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x4C)
72 #define DLN2_SPI_MAX_XFER_SIZE 256
73 #define DLN2_SPI_BUF_SIZE (DLN2_SPI_MAX_XFER_SIZE + 16)
74 #define DLN2_SPI_ATTR_LEAVE_SS_LOW BIT(0)
75 #define DLN2_TRANSFERS_WAIT_COMPLETE 1
76 #define DLN2_TRANSFERS_CANCEL 0
77 #define DLN2_RPM_AUTOSUSPEND_TIMEOUT 2000
80 struct platform_device *pdev;
81 struct spi_master *master;
85 * This buffer will be used mainly for read/write operations. Since
86 * they're quite large, we cannot use the stack. Protection is not
87 * needed because all SPI communication is serialized by the SPI core.
98 * Enable/Disable SPI module. The disable command will wait for transfers to
101 static int dln2_spi_enable(struct dln2_spi *dln2, bool enable)
106 u8 wait_for_completion;
108 unsigned len = sizeof(tx);
110 tx.port = dln2->port;
113 cmd = DLN2_SPI_ENABLE;
114 len -= sizeof(tx.wait_for_completion);
116 tx.wait_for_completion = DLN2_TRANSFERS_WAIT_COMPLETE;
117 cmd = DLN2_SPI_DISABLE;
120 return dln2_transfer_tx(dln2->pdev, cmd, &tx, len);
124 * Select/unselect multiple CS lines. The selected lines will be automatically
125 * toggled LOW/HIGH by the board firmware during transfers, provided they're
128 * Ex: cs_mask = 0x03 -> CS0 & CS1 will be selected and the next WR/RD operation
129 * will toggle the lines LOW/HIGH automatically.
131 static int dln2_spi_cs_set(struct dln2_spi *dln2, u8 cs_mask)
138 tx.port = dln2->port;
141 * According to Diolan docs, "a slave device can be selected by changing
142 * the corresponding bit value to 0". The rest must be set to 1. Hence
143 * the bitwise NOT in front.
147 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_SS, &tx, sizeof(tx));
151 * Select one CS line. The other lines will be un-selected.
153 static int dln2_spi_cs_set_one(struct dln2_spi *dln2, u8 cs)
155 return dln2_spi_cs_set(dln2, BIT(cs));
159 * Enable/disable CS lines for usage. The module has to be disabled first.
161 static int dln2_spi_cs_enable(struct dln2_spi *dln2, u8 cs_mask, bool enable)
169 tx.port = dln2->port;
171 cmd = enable ? DLN2_SPI_SS_MULTI_ENABLE : DLN2_SPI_SS_MULTI_DISABLE;
173 return dln2_transfer_tx(dln2->pdev, cmd, &tx, sizeof(tx));
176 static int dln2_spi_cs_enable_all(struct dln2_spi *dln2, bool enable)
178 u8 cs_mask = GENMASK(dln2->master->num_chipselect - 1, 0);
180 return dln2_spi_cs_enable(dln2, cs_mask, enable);
183 static int dln2_spi_get_cs_num(struct dln2_spi *dln2, u16 *cs_num)
192 unsigned rx_len = sizeof(rx);
194 tx.port = dln2->port;
195 ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SS_COUNT, &tx, sizeof(tx),
199 if (rx_len < sizeof(rx))
202 *cs_num = le16_to_cpu(rx.cs_count);
204 dev_dbg(&dln2->pdev->dev, "cs_num = %d\n", *cs_num);
209 static int dln2_spi_get_speed(struct dln2_spi *dln2, u16 cmd, u32 *freq)
218 unsigned rx_len = sizeof(rx);
220 tx.port = dln2->port;
222 ret = dln2_transfer(dln2->pdev, cmd, &tx, sizeof(tx), &rx, &rx_len);
225 if (rx_len < sizeof(rx))
228 *freq = le32_to_cpu(rx.speed);
234 * Get bus min/max frequencies.
236 static int dln2_spi_get_speed_range(struct dln2_spi *dln2, u32 *fmin, u32 *fmax)
240 ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MIN_FREQUENCY, fmin);
244 ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MAX_FREQUENCY, fmax);
248 dev_dbg(&dln2->pdev->dev, "freq_min = %d, freq_max = %d\n",
255 * Set the bus speed. The module will automatically round down to the closest
256 * available frequency and returns it. The module has to be disabled first.
258 static int dln2_spi_set_speed(struct dln2_spi *dln2, u32 speed)
268 int rx_len = sizeof(rx);
270 tx.port = dln2->port;
271 tx.speed = cpu_to_le32(speed);
273 ret = dln2_transfer(dln2->pdev, DLN2_SPI_SET_FREQUENCY, &tx, sizeof(tx),
277 if (rx_len < sizeof(rx))
284 * Change CPOL & CPHA. The module has to be disabled first.
286 static int dln2_spi_set_mode(struct dln2_spi *dln2, u8 mode)
293 tx.port = dln2->port;
296 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_MODE, &tx, sizeof(tx));
300 * Change frame size. The module has to be disabled first.
302 static int dln2_spi_set_bpw(struct dln2_spi *dln2, u8 bpw)
309 tx.port = dln2->port;
312 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_FRAME_SIZE,
316 static int dln2_spi_get_supported_frame_sizes(struct dln2_spi *dln2,
327 unsigned rx_len = sizeof(*rx);
330 tx.port = dln2->port;
332 ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SUPPORTED_FRAME_SIZES,
333 &tx, sizeof(tx), rx, &rx_len);
336 if (rx_len < sizeof(*rx))
338 if (rx->count > ARRAY_SIZE(rx->frame_sizes))
342 for (i = 0; i < rx->count; i++)
343 *bpw_mask |= BIT(rx->frame_sizes[i] - 1);
345 dev_dbg(&dln2->pdev->dev, "bpw_mask = 0x%X\n", *bpw_mask);
351 * Copy the data to DLN2 buffer and change the byte order to LE, requested by
352 * DLN2 module. SPI core makes sure that the data length is a multiple of word
355 static int dln2_spi_copy_to_buf(u8 *dln2_buf, const u8 *src, u16 len, u8 bpw)
357 #ifdef __LITTLE_ENDIAN
358 memcpy(dln2_buf, src, len);
361 memcpy(dln2_buf, src, len);
362 } else if (bpw <= 16) {
363 __le16 *d = (__le16 *)dln2_buf;
368 *d++ = cpu_to_le16p(s++);
370 __le32 *d = (__le32 *)dln2_buf;
375 *d++ = cpu_to_le32p(s++);
383 * Copy the data from DLN2 buffer and convert to CPU byte order since the DLN2
384 * buffer is LE ordered. SPI core makes sure that the data length is a multiple
385 * of word size. The RX dln2_buf is 2 byte aligned so, for BE, we have to make
386 * sure we avoid unaligned accesses for 32 bit case.
388 static int dln2_spi_copy_from_buf(u8 *dest, const u8 *dln2_buf, u16 len, u8 bpw)
390 #ifdef __LITTLE_ENDIAN
391 memcpy(dest, dln2_buf, len);
394 memcpy(dest, dln2_buf, len);
395 } else if (bpw <= 16) {
396 u16 *d = (u16 *)dest;
397 __le16 *s = (__le16 *)dln2_buf;
401 *d++ = le16_to_cpup(s++);
403 u32 *d = (u32 *)dest;
404 __le32 *s = (__le32 *)dln2_buf;
408 *d++ = get_unaligned_le32(s++);
416 * Perform one write operation.
418 static int dln2_spi_write_one(struct dln2_spi *dln2, const u8 *data,
419 u16 data_len, u8 attr)
425 u8 buf[DLN2_SPI_MAX_XFER_SIZE];
426 } __packed *tx = dln2->buf;
429 BUILD_BUG_ON(sizeof(*tx) > DLN2_SPI_BUF_SIZE);
431 if (data_len > DLN2_SPI_MAX_XFER_SIZE)
434 tx->port = dln2->port;
435 tx->size = cpu_to_le16(data_len);
438 dln2_spi_copy_to_buf(tx->buf, data, data_len, dln2->bpw);
440 tx_len = sizeof(*tx) + data_len - DLN2_SPI_MAX_XFER_SIZE;
441 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_WRITE, tx, tx_len);
445 * Perform one read operation.
447 static int dln2_spi_read_one(struct dln2_spi *dln2, u8 *data,
448 u16 data_len, u8 attr)
458 u8 buf[DLN2_SPI_MAX_XFER_SIZE];
459 } __packed *rx = dln2->buf;
460 unsigned rx_len = sizeof(*rx);
462 BUILD_BUG_ON(sizeof(*rx) > DLN2_SPI_BUF_SIZE);
464 if (data_len > DLN2_SPI_MAX_XFER_SIZE)
467 tx.port = dln2->port;
468 tx.size = cpu_to_le16(data_len);
471 ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ, &tx, sizeof(tx),
475 if (rx_len < sizeof(rx->size) + data_len)
477 if (le16_to_cpu(rx->size) != data_len)
480 dln2_spi_copy_from_buf(data, rx->buf, data_len, dln2->bpw);
486 * Perform one write & read operation.
488 static int dln2_spi_read_write_one(struct dln2_spi *dln2, const u8 *tx_data,
489 u8 *rx_data, u16 data_len, u8 attr)
496 u8 buf[DLN2_SPI_MAX_XFER_SIZE];
500 u8 buf[DLN2_SPI_MAX_XFER_SIZE];
502 unsigned tx_len, rx_len;
504 BUILD_BUG_ON(sizeof(*tx) > DLN2_SPI_BUF_SIZE ||
505 sizeof(*rx) > DLN2_SPI_BUF_SIZE);
507 if (data_len > DLN2_SPI_MAX_XFER_SIZE)
511 * Since this is a pseudo full-duplex communication, we're perfectly
512 * safe to use the same buffer for both tx and rx. When DLN2 sends the
513 * response back, with the rx data, we don't need the tx buffer anymore.
518 tx->port = dln2->port;
519 tx->size = cpu_to_le16(data_len);
522 dln2_spi_copy_to_buf(tx->buf, tx_data, data_len, dln2->bpw);
524 tx_len = sizeof(*tx) + data_len - DLN2_SPI_MAX_XFER_SIZE;
525 rx_len = sizeof(*rx);
527 ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ_WRITE, tx, tx_len,
531 if (rx_len < sizeof(rx->size) + data_len)
533 if (le16_to_cpu(rx->size) != data_len)
536 dln2_spi_copy_from_buf(rx_data, rx->buf, data_len, dln2->bpw);
542 * Read/Write wrapper. It will automatically split an operation into multiple
543 * single ones due to device buffer constraints.
545 static int dln2_spi_rdwr(struct dln2_spi *dln2, const u8 *tx_data,
546 u8 *rx_data, u16 data_len, u8 attr)
551 u16 remaining = data_len;
555 if (remaining > DLN2_SPI_MAX_XFER_SIZE) {
556 len = DLN2_SPI_MAX_XFER_SIZE;
557 temp_attr = DLN2_SPI_ATTR_LEAVE_SS_LOW;
563 offset = data_len - remaining;
565 if (tx_data && rx_data) {
566 ret = dln2_spi_read_write_one(dln2,
570 } else if (tx_data) {
571 ret = dln2_spi_write_one(dln2,
574 } else if (rx_data) {
575 ret = dln2_spi_read_one(dln2,
591 static int dln2_spi_prepare_message(struct spi_master *master,
592 struct spi_message *message)
595 struct dln2_spi *dln2 = spi_master_get_devdata(master);
596 struct spi_device *spi = message->spi;
598 if (dln2->cs != spi->chip_select) {
599 ret = dln2_spi_cs_set_one(dln2, spi->chip_select);
603 dln2->cs = spi->chip_select;
609 static int dln2_spi_transfer_setup(struct dln2_spi *dln2, u32 speed,
613 bool bus_setup_change;
615 bus_setup_change = dln2->speed != speed || dln2->mode != mode ||
618 if (!bus_setup_change)
621 ret = dln2_spi_enable(dln2, false);
625 if (dln2->speed != speed) {
626 ret = dln2_spi_set_speed(dln2, speed);
633 if (dln2->mode != mode) {
634 ret = dln2_spi_set_mode(dln2, mode & 0x3);
641 if (dln2->bpw != bpw) {
642 ret = dln2_spi_set_bpw(dln2, bpw);
649 return dln2_spi_enable(dln2, true);
652 static int dln2_spi_transfer_one(struct spi_master *master,
653 struct spi_device *spi,
654 struct spi_transfer *xfer)
656 struct dln2_spi *dln2 = spi_master_get_devdata(master);
660 status = dln2_spi_transfer_setup(dln2, xfer->speed_hz,
664 dev_err(&dln2->pdev->dev, "Cannot setup transfer\n");
668 if (!xfer->cs_change && !spi_transfer_is_last(master, xfer))
669 attr = DLN2_SPI_ATTR_LEAVE_SS_LOW;
671 status = dln2_spi_rdwr(dln2, xfer->tx_buf, xfer->rx_buf,
674 dev_err(&dln2->pdev->dev, "write/read failed!\n");
679 static int dln2_spi_probe(struct platform_device *pdev)
681 struct spi_master *master;
682 struct dln2_spi *dln2;
683 struct dln2_platform_data *pdata = dev_get_platdata(&pdev->dev);
684 struct device *dev = &pdev->dev;
687 master = spi_alloc_master(&pdev->dev, sizeof(*dln2));
691 platform_set_drvdata(pdev, master);
693 dln2 = spi_master_get_devdata(master);
695 dln2->buf = devm_kmalloc(&pdev->dev, DLN2_SPI_BUF_SIZE, GFP_KERNEL);
698 goto exit_free_master;
701 dln2->master = master;
702 dln2->master->dev.of_node = dev->of_node;
704 dln2->port = pdata->port;
705 /* cs/mode can never be 0xff, so the first transfer will set them */
709 /* disable SPI module before continuing with the setup */
710 ret = dln2_spi_enable(dln2, false);
712 dev_err(&pdev->dev, "Failed to disable SPI module\n");
713 goto exit_free_master;
716 ret = dln2_spi_get_cs_num(dln2, &master->num_chipselect);
718 dev_err(&pdev->dev, "Failed to get number of CS pins\n");
719 goto exit_free_master;
722 ret = dln2_spi_get_speed_range(dln2,
723 &master->min_speed_hz,
724 &master->max_speed_hz);
726 dev_err(&pdev->dev, "Failed to read bus min/max freqs\n");
727 goto exit_free_master;
730 ret = dln2_spi_get_supported_frame_sizes(dln2,
731 &master->bits_per_word_mask);
733 dev_err(&pdev->dev, "Failed to read supported frame sizes\n");
734 goto exit_free_master;
737 ret = dln2_spi_cs_enable_all(dln2, true);
739 dev_err(&pdev->dev, "Failed to enable CS pins\n");
740 goto exit_free_master;
743 master->bus_num = -1;
744 master->mode_bits = SPI_CPOL | SPI_CPHA;
745 master->prepare_message = dln2_spi_prepare_message;
746 master->transfer_one = dln2_spi_transfer_one;
747 master->auto_runtime_pm = true;
749 /* enable SPI module, we're good to go */
750 ret = dln2_spi_enable(dln2, true);
752 dev_err(&pdev->dev, "Failed to enable SPI module\n");
753 goto exit_free_master;
756 pm_runtime_set_autosuspend_delay(&pdev->dev,
757 DLN2_RPM_AUTOSUSPEND_TIMEOUT);
758 pm_runtime_use_autosuspend(&pdev->dev);
759 pm_runtime_set_active(&pdev->dev);
760 pm_runtime_enable(&pdev->dev);
762 ret = devm_spi_register_master(&pdev->dev, master);
764 dev_err(&pdev->dev, "Failed to register master\n");
771 pm_runtime_disable(&pdev->dev);
772 pm_runtime_set_suspended(&pdev->dev);
774 if (dln2_spi_enable(dln2, false) < 0)
775 dev_err(&pdev->dev, "Failed to disable SPI module\n");
777 spi_master_put(master);
782 static int dln2_spi_remove(struct platform_device *pdev)
784 struct spi_master *master = platform_get_drvdata(pdev);
785 struct dln2_spi *dln2 = spi_master_get_devdata(master);
787 pm_runtime_disable(&pdev->dev);
789 if (dln2_spi_enable(dln2, false) < 0)
790 dev_err(&pdev->dev, "Failed to disable SPI module\n");
795 #ifdef CONFIG_PM_SLEEP
796 static int dln2_spi_suspend(struct device *dev)
799 struct spi_master *master = dev_get_drvdata(dev);
800 struct dln2_spi *dln2 = spi_master_get_devdata(master);
802 ret = spi_master_suspend(master);
806 if (!pm_runtime_suspended(dev)) {
807 ret = dln2_spi_enable(dln2, false);
813 * USB power may be cut off during sleep. Resetting the following
814 * parameters will force the board to be set up before first transfer.
824 static int dln2_spi_resume(struct device *dev)
827 struct spi_master *master = dev_get_drvdata(dev);
828 struct dln2_spi *dln2 = spi_master_get_devdata(master);
830 if (!pm_runtime_suspended(dev)) {
831 ret = dln2_spi_cs_enable_all(dln2, true);
835 ret = dln2_spi_enable(dln2, true);
840 return spi_master_resume(master);
842 #endif /* CONFIG_PM_SLEEP */
845 static int dln2_spi_runtime_suspend(struct device *dev)
847 struct spi_master *master = dev_get_drvdata(dev);
848 struct dln2_spi *dln2 = spi_master_get_devdata(master);
850 return dln2_spi_enable(dln2, false);
853 static int dln2_spi_runtime_resume(struct device *dev)
855 struct spi_master *master = dev_get_drvdata(dev);
856 struct dln2_spi *dln2 = spi_master_get_devdata(master);
858 return dln2_spi_enable(dln2, true);
860 #endif /* CONFIG_PM */
862 static const struct dev_pm_ops dln2_spi_pm = {
863 SET_SYSTEM_SLEEP_PM_OPS(dln2_spi_suspend, dln2_spi_resume)
864 SET_RUNTIME_PM_OPS(dln2_spi_runtime_suspend,
865 dln2_spi_runtime_resume, NULL)
868 static struct platform_driver spi_dln2_driver = {
873 .probe = dln2_spi_probe,
874 .remove = dln2_spi_remove,
876 module_platform_driver(spi_dln2_driver);
878 MODULE_DESCRIPTION("Driver for the Diolan DLN2 SPI master interface");
879 MODULE_AUTHOR("Laurentiu Palcu <laurentiu.palcu@intel.com>");
880 MODULE_LICENSE("GPL v2");
881 MODULE_ALIAS("platform:dln2-spi");