drivers/spi/spi-cadence.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Cadence SPI controller driver (master and slave mode)
   4  *
   5  * Copyright (C) 2008 - 2014 Xilinx, Inc.
   6  *
   7  * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/gpio/consumer.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/module.h>
  16 #include <linux/of_irq.h>
  17 #include <linux/of_address.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/spi/spi.h>
  21
  22 /* Name of this driver */
  23 #define CDNS_SPI_NAME           "cdns-spi"
  24
  25 /* Register offset definitions */
  26 #define CDNS_SPI_CR     0x00 /* Configuration  Register, RW */
  27 #define CDNS_SPI_ISR    0x04 /* Interrupt Status Register, RO */
  28 #define CDNS_SPI_IER    0x08 /* Interrupt Enable Register, WO */
  29 #define CDNS_SPI_IDR    0x0c /* Interrupt Disable Register, WO */
  30 #define CDNS_SPI_IMR    0x10 /* Interrupt Enabled Mask Register, RO */
  31 #define CDNS_SPI_ER     0x14 /* Enable/Disable Register, RW */
  32 #define CDNS_SPI_DR     0x18 /* Delay Register, RW */
  33 #define CDNS_SPI_TXD    0x1C /* Data Transmit Register, WO */
  34 #define CDNS_SPI_RXD    0x20 /* Data Receive Register, RO */
  35 #define CDNS_SPI_SICR   0x24 /* Slave Idle Count Register, RW */
  36 #define CDNS_SPI_THLD   0x28 /* Transmit FIFO Watermark Register,RW */
  37
  38 #define SPI_AUTOSUSPEND_TIMEOUT         3000
  39 /*
  40  * SPI Configuration Register bit Masks
  41  *
  42  * This register contains various control bits that affect the operation
  43  * of the SPI controller
  44  */
  45 #define CDNS_SPI_CR_MANSTRT     0x00010000 /* Manual TX Start */
  46 #define CDNS_SPI_CR_CPHA                0x00000004 /* Clock Phase Control */
  47 #define CDNS_SPI_CR_CPOL                0x00000002 /* Clock Polarity Control */
  48 #define CDNS_SPI_CR_SSCTRL              0x00003C00 /* Slave Select Mask */
  49 #define CDNS_SPI_CR_PERI_SEL    0x00000200 /* Peripheral Select Decode */
  50 #define CDNS_SPI_CR_BAUD_DIV    0x00000038 /* Baud Rate Divisor Mask */
  51 #define CDNS_SPI_CR_MSTREN              0x00000001 /* Master Enable Mask */
  52 #define CDNS_SPI_CR_MANSTRTEN   0x00008000 /* Manual TX Enable Mask */
  53 #define CDNS_SPI_CR_SSFORCE     0x00004000 /* Manual SS Enable Mask */
  54 #define CDNS_SPI_CR_BAUD_DIV_4  0x00000008 /* Default Baud Div Mask */
  55 #define CDNS_SPI_CR_DEFAULT     (CDNS_SPI_CR_MSTREN | \
  56                                         CDNS_SPI_CR_SSCTRL | \
  57                                         CDNS_SPI_CR_SSFORCE | \
  58                                         CDNS_SPI_CR_BAUD_DIV_4)
  59
  60 /*
  61  * SPI Configuration Register - Baud rate and slave select
  62  *
  63  * These are the values used in the calculation of baud rate divisor and
  64  * setting the slave select.
  65  */
  66
  67 #define CDNS_SPI_BAUD_DIV_MAX           7 /* Baud rate divisor maximum */
  68 #define CDNS_SPI_BAUD_DIV_MIN           1 /* Baud rate divisor minimum */
  69 #define CDNS_SPI_BAUD_DIV_SHIFT         3 /* Baud rate divisor shift in CR */
  70 #define CDNS_SPI_SS_SHIFT               10 /* Slave Select field shift in CR */
  71 #define CDNS_SPI_SS0                    0x1 /* Slave Select zero */
  72 #define CDNS_SPI_NOSS                   0xF /* No Slave select */
  73
  74 /*
  75  * SPI Interrupt Registers bit Masks
  76  *
  77  * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
  78  * bit definitions.
  79  */
  80 #define CDNS_SPI_IXR_TXOW       0x00000004 /* SPI TX FIFO Overwater */
  81 #define CDNS_SPI_IXR_MODF       0x00000002 /* SPI Mode Fault */
  82 #define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
  83 #define CDNS_SPI_IXR_DEFAULT    (CDNS_SPI_IXR_TXOW | \
  84                                         CDNS_SPI_IXR_MODF)
  85 #define CDNS_SPI_IXR_TXFULL     0x00000008 /* SPI TX Full */
  86 #define CDNS_SPI_IXR_ALL        0x0000007F /* SPI all interrupts */
  87
  88 /*
  89  * SPI Enable Register bit Masks
  90  *
  91  * This register is used to enable or disable the SPI controller
  92  */
  93 #define CDNS_SPI_ER_ENABLE      0x00000001 /* SPI Enable Bit Mask */
  94 #define CDNS_SPI_ER_DISABLE     0x0 /* SPI Disable Bit Mask */
  95
  96 /* Default number of chip select lines */
  97 #define CDNS_SPI_DEFAULT_NUM_CS         4
  98
  99 /**
 100  * struct cdns_spi - This definition defines spi driver instance
 101  * @regs:               Virtual address of the SPI controller registers
 102  * @ref_clk:            Pointer to the peripheral clock
 103  * @pclk:               Pointer to the APB clock
 104  * @speed_hz:           Current SPI bus clock speed in Hz
 105  * @txbuf:              Pointer to the TX buffer
 106  * @rxbuf:              Pointer to the RX buffer
 107  * @tx_bytes:           Number of bytes left to transfer
 108  * @rx_bytes:           Number of bytes requested
 109  * @dev_busy:           Device busy flag
 110  * @is_decoded_cs:      Flag for decoder property set or not
 111  * @tx_fifo_depth:      Depth of the TX FIFO
 112  */
 113 struct cdns_spi {
 114         void __iomem *regs;
 115         struct clk *ref_clk;
 116         struct clk *pclk;
 117         unsigned int clk_rate;
 118         u32 speed_hz;
 119         const u8 *txbuf;
 120         u8 *rxbuf;
 121         int tx_bytes;
 122         int rx_bytes;
 123         u8 dev_busy;
 124         u32 is_decoded_cs;
 125         unsigned int tx_fifo_depth;
 126 };
 127
 128 /* Macros for the SPI controller read/write */
 129 static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
 130 {
 131         return readl_relaxed(xspi->regs + offset);
 132 }
 133
 134 static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
 135 {
 136         writel_relaxed(val, xspi->regs + offset);
 137 }
 138
 139 /**
 140  * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
 141  * @xspi:       Pointer to the cdns_spi structure
 142  * @is_slave:   Flag to indicate slave or master mode
 143  * * On reset the SPI controller is configured to slave or  master mode.
 144  * In master mode baud rate divisor is set to 4, threshold value for TX FIFO
 145  * not full interrupt is set to 1 and size of the word to be transferred as 8 bit.
 146  *
 147  * This function initializes the SPI controller to disable and clear all the
 148  * interrupts, enable manual slave select and manual start, deselect all the
 149  * chip select lines, and enable the SPI controller.
 150  */
 151 static void cdns_spi_init_hw(struct cdns_spi *xspi, bool is_slave)
 152 {
 153         u32 ctrl_reg = 0;
 154
 155         if (!is_slave)
 156                 ctrl_reg |= CDNS_SPI_CR_DEFAULT;
 157
 158         if (xspi->is_decoded_cs)
 159                 ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
 160
 161         cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
 162         cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL);
 163
 164         /* Clear the RX FIFO */
 165         while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY)
 166                 cdns_spi_read(xspi, CDNS_SPI_RXD);
 167
 168         cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL);
 169         cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
 170         cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
 171 }
 172
 173 /**
 174  * cdns_spi_chipselect - Select or deselect the chip select line
 175  * @spi:        Pointer to the spi_device structure
 176  * @is_high:    Select(0) or deselect (1) the chip select line
 177  */
 178 static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
 179 {
 180         struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
 181         u32 ctrl_reg;
 182
 183         ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
 184
 185         if (is_high) {
 186                 /* Deselect the slave */
 187                 ctrl_reg |= CDNS_SPI_CR_SSCTRL;
 188         } else {
 189                 /* Select the slave */
 190                 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
 191                 if (!(xspi->is_decoded_cs))
 192                         ctrl_reg |= ((~(CDNS_SPI_SS0 << spi_get_chipselect(spi, 0))) <<
 193                                      CDNS_SPI_SS_SHIFT) &
 194                                      CDNS_SPI_CR_SSCTRL;
 195                 else
 196                         ctrl_reg |= (spi_get_chipselect(spi, 0) << CDNS_SPI_SS_SHIFT) &
 197                                      CDNS_SPI_CR_SSCTRL;
 198         }
 199
 200         cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
 201 }
 202
 203 /**
 204  * cdns_spi_config_clock_mode - Sets clock polarity and phase
 205  * @spi:        Pointer to the spi_device structure
 206  *
 207  * Sets the requested clock polarity and phase.
 208  */
 209 static void cdns_spi_config_clock_mode(struct spi_device *spi)
 210 {
 211         struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
 212         u32 ctrl_reg, new_ctrl_reg;
 213
 214         new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
 215         ctrl_reg = new_ctrl_reg;
 216
 217         /* Set the SPI clock phase and clock polarity */
 218         new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL);
 219         if (spi->mode & SPI_CPHA)
 220                 new_ctrl_reg |= CDNS_SPI_CR_CPHA;
 221         if (spi->mode & SPI_CPOL)
 222                 new_ctrl_reg |= CDNS_SPI_CR_CPOL;
 223
 224         if (new_ctrl_reg != ctrl_reg) {
 225                 /*
 226                  * Just writing the CR register does not seem to apply the clock
 227                  * setting changes. This is problematic when changing the clock
 228                  * polarity as it will cause the SPI slave to see spurious clock
 229                  * transitions. To workaround the issue toggle the ER register.
 230                  */
 231                 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
 232                 cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg);
 233                 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
 234         }
 235 }
 236
 237 /**
 238  * cdns_spi_config_clock_freq - Sets clock frequency
 239  * @spi:        Pointer to the spi_device structure
 240  * @transfer:   Pointer to the spi_transfer structure which provides
 241  *              information about next transfer setup parameters
 242  *
 243  * Sets the requested clock frequency.
 244  * Note: If the requested frequency is not an exact match with what can be
 245  * obtained using the prescalar value the driver sets the clock frequency which
 246  * is lower than the requested frequency (maximum lower) for the transfer. If
 247  * the requested frequency is higher or lower than that is supported by the SPI
 248  * controller the driver will set the highest or lowest frequency supported by
 249  * controller.
 250  */
 251 static void cdns_spi_config_clock_freq(struct spi_device *spi,
 252                                        struct spi_transfer *transfer)
 253 {
 254         struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
 255         u32 ctrl_reg, baud_rate_val;
 256         unsigned long frequency;
 257
 258         frequency = xspi->clk_rate;
 259
 260         ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
 261
 262         /* Set the clock frequency */
 263         if (xspi->speed_hz != transfer->speed_hz) {
 264                 /* first valid value is 1 */
 265                 baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
 266                 while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
 267                        (frequency / (2 << baud_rate_val)) > transfer->speed_hz)
 268                         baud_rate_val++;
 269
 270                 ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;
 271                 ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
 272
 273                 xspi->speed_hz = frequency / (2 << baud_rate_val);
 274         }
 275         cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
 276 }
 277
 278 /**
 279  * cdns_spi_setup_transfer - Configure SPI controller for specified transfer
 280  * @spi:        Pointer to the spi_device structure
 281  * @transfer:   Pointer to the spi_transfer structure which provides
 282  *              information about next transfer setup parameters
 283  *
 284  * Sets the operational mode of SPI controller for the next SPI transfer and
 285  * sets the requested clock frequency.
 286  *
 287  * Return:      Always 0
 288  */
 289 static int cdns_spi_setup_transfer(struct spi_device *spi,
 290                                    struct spi_transfer *transfer)
 291 {
 292         struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
 293
 294         cdns_spi_config_clock_freq(spi, transfer);
 295
 296         dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
 297                 __func__, spi->mode, spi->bits_per_word,
 298                 xspi->speed_hz);
 299
 300         return 0;
 301 }
 302
 303 /**
 304  * cdns_spi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
 305  * @xspi:       Pointer to the cdns_spi structure
 306  */
 307 static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi)
 308 {
 309         unsigned long trans_cnt = 0;
 310
 311         while ((trans_cnt < xspi->tx_fifo_depth) &&
 312                (xspi->tx_bytes > 0)) {
 313
 314                 /* When xspi in busy condition, bytes may send failed,
 315                  * then spi control did't work thoroughly, add one byte delay
 316                  */
 317                 if (cdns_spi_read(xspi, CDNS_SPI_ISR) &
 318                     CDNS_SPI_IXR_TXFULL)
 319                         udelay(10);
 320
 321                 if (xspi->txbuf)
 322                         cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
 323                 else
 324                         cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
 325
 326                 xspi->tx_bytes--;
 327                 trans_cnt++;
 328         }
 329 }
 330
 331 /**
 332  * cdns_spi_read_rx_fifo - Reads the RX FIFO with as many bytes as possible
 333  * @xspi:       Pointer to the cdns_spi structure
 334  * @count:      Read byte count
 335  */
 336 static void cdns_spi_read_rx_fifo(struct cdns_spi *xspi, unsigned long count)
 337 {
 338         u8 data;
 339
 340         /* Read out the data from the RX FIFO */
 341         while (count > 0) {
 342                 data = cdns_spi_read(xspi, CDNS_SPI_RXD);
 343                 if (xspi->rxbuf)
 344                         *xspi->rxbuf++ = data;
 345                 xspi->rx_bytes--;
 346                 count--;
 347         }
 348 }
 349
 350 /**
 351  * cdns_spi_irq - Interrupt service routine of the SPI controller
 352  * @irq:        IRQ number
 353  * @dev_id:     Pointer to the xspi structure
 354  *
 355  * This function handles TX empty and Mode Fault interrupts only.
 356  * On TX empty interrupt this function reads the received data from RX FIFO and
 357  * fills the TX FIFO if there is any data remaining to be transferred.
 358  * On Mode Fault interrupt this function indicates that transfer is completed,
 359  * the SPI subsystem will identify the error as the remaining bytes to be
 360  * transferred is non-zero.
 361  *
 362  * Return:      IRQ_HANDLED when handled; IRQ_NONE otherwise.
 363  */
 364 static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
 365 {
 366         struct spi_controller *ctlr = dev_id;
 367         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 368         irqreturn_t status;
 369         u32 intr_status;
 370
 371         status = IRQ_NONE;
 372         intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
 373         cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
 374
 375         if (intr_status & CDNS_SPI_IXR_MODF) {
 376                 /* Indicate that transfer is completed, the SPI subsystem will
 377                  * identify the error as the remaining bytes to be
 378                  * transferred is non-zero
 379                  */
 380                 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT);
 381                 spi_finalize_current_transfer(ctlr);
 382                 status = IRQ_HANDLED;
 383         } else if (intr_status & CDNS_SPI_IXR_TXOW) {
 384                 int trans_cnt = cdns_spi_read(xspi, CDNS_SPI_THLD);
 385                 /* Set threshold to one if number of pending are
 386                  * less than half fifo
 387                  */
 388                 if (xspi->tx_bytes < xspi->tx_fifo_depth >> 1)
 389                         cdns_spi_write(xspi, CDNS_SPI_THLD, 1);
 390
 391                 while (trans_cnt) {
 392                         cdns_spi_read_rx_fifo(xspi, 1);
 393
 394                         if (xspi->tx_bytes) {
 395                                 if (xspi->txbuf)
 396                                         cdns_spi_write(xspi, CDNS_SPI_TXD,
 397                                                        *xspi->txbuf++);
 398                                 else
 399                                         cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
 400                                 xspi->tx_bytes--;
 401                         }
 402                         trans_cnt--;
 403                 }
 404                 if (!xspi->tx_bytes) {
 405                         /* Fixed delay due to controller limitation with
 406                          * RX_NEMPTY incorrect status
 407                          * Xilinx AR:65885 contains more details
 408                          */
 409                         udelay(10);
 410                         cdns_spi_read_rx_fifo(xspi, xspi->rx_bytes);
 411                         cdns_spi_write(xspi, CDNS_SPI_IDR,
 412                                        CDNS_SPI_IXR_DEFAULT);
 413                         spi_finalize_current_transfer(ctlr);
 414                 }
 415                 status = IRQ_HANDLED;
 416         }
 417
 418         return status;
 419 }
 420
 421 static int cdns_prepare_message(struct spi_controller *ctlr,
 422                                 struct spi_message *msg)
 423 {
 424         if (!spi_controller_is_slave(ctlr))
 425                 cdns_spi_config_clock_mode(msg->spi);
 426         return 0;
 427 }
 428
 429 /**
 430  * cdns_transfer_one - Initiates the SPI transfer
 431  * @ctlr:       Pointer to spi_controller structure
 432  * @spi:        Pointer to the spi_device structure
 433  * @transfer:   Pointer to the spi_transfer structure which provides
 434  *              information about next transfer parameters
 435  *
 436  * This function in master mode fills the TX FIFO, starts the SPI transfer and
 437  * returns a positive transfer count so that core will wait for completion.
 438  * This function in slave mode fills the TX FIFO and wait for transfer trigger.
 439  *
 440  * Return:      Number of bytes transferred in the last transfer
 441  */
 442 static int cdns_transfer_one(struct spi_controller *ctlr,
 443                              struct spi_device *spi,
 444                              struct spi_transfer *transfer)
 445 {
 446         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 447
 448         xspi->txbuf = transfer->tx_buf;
 449         xspi->rxbuf = transfer->rx_buf;
 450         xspi->tx_bytes = transfer->len;
 451         xspi->rx_bytes = transfer->len;
 452
 453         if (!spi_controller_is_slave(ctlr))
 454                 cdns_spi_setup_transfer(spi, transfer);
 455
 456         /* Set TX empty threshold to half of FIFO depth
 457          * only if TX bytes are more than half FIFO depth.
 458          */
 459         if (xspi->tx_bytes > (xspi->tx_fifo_depth >> 1))
 460                 cdns_spi_write(xspi, CDNS_SPI_THLD, xspi->tx_fifo_depth >> 1);
 461
 462         cdns_spi_fill_tx_fifo(xspi);
 463         spi_transfer_delay_exec(transfer);
 464
 465         cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT);
 466         return transfer->len;
 467 }
 468
 469 /**
 470  * cdns_prepare_transfer_hardware - Prepares hardware for transfer.
 471  * @ctlr:       Pointer to the spi_controller structure which provides
 472  *              information about the controller.
 473  *
 474  * This function enables SPI master controller.
 475  *
 476  * Return:      0 always
 477  */
 478 static int cdns_prepare_transfer_hardware(struct spi_controller *ctlr)
 479 {
 480         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 481
 482         cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
 483
 484         return 0;
 485 }
 486
 487 /**
 488  * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
 489  * @ctlr:       Pointer to the spi_controller structure which provides
 490  *              information about the controller.
 491  *
 492  * This function disables the SPI master controller when no slave selected.
 493  * This function flush out if any pending data in FIFO.
 494  *
 495  * Return:      0 always
 496  */
 497 static int cdns_unprepare_transfer_hardware(struct spi_controller *ctlr)
 498 {
 499         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 500         u32 ctrl_reg;
 501         unsigned int cnt = xspi->tx_fifo_depth;
 502
 503         if (spi_controller_is_slave(ctlr)) {
 504                 while (cnt--)
 505                         cdns_spi_read(xspi, CDNS_SPI_RXD);
 506         }
 507
 508         /* Disable the SPI if slave is deselected */
 509         ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
 510         ctrl_reg = (ctrl_reg & CDNS_SPI_CR_SSCTRL) >>  CDNS_SPI_SS_SHIFT;
 511         if (ctrl_reg == CDNS_SPI_NOSS || spi_controller_is_slave(ctlr))
 512                 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
 513
 514         /* Reset to default */
 515         cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
 516         return 0;
 517 }
 518
 519 /**
 520  * cdns_spi_detect_fifo_depth - Detect the FIFO depth of the hardware
 521  * @xspi:       Pointer to the cdns_spi structure
 522  *
 523  * The depth of the TX FIFO is a synthesis configuration parameter of the SPI
 524  * IP. The FIFO threshold register is sized so that its maximum value can be the
 525  * FIFO size - 1. This is used to detect the size of the FIFO.
 526  */
 527 static void cdns_spi_detect_fifo_depth(struct cdns_spi *xspi)
 528 {
 529         /* The MSBs will get truncated giving us the size of the FIFO */
 530         cdns_spi_write(xspi, CDNS_SPI_THLD, 0xffff);
 531         xspi->tx_fifo_depth = cdns_spi_read(xspi, CDNS_SPI_THLD) + 1;
 532
 533         /* Reset to default */
 534         cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
 535 }
 536
 537 /**
 538  * cdns_slave_abort - Abort slave transfer
 539  * @ctlr:       Pointer to the spi_controller structure
 540  *
 541  * This function abort slave transfer if there any transfer timeout.
 542  *
 543  * Return:      0 always
 544  */
 545 static int cdns_slave_abort(struct spi_controller *ctlr)
 546 {
 547         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 548         u32 intr_status;
 549
 550         intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
 551         cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
 552         cdns_spi_write(xspi, CDNS_SPI_IDR, (CDNS_SPI_IXR_MODF | CDNS_SPI_IXR_RXNEMTY));
 553         spi_finalize_current_transfer(ctlr);
 554
 555         return 0;
 556 }
 557
 558 /**
 559  * cdns_spi_probe - Probe method for the SPI driver
 560  * @pdev:       Pointer to the platform_device structure
 561  *
 562  * This function initializes the driver data structures and the hardware.
 563  *
 564  * Return:      0 on success and error value on error
 565  */
 566 static int cdns_spi_probe(struct platform_device *pdev)
 567 {
 568         int ret = 0, irq;
 569         struct spi_controller *ctlr;
 570         struct cdns_spi *xspi;
 571         u32 num_cs;
 572         bool slave;
 573
 574         slave = of_property_read_bool(pdev->dev.of_node, "spi-slave");
 575         if (slave)
 576                 ctlr = spi_alloc_slave(&pdev->dev, sizeof(*xspi));
 577         else
 578                 ctlr = spi_alloc_master(&pdev->dev, sizeof(*xspi));
 579
 580         if (!ctlr)
 581                 return -ENOMEM;
 582
 583         xspi = spi_controller_get_devdata(ctlr);
 584         ctlr->dev.of_node = pdev->dev.of_node;
 585         platform_set_drvdata(pdev, ctlr);
 586
 587         xspi->regs = devm_platform_ioremap_resource(pdev, 0);
 588         if (IS_ERR(xspi->regs)) {
 589                 ret = PTR_ERR(xspi->regs);
 590                 goto remove_ctlr;
 591         }
 592
 593         xspi->pclk = devm_clk_get(&pdev->dev, "pclk");
 594         if (IS_ERR(xspi->pclk)) {
 595                 dev_err(&pdev->dev, "pclk clock not found.\n");
 596                 ret = PTR_ERR(xspi->pclk);
 597                 goto remove_ctlr;
 598         }
 599
 600         ret = clk_prepare_enable(xspi->pclk);
 601         if (ret) {
 602                 dev_err(&pdev->dev, "Unable to enable APB clock.\n");
 603                 goto remove_ctlr;
 604         }
 605
 606         if (!spi_controller_is_slave(ctlr)) {
 607                 xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
 608                 if (IS_ERR(xspi->ref_clk)) {
 609                         dev_err(&pdev->dev, "ref_clk clock not found.\n");
 610                         ret = PTR_ERR(xspi->ref_clk);
 611                         goto clk_dis_apb;
 612                 }
 613
 614                 ret = clk_prepare_enable(xspi->ref_clk);
 615                 if (ret) {
 616                         dev_err(&pdev->dev, "Unable to enable device clock.\n");
 617                         goto clk_dis_apb;
 618                 }
 619
 620                 pm_runtime_use_autosuspend(&pdev->dev);
 621                 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
 622                 pm_runtime_get_noresume(&pdev->dev);
 623                 pm_runtime_set_active(&pdev->dev);
 624                 pm_runtime_enable(&pdev->dev);
 625
 626                 ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
 627                 if (ret < 0)
 628                         ctlr->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
 629                 else
 630                         ctlr->num_chipselect = num_cs;
 631
 632                 ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
 633                                            &xspi->is_decoded_cs);
 634                 if (ret < 0)
 635                         xspi->is_decoded_cs = 0;
 636         }
 637
 638         cdns_spi_detect_fifo_depth(xspi);
 639
 640         /* SPI controller initializations */
 641         cdns_spi_init_hw(xspi, spi_controller_is_slave(ctlr));
 642
 643         irq = platform_get_irq(pdev, 0);
 644         if (irq <= 0) {
 645                 ret = -ENXIO;
 646                 goto clk_dis_all;
 647         }
 648
 649         ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
 650                                0, pdev->name, ctlr);
 651         if (ret != 0) {
 652                 ret = -ENXIO;
 653                 dev_err(&pdev->dev, "request_irq failed\n");
 654                 goto clk_dis_all;
 655         }
 656
 657         ctlr->use_gpio_descriptors = true;
 658         ctlr->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
 659         ctlr->prepare_message = cdns_prepare_message;
 660         ctlr->transfer_one = cdns_transfer_one;
 661         ctlr->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
 662         ctlr->mode_bits = SPI_CPOL | SPI_CPHA;
 663         ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
 664
 665         if (!spi_controller_is_slave(ctlr)) {
 666                 ctlr->mode_bits |=  SPI_CS_HIGH;
 667                 ctlr->set_cs = cdns_spi_chipselect;
 668                 ctlr->auto_runtime_pm = true;
 669                 xspi->clk_rate = clk_get_rate(xspi->ref_clk);
 670                 /* Set to default valid value */
 671                 ctlr->max_speed_hz = xspi->clk_rate / 4;
 672                 xspi->speed_hz = ctlr->max_speed_hz;
 673                 pm_runtime_mark_last_busy(&pdev->dev);
 674                 pm_runtime_put_autosuspend(&pdev->dev);
 675         } else {
 676                 ctlr->mode_bits |= SPI_NO_CS;
 677                 ctlr->slave_abort = cdns_slave_abort;
 678         }
 679         ret = spi_register_controller(ctlr);
 680         if (ret) {
 681                 dev_err(&pdev->dev, "spi_register_controller failed\n");
 682                 goto clk_dis_all;
 683         }
 684
 685         return ret;
 686
 687 clk_dis_all:
 688         if (!spi_controller_is_slave(ctlr)) {
 689                 pm_runtime_set_suspended(&pdev->dev);
 690                 pm_runtime_disable(&pdev->dev);
 691                 clk_disable_unprepare(xspi->ref_clk);
 692         }
 693 clk_dis_apb:
 694         clk_disable_unprepare(xspi->pclk);
 695 remove_ctlr:
 696         spi_controller_put(ctlr);
 697         return ret;
 698 }
 699
 700 /**
 701  * cdns_spi_remove - Remove method for the SPI driver
 702  * @pdev:       Pointer to the platform_device structure
 703  *
 704  * This function is called if a device is physically removed from the system or
 705  * if the driver module is being unloaded. It frees all resources allocated to
 706  * the device.
 707  *
 708  * Return:      0 on success and error value on error
 709  */
 710 static void cdns_spi_remove(struct platform_device *pdev)
 711 {
 712         struct spi_controller *ctlr = platform_get_drvdata(pdev);
 713         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 714
 715         cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
 716
 717         clk_disable_unprepare(xspi->ref_clk);
 718         clk_disable_unprepare(xspi->pclk);
 719         pm_runtime_set_suspended(&pdev->dev);
 720         pm_runtime_disable(&pdev->dev);
 721
 722         spi_unregister_controller(ctlr);
 723 }
 724
 725 /**
 726  * cdns_spi_suspend - Suspend method for the SPI driver
 727  * @dev:        Address of the platform_device structure
 728  *
 729  * This function disables the SPI controller and
 730  * changes the driver state to "suspend"
 731  *
 732  * Return:      0 on success and error value on error
 733  */
 734 static int __maybe_unused cdns_spi_suspend(struct device *dev)
 735 {
 736         struct spi_controller *ctlr = dev_get_drvdata(dev);
 737
 738         return spi_controller_suspend(ctlr);
 739 }
 740
 741 /**
 742  * cdns_spi_resume - Resume method for the SPI driver
 743  * @dev:        Address of the platform_device structure
 744  *
 745  * This function changes the driver state to "ready"
 746  *
 747  * Return:      0 on success and error value on error
 748  */
 749 static int __maybe_unused cdns_spi_resume(struct device *dev)
 750 {
 751         struct spi_controller *ctlr = dev_get_drvdata(dev);
 752         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 753
 754         cdns_spi_init_hw(xspi, spi_controller_is_slave(ctlr));
 755         return spi_controller_resume(ctlr);
 756 }
 757
 758 /**
 759  * cdns_spi_runtime_resume - Runtime resume method for the SPI driver
 760  * @dev:        Address of the platform_device structure
 761  *
 762  * This function enables the clocks
 763  *
 764  * Return:      0 on success and error value on error
 765  */
 766 static int __maybe_unused cdns_spi_runtime_resume(struct device *dev)
 767 {
 768         struct spi_controller *ctlr = dev_get_drvdata(dev);
 769         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 770         int ret;
 771
 772         ret = clk_prepare_enable(xspi->pclk);
 773         if (ret) {
 774                 dev_err(dev, "Cannot enable APB clock.\n");
 775                 return ret;
 776         }
 777
 778         ret = clk_prepare_enable(xspi->ref_clk);
 779         if (ret) {
 780                 dev_err(dev, "Cannot enable device clock.\n");
 781                 clk_disable_unprepare(xspi->pclk);
 782                 return ret;
 783         }
 784         return 0;
 785 }
 786
 787 /**
 788  * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver
 789  * @dev:        Address of the platform_device structure
 790  *
 791  * This function disables the clocks
 792  *
 793  * Return:      Always 0
 794  */
 795 static int __maybe_unused cdns_spi_runtime_suspend(struct device *dev)
 796 {
 797         struct spi_controller *ctlr = dev_get_drvdata(dev);
 798         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 799
 800         clk_disable_unprepare(xspi->ref_clk);
 801         clk_disable_unprepare(xspi->pclk);
 802
 803         return 0;
 804 }
 805
 806 static const struct dev_pm_ops cdns_spi_dev_pm_ops = {
 807         SET_RUNTIME_PM_OPS(cdns_spi_runtime_suspend,
 808                            cdns_spi_runtime_resume, NULL)
 809         SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume)
 810 };
 811
 812 static const struct of_device_id cdns_spi_of_match[] = {
 813         { .compatible = "xlnx,zynq-spi-r1p6" },
 814         { .compatible = "cdns,spi-r1p6" },
 815         { /* end of table */ }
 816 };
 817 MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
 818
 819 /* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
 820 static struct platform_driver cdns_spi_driver = {
 821         .probe  = cdns_spi_probe,
 822         .remove_new = cdns_spi_remove,
 823         .driver = {
 824                 .name = CDNS_SPI_NAME,
 825                 .of_match_table = cdns_spi_of_match,
 826                 .pm = &cdns_spi_dev_pm_ops,
 827         },
 828 };
 829
 830 module_platform_driver(cdns_spi_driver);
 831
 832 MODULE_AUTHOR("Xilinx, Inc.");
 833 MODULE_DESCRIPTION("Cadence SPI driver");
 834 MODULE_LICENSE("GPL");