drivers/spi/spi-cadence-quadspi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 //
   3 // Driver for Cadence QSPI Controller
   4 //
   5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
   6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
   7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
   8
   9 #include <linux/clk.h>
  10 #include <linux/completion.h>
  11 #include <linux/delay.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/dmaengine.h>
  14 #include <linux/err.h>
  15 #include <linux/errno.h>
  16 #include <linux/firmware/xlnx-zynqmp.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/jiffies.h>
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/reset.h>
  28 #include <linux/sched.h>
  29 #include <linux/spi/spi.h>
  30 #include <linux/spi/spi-mem.h>
  31 #include <linux/timer.h>
  32
  33 #define CQSPI_NAME                      "cadence-qspi"
  34 #define CQSPI_MAX_CHIPSELECT            16
  35
  36 /* Quirks */
  37 #define CQSPI_NEEDS_WR_DELAY            BIT(0)
  38 #define CQSPI_DISABLE_DAC_MODE          BIT(1)
  39 #define CQSPI_SUPPORT_EXTERNAL_DMA      BIT(2)
  40
  41 /* Capabilities */
  42 #define CQSPI_SUPPORTS_OCTAL            BIT(0)
  43
  44 struct cqspi_st;
  45
  46 struct cqspi_flash_pdata {
  47         struct cqspi_st *cqspi;
  48         u32             clk_rate;
  49         u32             read_delay;
  50         u32             tshsl_ns;
  51         u32             tsd2d_ns;
  52         u32             tchsh_ns;
  53         u32             tslch_ns;
  54         u8              inst_width;
  55         u8              addr_width;
  56         u8              data_width;
  57         bool            dtr;
  58         u8              cs;
  59 };
  60
  61 struct cqspi_st {
  62         struct platform_device  *pdev;
  63
  64         struct clk              *clk;
  65         unsigned int            sclk;
  66
  67         void __iomem            *iobase;
  68         void __iomem            *ahb_base;
  69         resource_size_t         ahb_size;
  70         struct completion       transfer_complete;
  71
  72         struct dma_chan         *rx_chan;
  73         struct completion       rx_dma_complete;
  74         dma_addr_t              mmap_phys_base;
  75
  76         int                     current_cs;
  77         unsigned long           master_ref_clk_hz;
  78         bool                    is_decoded_cs;
  79         u32                     fifo_depth;
  80         u32                     fifo_width;
  81         u32                     num_chipselect;
  82         bool                    rclk_en;
  83         u32                     trigger_address;
  84         u32                     wr_delay;
  85         bool                    use_direct_mode;
  86         struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
  87         bool                    use_dma_read;
  88         u32                     pd_dev_id;
  89 };
  90
  91 struct cqspi_driver_platdata {
  92         u32 hwcaps_mask;
  93         u8 quirks;
  94         int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata,
  95                                  u_char *rxbuf, loff_t from_addr, size_t n_rx);
  96         u32 (*get_dma_status)(struct cqspi_st *cqspi);
  97 };
  98
  99 /* Operation timeout value */
 100 #define CQSPI_TIMEOUT_MS                        500
 101 #define CQSPI_READ_TIMEOUT_MS                   10
 102
 103 /* Instruction type */
 104 #define CQSPI_INST_TYPE_SINGLE                  0
 105 #define CQSPI_INST_TYPE_DUAL                    1
 106 #define CQSPI_INST_TYPE_QUAD                    2
 107 #define CQSPI_INST_TYPE_OCTAL                   3
 108
 109 #define CQSPI_DUMMY_CLKS_PER_BYTE               8
 110 #define CQSPI_DUMMY_BYTES_MAX                   4
 111 #define CQSPI_DUMMY_CLKS_MAX                    31
 112
 113 #define CQSPI_STIG_DATA_LEN_MAX                 8
 114
 115 /* Register map */
 116 #define CQSPI_REG_CONFIG                        0x00
 117 #define CQSPI_REG_CONFIG_ENABLE_MASK            BIT(0)
 118 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL       BIT(7)
 119 #define CQSPI_REG_CONFIG_DECODE_MASK            BIT(9)
 120 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
 121 #define CQSPI_REG_CONFIG_DMA_MASK               BIT(15)
 122 #define CQSPI_REG_CONFIG_BAUD_LSB               19
 123 #define CQSPI_REG_CONFIG_DTR_PROTO              BIT(24)
 124 #define CQSPI_REG_CONFIG_DUAL_OPCODE            BIT(30)
 125 #define CQSPI_REG_CONFIG_IDLE_LSB               31
 126 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
 127 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
 128
 129 #define CQSPI_REG_RD_INSTR                      0x04
 130 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
 131 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
 132 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
 133 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
 134 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
 135 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
 136 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
 137 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
 138 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
 139 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
 140
 141 #define CQSPI_REG_WR_INSTR                      0x08
 142 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
 143 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB        12
 144 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB        16
 145
 146 #define CQSPI_REG_DELAY                         0x0C
 147 #define CQSPI_REG_DELAY_TSLCH_LSB               0
 148 #define CQSPI_REG_DELAY_TCHSH_LSB               8
 149 #define CQSPI_REG_DELAY_TSD2D_LSB               16
 150 #define CQSPI_REG_DELAY_TSHSL_LSB               24
 151 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
 152 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
 153 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
 154 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
 155
 156 #define CQSPI_REG_READCAPTURE                   0x10
 157 #define CQSPI_REG_READCAPTURE_BYPASS_LSB        0
 158 #define CQSPI_REG_READCAPTURE_DELAY_LSB         1
 159 #define CQSPI_REG_READCAPTURE_DELAY_MASK        0xF
 160
 161 #define CQSPI_REG_SIZE                          0x14
 162 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 163 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 164 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 165 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 166 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 167 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 168
 169 #define CQSPI_REG_SRAMPARTITION                 0x18
 170 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 171
 172 #define CQSPI_REG_DMA                           0x20
 173 #define CQSPI_REG_DMA_SINGLE_LSB                0
 174 #define CQSPI_REG_DMA_BURST_LSB                 8
 175 #define CQSPI_REG_DMA_SINGLE_MASK               0xFF
 176 #define CQSPI_REG_DMA_BURST_MASK                0xFF
 177
 178 #define CQSPI_REG_REMAP                         0x24
 179 #define CQSPI_REG_MODE_BIT                      0x28
 180
 181 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 182 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 183 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 184 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 185 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 186
 187 #define CQSPI_REG_WR_COMPLETION_CTRL            0x38
 188 #define CQSPI_REG_WR_DISABLE_AUTO_POLL          BIT(14)
 189
 190 #define CQSPI_REG_IRQSTATUS                     0x40
 191 #define CQSPI_REG_IRQMASK                       0x44
 192
 193 #define CQSPI_REG_INDIRECTRD                    0x60
 194 #define CQSPI_REG_INDIRECTRD_START_MASK         BIT(0)
 195 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK        BIT(1)
 196 #define CQSPI_REG_INDIRECTRD_DONE_MASK          BIT(5)
 197
 198 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 199 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 200 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 201
 202 #define CQSPI_REG_CMDCTRL                       0x90
 203 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK          BIT(0)
 204 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK       BIT(1)
 205 #define CQSPI_REG_CMDCTRL_DUMMY_LSB             7
 206 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 207 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 208 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 209 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 210 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 211 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 212 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 213 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 214 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 215 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 216 #define CQSPI_REG_CMDCTRL_DUMMY_MASK            0x1F
 217
 218 #define CQSPI_REG_INDIRECTWR                    0x70
 219 #define CQSPI_REG_INDIRECTWR_START_MASK         BIT(0)
 220 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK        BIT(1)
 221 #define CQSPI_REG_INDIRECTWR_DONE_MASK          BIT(5)
 222
 223 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 224 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 225 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 226
 227 #define CQSPI_REG_INDTRIG_ADDRRANGE             0x80
 228
 229 #define CQSPI_REG_CMDADDRESS                    0x94
 230 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 231 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 232 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 233 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 234
 235 #define CQSPI_REG_POLLING_STATUS                0xB0
 236 #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB      16
 237
 238 #define CQSPI_REG_OP_EXT_LOWER                  0xE0
 239 #define CQSPI_REG_OP_EXT_READ_LSB               24
 240 #define CQSPI_REG_OP_EXT_WRITE_LSB              16
 241 #define CQSPI_REG_OP_EXT_STIG_LSB               0
 242
 243 #define CQSPI_REG_VERSAL_DMA_SRC_ADDR           0x1000
 244
 245 #define CQSPI_REG_VERSAL_DMA_DST_ADDR           0x1800
 246 #define CQSPI_REG_VERSAL_DMA_DST_SIZE           0x1804
 247
 248 #define CQSPI_REG_VERSAL_DMA_DST_CTRL           0x180C
 249
 250 #define CQSPI_REG_VERSAL_DMA_DST_I_STS          0x1814
 251 #define CQSPI_REG_VERSAL_DMA_DST_I_EN           0x1818
 252 #define CQSPI_REG_VERSAL_DMA_DST_I_DIS          0x181C
 253 #define CQSPI_REG_VERSAL_DMA_DST_DONE_MASK      BIT(1)
 254
 255 #define CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB       0x1828
 256
 257 #define CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL       0xF43FFA00
 258 #define CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL    0x6
 259
 260 /* Interrupt status bits */
 261 #define CQSPI_REG_IRQ_MODE_ERR                  BIT(0)
 262 #define CQSPI_REG_IRQ_UNDERFLOW                 BIT(1)
 263 #define CQSPI_REG_IRQ_IND_COMP                  BIT(2)
 264 #define CQSPI_REG_IRQ_IND_RD_REJECT             BIT(3)
 265 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR          BIT(4)
 266 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR           BIT(5)
 267 #define CQSPI_REG_IRQ_WATERMARK                 BIT(6)
 268 #define CQSPI_REG_IRQ_IND_SRAM_FULL             BIT(12)
 269
 270 #define CQSPI_IRQ_MASK_RD               (CQSPI_REG_IRQ_WATERMARK        | \
 271                                          CQSPI_REG_IRQ_IND_SRAM_FULL    | \
 272                                          CQSPI_REG_IRQ_IND_COMP)
 273
 274 #define CQSPI_IRQ_MASK_WR               (CQSPI_REG_IRQ_IND_COMP         | \
 275                                          CQSPI_REG_IRQ_WATERMARK        | \
 276                                          CQSPI_REG_IRQ_UNDERFLOW)
 277
 278 #define CQSPI_IRQ_STATUS_MASK           0x1FFFF
 279 #define CQSPI_DMA_UNALIGN               0x3
 280
 281 #define CQSPI_REG_VERSAL_DMA_VAL                0x602
 282
 283 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr)
 284 {
 285         u32 val;
 286
 287         return readl_relaxed_poll_timeout(reg, val,
 288                                           (((clr ? ~val : val) & mask) == mask),
 289                                           10, CQSPI_TIMEOUT_MS * 1000);
 290 }
 291
 292 static bool cqspi_is_idle(struct cqspi_st *cqspi)
 293 {
 294         u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 295
 296         return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB);
 297 }
 298
 299 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
 300 {
 301         u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
 302
 303         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 304         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 305 }
 306
 307 static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi)
 308 {
 309         u32 dma_status;
 310
 311         dma_status = readl(cqspi->iobase +
 312                                            CQSPI_REG_VERSAL_DMA_DST_I_STS);
 313         writel(dma_status, cqspi->iobase +
 314                    CQSPI_REG_VERSAL_DMA_DST_I_STS);
 315
 316         return dma_status & CQSPI_REG_VERSAL_DMA_DST_DONE_MASK;
 317 }
 318
 319 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
 320 {
 321         struct cqspi_st *cqspi = dev;
 322         unsigned int irq_status;
 323         struct device *device = &cqspi->pdev->dev;
 324         const struct cqspi_driver_platdata *ddata;
 325
 326         ddata = of_device_get_match_data(device);
 327
 328         /* Read interrupt status */
 329         irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
 330
 331         /* Clear interrupt */
 332         writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
 333
 334         if (cqspi->use_dma_read && ddata && ddata->get_dma_status) {
 335                 if (ddata->get_dma_status(cqspi)) {
 336                         complete(&cqspi->transfer_complete);
 337                         return IRQ_HANDLED;
 338                 }
 339         }
 340
 341         irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
 342
 343         if (irq_status)
 344                 complete(&cqspi->transfer_complete);
 345
 346         return IRQ_HANDLED;
 347 }
 348
 349 static unsigned int cqspi_calc_rdreg(struct cqspi_flash_pdata *f_pdata)
 350 {
 351         u32 rdreg = 0;
 352
 353         rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
 354         rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
 355         rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 356
 357         return rdreg;
 358 }
 359
 360 static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr)
 361 {
 362         unsigned int dummy_clk;
 363
 364         if (!op->dummy.nbytes)
 365                 return 0;
 366
 367         dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);
 368         if (dtr)
 369                 dummy_clk /= 2;
 370
 371         return dummy_clk;
 372 }
 373
 374 static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata,
 375                               const struct spi_mem_op *op)
 376 {
 377         f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
 378         f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
 379         f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
 380
 381         /*
 382          * For an op to be DTR, cmd phase along with every other non-empty
 383          * phase should have dtr field set to 1. If an op phase has zero
 384          * nbytes, ignore its dtr field; otherwise, check its dtr field.
 385          */
 386         f_pdata->dtr = op->cmd.dtr &&
 387                        (!op->addr.nbytes || op->addr.dtr) &&
 388                        (!op->data.nbytes || op->data.dtr);
 389
 390         switch (op->data.buswidth) {
 391         case 0:
 392                 break;
 393         case 1:
 394                 f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
 395                 break;
 396         case 2:
 397                 f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
 398                 break;
 399         case 4:
 400                 f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
 401                 break;
 402         case 8:
 403                 f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
 404                 break;
 405         default:
 406                 return -EINVAL;
 407         }
 408
 409         /* Right now we only support 8-8-8 DTR mode. */
 410         if (f_pdata->dtr) {
 411                 switch (op->cmd.buswidth) {
 412                 case 0:
 413                         break;
 414                 case 8:
 415                         f_pdata->inst_width = CQSPI_INST_TYPE_OCTAL;
 416                         break;
 417                 default:
 418                         return -EINVAL;
 419                 }
 420
 421                 switch (op->addr.buswidth) {
 422                 case 0:
 423                         break;
 424                 case 8:
 425                         f_pdata->addr_width = CQSPI_INST_TYPE_OCTAL;
 426                         break;
 427                 default:
 428                         return -EINVAL;
 429                 }
 430
 431                 switch (op->data.buswidth) {
 432                 case 0:
 433                         break;
 434                 case 8:
 435                         f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
 436                         break;
 437                 default:
 438                         return -EINVAL;
 439                 }
 440         }
 441
 442         return 0;
 443 }
 444
 445 static int cqspi_wait_idle(struct cqspi_st *cqspi)
 446 {
 447         const unsigned int poll_idle_retry = 3;
 448         unsigned int count = 0;
 449         unsigned long timeout;
 450
 451         timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 452         while (1) {
 453                 /*
 454                  * Read few times in succession to ensure the controller
 455                  * is indeed idle, that is, the bit does not transition
 456                  * low again.
 457                  */
 458                 if (cqspi_is_idle(cqspi))
 459                         count++;
 460                 else
 461                         count = 0;
 462
 463                 if (count >= poll_idle_retry)
 464                         return 0;
 465
 466                 if (time_after(jiffies, timeout)) {
 467                         /* Timeout, in busy mode. */
 468                         dev_err(&cqspi->pdev->dev,
 469                                 "QSPI is still busy after %dms timeout.\n",
 470                                 CQSPI_TIMEOUT_MS);
 471                         return -ETIMEDOUT;
 472                 }
 473
 474                 cpu_relax();
 475         }
 476 }
 477
 478 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
 479 {
 480         void __iomem *reg_base = cqspi->iobase;
 481         int ret;
 482
 483         /* Write the CMDCTRL without start execution. */
 484         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 485         /* Start execute */
 486         reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
 487         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 488
 489         /* Polling for completion. */
 490         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
 491                                  CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
 492         if (ret) {
 493                 dev_err(&cqspi->pdev->dev,
 494                         "Flash command execution timed out.\n");
 495                 return ret;
 496         }
 497
 498         /* Polling QSPI idle status. */
 499         return cqspi_wait_idle(cqspi);
 500 }
 501
 502 static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata,
 503                                   const struct spi_mem_op *op,
 504                                   unsigned int shift)
 505 {
 506         struct cqspi_st *cqspi = f_pdata->cqspi;
 507         void __iomem *reg_base = cqspi->iobase;
 508         unsigned int reg;
 509         u8 ext;
 510
 511         if (op->cmd.nbytes != 2)
 512                 return -EINVAL;
 513
 514         /* Opcode extension is the LSB. */
 515         ext = op->cmd.opcode & 0xff;
 516
 517         reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER);
 518         reg &= ~(0xff << shift);
 519         reg |= ext << shift;
 520         writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER);
 521
 522         return 0;
 523 }
 524
 525 static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata,
 526                             const struct spi_mem_op *op, unsigned int shift,
 527                             bool enable)
 528 {
 529         struct cqspi_st *cqspi = f_pdata->cqspi;
 530         void __iomem *reg_base = cqspi->iobase;
 531         unsigned int reg;
 532         int ret;
 533
 534         reg = readl(reg_base + CQSPI_REG_CONFIG);
 535
 536         /*
 537          * We enable dual byte opcode here. The callers have to set up the
 538          * extension opcode based on which type of operation it is.
 539          */
 540         if (enable) {
 541                 reg |= CQSPI_REG_CONFIG_DTR_PROTO;
 542                 reg |= CQSPI_REG_CONFIG_DUAL_OPCODE;
 543
 544                 /* Set up command opcode extension. */
 545                 ret = cqspi_setup_opcode_ext(f_pdata, op, shift);
 546                 if (ret)
 547                         return ret;
 548         } else {
 549                 reg &= ~CQSPI_REG_CONFIG_DTR_PROTO;
 550                 reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE;
 551         }
 552
 553         writel(reg, reg_base + CQSPI_REG_CONFIG);
 554
 555         return cqspi_wait_idle(cqspi);
 556 }
 557
 558 static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
 559                               const struct spi_mem_op *op)
 560 {
 561         struct cqspi_st *cqspi = f_pdata->cqspi;
 562         void __iomem *reg_base = cqspi->iobase;
 563         u8 *rxbuf = op->data.buf.in;
 564         u8 opcode;
 565         size_t n_rx = op->data.nbytes;
 566         unsigned int rdreg;
 567         unsigned int reg;
 568         unsigned int dummy_clk;
 569         size_t read_len;
 570         int status;
 571
 572         status = cqspi_set_protocol(f_pdata, op);
 573         if (status)
 574                 return status;
 575
 576         status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB,
 577                                   f_pdata->dtr);
 578         if (status)
 579                 return status;
 580
 581         if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
 582                 dev_err(&cqspi->pdev->dev,
 583                         "Invalid input argument, len %zu rxbuf 0x%p\n",
 584                         n_rx, rxbuf);
 585                 return -EINVAL;
 586         }
 587
 588         if (f_pdata->dtr)
 589                 opcode = op->cmd.opcode >> 8;
 590         else
 591                 opcode = op->cmd.opcode;
 592
 593         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 594
 595         rdreg = cqspi_calc_rdreg(f_pdata);
 596         writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
 597
 598         dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr);
 599         if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 600                 return -EOPNOTSUPP;
 601
 602         if (dummy_clk)
 603                 reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK)
 604                      << CQSPI_REG_CMDCTRL_DUMMY_LSB;
 605
 606         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 607
 608         /* 0 means 1 byte. */
 609         reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 610                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 611         status = cqspi_exec_flash_cmd(cqspi, reg);
 612         if (status)
 613                 return status;
 614
 615         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 616
 617         /* Put the read value into rx_buf */
 618         read_len = (n_rx > 4) ? 4 : n_rx;
 619         memcpy(rxbuf, &reg, read_len);
 620         rxbuf += read_len;
 621
 622         if (n_rx > 4) {
 623                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 624
 625                 read_len = n_rx - read_len;
 626                 memcpy(rxbuf, &reg, read_len);
 627         }
 628
 629         return 0;
 630 }
 631
 632 static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata,
 633                                const struct spi_mem_op *op)
 634 {
 635         struct cqspi_st *cqspi = f_pdata->cqspi;
 636         void __iomem *reg_base = cqspi->iobase;
 637         u8 opcode;
 638         const u8 *txbuf = op->data.buf.out;
 639         size_t n_tx = op->data.nbytes;
 640         unsigned int reg;
 641         unsigned int data;
 642         size_t write_len;
 643         int ret;
 644
 645         ret = cqspi_set_protocol(f_pdata, op);
 646         if (ret)
 647                 return ret;
 648
 649         ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB,
 650                                f_pdata->dtr);
 651         if (ret)
 652                 return ret;
 653
 654         if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
 655                 dev_err(&cqspi->pdev->dev,
 656                         "Invalid input argument, cmdlen %zu txbuf 0x%p\n",
 657                         n_tx, txbuf);
 658                 return -EINVAL;
 659         }
 660
 661         reg = cqspi_calc_rdreg(f_pdata);
 662         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 663
 664         if (f_pdata->dtr)
 665                 opcode = op->cmd.opcode >> 8;
 666         else
 667                 opcode = op->cmd.opcode;
 668
 669         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 670
 671         if (op->addr.nbytes) {
 672                 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 673                 reg |= ((op->addr.nbytes - 1) &
 674                         CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 675                         << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 676
 677                 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
 678         }
 679
 680         if (n_tx) {
 681                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 682                 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 683                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 684                 data = 0;
 685                 write_len = (n_tx > 4) ? 4 : n_tx;
 686                 memcpy(&data, txbuf, write_len);
 687                 txbuf += write_len;
 688                 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
 689
 690                 if (n_tx > 4) {
 691                         data = 0;
 692                         write_len = n_tx - 4;
 693                         memcpy(&data, txbuf, write_len);
 694                         writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
 695                 }
 696         }
 697
 698         return cqspi_exec_flash_cmd(cqspi, reg);
 699 }
 700
 701 static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata,
 702                             const struct spi_mem_op *op)
 703 {
 704         struct cqspi_st *cqspi = f_pdata->cqspi;
 705         void __iomem *reg_base = cqspi->iobase;
 706         unsigned int dummy_clk = 0;
 707         unsigned int reg;
 708         int ret;
 709         u8 opcode;
 710
 711         ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB,
 712                                f_pdata->dtr);
 713         if (ret)
 714                 return ret;
 715
 716         if (f_pdata->dtr)
 717                 opcode = op->cmd.opcode >> 8;
 718         else
 719                 opcode = op->cmd.opcode;
 720
 721         reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 722         reg |= cqspi_calc_rdreg(f_pdata);
 723
 724         /* Setup dummy clock cycles */
 725         dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr);
 726
 727         if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 728                 return -EOPNOTSUPP;
 729
 730         if (dummy_clk)
 731                 reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 732                        << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 733
 734         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 735
 736         /* Set address width */
 737         reg = readl(reg_base + CQSPI_REG_SIZE);
 738         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 739         reg |= (op->addr.nbytes - 1);
 740         writel(reg, reg_base + CQSPI_REG_SIZE);
 741         return 0;
 742 }
 743
 744 static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
 745                                        u8 *rxbuf, loff_t from_addr,
 746                                        const size_t n_rx)
 747 {
 748         struct cqspi_st *cqspi = f_pdata->cqspi;
 749         struct device *dev = &cqspi->pdev->dev;
 750         void __iomem *reg_base = cqspi->iobase;
 751         void __iomem *ahb_base = cqspi->ahb_base;
 752         unsigned int remaining = n_rx;
 753         unsigned int mod_bytes = n_rx % 4;
 754         unsigned int bytes_to_read = 0;
 755         u8 *rxbuf_end = rxbuf + n_rx;
 756         int ret = 0;
 757
 758         writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
 759         writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
 760
 761         /* Clear all interrupts. */
 762         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 763
 764         writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
 765
 766         reinit_completion(&cqspi->transfer_complete);
 767         writel(CQSPI_REG_INDIRECTRD_START_MASK,
 768                reg_base + CQSPI_REG_INDIRECTRD);
 769
 770         while (remaining > 0) {
 771                 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
 772                                                  msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
 773                         ret = -ETIMEDOUT;
 774
 775                 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 776
 777                 if (ret && bytes_to_read == 0) {
 778                         dev_err(dev, "Indirect read timeout, no bytes\n");
 779                         goto failrd;
 780                 }
 781
 782                 while (bytes_to_read != 0) {
 783                         unsigned int word_remain = round_down(remaining, 4);
 784
 785                         bytes_to_read *= cqspi->fifo_width;
 786                         bytes_to_read = bytes_to_read > remaining ?
 787                                         remaining : bytes_to_read;
 788                         bytes_to_read = round_down(bytes_to_read, 4);
 789                         /* Read 4 byte word chunks then single bytes */
 790                         if (bytes_to_read) {
 791                                 ioread32_rep(ahb_base, rxbuf,
 792                                              (bytes_to_read / 4));
 793                         } else if (!word_remain && mod_bytes) {
 794                                 unsigned int temp = ioread32(ahb_base);
 795
 796                                 bytes_to_read = mod_bytes;
 797                                 memcpy(rxbuf, &temp, min((unsigned int)
 798                                                          (rxbuf_end - rxbuf),
 799                                                          bytes_to_read));
 800                         }
 801                         rxbuf += bytes_to_read;
 802                         remaining -= bytes_to_read;
 803                         bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 804                 }
 805
 806                 if (remaining > 0)
 807                         reinit_completion(&cqspi->transfer_complete);
 808         }
 809
 810         /* Check indirect done status */
 811         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
 812                                  CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
 813         if (ret) {
 814                 dev_err(dev, "Indirect read completion error (%i)\n", ret);
 815                 goto failrd;
 816         }
 817
 818         /* Disable interrupt */
 819         writel(0, reg_base + CQSPI_REG_IRQMASK);
 820
 821         /* Clear indirect completion status */
 822         writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
 823
 824         return 0;
 825
 826 failrd:
 827         /* Disable interrupt */
 828         writel(0, reg_base + CQSPI_REG_IRQMASK);
 829
 830         /* Cancel the indirect read */
 831         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 832                reg_base + CQSPI_REG_INDIRECTRD);
 833         return ret;
 834 }
 835
 836 static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata,
 837                                           u_char *rxbuf, loff_t from_addr,
 838                                           size_t n_rx)
 839 {
 840         struct cqspi_st *cqspi = f_pdata->cqspi;
 841         struct device *dev = &cqspi->pdev->dev;
 842         void __iomem *reg_base = cqspi->iobase;
 843         u32 reg, bytes_to_dma;
 844         loff_t addr = from_addr;
 845         void *buf = rxbuf;
 846         dma_addr_t dma_addr;
 847         u8 bytes_rem;
 848         int ret = 0;
 849
 850         bytes_rem = n_rx % 4;
 851         bytes_to_dma = (n_rx - bytes_rem);
 852
 853         if (!bytes_to_dma)
 854                 goto nondmard;
 855
 856         ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA);
 857         if (ret)
 858                 return ret;
 859
 860         reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 861         reg |= CQSPI_REG_CONFIG_DMA_MASK;
 862         writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
 863
 864         dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE);
 865         if (dma_mapping_error(dev, dma_addr)) {
 866                 dev_err(dev, "dma mapping failed\n");
 867                 return -ENOMEM;
 868         }
 869
 870         writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
 871         writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES);
 872         writel(CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL,
 873                reg_base + CQSPI_REG_INDTRIG_ADDRRANGE);
 874
 875         /* Clear all interrupts. */
 876         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 877
 878         /* Enable DMA done interrupt */
 879         writel(CQSPI_REG_VERSAL_DMA_DST_DONE_MASK,
 880                reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN);
 881
 882         /* Default DMA periph configuration */
 883         writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA);
 884
 885         /* Configure DMA Dst address */
 886         writel(lower_32_bits(dma_addr),
 887                reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR);
 888         writel(upper_32_bits(dma_addr),
 889                reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB);
 890
 891         /* Configure DMA Src address */
 892         writel(cqspi->trigger_address, reg_base +
 893                CQSPI_REG_VERSAL_DMA_SRC_ADDR);
 894
 895         /* Set DMA destination size */
 896         writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE);
 897
 898         /* Set DMA destination control */
 899         writel(CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL,
 900                reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL);
 901
 902         writel(CQSPI_REG_INDIRECTRD_START_MASK,
 903                reg_base + CQSPI_REG_INDIRECTRD);
 904
 905         reinit_completion(&cqspi->transfer_complete);
 906
 907         if (!wait_for_completion_timeout(&cqspi->transfer_complete,
 908                                          msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) {
 909                 ret = -ETIMEDOUT;
 910                 goto failrd;
 911         }
 912
 913         /* Disable DMA interrupt */
 914         writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS);
 915
 916         /* Clear indirect completion status */
 917         writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
 918                cqspi->iobase + CQSPI_REG_INDIRECTRD);
 919         dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE);
 920
 921         reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 922         reg &= ~CQSPI_REG_CONFIG_DMA_MASK;
 923         writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
 924
 925         ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id,
 926                                         PM_OSPI_MUX_SEL_LINEAR);
 927         if (ret)
 928                 return ret;
 929
 930 nondmard:
 931         if (bytes_rem) {
 932                 addr += bytes_to_dma;
 933                 buf += bytes_to_dma;
 934                 ret = cqspi_indirect_read_execute(f_pdata, buf, addr,
 935                                                   bytes_rem);
 936                 if (ret)
 937                         return ret;
 938         }
 939
 940         return 0;
 941
 942 failrd:
 943         /* Disable DMA interrupt */
 944         writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS);
 945
 946         /* Cancel the indirect read */
 947         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 948                reg_base + CQSPI_REG_INDIRECTRD);
 949
 950         dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE);
 951
 952         reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 953         reg &= ~CQSPI_REG_CONFIG_DMA_MASK;
 954         writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
 955
 956         zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR);
 957
 958         return ret;
 959 }
 960
 961 static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
 962                              const struct spi_mem_op *op)
 963 {
 964         unsigned int reg;
 965         int ret;
 966         struct cqspi_st *cqspi = f_pdata->cqspi;
 967         void __iomem *reg_base = cqspi->iobase;
 968         u8 opcode;
 969
 970         ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB,
 971                                f_pdata->dtr);
 972         if (ret)
 973                 return ret;
 974
 975         if (f_pdata->dtr)
 976                 opcode = op->cmd.opcode >> 8;
 977         else
 978                 opcode = op->cmd.opcode;
 979
 980         /* Set opcode. */
 981         reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 982         reg |= f_pdata->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
 983         reg |= f_pdata->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB;
 984         writel(reg, reg_base + CQSPI_REG_WR_INSTR);
 985         reg = cqspi_calc_rdreg(f_pdata);
 986         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 987
 988         /*
 989          * SPI NAND flashes require the address of the status register to be
 990          * passed in the Read SR command. Also, some SPI NOR flashes like the
 991          * cypress Semper flash expect a 4-byte dummy address in the Read SR
 992          * command in DTR mode.
 993          *
 994          * But this controller does not support address phase in the Read SR
 995          * command when doing auto-HW polling. So, disable write completion
 996          * polling on the controller's side. spinand and spi-nor will take
 997          * care of polling the status register.
 998          */
 999         reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
1000         reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
1001         writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
1002
1003         reg = readl(reg_base + CQSPI_REG_SIZE);
1004         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
1005         reg |= (op->addr.nbytes - 1);
1006         writel(reg, reg_base + CQSPI_REG_SIZE);
1007         return 0;
1008 }
1009
1010 static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata,
1011                                         loff_t to_addr, const u8 *txbuf,
1012                                         const size_t n_tx)
1013 {
1014         struct cqspi_st *cqspi = f_pdata->cqspi;
1015         struct device *dev = &cqspi->pdev->dev;
1016         void __iomem *reg_base = cqspi->iobase;
1017         unsigned int remaining = n_tx;
1018         unsigned int write_bytes;
1019         int ret;
1020
1021         writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
1022         writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
1023
1024         /* Clear all interrupts. */
1025         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
1026
1027         writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
1028
1029         reinit_completion(&cqspi->transfer_complete);
1030         writel(CQSPI_REG_INDIRECTWR_START_MASK,
1031                reg_base + CQSPI_REG_INDIRECTWR);
1032         /*
1033          * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
1034          * Controller programming sequence, couple of cycles of
1035          * QSPI_REF_CLK delay is required for the above bit to
1036          * be internally synchronized by the QSPI module. Provide 5
1037          * cycles of delay.
1038          */
1039         if (cqspi->wr_delay)
1040                 ndelay(cqspi->wr_delay);
1041
1042         while (remaining > 0) {
1043                 size_t write_words, mod_bytes;
1044
1045                 write_bytes = remaining;
1046                 write_words = write_bytes / 4;
1047                 mod_bytes = write_bytes % 4;
1048                 /* Write 4 bytes at a time then single bytes. */
1049                 if (write_words) {
1050                         iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
1051                         txbuf += (write_words * 4);
1052                 }
1053                 if (mod_bytes) {
1054                         unsigned int temp = 0xFFFFFFFF;
1055
1056                         memcpy(&temp, txbuf, mod_bytes);
1057                         iowrite32(temp, cqspi->ahb_base);
1058                         txbuf += mod_bytes;
1059                 }
1060
1061                 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
1062                                                  msecs_to_jiffies(CQSPI_TIMEOUT_MS))) {
1063                         dev_err(dev, "Indirect write timeout\n");
1064                         ret = -ETIMEDOUT;
1065                         goto failwr;
1066                 }
1067
1068                 remaining -= write_bytes;
1069
1070                 if (remaining > 0)
1071                         reinit_completion(&cqspi->transfer_complete);
1072         }
1073
1074         /* Check indirect done status */
1075         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
1076                                  CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
1077         if (ret) {
1078                 dev_err(dev, "Indirect write completion error (%i)\n", ret);
1079                 goto failwr;
1080         }
1081
1082         /* Disable interrupt. */
1083         writel(0, reg_base + CQSPI_REG_IRQMASK);
1084
1085         /* Clear indirect completion status */
1086         writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
1087
1088         cqspi_wait_idle(cqspi);
1089
1090         return 0;
1091
1092 failwr:
1093         /* Disable interrupt. */
1094         writel(0, reg_base + CQSPI_REG_IRQMASK);
1095
1096         /* Cancel the indirect write */
1097         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
1098                reg_base + CQSPI_REG_INDIRECTWR);
1099         return ret;
1100 }
1101
1102 static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata)
1103 {
1104         struct cqspi_st *cqspi = f_pdata->cqspi;
1105         void __iomem *reg_base = cqspi->iobase;
1106         unsigned int chip_select = f_pdata->cs;
1107         unsigned int reg;
1108
1109         reg = readl(reg_base + CQSPI_REG_CONFIG);
1110         if (cqspi->is_decoded_cs) {
1111                 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
1112         } else {
1113                 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
1114
1115                 /* Convert CS if without decoder.
1116                  * CS0 to 4b'1110
1117                  * CS1 to 4b'1101
1118                  * CS2 to 4b'1011
1119                  * CS3 to 4b'0111
1120                  */
1121                 chip_select = 0xF & ~(1 << chip_select);
1122         }
1123
1124         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
1125                  << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
1126         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
1127             << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
1128         writel(reg, reg_base + CQSPI_REG_CONFIG);
1129 }
1130
1131 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
1132                                            const unsigned int ns_val)
1133 {
1134         unsigned int ticks;
1135
1136         ticks = ref_clk_hz / 1000;      /* kHz */
1137         ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
1138
1139         return ticks;
1140 }
1141
1142 static void cqspi_delay(struct cqspi_flash_pdata *f_pdata)
1143 {
1144         struct cqspi_st *cqspi = f_pdata->cqspi;
1145         void __iomem *iobase = cqspi->iobase;
1146         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
1147         unsigned int tshsl, tchsh, tslch, tsd2d;
1148         unsigned int reg;
1149         unsigned int tsclk;
1150
1151         /* calculate the number of ref ticks for one sclk tick */
1152         tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
1153
1154         tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
1155         /* this particular value must be at least one sclk */
1156         if (tshsl < tsclk)
1157                 tshsl = tsclk;
1158
1159         tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
1160         tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
1161         tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
1162
1163         reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
1164                << CQSPI_REG_DELAY_TSHSL_LSB;
1165         reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
1166                 << CQSPI_REG_DELAY_TCHSH_LSB;
1167         reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
1168                 << CQSPI_REG_DELAY_TSLCH_LSB;
1169         reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
1170                 << CQSPI_REG_DELAY_TSD2D_LSB;
1171         writel(reg, iobase + CQSPI_REG_DELAY);
1172 }
1173
1174 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
1175 {
1176         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
1177         void __iomem *reg_base = cqspi->iobase;
1178         u32 reg, div;
1179
1180         /* Recalculate the baudrate divisor based on QSPI specification. */
1181         div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
1182
1183         reg = readl(reg_base + CQSPI_REG_CONFIG);
1184         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
1185         reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
1186         writel(reg, reg_base + CQSPI_REG_CONFIG);
1187 }
1188
1189 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
1190                                    const bool bypass,
1191                                    const unsigned int delay)
1192 {
1193         void __iomem *reg_base = cqspi->iobase;
1194         unsigned int reg;
1195
1196         reg = readl(reg_base + CQSPI_REG_READCAPTURE);
1197
1198         if (bypass)
1199                 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
1200         else
1201                 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
1202
1203         reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
1204                  << CQSPI_REG_READCAPTURE_DELAY_LSB);
1205
1206         reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
1207                 << CQSPI_REG_READCAPTURE_DELAY_LSB;
1208
1209         writel(reg, reg_base + CQSPI_REG_READCAPTURE);
1210 }
1211
1212 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
1213 {
1214         void __iomem *reg_base = cqspi->iobase;
1215         unsigned int reg;
1216
1217         reg = readl(reg_base + CQSPI_REG_CONFIG);
1218
1219         if (enable)
1220                 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
1221         else
1222                 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
1223
1224         writel(reg, reg_base + CQSPI_REG_CONFIG);
1225 }
1226
1227 static void cqspi_configure(struct cqspi_flash_pdata *f_pdata,
1228                             unsigned long sclk)
1229 {
1230         struct cqspi_st *cqspi = f_pdata->cqspi;
1231         int switch_cs = (cqspi->current_cs != f_pdata->cs);
1232         int switch_ck = (cqspi->sclk != sclk);
1233
1234         if (switch_cs || switch_ck)
1235                 cqspi_controller_enable(cqspi, 0);
1236
1237         /* Switch chip select. */
1238         if (switch_cs) {
1239                 cqspi->current_cs = f_pdata->cs;
1240                 cqspi_chipselect(f_pdata);
1241         }
1242
1243         /* Setup baudrate divisor and delays */
1244         if (switch_ck) {
1245                 cqspi->sclk = sclk;
1246                 cqspi_config_baudrate_div(cqspi);
1247                 cqspi_delay(f_pdata);
1248                 cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
1249                                        f_pdata->read_delay);
1250         }
1251
1252         if (switch_cs || switch_ck)
1253                 cqspi_controller_enable(cqspi, 1);
1254 }
1255
1256 static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
1257                            const struct spi_mem_op *op)
1258 {
1259         struct cqspi_st *cqspi = f_pdata->cqspi;
1260         loff_t to = op->addr.val;
1261         size_t len = op->data.nbytes;
1262         const u_char *buf = op->data.buf.out;
1263         int ret;
1264
1265         ret = cqspi_set_protocol(f_pdata, op);
1266         if (ret)
1267                 return ret;
1268
1269         ret = cqspi_write_setup(f_pdata, op);
1270         if (ret)
1271                 return ret;
1272
1273         /*
1274          * Some flashes like the Cypress Semper flash expect a dummy 4-byte
1275          * address (all 0s) with the read status register command in DTR mode.
1276          * But this controller does not support sending dummy address bytes to
1277          * the flash when it is polling the write completion register in DTR
1278          * mode. So, we can not use direct mode when in DTR mode for writing
1279          * data.
1280          */
1281         if (!f_pdata->dtr && cqspi->use_direct_mode &&
1282             ((to + len) <= cqspi->ahb_size)) {
1283                 memcpy_toio(cqspi->ahb_base + to, buf, len);
1284                 return cqspi_wait_idle(cqspi);
1285         }
1286
1287         return cqspi_indirect_write_execute(f_pdata, to, buf, len);
1288 }
1289
1290 static void cqspi_rx_dma_callback(void *param)
1291 {
1292         struct cqspi_st *cqspi = param;
1293
1294         complete(&cqspi->rx_dma_complete);
1295 }
1296
1297 static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata,
1298                                      u_char *buf, loff_t from, size_t len)
1299 {
1300         struct cqspi_st *cqspi = f_pdata->cqspi;
1301         struct device *dev = &cqspi->pdev->dev;
1302         enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
1303         dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
1304         int ret = 0;
1305         struct dma_async_tx_descriptor *tx;
1306         dma_cookie_t cookie;
1307         dma_addr_t dma_dst;
1308         struct device *ddev;
1309
1310         if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
1311                 memcpy_fromio(buf, cqspi->ahb_base + from, len);
1312                 return 0;
1313         }
1314
1315         ddev = cqspi->rx_chan->device->dev;
1316         dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE);
1317         if (dma_mapping_error(ddev, dma_dst)) {
1318                 dev_err(dev, "dma mapping failed\n");
1319                 return -ENOMEM;
1320         }
1321         tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
1322                                        len, flags);
1323         if (!tx) {
1324                 dev_err(dev, "device_prep_dma_memcpy error\n");
1325                 ret = -EIO;
1326                 goto err_unmap;
1327         }
1328
1329         tx->callback = cqspi_rx_dma_callback;
1330         tx->callback_param = cqspi;
1331         cookie = tx->tx_submit(tx);
1332         reinit_completion(&cqspi->rx_dma_complete);
1333
1334         ret = dma_submit_error(cookie);
1335         if (ret) {
1336                 dev_err(dev, "dma_submit_error %d\n", cookie);
1337                 ret = -EIO;
1338                 goto err_unmap;
1339         }
1340
1341         dma_async_issue_pending(cqspi->rx_chan);
1342         if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
1343                                          msecs_to_jiffies(max_t(size_t, len, 500)))) {
1344                 dmaengine_terminate_sync(cqspi->rx_chan);
1345                 dev_err(dev, "DMA wait_for_completion_timeout\n");
1346                 ret = -ETIMEDOUT;
1347                 goto err_unmap;
1348         }
1349
1350 err_unmap:
1351         dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE);
1352
1353         return ret;
1354 }
1355
1356 static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata,
1357                           const struct spi_mem_op *op)
1358 {
1359         struct cqspi_st *cqspi = f_pdata->cqspi;
1360         struct device *dev = &cqspi->pdev->dev;
1361         const struct cqspi_driver_platdata *ddata;
1362         loff_t from = op->addr.val;
1363         size_t len = op->data.nbytes;
1364         u_char *buf = op->data.buf.in;
1365         u64 dma_align = (u64)(uintptr_t)buf;
1366         int ret;
1367
1368         ddata = of_device_get_match_data(dev);
1369         ret = cqspi_set_protocol(f_pdata, op);
1370         if (ret)
1371                 return ret;
1372
1373         ret = cqspi_read_setup(f_pdata, op);
1374         if (ret)
1375                 return ret;
1376
1377         if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size))
1378                 return cqspi_direct_read_execute(f_pdata, buf, from, len);
1379
1380         if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma &&
1381             virt_addr_valid(buf) && ((dma_align & CQSPI_DMA_UNALIGN) == 0))
1382                 return ddata->indirect_read_dma(f_pdata, buf, from, len);
1383
1384         return cqspi_indirect_read_execute(f_pdata, buf, from, len);
1385 }
1386
1387 static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
1388 {
1389         struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
1390         struct cqspi_flash_pdata *f_pdata;
1391
1392         f_pdata = &cqspi->f_pdata[mem->spi->chip_select];
1393         cqspi_configure(f_pdata, mem->spi->max_speed_hz);
1394
1395         if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
1396                 if (!op->addr.nbytes)
1397                         return cqspi_command_read(f_pdata, op);
1398
1399                 return cqspi_read(f_pdata, op);
1400         }
1401
1402         if (!op->addr.nbytes || !op->data.buf.out)
1403                 return cqspi_command_write(f_pdata, op);
1404
1405         return cqspi_write(f_pdata, op);
1406 }
1407
1408 static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
1409 {
1410         int ret;
1411
1412         ret = cqspi_mem_process(mem, op);
1413         if (ret)
1414                 dev_err(&mem->spi->dev, "operation failed with %d\n", ret);
1415
1416         return ret;
1417 }
1418
1419 static bool cqspi_supports_mem_op(struct spi_mem *mem,
1420                                   const struct spi_mem_op *op)
1421 {
1422         bool all_true, all_false;
1423
1424         /*
1425          * op->dummy.dtr is required for converting nbytes into ncycles.
1426          * Also, don't check the dtr field of the op phase having zero nbytes.
1427          */
1428         all_true = op->cmd.dtr &&
1429                    (!op->addr.nbytes || op->addr.dtr) &&
1430                    (!op->dummy.nbytes || op->dummy.dtr) &&
1431                    (!op->data.nbytes || op->data.dtr);
1432
1433         all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
1434                     !op->data.dtr;
1435
1436         /* Mixed DTR modes not supported. */
1437         if (!(all_true || all_false))
1438                 return false;
1439
1440         if (all_true)
1441                 return spi_mem_dtr_supports_op(mem, op);
1442         else
1443                 return spi_mem_default_supports_op(mem, op);
1444 }
1445
1446 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
1447                                     struct cqspi_flash_pdata *f_pdata,
1448                                     struct device_node *np)
1449 {
1450         if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
1451                 dev_err(&pdev->dev, "couldn't determine read-delay\n");
1452                 return -ENXIO;
1453         }
1454
1455         if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1456                 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1457                 return -ENXIO;
1458         }
1459
1460         if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1461                 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1462                 return -ENXIO;
1463         }
1464
1465         if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1466                 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1467                 return -ENXIO;
1468         }
1469
1470         if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1471                 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1472                 return -ENXIO;
1473         }
1474
1475         if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1476                 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1477                 return -ENXIO;
1478         }
1479
1480         return 0;
1481 }
1482
1483 static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
1484 {
1485         struct device *dev = &cqspi->pdev->dev;
1486         struct device_node *np = dev->of_node;
1487         u32 id[2];
1488
1489         cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1490
1491         if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1492                 dev_err(dev, "couldn't determine fifo-depth\n");
1493                 return -ENXIO;
1494         }
1495
1496         if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1497                 dev_err(dev, "couldn't determine fifo-width\n");
1498                 return -ENXIO;
1499         }
1500
1501         if (of_property_read_u32(np, "cdns,trigger-address",
1502                                  &cqspi->trigger_address)) {
1503                 dev_err(dev, "couldn't determine trigger-address\n");
1504                 return -ENXIO;
1505         }
1506
1507         if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect))
1508                 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT;
1509
1510         cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1511
1512         if (!of_property_read_u32_array(np, "power-domains", id,
1513                                         ARRAY_SIZE(id)))
1514                 cqspi->pd_dev_id = id[1];
1515
1516         return 0;
1517 }
1518
1519 static void cqspi_controller_init(struct cqspi_st *cqspi)
1520 {
1521         u32 reg;
1522
1523         cqspi_controller_enable(cqspi, 0);
1524
1525         /* Configure the remap address register, no remap */
1526         writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1527
1528         /* Disable all interrupts. */
1529         writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1530
1531         /* Configure the SRAM split to 1:1 . */
1532         writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1533
1534         /* Load indirect trigger address. */
1535         writel(cqspi->trigger_address,
1536                cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1537
1538         /* Program read watermark -- 1/2 of the FIFO. */
1539         writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1540                cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1541         /* Program write watermark -- 1/8 of the FIFO. */
1542         writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1543                cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1544
1545         /* Disable direct access controller */
1546         if (!cqspi->use_direct_mode) {
1547                 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1548                 reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
1549                 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1550         }
1551
1552         /* Enable DMA interface */
1553         if (cqspi->use_dma_read) {
1554                 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1555                 reg |= CQSPI_REG_CONFIG_DMA_MASK;
1556                 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1557         }
1558
1559         cqspi_controller_enable(cqspi, 1);
1560 }
1561
1562 static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
1563 {
1564         dma_cap_mask_t mask;
1565
1566         dma_cap_zero(mask);
1567         dma_cap_set(DMA_MEMCPY, mask);
1568
1569         cqspi->rx_chan = dma_request_chan_by_mask(&mask);
1570         if (IS_ERR(cqspi->rx_chan)) {
1571                 int ret = PTR_ERR(cqspi->rx_chan);
1572                 cqspi->rx_chan = NULL;
1573                 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n");
1574         }
1575         init_completion(&cqspi->rx_dma_complete);
1576
1577         return 0;
1578 }
1579
1580 static const char *cqspi_get_name(struct spi_mem *mem)
1581 {
1582         struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
1583         struct device *dev = &cqspi->pdev->dev;
1584
1585         return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select);
1586 }
1587
1588 static const struct spi_controller_mem_ops cqspi_mem_ops = {
1589         .exec_op = cqspi_exec_mem_op,
1590         .get_name = cqspi_get_name,
1591         .supports_op = cqspi_supports_mem_op,
1592 };
1593
1594 static int cqspi_setup_flash(struct cqspi_st *cqspi)
1595 {
1596         struct platform_device *pdev = cqspi->pdev;
1597         struct device *dev = &pdev->dev;
1598         struct device_node *np = dev->of_node;
1599         struct cqspi_flash_pdata *f_pdata;
1600         unsigned int cs;
1601         int ret;
1602
1603         /* Get flash device data */
1604         for_each_available_child_of_node(dev->of_node, np) {
1605                 ret = of_property_read_u32(np, "reg", &cs);
1606                 if (ret) {
1607                         dev_err(dev, "Couldn't determine chip select.\n");
1608                         of_node_put(np);
1609                         return ret;
1610                 }
1611
1612                 if (cs >= CQSPI_MAX_CHIPSELECT) {
1613                         dev_err(dev, "Chip select %d out of range.\n", cs);
1614                         of_node_put(np);
1615                         return -EINVAL;
1616                 }
1617
1618                 f_pdata = &cqspi->f_pdata[cs];
1619                 f_pdata->cqspi = cqspi;
1620                 f_pdata->cs = cs;
1621
1622                 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1623                 if (ret) {
1624                         of_node_put(np);
1625                         return ret;
1626                 }
1627         }
1628
1629         return 0;
1630 }
1631
1632 static int cqspi_probe(struct platform_device *pdev)
1633 {
1634         const struct cqspi_driver_platdata *ddata;
1635         struct reset_control *rstc, *rstc_ocp;
1636         struct device *dev = &pdev->dev;
1637         struct spi_master *master;
1638         struct resource *res_ahb;
1639         struct cqspi_st *cqspi;
1640         struct resource *res;
1641         int ret;
1642         int irq;
1643
1644         master = spi_alloc_master(&pdev->dev, sizeof(*cqspi));
1645         if (!master) {
1646                 dev_err(&pdev->dev, "spi_alloc_master failed\n");
1647                 return -ENOMEM;
1648         }
1649         master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL;
1650         master->mem_ops = &cqspi_mem_ops;
1651         master->dev.of_node = pdev->dev.of_node;
1652
1653         cqspi = spi_master_get_devdata(master);
1654
1655         cqspi->pdev = pdev;
1656         platform_set_drvdata(pdev, cqspi);
1657
1658         /* Obtain configuration from OF. */
1659         ret = cqspi_of_get_pdata(cqspi);
1660         if (ret) {
1661                 dev_err(dev, "Cannot get mandatory OF data.\n");
1662                 ret = -ENODEV;
1663                 goto probe_master_put;
1664         }
1665
1666         /* Obtain QSPI clock. */
1667         cqspi->clk = devm_clk_get(dev, NULL);
1668         if (IS_ERR(cqspi->clk)) {
1669                 dev_err(dev, "Cannot claim QSPI clock.\n");
1670                 ret = PTR_ERR(cqspi->clk);
1671                 goto probe_master_put;
1672         }
1673
1674         /* Obtain and remap controller address. */
1675         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1676         cqspi->iobase = devm_ioremap_resource(dev, res);
1677         if (IS_ERR(cqspi->iobase)) {
1678                 dev_err(dev, "Cannot remap controller address.\n");
1679                 ret = PTR_ERR(cqspi->iobase);
1680                 goto probe_master_put;
1681         }
1682
1683         /* Obtain and remap AHB address. */
1684         res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1685         cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1686         if (IS_ERR(cqspi->ahb_base)) {
1687                 dev_err(dev, "Cannot remap AHB address.\n");
1688                 ret = PTR_ERR(cqspi->ahb_base);
1689                 goto probe_master_put;
1690         }
1691         cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
1692         cqspi->ahb_size = resource_size(res_ahb);
1693
1694         init_completion(&cqspi->transfer_complete);
1695
1696         /* Obtain IRQ line. */
1697         irq = platform_get_irq(pdev, 0);
1698         if (irq < 0) {
1699                 ret = -ENXIO;
1700                 goto probe_master_put;
1701         }
1702
1703         pm_runtime_enable(dev);
1704         ret = pm_runtime_get_sync(dev);
1705         if (ret < 0) {
1706                 pm_runtime_put_noidle(dev);
1707                 goto probe_master_put;
1708         }
1709
1710         ret = clk_prepare_enable(cqspi->clk);
1711         if (ret) {
1712                 dev_err(dev, "Cannot enable QSPI clock.\n");
1713                 goto probe_clk_failed;
1714         }
1715
1716         /* Obtain QSPI reset control */
1717         rstc = devm_reset_control_get_optional_exclusive(dev, "qspi");
1718         if (IS_ERR(rstc)) {
1719                 ret = PTR_ERR(rstc);
1720                 dev_err(dev, "Cannot get QSPI reset.\n");
1721                 goto probe_reset_failed;
1722         }
1723
1724         rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");
1725         if (IS_ERR(rstc_ocp)) {
1726                 ret = PTR_ERR(rstc_ocp);
1727                 dev_err(dev, "Cannot get QSPI OCP reset.\n");
1728                 goto probe_reset_failed;
1729         }
1730
1731         reset_control_assert(rstc);
1732         reset_control_deassert(rstc);
1733
1734         reset_control_assert(rstc_ocp);
1735         reset_control_deassert(rstc_ocp);
1736
1737         cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1738         master->max_speed_hz = cqspi->master_ref_clk_hz;
1739         ddata  = of_device_get_match_data(dev);
1740         if (ddata) {
1741                 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
1742                         cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC,
1743                                                 cqspi->master_ref_clk_hz);
1744                 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL)
1745                         master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL;
1746                 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE))
1747                         cqspi->use_direct_mode = true;
1748                 if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA)
1749                         cqspi->use_dma_read = true;
1750
1751                 if (of_device_is_compatible(pdev->dev.of_node,
1752                                             "xlnx,versal-ospi-1.0"))
1753                         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1754         }
1755
1756         ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1757                                pdev->name, cqspi);
1758         if (ret) {
1759                 dev_err(dev, "Cannot request IRQ.\n");
1760                 goto probe_reset_failed;
1761         }
1762
1763         cqspi_wait_idle(cqspi);
1764         cqspi_controller_init(cqspi);
1765         cqspi->current_cs = -1;
1766         cqspi->sclk = 0;
1767
1768         master->num_chipselect = cqspi->num_chipselect;
1769
1770         ret = cqspi_setup_flash(cqspi);
1771         if (ret) {
1772                 dev_err(dev, "failed to setup flash parameters %d\n", ret);
1773                 goto probe_setup_failed;
1774         }
1775
1776         if (cqspi->use_direct_mode) {
1777                 ret = cqspi_request_mmap_dma(cqspi);
1778                 if (ret == -EPROBE_DEFER)
1779                         goto probe_setup_failed;
1780         }
1781
1782         ret = devm_spi_register_master(dev, master);
1783         if (ret) {
1784                 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret);
1785                 goto probe_setup_failed;
1786         }
1787
1788         return 0;
1789 probe_setup_failed:
1790         cqspi_controller_enable(cqspi, 0);
1791 probe_reset_failed:
1792         clk_disable_unprepare(cqspi->clk);
1793 probe_clk_failed:
1794         pm_runtime_put_sync(dev);
1795         pm_runtime_disable(dev);
1796 probe_master_put:
1797         spi_master_put(master);
1798         return ret;
1799 }
1800
1801 static int cqspi_remove(struct platform_device *pdev)
1802 {
1803         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1804
1805         cqspi_controller_enable(cqspi, 0);
1806
1807         if (cqspi->rx_chan)
1808                 dma_release_channel(cqspi->rx_chan);
1809
1810         clk_disable_unprepare(cqspi->clk);
1811
1812         pm_runtime_put_sync(&pdev->dev);
1813         pm_runtime_disable(&pdev->dev);
1814
1815         return 0;
1816 }
1817
1818 #ifdef CONFIG_PM_SLEEP
1819 static int cqspi_suspend(struct device *dev)
1820 {
1821         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1822
1823         cqspi_controller_enable(cqspi, 0);
1824         return 0;
1825 }
1826
1827 static int cqspi_resume(struct device *dev)
1828 {
1829         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1830
1831         cqspi_controller_enable(cqspi, 1);
1832         return 0;
1833 }
1834
1835 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1836         .suspend = cqspi_suspend,
1837         .resume = cqspi_resume,
1838 };
1839
1840 #define CQSPI_DEV_PM_OPS        (&cqspi__dev_pm_ops)
1841 #else
1842 #define CQSPI_DEV_PM_OPS        NULL
1843 #endif
1844
1845 static const struct cqspi_driver_platdata cdns_qspi = {
1846         .quirks = CQSPI_DISABLE_DAC_MODE,
1847 };
1848
1849 static const struct cqspi_driver_platdata k2g_qspi = {
1850         .quirks = CQSPI_NEEDS_WR_DELAY,
1851 };
1852
1853 static const struct cqspi_driver_platdata am654_ospi = {
1854         .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
1855         .quirks = CQSPI_NEEDS_WR_DELAY,
1856 };
1857
1858 static const struct cqspi_driver_platdata intel_lgm_qspi = {
1859         .quirks = CQSPI_DISABLE_DAC_MODE,
1860 };
1861
1862 static const struct cqspi_driver_platdata versal_ospi = {
1863         .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
1864         .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA,
1865         .indirect_read_dma = cqspi_versal_indirect_read_dma,
1866         .get_dma_status = cqspi_get_versal_dma_status,
1867 };
1868
1869 static const struct of_device_id cqspi_dt_ids[] = {
1870         {
1871                 .compatible = "cdns,qspi-nor",
1872                 .data = &cdns_qspi,
1873         },
1874         {
1875                 .compatible = "ti,k2g-qspi",
1876                 .data = &k2g_qspi,
1877         },
1878         {
1879                 .compatible = "ti,am654-ospi",
1880                 .data = &am654_ospi,
1881         },
1882         {
1883                 .compatible = "intel,lgm-qspi",
1884                 .data = &intel_lgm_qspi,
1885         },
1886         {
1887                 .compatible = "xlnx,versal-ospi-1.0",
1888                 .data = (void *)&versal_ospi,
1889         },
1890         { /* end of table */ }
1891 };
1892
1893 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1894
1895 static struct platform_driver cqspi_platform_driver = {
1896         .probe = cqspi_probe,
1897         .remove = cqspi_remove,
1898         .driver = {
1899                 .name = CQSPI_NAME,
1900                 .pm = CQSPI_DEV_PM_OPS,
1901                 .of_match_table = cqspi_dt_ids,
1902         },
1903 };
1904
1905 module_platform_driver(cqspi_platform_driver);
1906
1907 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1908 MODULE_LICENSE("GPL v2");
1909 MODULE_ALIAS("platform:" CQSPI_NAME);
1910 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
1911 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");
1912 MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>");
1913 MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>");
1914 MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>");