1 // SPDX-License-Identifier: GPL-2.0-only
3 // Driver for Cadence QSPI Controller
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
10 #include <linux/completion.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/dmaengine.h>
14 #include <linux/err.h>
15 #include <linux/errno.h>
16 #include <linux/interrupt.h>
18 #include <linux/iopoll.h>
19 #include <linux/jiffies.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/of_device.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/reset.h>
27 #include <linux/sched.h>
28 #include <linux/spi/spi.h>
29 #include <linux/spi/spi-mem.h>
30 #include <linux/timer.h>
32 #define CQSPI_NAME "cadence-qspi"
33 #define CQSPI_MAX_CHIPSELECT 16
36 #define CQSPI_NEEDS_WR_DELAY BIT(0)
37 #define CQSPI_DISABLE_DAC_MODE BIT(1)
40 #define CQSPI_SUPPORTS_OCTAL BIT(0)
44 struct cqspi_flash_pdata {
45 struct cqspi_st *cqspi;
60 struct platform_device *pdev;
66 void __iomem *ahb_base;
67 resource_size_t ahb_size;
68 struct completion transfer_complete;
70 struct dma_chan *rx_chan;
71 struct completion rx_dma_complete;
72 dma_addr_t mmap_phys_base;
75 unsigned long master_ref_clk_hz;
84 struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
87 struct cqspi_driver_platdata {
92 /* Operation timeout value */
93 #define CQSPI_TIMEOUT_MS 500
94 #define CQSPI_READ_TIMEOUT_MS 10
96 /* Instruction type */
97 #define CQSPI_INST_TYPE_SINGLE 0
98 #define CQSPI_INST_TYPE_DUAL 1
99 #define CQSPI_INST_TYPE_QUAD 2
100 #define CQSPI_INST_TYPE_OCTAL 3
102 #define CQSPI_DUMMY_CLKS_PER_BYTE 8
103 #define CQSPI_DUMMY_BYTES_MAX 4
104 #define CQSPI_DUMMY_CLKS_MAX 31
106 #define CQSPI_STIG_DATA_LEN_MAX 8
109 #define CQSPI_REG_CONFIG 0x00
110 #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0)
111 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7)
112 #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9)
113 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
114 #define CQSPI_REG_CONFIG_DMA_MASK BIT(15)
115 #define CQSPI_REG_CONFIG_BAUD_LSB 19
116 #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24)
117 #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30)
118 #define CQSPI_REG_CONFIG_IDLE_LSB 31
119 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
120 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF
122 #define CQSPI_REG_RD_INSTR 0x04
123 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
124 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
125 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
126 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
127 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
128 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
129 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
130 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
131 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
132 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
134 #define CQSPI_REG_WR_INSTR 0x08
135 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
136 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12
137 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16
139 #define CQSPI_REG_DELAY 0x0C
140 #define CQSPI_REG_DELAY_TSLCH_LSB 0
141 #define CQSPI_REG_DELAY_TCHSH_LSB 8
142 #define CQSPI_REG_DELAY_TSD2D_LSB 16
143 #define CQSPI_REG_DELAY_TSHSL_LSB 24
144 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
145 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
146 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
147 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
149 #define CQSPI_REG_READCAPTURE 0x10
150 #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0
151 #define CQSPI_REG_READCAPTURE_DELAY_LSB 1
152 #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF
154 #define CQSPI_REG_SIZE 0x14
155 #define CQSPI_REG_SIZE_ADDRESS_LSB 0
156 #define CQSPI_REG_SIZE_PAGE_LSB 4
157 #define CQSPI_REG_SIZE_BLOCK_LSB 16
158 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
159 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
160 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
162 #define CQSPI_REG_SRAMPARTITION 0x18
163 #define CQSPI_REG_INDIRECTTRIGGER 0x1C
165 #define CQSPI_REG_DMA 0x20
166 #define CQSPI_REG_DMA_SINGLE_LSB 0
167 #define CQSPI_REG_DMA_BURST_LSB 8
168 #define CQSPI_REG_DMA_SINGLE_MASK 0xFF
169 #define CQSPI_REG_DMA_BURST_MASK 0xFF
171 #define CQSPI_REG_REMAP 0x24
172 #define CQSPI_REG_MODE_BIT 0x28
174 #define CQSPI_REG_SDRAMLEVEL 0x2C
175 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
176 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
177 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
178 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
180 #define CQSPI_REG_WR_COMPLETION_CTRL 0x38
181 #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14)
183 #define CQSPI_REG_IRQSTATUS 0x40
184 #define CQSPI_REG_IRQMASK 0x44
186 #define CQSPI_REG_INDIRECTRD 0x60
187 #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0)
188 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1)
189 #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5)
191 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64
192 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
193 #define CQSPI_REG_INDIRECTRDBYTES 0x6C
195 #define CQSPI_REG_CMDCTRL 0x90
196 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0)
197 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1)
198 #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
199 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
200 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
201 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
202 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
203 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
204 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
205 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
206 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
207 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
208 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
209 #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F
211 #define CQSPI_REG_INDIRECTWR 0x70
212 #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0)
213 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1)
214 #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5)
216 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74
217 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
218 #define CQSPI_REG_INDIRECTWRBYTES 0x7C
220 #define CQSPI_REG_CMDADDRESS 0x94
221 #define CQSPI_REG_CMDREADDATALOWER 0xA0
222 #define CQSPI_REG_CMDREADDATAUPPER 0xA4
223 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8
224 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
226 #define CQSPI_REG_POLLING_STATUS 0xB0
227 #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16
229 #define CQSPI_REG_OP_EXT_LOWER 0xE0
230 #define CQSPI_REG_OP_EXT_READ_LSB 24
231 #define CQSPI_REG_OP_EXT_WRITE_LSB 16
232 #define CQSPI_REG_OP_EXT_STIG_LSB 0
234 /* Interrupt status bits */
235 #define CQSPI_REG_IRQ_MODE_ERR BIT(0)
236 #define CQSPI_REG_IRQ_UNDERFLOW BIT(1)
237 #define CQSPI_REG_IRQ_IND_COMP BIT(2)
238 #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3)
239 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4)
240 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5)
241 #define CQSPI_REG_IRQ_WATERMARK BIT(6)
242 #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12)
244 #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \
245 CQSPI_REG_IRQ_IND_SRAM_FULL | \
246 CQSPI_REG_IRQ_IND_COMP)
248 #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \
249 CQSPI_REG_IRQ_WATERMARK | \
250 CQSPI_REG_IRQ_UNDERFLOW)
252 #define CQSPI_IRQ_STATUS_MASK 0x1FFFF
254 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr)
258 return readl_relaxed_poll_timeout(reg, val,
259 (((clr ? ~val : val) & mask) == mask),
260 10, CQSPI_TIMEOUT_MS * 1000);
263 static bool cqspi_is_idle(struct cqspi_st *cqspi)
265 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
267 return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB);
270 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
272 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
274 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
275 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
278 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
280 struct cqspi_st *cqspi = dev;
281 unsigned int irq_status;
283 /* Read interrupt status */
284 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
286 /* Clear interrupt */
287 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
289 irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
292 complete(&cqspi->transfer_complete);
297 static unsigned int cqspi_calc_rdreg(struct cqspi_flash_pdata *f_pdata)
301 rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
302 rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
303 rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
308 static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr)
310 unsigned int dummy_clk;
312 if (!op->dummy.nbytes)
315 dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);
322 static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata,
323 const struct spi_mem_op *op)
325 f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
326 f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
327 f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
328 f_pdata->dtr = op->data.dtr && op->cmd.dtr && op->addr.dtr;
330 switch (op->data.buswidth) {
334 f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
337 f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
340 f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
343 f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
349 /* Right now we only support 8-8-8 DTR mode. */
351 switch (op->cmd.buswidth) {
355 f_pdata->inst_width = CQSPI_INST_TYPE_OCTAL;
361 switch (op->addr.buswidth) {
365 f_pdata->addr_width = CQSPI_INST_TYPE_OCTAL;
371 switch (op->data.buswidth) {
375 f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
385 static int cqspi_wait_idle(struct cqspi_st *cqspi)
387 const unsigned int poll_idle_retry = 3;
388 unsigned int count = 0;
389 unsigned long timeout;
391 timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
394 * Read few times in succession to ensure the controller
395 * is indeed idle, that is, the bit does not transition
398 if (cqspi_is_idle(cqspi))
403 if (count >= poll_idle_retry)
406 if (time_after(jiffies, timeout)) {
407 /* Timeout, in busy mode. */
408 dev_err(&cqspi->pdev->dev,
409 "QSPI is still busy after %dms timeout.\n",
418 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
420 void __iomem *reg_base = cqspi->iobase;
423 /* Write the CMDCTRL without start execution. */
424 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
426 reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
427 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
429 /* Polling for completion. */
430 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
431 CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
433 dev_err(&cqspi->pdev->dev,
434 "Flash command execution timed out.\n");
438 /* Polling QSPI idle status. */
439 return cqspi_wait_idle(cqspi);
442 static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata,
443 const struct spi_mem_op *op,
446 struct cqspi_st *cqspi = f_pdata->cqspi;
447 void __iomem *reg_base = cqspi->iobase;
451 if (op->cmd.nbytes != 2)
454 /* Opcode extension is the LSB. */
455 ext = op->cmd.opcode & 0xff;
457 reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER);
458 reg &= ~(0xff << shift);
460 writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER);
465 static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata,
466 const struct spi_mem_op *op, unsigned int shift,
469 struct cqspi_st *cqspi = f_pdata->cqspi;
470 void __iomem *reg_base = cqspi->iobase;
474 reg = readl(reg_base + CQSPI_REG_CONFIG);
477 * We enable dual byte opcode here. The callers have to set up the
478 * extension opcode based on which type of operation it is.
481 reg |= CQSPI_REG_CONFIG_DTR_PROTO;
482 reg |= CQSPI_REG_CONFIG_DUAL_OPCODE;
484 /* Set up command opcode extension. */
485 ret = cqspi_setup_opcode_ext(f_pdata, op, shift);
489 reg &= ~CQSPI_REG_CONFIG_DTR_PROTO;
490 reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE;
493 writel(reg, reg_base + CQSPI_REG_CONFIG);
495 return cqspi_wait_idle(cqspi);
498 static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
499 const struct spi_mem_op *op)
501 struct cqspi_st *cqspi = f_pdata->cqspi;
502 void __iomem *reg_base = cqspi->iobase;
503 u8 *rxbuf = op->data.buf.in;
505 size_t n_rx = op->data.nbytes;
508 unsigned int dummy_clk;
512 status = cqspi_set_protocol(f_pdata, op);
516 status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB,
521 if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
522 dev_err(&cqspi->pdev->dev,
523 "Invalid input argument, len %zu rxbuf 0x%p\n",
529 opcode = op->cmd.opcode >> 8;
531 opcode = op->cmd.opcode;
533 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
535 rdreg = cqspi_calc_rdreg(f_pdata);
536 writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
538 dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr);
539 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
543 reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK)
544 << CQSPI_REG_CMDCTRL_DUMMY_LSB;
546 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
548 /* 0 means 1 byte. */
549 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
550 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
551 status = cqspi_exec_flash_cmd(cqspi, reg);
555 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
557 /* Put the read value into rx_buf */
558 read_len = (n_rx > 4) ? 4 : n_rx;
559 memcpy(rxbuf, ®, read_len);
563 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
565 read_len = n_rx - read_len;
566 memcpy(rxbuf, ®, read_len);
572 static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata,
573 const struct spi_mem_op *op)
575 struct cqspi_st *cqspi = f_pdata->cqspi;
576 void __iomem *reg_base = cqspi->iobase;
578 const u8 *txbuf = op->data.buf.out;
579 size_t n_tx = op->data.nbytes;
585 ret = cqspi_set_protocol(f_pdata, op);
589 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB,
594 if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
595 dev_err(&cqspi->pdev->dev,
596 "Invalid input argument, cmdlen %zu txbuf 0x%p\n",
601 reg = cqspi_calc_rdreg(f_pdata);
602 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
605 opcode = op->cmd.opcode >> 8;
607 opcode = op->cmd.opcode;
609 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
611 if (op->addr.nbytes) {
612 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
613 reg |= ((op->addr.nbytes - 1) &
614 CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
615 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
617 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
621 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
622 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
623 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
625 write_len = (n_tx > 4) ? 4 : n_tx;
626 memcpy(&data, txbuf, write_len);
628 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
632 write_len = n_tx - 4;
633 memcpy(&data, txbuf, write_len);
634 writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
638 return cqspi_exec_flash_cmd(cqspi, reg);
641 static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata,
642 const struct spi_mem_op *op)
644 struct cqspi_st *cqspi = f_pdata->cqspi;
645 void __iomem *reg_base = cqspi->iobase;
646 unsigned int dummy_clk = 0;
651 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB,
657 opcode = op->cmd.opcode >> 8;
659 opcode = op->cmd.opcode;
661 reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
662 reg |= cqspi_calc_rdreg(f_pdata);
664 /* Setup dummy clock cycles */
665 dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr);
667 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
671 reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
672 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
674 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
676 /* Set address width */
677 reg = readl(reg_base + CQSPI_REG_SIZE);
678 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
679 reg |= (op->addr.nbytes - 1);
680 writel(reg, reg_base + CQSPI_REG_SIZE);
684 static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
685 u8 *rxbuf, loff_t from_addr,
688 struct cqspi_st *cqspi = f_pdata->cqspi;
689 struct device *dev = &cqspi->pdev->dev;
690 void __iomem *reg_base = cqspi->iobase;
691 void __iomem *ahb_base = cqspi->ahb_base;
692 unsigned int remaining = n_rx;
693 unsigned int mod_bytes = n_rx % 4;
694 unsigned int bytes_to_read = 0;
695 u8 *rxbuf_end = rxbuf + n_rx;
698 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
699 writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
701 /* Clear all interrupts. */
702 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
704 writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
706 reinit_completion(&cqspi->transfer_complete);
707 writel(CQSPI_REG_INDIRECTRD_START_MASK,
708 reg_base + CQSPI_REG_INDIRECTRD);
710 while (remaining > 0) {
711 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
712 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
715 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
717 if (ret && bytes_to_read == 0) {
718 dev_err(dev, "Indirect read timeout, no bytes\n");
722 while (bytes_to_read != 0) {
723 unsigned int word_remain = round_down(remaining, 4);
725 bytes_to_read *= cqspi->fifo_width;
726 bytes_to_read = bytes_to_read > remaining ?
727 remaining : bytes_to_read;
728 bytes_to_read = round_down(bytes_to_read, 4);
729 /* Read 4 byte word chunks then single bytes */
731 ioread32_rep(ahb_base, rxbuf,
732 (bytes_to_read / 4));
733 } else if (!word_remain && mod_bytes) {
734 unsigned int temp = ioread32(ahb_base);
736 bytes_to_read = mod_bytes;
737 memcpy(rxbuf, &temp, min((unsigned int)
741 rxbuf += bytes_to_read;
742 remaining -= bytes_to_read;
743 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
747 reinit_completion(&cqspi->transfer_complete);
750 /* Check indirect done status */
751 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
752 CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
754 dev_err(dev, "Indirect read completion error (%i)\n", ret);
758 /* Disable interrupt */
759 writel(0, reg_base + CQSPI_REG_IRQMASK);
761 /* Clear indirect completion status */
762 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
767 /* Disable interrupt */
768 writel(0, reg_base + CQSPI_REG_IRQMASK);
770 /* Cancel the indirect read */
771 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
772 reg_base + CQSPI_REG_INDIRECTRD);
776 static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
777 const struct spi_mem_op *op)
781 struct cqspi_st *cqspi = f_pdata->cqspi;
782 void __iomem *reg_base = cqspi->iobase;
785 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB,
791 opcode = op->cmd.opcode >> 8;
793 opcode = op->cmd.opcode;
796 reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
797 reg |= f_pdata->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
798 reg |= f_pdata->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB;
799 writel(reg, reg_base + CQSPI_REG_WR_INSTR);
800 reg = cqspi_calc_rdreg(f_pdata);
801 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
804 * SPI NAND flashes require the address of the status register to be
805 * passed in the Read SR command. Also, some SPI NOR flashes like the
806 * cypress Semper flash expect a 4-byte dummy address in the Read SR
807 * command in DTR mode.
809 * But this controller does not support address phase in the Read SR
810 * command when doing auto-HW polling. So, disable write completion
811 * polling on the controller's side. spinand and spi-nor will take
812 * care of polling the status register.
814 reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
815 reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
816 writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
818 reg = readl(reg_base + CQSPI_REG_SIZE);
819 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
820 reg |= (op->addr.nbytes - 1);
821 writel(reg, reg_base + CQSPI_REG_SIZE);
825 static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata,
826 loff_t to_addr, const u8 *txbuf,
829 struct cqspi_st *cqspi = f_pdata->cqspi;
830 struct device *dev = &cqspi->pdev->dev;
831 void __iomem *reg_base = cqspi->iobase;
832 unsigned int remaining = n_tx;
833 unsigned int write_bytes;
836 writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
837 writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
839 /* Clear all interrupts. */
840 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
842 writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
844 reinit_completion(&cqspi->transfer_complete);
845 writel(CQSPI_REG_INDIRECTWR_START_MASK,
846 reg_base + CQSPI_REG_INDIRECTWR);
848 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
849 * Controller programming sequence, couple of cycles of
850 * QSPI_REF_CLK delay is required for the above bit to
851 * be internally synchronized by the QSPI module. Provide 5
855 ndelay(cqspi->wr_delay);
857 while (remaining > 0) {
858 size_t write_words, mod_bytes;
860 write_bytes = remaining;
861 write_words = write_bytes / 4;
862 mod_bytes = write_bytes % 4;
863 /* Write 4 bytes at a time then single bytes. */
865 iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
866 txbuf += (write_words * 4);
869 unsigned int temp = 0xFFFFFFFF;
871 memcpy(&temp, txbuf, mod_bytes);
872 iowrite32(temp, cqspi->ahb_base);
876 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
877 msecs_to_jiffies(CQSPI_TIMEOUT_MS))) {
878 dev_err(dev, "Indirect write timeout\n");
883 remaining -= write_bytes;
886 reinit_completion(&cqspi->transfer_complete);
889 /* Check indirect done status */
890 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
891 CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
893 dev_err(dev, "Indirect write completion error (%i)\n", ret);
897 /* Disable interrupt. */
898 writel(0, reg_base + CQSPI_REG_IRQMASK);
900 /* Clear indirect completion status */
901 writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
903 cqspi_wait_idle(cqspi);
908 /* Disable interrupt. */
909 writel(0, reg_base + CQSPI_REG_IRQMASK);
911 /* Cancel the indirect write */
912 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
913 reg_base + CQSPI_REG_INDIRECTWR);
917 static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata)
919 struct cqspi_st *cqspi = f_pdata->cqspi;
920 void __iomem *reg_base = cqspi->iobase;
921 unsigned int chip_select = f_pdata->cs;
924 reg = readl(reg_base + CQSPI_REG_CONFIG);
925 if (cqspi->is_decoded_cs) {
926 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
928 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
930 /* Convert CS if without decoder.
936 chip_select = 0xF & ~(1 << chip_select);
939 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
940 << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
941 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
942 << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
943 writel(reg, reg_base + CQSPI_REG_CONFIG);
946 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
947 const unsigned int ns_val)
951 ticks = ref_clk_hz / 1000; /* kHz */
952 ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
957 static void cqspi_delay(struct cqspi_flash_pdata *f_pdata)
959 struct cqspi_st *cqspi = f_pdata->cqspi;
960 void __iomem *iobase = cqspi->iobase;
961 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
962 unsigned int tshsl, tchsh, tslch, tsd2d;
966 /* calculate the number of ref ticks for one sclk tick */
967 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
969 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
970 /* this particular value must be at least one sclk */
974 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
975 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
976 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
978 reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
979 << CQSPI_REG_DELAY_TSHSL_LSB;
980 reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
981 << CQSPI_REG_DELAY_TCHSH_LSB;
982 reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
983 << CQSPI_REG_DELAY_TSLCH_LSB;
984 reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
985 << CQSPI_REG_DELAY_TSD2D_LSB;
986 writel(reg, iobase + CQSPI_REG_DELAY);
989 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
991 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
992 void __iomem *reg_base = cqspi->iobase;
995 /* Recalculate the baudrate divisor based on QSPI specification. */
996 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
998 reg = readl(reg_base + CQSPI_REG_CONFIG);
999 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
1000 reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
1001 writel(reg, reg_base + CQSPI_REG_CONFIG);
1004 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
1006 const unsigned int delay)
1008 void __iomem *reg_base = cqspi->iobase;
1011 reg = readl(reg_base + CQSPI_REG_READCAPTURE);
1014 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
1016 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
1018 reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
1019 << CQSPI_REG_READCAPTURE_DELAY_LSB);
1021 reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
1022 << CQSPI_REG_READCAPTURE_DELAY_LSB;
1024 writel(reg, reg_base + CQSPI_REG_READCAPTURE);
1027 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
1029 void __iomem *reg_base = cqspi->iobase;
1032 reg = readl(reg_base + CQSPI_REG_CONFIG);
1035 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
1037 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
1039 writel(reg, reg_base + CQSPI_REG_CONFIG);
1042 static void cqspi_configure(struct cqspi_flash_pdata *f_pdata,
1045 struct cqspi_st *cqspi = f_pdata->cqspi;
1046 int switch_cs = (cqspi->current_cs != f_pdata->cs);
1047 int switch_ck = (cqspi->sclk != sclk);
1049 if (switch_cs || switch_ck)
1050 cqspi_controller_enable(cqspi, 0);
1052 /* Switch chip select. */
1054 cqspi->current_cs = f_pdata->cs;
1055 cqspi_chipselect(f_pdata);
1058 /* Setup baudrate divisor and delays */
1061 cqspi_config_baudrate_div(cqspi);
1062 cqspi_delay(f_pdata);
1063 cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
1064 f_pdata->read_delay);
1067 if (switch_cs || switch_ck)
1068 cqspi_controller_enable(cqspi, 1);
1071 static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
1072 const struct spi_mem_op *op)
1074 struct cqspi_st *cqspi = f_pdata->cqspi;
1075 loff_t to = op->addr.val;
1076 size_t len = op->data.nbytes;
1077 const u_char *buf = op->data.buf.out;
1080 ret = cqspi_set_protocol(f_pdata, op);
1084 ret = cqspi_write_setup(f_pdata, op);
1089 * Some flashes like the Cypress Semper flash expect a dummy 4-byte
1090 * address (all 0s) with the read status register command in DTR mode.
1091 * But this controller does not support sending dummy address bytes to
1092 * the flash when it is polling the write completion register in DTR
1093 * mode. So, we can not use direct mode when in DTR mode for writing
1096 if (!f_pdata->dtr && cqspi->use_direct_mode &&
1097 ((to + len) <= cqspi->ahb_size)) {
1098 memcpy_toio(cqspi->ahb_base + to, buf, len);
1099 return cqspi_wait_idle(cqspi);
1102 return cqspi_indirect_write_execute(f_pdata, to, buf, len);
1105 static void cqspi_rx_dma_callback(void *param)
1107 struct cqspi_st *cqspi = param;
1109 complete(&cqspi->rx_dma_complete);
1112 static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata,
1113 u_char *buf, loff_t from, size_t len)
1115 struct cqspi_st *cqspi = f_pdata->cqspi;
1116 struct device *dev = &cqspi->pdev->dev;
1117 enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
1118 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
1120 struct dma_async_tx_descriptor *tx;
1121 dma_cookie_t cookie;
1123 struct device *ddev;
1125 if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
1126 memcpy_fromio(buf, cqspi->ahb_base + from, len);
1130 ddev = cqspi->rx_chan->device->dev;
1131 dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE);
1132 if (dma_mapping_error(ddev, dma_dst)) {
1133 dev_err(dev, "dma mapping failed\n");
1136 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
1139 dev_err(dev, "device_prep_dma_memcpy error\n");
1144 tx->callback = cqspi_rx_dma_callback;
1145 tx->callback_param = cqspi;
1146 cookie = tx->tx_submit(tx);
1147 reinit_completion(&cqspi->rx_dma_complete);
1149 ret = dma_submit_error(cookie);
1151 dev_err(dev, "dma_submit_error %d\n", cookie);
1156 dma_async_issue_pending(cqspi->rx_chan);
1157 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
1158 msecs_to_jiffies(max_t(size_t, len, 500)))) {
1159 dmaengine_terminate_sync(cqspi->rx_chan);
1160 dev_err(dev, "DMA wait_for_completion_timeout\n");
1166 dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE);
1171 static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata,
1172 const struct spi_mem_op *op)
1174 struct cqspi_st *cqspi = f_pdata->cqspi;
1175 loff_t from = op->addr.val;
1176 size_t len = op->data.nbytes;
1177 u_char *buf = op->data.buf.in;
1180 ret = cqspi_set_protocol(f_pdata, op);
1184 ret = cqspi_read_setup(f_pdata, op);
1188 if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size))
1189 return cqspi_direct_read_execute(f_pdata, buf, from, len);
1191 return cqspi_indirect_read_execute(f_pdata, buf, from, len);
1194 static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
1196 struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
1197 struct cqspi_flash_pdata *f_pdata;
1199 f_pdata = &cqspi->f_pdata[mem->spi->chip_select];
1200 cqspi_configure(f_pdata, mem->spi->max_speed_hz);
1202 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
1203 if (!op->addr.nbytes)
1204 return cqspi_command_read(f_pdata, op);
1206 return cqspi_read(f_pdata, op);
1209 if (!op->addr.nbytes || !op->data.buf.out)
1210 return cqspi_command_write(f_pdata, op);
1212 return cqspi_write(f_pdata, op);
1215 static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
1219 ret = cqspi_mem_process(mem, op);
1221 dev_err(&mem->spi->dev, "operation failed with %d\n", ret);
1226 static bool cqspi_supports_mem_op(struct spi_mem *mem,
1227 const struct spi_mem_op *op)
1229 bool all_true, all_false;
1231 all_true = op->cmd.dtr && op->addr.dtr && op->dummy.dtr &&
1233 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
1236 /* Mixed DTR modes not supported. */
1237 if (!(all_true || all_false))
1241 return spi_mem_dtr_supports_op(mem, op);
1243 return spi_mem_default_supports_op(mem, op);
1246 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
1247 struct cqspi_flash_pdata *f_pdata,
1248 struct device_node *np)
1250 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
1251 dev_err(&pdev->dev, "couldn't determine read-delay\n");
1255 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1256 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1260 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1261 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1265 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1266 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1270 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1271 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1275 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1276 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1283 static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
1285 struct device *dev = &cqspi->pdev->dev;
1286 struct device_node *np = dev->of_node;
1288 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1290 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1291 dev_err(dev, "couldn't determine fifo-depth\n");
1295 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1296 dev_err(dev, "couldn't determine fifo-width\n");
1300 if (of_property_read_u32(np, "cdns,trigger-address",
1301 &cqspi->trigger_address)) {
1302 dev_err(dev, "couldn't determine trigger-address\n");
1306 if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect))
1307 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT;
1309 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1314 static void cqspi_controller_init(struct cqspi_st *cqspi)
1318 cqspi_controller_enable(cqspi, 0);
1320 /* Configure the remap address register, no remap */
1321 writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1323 /* Disable all interrupts. */
1324 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1326 /* Configure the SRAM split to 1:1 . */
1327 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1329 /* Load indirect trigger address. */
1330 writel(cqspi->trigger_address,
1331 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1333 /* Program read watermark -- 1/2 of the FIFO. */
1334 writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1335 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1336 /* Program write watermark -- 1/8 of the FIFO. */
1337 writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1338 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1340 /* Disable direct access controller */
1341 if (!cqspi->use_direct_mode) {
1342 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1343 reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
1344 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1347 cqspi_controller_enable(cqspi, 1);
1350 static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
1352 dma_cap_mask_t mask;
1355 dma_cap_set(DMA_MEMCPY, mask);
1357 cqspi->rx_chan = dma_request_chan_by_mask(&mask);
1358 if (IS_ERR(cqspi->rx_chan)) {
1359 int ret = PTR_ERR(cqspi->rx_chan);
1360 cqspi->rx_chan = NULL;
1361 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n");
1363 init_completion(&cqspi->rx_dma_complete);
1368 static const char *cqspi_get_name(struct spi_mem *mem)
1370 struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
1371 struct device *dev = &cqspi->pdev->dev;
1373 return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select);
1376 static const struct spi_controller_mem_ops cqspi_mem_ops = {
1377 .exec_op = cqspi_exec_mem_op,
1378 .get_name = cqspi_get_name,
1379 .supports_op = cqspi_supports_mem_op,
1382 static int cqspi_setup_flash(struct cqspi_st *cqspi)
1384 struct platform_device *pdev = cqspi->pdev;
1385 struct device *dev = &pdev->dev;
1386 struct device_node *np = dev->of_node;
1387 struct cqspi_flash_pdata *f_pdata;
1391 /* Get flash device data */
1392 for_each_available_child_of_node(dev->of_node, np) {
1393 ret = of_property_read_u32(np, "reg", &cs);
1395 dev_err(dev, "Couldn't determine chip select.\n");
1400 if (cs >= CQSPI_MAX_CHIPSELECT) {
1401 dev_err(dev, "Chip select %d out of range.\n", cs);
1406 f_pdata = &cqspi->f_pdata[cs];
1407 f_pdata->cqspi = cqspi;
1410 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1420 static int cqspi_probe(struct platform_device *pdev)
1422 const struct cqspi_driver_platdata *ddata;
1423 struct reset_control *rstc, *rstc_ocp;
1424 struct device *dev = &pdev->dev;
1425 struct spi_master *master;
1426 struct resource *res_ahb;
1427 struct cqspi_st *cqspi;
1428 struct resource *res;
1432 master = spi_alloc_master(&pdev->dev, sizeof(*cqspi));
1434 dev_err(&pdev->dev, "spi_alloc_master failed\n");
1437 master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL;
1438 master->mem_ops = &cqspi_mem_ops;
1439 master->dev.of_node = pdev->dev.of_node;
1441 cqspi = spi_master_get_devdata(master);
1444 platform_set_drvdata(pdev, cqspi);
1446 /* Obtain configuration from OF. */
1447 ret = cqspi_of_get_pdata(cqspi);
1449 dev_err(dev, "Cannot get mandatory OF data.\n");
1451 goto probe_master_put;
1454 /* Obtain QSPI clock. */
1455 cqspi->clk = devm_clk_get(dev, NULL);
1456 if (IS_ERR(cqspi->clk)) {
1457 dev_err(dev, "Cannot claim QSPI clock.\n");
1458 ret = PTR_ERR(cqspi->clk);
1459 goto probe_master_put;
1462 /* Obtain and remap controller address. */
1463 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1464 cqspi->iobase = devm_ioremap_resource(dev, res);
1465 if (IS_ERR(cqspi->iobase)) {
1466 dev_err(dev, "Cannot remap controller address.\n");
1467 ret = PTR_ERR(cqspi->iobase);
1468 goto probe_master_put;
1471 /* Obtain and remap AHB address. */
1472 res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1473 cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1474 if (IS_ERR(cqspi->ahb_base)) {
1475 dev_err(dev, "Cannot remap AHB address.\n");
1476 ret = PTR_ERR(cqspi->ahb_base);
1477 goto probe_master_put;
1479 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
1480 cqspi->ahb_size = resource_size(res_ahb);
1482 init_completion(&cqspi->transfer_complete);
1484 /* Obtain IRQ line. */
1485 irq = platform_get_irq(pdev, 0);
1488 goto probe_master_put;
1491 pm_runtime_enable(dev);
1492 ret = pm_runtime_get_sync(dev);
1494 pm_runtime_put_noidle(dev);
1495 goto probe_master_put;
1498 ret = clk_prepare_enable(cqspi->clk);
1500 dev_err(dev, "Cannot enable QSPI clock.\n");
1501 goto probe_clk_failed;
1504 /* Obtain QSPI reset control */
1505 rstc = devm_reset_control_get_optional_exclusive(dev, "qspi");
1507 ret = PTR_ERR(rstc);
1508 dev_err(dev, "Cannot get QSPI reset.\n");
1509 goto probe_reset_failed;
1512 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");
1513 if (IS_ERR(rstc_ocp)) {
1514 ret = PTR_ERR(rstc_ocp);
1515 dev_err(dev, "Cannot get QSPI OCP reset.\n");
1516 goto probe_reset_failed;
1519 reset_control_assert(rstc);
1520 reset_control_deassert(rstc);
1522 reset_control_assert(rstc_ocp);
1523 reset_control_deassert(rstc_ocp);
1525 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1526 master->max_speed_hz = cqspi->master_ref_clk_hz;
1527 ddata = of_device_get_match_data(dev);
1529 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
1530 cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC,
1531 cqspi->master_ref_clk_hz);
1532 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL)
1533 master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL;
1534 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE))
1535 cqspi->use_direct_mode = true;
1538 ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1541 dev_err(dev, "Cannot request IRQ.\n");
1542 goto probe_reset_failed;
1545 cqspi_wait_idle(cqspi);
1546 cqspi_controller_init(cqspi);
1547 cqspi->current_cs = -1;
1550 master->num_chipselect = cqspi->num_chipselect;
1552 ret = cqspi_setup_flash(cqspi);
1554 dev_err(dev, "failed to setup flash parameters %d\n", ret);
1555 goto probe_setup_failed;
1558 if (cqspi->use_direct_mode) {
1559 ret = cqspi_request_mmap_dma(cqspi);
1560 if (ret == -EPROBE_DEFER)
1561 goto probe_setup_failed;
1564 ret = devm_spi_register_master(dev, master);
1566 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret);
1567 goto probe_setup_failed;
1572 cqspi_controller_enable(cqspi, 0);
1574 clk_disable_unprepare(cqspi->clk);
1576 pm_runtime_put_sync(dev);
1577 pm_runtime_disable(dev);
1579 spi_master_put(master);
1583 static int cqspi_remove(struct platform_device *pdev)
1585 struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1587 cqspi_controller_enable(cqspi, 0);
1590 dma_release_channel(cqspi->rx_chan);
1592 clk_disable_unprepare(cqspi->clk);
1594 pm_runtime_put_sync(&pdev->dev);
1595 pm_runtime_disable(&pdev->dev);
1600 #ifdef CONFIG_PM_SLEEP
1601 static int cqspi_suspend(struct device *dev)
1603 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1605 cqspi_controller_enable(cqspi, 0);
1609 static int cqspi_resume(struct device *dev)
1611 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1613 cqspi_controller_enable(cqspi, 1);
1617 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1618 .suspend = cqspi_suspend,
1619 .resume = cqspi_resume,
1622 #define CQSPI_DEV_PM_OPS (&cqspi__dev_pm_ops)
1624 #define CQSPI_DEV_PM_OPS NULL
1627 static const struct cqspi_driver_platdata cdns_qspi = {
1628 .quirks = CQSPI_DISABLE_DAC_MODE,
1631 static const struct cqspi_driver_platdata k2g_qspi = {
1632 .quirks = CQSPI_NEEDS_WR_DELAY,
1635 static const struct cqspi_driver_platdata am654_ospi = {
1636 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
1637 .quirks = CQSPI_NEEDS_WR_DELAY,
1640 static const struct cqspi_driver_platdata intel_lgm_qspi = {
1641 .quirks = CQSPI_DISABLE_DAC_MODE,
1644 static const struct of_device_id cqspi_dt_ids[] = {
1646 .compatible = "cdns,qspi-nor",
1650 .compatible = "ti,k2g-qspi",
1654 .compatible = "ti,am654-ospi",
1655 .data = &am654_ospi,
1658 .compatible = "intel,lgm-qspi",
1659 .data = &intel_lgm_qspi,
1661 { /* end of table */ }
1664 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1666 static struct platform_driver cqspi_platform_driver = {
1667 .probe = cqspi_probe,
1668 .remove = cqspi_remove,
1671 .pm = CQSPI_DEV_PM_OPS,
1672 .of_match_table = cqspi_dt_ids,
1676 module_platform_driver(cqspi_platform_driver);
1678 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1679 MODULE_LICENSE("GPL v2");
1680 MODULE_ALIAS("platform:" CQSPI_NAME);
1681 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
1682 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");
1683 MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>");
1684 MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>");
1685 MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>");