drivers/spi/spi-bcm63xx.c

   1 /*
   2  * Broadcom BCM63xx SPI controller support
   3  *
   4  * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
   5  * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the
  19  * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/clk.h>
  25 #include <linux/io.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/delay.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/spi/spi.h>
  31 #include <linux/completion.h>
  32 #include <linux/err.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/pm_runtime.h>
  35
  36 #include <bcm63xx_dev_spi.h>
  37
  38 #define BCM63XX_SPI_MAX_PREPEND         15
  39
  40 struct bcm63xx_spi {
  41         struct completion       done;
  42
  43         void __iomem            *regs;
  44         int                     irq;
  45
  46         /* Platform data */
  47         unsigned                fifo_size;
  48         unsigned int            msg_type_shift;
  49         unsigned int            msg_ctl_width;
  50
  51         /* data iomem */
  52         u8 __iomem              *tx_io;
  53         const u8 __iomem        *rx_io;
  54
  55         struct clk              *clk;
  56         struct platform_device  *pdev;
  57 };
  58
  59 static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
  60                                 unsigned int offset)
  61 {
  62         return bcm_readb(bs->regs + bcm63xx_spireg(offset));
  63 }
  64
  65 static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
  66                                 unsigned int offset)
  67 {
  68         return bcm_readw(bs->regs + bcm63xx_spireg(offset));
  69 }
  70
  71 static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
  72                                   u8 value, unsigned int offset)
  73 {
  74         bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
  75 }
  76
  77 static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
  78                                   u16 value, unsigned int offset)
  79 {
  80         bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
  81 }
  82
  83 static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
  84         { 20000000, SPI_CLK_20MHZ },
  85         { 12500000, SPI_CLK_12_50MHZ },
  86         {  6250000, SPI_CLK_6_250MHZ },
  87         {  3125000, SPI_CLK_3_125MHZ },
  88         {  1563000, SPI_CLK_1_563MHZ },
  89         {   781000, SPI_CLK_0_781MHZ },
  90         {   391000, SPI_CLK_0_391MHZ }
  91 };
  92
  93 static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
  94                                       struct spi_transfer *t)
  95 {
  96         struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
  97         u8 clk_cfg, reg;
  98         int i;
  99
 100         /* Find the closest clock configuration */
 101         for (i = 0; i < SPI_CLK_MASK; i++) {
 102                 if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
 103                         clk_cfg = bcm63xx_spi_freq_table[i][1];
 104                         break;
 105                 }
 106         }
 107
 108         /* No matching configuration found, default to lowest */
 109         if (i == SPI_CLK_MASK)
 110                 clk_cfg = SPI_CLK_0_391MHZ;
 111
 112         /* clear existing clock configuration bits of the register */
 113         reg = bcm_spi_readb(bs, SPI_CLK_CFG);
 114         reg &= ~SPI_CLK_MASK;
 115         reg |= clk_cfg;
 116
 117         bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
 118         dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
 119                 clk_cfg, t->speed_hz);
 120 }
 121
 122 /* the spi->mode bits understood by this driver: */
 123 #define MODEBITS (SPI_CPOL | SPI_CPHA)
 124
 125 static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
 126                                 unsigned int num_transfers)
 127 {
 128         struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 129         u16 msg_ctl;
 130         u16 cmd;
 131         u8 rx_tail;
 132         unsigned int i, timeout = 0, prepend_len = 0, len = 0;
 133         struct spi_transfer *t = first;
 134         bool do_rx = false;
 135         bool do_tx = false;
 136
 137         /* Disable the CMD_DONE interrupt */
 138         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 139
 140         dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
 141                 t->tx_buf, t->rx_buf, t->len);
 142
 143         if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
 144                 prepend_len = t->len;
 145
 146         /* prepare the buffer */
 147         for (i = 0; i < num_transfers; i++) {
 148                 if (t->tx_buf) {
 149                         do_tx = true;
 150                         memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
 151
 152                         /* don't prepend more than one tx */
 153                         if (t != first)
 154                                 prepend_len = 0;
 155                 }
 156
 157                 if (t->rx_buf) {
 158                         do_rx = true;
 159                         /* prepend is half-duplex write only */
 160                         if (t == first)
 161                                 prepend_len = 0;
 162                 }
 163
 164                 len += t->len;
 165
 166                 t = list_entry(t->transfer_list.next, struct spi_transfer,
 167                                transfer_list);
 168         }
 169
 170         reinit_completion(&bs->done);
 171
 172         /* Fill in the Message control register */
 173         msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
 174
 175         if (do_rx && do_tx && prepend_len == 0)
 176                 msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
 177         else if (do_rx)
 178                 msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
 179         else if (do_tx)
 180                 msg_ctl |= (SPI_HD_W << bs->msg_type_shift);
 181
 182         switch (bs->msg_ctl_width) {
 183         case 8:
 184                 bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
 185                 break;
 186         case 16:
 187                 bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
 188                 break;
 189         }
 190
 191         /* Issue the transfer */
 192         cmd = SPI_CMD_START_IMMEDIATE;
 193         cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
 194         cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
 195         bcm_spi_writew(bs, cmd, SPI_CMD);
 196
 197         /* Enable the CMD_DONE interrupt */
 198         bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
 199
 200         timeout = wait_for_completion_timeout(&bs->done, HZ);
 201         if (!timeout)
 202                 return -ETIMEDOUT;
 203
 204         if (!do_rx)
 205                 return 0;
 206
 207         len = 0;
 208         t = first;
 209         /* Read out all the data */
 210         for (i = 0; i < num_transfers; i++) {
 211                 if (t->rx_buf)
 212                         memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
 213
 214                 if (t != first || prepend_len == 0)
 215                         len += t->len;
 216
 217                 t = list_entry(t->transfer_list.next, struct spi_transfer,
 218                                transfer_list);
 219         }
 220
 221         return 0;
 222 }
 223
 224 static int bcm63xx_spi_transfer_one(struct spi_master *master,
 225                                         struct spi_message *m)
 226 {
 227         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 228         struct spi_transfer *t, *first = NULL;
 229         struct spi_device *spi = m->spi;
 230         int status = 0;
 231         unsigned int n_transfers = 0, total_len = 0;
 232         bool can_use_prepend = false;
 233
 234         /*
 235          * This SPI controller does not support keeping CS active after a
 236          * transfer.
 237          * Work around this by merging as many transfers we can into one big
 238          * full-duplex transfers.
 239          */
 240         list_for_each_entry(t, &m->transfers, transfer_list) {
 241                 if (!first)
 242                         first = t;
 243
 244                 n_transfers++;
 245                 total_len += t->len;
 246
 247                 if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
 248                     first->len <= BCM63XX_SPI_MAX_PREPEND)
 249                         can_use_prepend = true;
 250                 else if (can_use_prepend && t->tx_buf)
 251                         can_use_prepend = false;
 252
 253                 /* we can only transfer one fifo worth of data */
 254                 if ((can_use_prepend &&
 255                      total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
 256                     (!can_use_prepend && total_len > bs->fifo_size)) {
 257                         dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
 258                                 total_len, bs->fifo_size);
 259                         status = -EINVAL;
 260                         goto exit;
 261                 }
 262
 263                 /* all combined transfers have to have the same speed */
 264                 if (t->speed_hz != first->speed_hz) {
 265                         dev_err(&spi->dev, "unable to change speed between transfers\n");
 266                         status = -EINVAL;
 267                         goto exit;
 268                 }
 269
 270                 /* CS will be deasserted directly after transfer */
 271                 if (t->delay_usecs) {
 272                         dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
 273                         status = -EINVAL;
 274                         goto exit;
 275                 }
 276
 277                 if (t->cs_change ||
 278                     list_is_last(&t->transfer_list, &m->transfers)) {
 279                         /* configure adapter for a new transfer */
 280                         bcm63xx_spi_setup_transfer(spi, first);
 281
 282                         /* send the data */
 283                         status = bcm63xx_txrx_bufs(spi, first, n_transfers);
 284                         if (status)
 285                                 goto exit;
 286
 287                         m->actual_length += total_len;
 288
 289                         first = NULL;
 290                         n_transfers = 0;
 291                         total_len = 0;
 292                         can_use_prepend = false;
 293                 }
 294         }
 295 exit:
 296         m->status = status;
 297         spi_finalize_current_message(master);
 298
 299         return 0;
 300 }
 301
 302 /* This driver supports single master mode only. Hence
 303  * CMD_DONE is the only interrupt we care about
 304  */
 305 static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
 306 {
 307         struct spi_master *master = (struct spi_master *)dev_id;
 308         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 309         u8 intr;
 310
 311         /* Read interupts and clear them immediately */
 312         intr = bcm_spi_readb(bs, SPI_INT_STATUS);
 313         bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 314         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 315
 316         /* A transfer completed */
 317         if (intr & SPI_INTR_CMD_DONE)
 318                 complete(&bs->done);
 319
 320         return IRQ_HANDLED;
 321 }
 322
 323
 324 static int bcm63xx_spi_probe(struct platform_device *pdev)
 325 {
 326         struct resource *r;
 327         struct device *dev = &pdev->dev;
 328         struct bcm63xx_spi_pdata *pdata = dev_get_platdata(&pdev->dev);
 329         int irq;
 330         struct spi_master *master;
 331         struct clk *clk;
 332         struct bcm63xx_spi *bs;
 333         int ret;
 334
 335         irq = platform_get_irq(pdev, 0);
 336         if (irq < 0) {
 337                 dev_err(dev, "no irq\n");
 338                 return -ENXIO;
 339         }
 340
 341         clk = devm_clk_get(dev, "spi");
 342         if (IS_ERR(clk)) {
 343                 dev_err(dev, "no clock for device\n");
 344                 return PTR_ERR(clk);
 345         }
 346
 347         master = spi_alloc_master(dev, sizeof(*bs));
 348         if (!master) {
 349                 dev_err(dev, "out of memory\n");
 350                 return -ENOMEM;
 351         }
 352
 353         bs = spi_master_get_devdata(master);
 354         init_completion(&bs->done);
 355
 356         platform_set_drvdata(pdev, master);
 357         bs->pdev = pdev;
 358
 359         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 360         bs->regs = devm_ioremap_resource(&pdev->dev, r);
 361         if (IS_ERR(bs->regs)) {
 362                 ret = PTR_ERR(bs->regs);
 363                 goto out_err;
 364         }
 365
 366         bs->irq = irq;
 367         bs->clk = clk;
 368         bs->fifo_size = pdata->fifo_size;
 369
 370         ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
 371                                                         pdev->name, master);
 372         if (ret) {
 373                 dev_err(dev, "unable to request irq\n");
 374                 goto out_err;
 375         }
 376
 377         master->bus_num = pdata->bus_num;
 378         master->num_chipselect = pdata->num_chipselect;
 379         master->transfer_one_message = bcm63xx_spi_transfer_one;
 380         master->mode_bits = MODEBITS;
 381         master->bits_per_word_mask = SPI_BPW_MASK(8);
 382         master->auto_runtime_pm = true;
 383         bs->msg_type_shift = pdata->msg_type_shift;
 384         bs->msg_ctl_width = pdata->msg_ctl_width;
 385         bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
 386         bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
 387
 388         switch (bs->msg_ctl_width) {
 389         case 8:
 390         case 16:
 391                 break;
 392         default:
 393                 dev_err(dev, "unsupported MSG_CTL width: %d\n",
 394                          bs->msg_ctl_width);
 395                 goto out_err;
 396         }
 397
 398         /* Initialize hardware */
 399         ret = clk_prepare_enable(bs->clk);
 400         if (ret)
 401                 goto out_err;
 402
 403         bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 404
 405         /* register and we are done */
 406         ret = devm_spi_register_master(dev, master);
 407         if (ret) {
 408                 dev_err(dev, "spi register failed\n");
 409                 goto out_clk_disable;
 410         }
 411
 412         dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n",
 413                  r->start, irq, bs->fifo_size);
 414
 415         return 0;
 416
 417 out_clk_disable:
 418         clk_disable_unprepare(clk);
 419 out_err:
 420         spi_master_put(master);
 421         return ret;
 422 }
 423
 424 static int bcm63xx_spi_remove(struct platform_device *pdev)
 425 {
 426         struct spi_master *master = platform_get_drvdata(pdev);
 427         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 428
 429         /* reset spi block */
 430         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 431
 432         /* HW shutdown */
 433         clk_disable_unprepare(bs->clk);
 434
 435         return 0;
 436 }
 437
 438 #ifdef CONFIG_PM_SLEEP
 439 static int bcm63xx_spi_suspend(struct device *dev)
 440 {
 441         struct spi_master *master = dev_get_drvdata(dev);
 442         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 443
 444         spi_master_suspend(master);
 445
 446         clk_disable_unprepare(bs->clk);
 447
 448         return 0;
 449 }
 450
 451 static int bcm63xx_spi_resume(struct device *dev)
 452 {
 453         struct spi_master *master = dev_get_drvdata(dev);
 454         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 455         int ret;
 456
 457         ret = clk_prepare_enable(bs->clk);
 458         if (ret)
 459                 return ret;
 460
 461         spi_master_resume(master);
 462
 463         return 0;
 464 }
 465 #endif
 466
 467 static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
 468         SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume)
 469 };
 470
 471 static struct platform_driver bcm63xx_spi_driver = {
 472         .driver = {
 473                 .name   = "bcm63xx-spi",
 474                 .owner  = THIS_MODULE,
 475                 .pm     = &bcm63xx_spi_pm_ops,
 476         },
 477         .probe          = bcm63xx_spi_probe,
 478         .remove         = bcm63xx_spi_remove,
 479 };
 480
 481 module_platform_driver(bcm63xx_spi_driver);
 482
 483 MODULE_ALIAS("platform:bcm63xx_spi");
 484 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
 485 MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
 486 MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
 487 MODULE_LICENSE("GPL");