1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for Atmel AT32 and AT91 SPI Controllers
5 * Copyright (C) 2006 Atmel Corporation
8 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/delay.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/dmaengine.h>
15 #include <linux/err.h>
16 #include <linux/interrupt.h>
17 #include <linux/spi/spi.h>
18 #include <linux/slab.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/iopoll.h>
26 #include <trace/events/spi.h>
28 /* SPI register offsets */
31 #define SPI_RDR 0x0008
32 #define SPI_TDR 0x000c
34 #define SPI_IER 0x0014
35 #define SPI_IDR 0x0018
36 #define SPI_IMR 0x001c
37 #define SPI_CSR0 0x0030
38 #define SPI_CSR1 0x0034
39 #define SPI_CSR2 0x0038
40 #define SPI_CSR3 0x003c
41 #define SPI_FMR 0x0040
42 #define SPI_FLR 0x0044
43 #define SPI_VERSION 0x00fc
44 #define SPI_RPR 0x0100
45 #define SPI_RCR 0x0104
46 #define SPI_TPR 0x0108
47 #define SPI_TCR 0x010c
48 #define SPI_RNPR 0x0110
49 #define SPI_RNCR 0x0114
50 #define SPI_TNPR 0x0118
51 #define SPI_TNCR 0x011c
52 #define SPI_PTCR 0x0120
53 #define SPI_PTSR 0x0124
56 #define SPI_SPIEN_OFFSET 0
57 #define SPI_SPIEN_SIZE 1
58 #define SPI_SPIDIS_OFFSET 1
59 #define SPI_SPIDIS_SIZE 1
60 #define SPI_SWRST_OFFSET 7
61 #define SPI_SWRST_SIZE 1
62 #define SPI_LASTXFER_OFFSET 24
63 #define SPI_LASTXFER_SIZE 1
64 #define SPI_TXFCLR_OFFSET 16
65 #define SPI_TXFCLR_SIZE 1
66 #define SPI_RXFCLR_OFFSET 17
67 #define SPI_RXFCLR_SIZE 1
68 #define SPI_FIFOEN_OFFSET 30
69 #define SPI_FIFOEN_SIZE 1
70 #define SPI_FIFODIS_OFFSET 31
71 #define SPI_FIFODIS_SIZE 1
74 #define SPI_MSTR_OFFSET 0
75 #define SPI_MSTR_SIZE 1
76 #define SPI_PS_OFFSET 1
78 #define SPI_PCSDEC_OFFSET 2
79 #define SPI_PCSDEC_SIZE 1
80 #define SPI_FDIV_OFFSET 3
81 #define SPI_FDIV_SIZE 1
82 #define SPI_MODFDIS_OFFSET 4
83 #define SPI_MODFDIS_SIZE 1
84 #define SPI_WDRBT_OFFSET 5
85 #define SPI_WDRBT_SIZE 1
86 #define SPI_LLB_OFFSET 7
87 #define SPI_LLB_SIZE 1
88 #define SPI_PCS_OFFSET 16
89 #define SPI_PCS_SIZE 4
90 #define SPI_DLYBCS_OFFSET 24
91 #define SPI_DLYBCS_SIZE 8
93 /* Bitfields in RDR */
94 #define SPI_RD_OFFSET 0
95 #define SPI_RD_SIZE 16
97 /* Bitfields in TDR */
98 #define SPI_TD_OFFSET 0
99 #define SPI_TD_SIZE 16
101 /* Bitfields in SR */
102 #define SPI_RDRF_OFFSET 0
103 #define SPI_RDRF_SIZE 1
104 #define SPI_TDRE_OFFSET 1
105 #define SPI_TDRE_SIZE 1
106 #define SPI_MODF_OFFSET 2
107 #define SPI_MODF_SIZE 1
108 #define SPI_OVRES_OFFSET 3
109 #define SPI_OVRES_SIZE 1
110 #define SPI_ENDRX_OFFSET 4
111 #define SPI_ENDRX_SIZE 1
112 #define SPI_ENDTX_OFFSET 5
113 #define SPI_ENDTX_SIZE 1
114 #define SPI_RXBUFF_OFFSET 6
115 #define SPI_RXBUFF_SIZE 1
116 #define SPI_TXBUFE_OFFSET 7
117 #define SPI_TXBUFE_SIZE 1
118 #define SPI_NSSR_OFFSET 8
119 #define SPI_NSSR_SIZE 1
120 #define SPI_TXEMPTY_OFFSET 9
121 #define SPI_TXEMPTY_SIZE 1
122 #define SPI_SPIENS_OFFSET 16
123 #define SPI_SPIENS_SIZE 1
124 #define SPI_TXFEF_OFFSET 24
125 #define SPI_TXFEF_SIZE 1
126 #define SPI_TXFFF_OFFSET 25
127 #define SPI_TXFFF_SIZE 1
128 #define SPI_TXFTHF_OFFSET 26
129 #define SPI_TXFTHF_SIZE 1
130 #define SPI_RXFEF_OFFSET 27
131 #define SPI_RXFEF_SIZE 1
132 #define SPI_RXFFF_OFFSET 28
133 #define SPI_RXFFF_SIZE 1
134 #define SPI_RXFTHF_OFFSET 29
135 #define SPI_RXFTHF_SIZE 1
136 #define SPI_TXFPTEF_OFFSET 30
137 #define SPI_TXFPTEF_SIZE 1
138 #define SPI_RXFPTEF_OFFSET 31
139 #define SPI_RXFPTEF_SIZE 1
141 /* Bitfields in CSR0 */
142 #define SPI_CPOL_OFFSET 0
143 #define SPI_CPOL_SIZE 1
144 #define SPI_NCPHA_OFFSET 1
145 #define SPI_NCPHA_SIZE 1
146 #define SPI_CSAAT_OFFSET 3
147 #define SPI_CSAAT_SIZE 1
148 #define SPI_BITS_OFFSET 4
149 #define SPI_BITS_SIZE 4
150 #define SPI_SCBR_OFFSET 8
151 #define SPI_SCBR_SIZE 8
152 #define SPI_DLYBS_OFFSET 16
153 #define SPI_DLYBS_SIZE 8
154 #define SPI_DLYBCT_OFFSET 24
155 #define SPI_DLYBCT_SIZE 8
157 /* Bitfields in RCR */
158 #define SPI_RXCTR_OFFSET 0
159 #define SPI_RXCTR_SIZE 16
161 /* Bitfields in TCR */
162 #define SPI_TXCTR_OFFSET 0
163 #define SPI_TXCTR_SIZE 16
165 /* Bitfields in RNCR */
166 #define SPI_RXNCR_OFFSET 0
167 #define SPI_RXNCR_SIZE 16
169 /* Bitfields in TNCR */
170 #define SPI_TXNCR_OFFSET 0
171 #define SPI_TXNCR_SIZE 16
173 /* Bitfields in PTCR */
174 #define SPI_RXTEN_OFFSET 0
175 #define SPI_RXTEN_SIZE 1
176 #define SPI_RXTDIS_OFFSET 1
177 #define SPI_RXTDIS_SIZE 1
178 #define SPI_TXTEN_OFFSET 8
179 #define SPI_TXTEN_SIZE 1
180 #define SPI_TXTDIS_OFFSET 9
181 #define SPI_TXTDIS_SIZE 1
183 /* Bitfields in FMR */
184 #define SPI_TXRDYM_OFFSET 0
185 #define SPI_TXRDYM_SIZE 2
186 #define SPI_RXRDYM_OFFSET 4
187 #define SPI_RXRDYM_SIZE 2
188 #define SPI_TXFTHRES_OFFSET 16
189 #define SPI_TXFTHRES_SIZE 6
190 #define SPI_RXFTHRES_OFFSET 24
191 #define SPI_RXFTHRES_SIZE 6
193 /* Bitfields in FLR */
194 #define SPI_TXFL_OFFSET 0
195 #define SPI_TXFL_SIZE 6
196 #define SPI_RXFL_OFFSET 16
197 #define SPI_RXFL_SIZE 6
199 /* Constants for BITS */
200 #define SPI_BITS_8_BPT 0
201 #define SPI_BITS_9_BPT 1
202 #define SPI_BITS_10_BPT 2
203 #define SPI_BITS_11_BPT 3
204 #define SPI_BITS_12_BPT 4
205 #define SPI_BITS_13_BPT 5
206 #define SPI_BITS_14_BPT 6
207 #define SPI_BITS_15_BPT 7
208 #define SPI_BITS_16_BPT 8
209 #define SPI_ONE_DATA 0
210 #define SPI_TWO_DATA 1
211 #define SPI_FOUR_DATA 2
213 /* Bit manipulation macros */
214 #define SPI_BIT(name) \
215 (1 << SPI_##name##_OFFSET)
216 #define SPI_BF(name, value) \
217 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
218 #define SPI_BFEXT(name, value) \
219 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
220 #define SPI_BFINS(name, value, old) \
221 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
222 | SPI_BF(name, value))
224 /* Register access macros */
225 #define spi_readl(port, reg) \
226 readl_relaxed((port)->regs + SPI_##reg)
227 #define spi_writel(port, reg, value) \
228 writel_relaxed((value), (port)->regs + SPI_##reg)
229 #define spi_writew(port, reg, value) \
230 writew_relaxed((value), (port)->regs + SPI_##reg)
232 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
233 * cache operations; better heuristics consider wordsize and bitrate.
235 #define DMA_MIN_BYTES 16
237 #define AUTOSUSPEND_TIMEOUT 2000
239 struct atmel_spi_caps {
242 bool has_dma_support;
243 bool has_pdc_support;
247 * The core SPI transfer engine just talks to a register bank to set up
248 * DMA transfers; transfer queue progress is driven by IRQs. The clock
249 * framework provides the base clock, subdivided for each spi_device.
259 struct platform_device *pdev;
260 unsigned long spi_clk;
262 struct spi_transfer *current_transfer;
263 int current_remaining_bytes;
265 dma_addr_t dma_addr_rx_bbuf;
266 dma_addr_t dma_addr_tx_bbuf;
270 struct completion xfer_completion;
272 struct atmel_spi_caps caps;
282 u8 native_cs_for_gpio;
285 /* Controller-specific per-slave state */
286 struct atmel_spi_device {
290 #define SPI_MAX_DMA_XFER 65535 /* true for both PDC and DMA */
291 #define INVALID_DMA_ADDRESS 0xffffffff
294 * This frequency can be anything supported by the controller, but to avoid
295 * unnecessary delay, the highest possible frequency is chosen.
297 * This frequency is the highest possible which is not interfering with other
298 * chip select registers (see Note for Serial Clock Bit Rate configuration in
299 * Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16, page 1283)
301 #define DUMMY_MSG_FREQUENCY 0x02
303 * 8 bits is the minimum data the controller is capable of sending.
305 * This message can be anything as it should not be treated by any SPI device.
307 #define DUMMY_MSG 0xAA
310 * Version 2 of the SPI controller has
312 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
313 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
315 * - SPI_CSRx.SBCR allows faster clocking
317 static bool atmel_spi_is_v2(struct atmel_spi *as)
319 return as->caps.is_spi2;
323 * Send a dummy message.
325 * This is sometimes needed when using a CS GPIO to force clock transition when
326 * switching between devices with different polarities.
328 static void atmel_spi_send_dummy(struct atmel_spi *as, struct spi_device *spi, int chip_select)
334 * Set a clock frequency to allow sending message on SPI bus.
335 * The frequency here can be anything, but is needed for
336 * the controller to send the data.
338 csr = spi_readl(as, CSR0 + 4 * chip_select);
339 csr = SPI_BFINS(SCBR, DUMMY_MSG_FREQUENCY, csr);
340 spi_writel(as, CSR0 + 4 * chip_select, csr);
343 * Read all data coming from SPI bus, needed to be able to send
347 while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
352 spi_writel(as, TDR, DUMMY_MSG);
354 readl_poll_timeout_atomic(as->regs + SPI_SR, status,
355 (status & SPI_BIT(TXEMPTY)), 1, 1000);
360 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
361 * they assume that spi slave device state will not change on deselect, so
362 * that automagic deselection is OK. ("NPCSx rises if no data is to be
363 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
364 * controllers have CSAAT and friends.
366 * Even controller newer than ar91rm9200, using GPIOs can make sens as
367 * it lets us support active-high chipselects despite the controller's
368 * belief that only active-low devices/systems exists.
370 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
371 * right when driven with GPIO. ("Mode Fault does not allow more than one
372 * Master on Chip Select 0.") No workaround exists for that ... so for
373 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
374 * and (c) will trigger that first erratum in some cases.
376 * When changing the clock polarity, the SPI controller waits for the next
377 * transmission to enforce the default clock state. This may be an issue when
378 * using a GPIO as Chip Select: the clock level is applied only when the first
379 * packet is sent, once the CS has already been asserted. The workaround is to
380 * avoid this by sending a first (dummy) message before toggling the CS state.
382 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
384 struct atmel_spi_device *asd = spi->controller_state;
389 if (spi_get_csgpiod(spi, 0))
390 chip_select = as->native_cs_for_gpio;
392 chip_select = spi_get_chipselect(spi, 0);
394 if (atmel_spi_is_v2(as)) {
395 spi_writel(as, CSR0 + 4 * chip_select, asd->csr);
396 /* For the low SPI version, there is a issue that PDC transfer
397 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
399 spi_writel(as, CSR0, asd->csr);
400 if (as->caps.has_wdrbt) {
402 SPI_BF(PCS, ~(0x01 << chip_select))
408 SPI_BF(PCS, ~(0x01 << chip_select))
413 mr = spi_readl(as, MR);
416 * Ensures the clock polarity is valid before we actually
417 * assert the CS to avoid spurious clock edges to be
418 * processed by the spi devices.
420 if (spi_get_csgpiod(spi, 0)) {
421 new_polarity = (asd->csr & SPI_BIT(CPOL)) != 0;
422 if (new_polarity != as->last_polarity) {
424 * Need to disable the GPIO before sending the dummy
425 * message because it is already set by the spi core.
427 gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), 0);
428 atmel_spi_send_dummy(as, spi, chip_select);
429 as->last_polarity = new_polarity;
430 gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), 1);
434 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
438 /* Make sure clock polarity is correct */
439 for (i = 0; i < spi->controller->num_chipselect; i++) {
440 csr = spi_readl(as, CSR0 + 4 * i);
441 if ((csr ^ cpol) & SPI_BIT(CPOL))
442 spi_writel(as, CSR0 + 4 * i,
443 csr ^ SPI_BIT(CPOL));
446 mr = spi_readl(as, MR);
447 mr = SPI_BFINS(PCS, ~(1 << chip_select), mr);
448 spi_writel(as, MR, mr);
451 dev_dbg(&spi->dev, "activate NPCS, mr %08x\n", mr);
454 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
459 if (spi_get_csgpiod(spi, 0))
460 chip_select = as->native_cs_for_gpio;
462 chip_select = spi_get_chipselect(spi, 0);
464 /* only deactivate *this* device; sometimes transfers to
465 * another device may be active when this routine is called.
467 mr = spi_readl(as, MR);
468 if (~SPI_BFEXT(PCS, mr) & (1 << chip_select)) {
469 mr = SPI_BFINS(PCS, 0xf, mr);
470 spi_writel(as, MR, mr);
473 dev_dbg(&spi->dev, "DEactivate NPCS, mr %08x\n", mr);
475 if (!spi_get_csgpiod(spi, 0))
476 spi_writel(as, CR, SPI_BIT(LASTXFER));
479 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
481 spin_lock_irqsave(&as->lock, as->flags);
484 static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
486 spin_unlock_irqrestore(&as->lock, as->flags);
489 static inline bool atmel_spi_is_vmalloc_xfer(struct spi_transfer *xfer)
491 return is_vmalloc_addr(xfer->tx_buf) || is_vmalloc_addr(xfer->rx_buf);
494 static inline bool atmel_spi_use_dma(struct atmel_spi *as,
495 struct spi_transfer *xfer)
497 return as->use_dma && xfer->len >= DMA_MIN_BYTES;
500 static bool atmel_spi_can_dma(struct spi_controller *host,
501 struct spi_device *spi,
502 struct spi_transfer *xfer)
504 struct atmel_spi *as = spi_controller_get_devdata(host);
506 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5))
507 return atmel_spi_use_dma(as, xfer) &&
508 !atmel_spi_is_vmalloc_xfer(xfer);
510 return atmel_spi_use_dma(as, xfer);
514 static int atmel_spi_dma_slave_config(struct atmel_spi *as, u8 bits_per_word)
516 struct spi_controller *host = platform_get_drvdata(as->pdev);
517 struct dma_slave_config slave_config;
520 if (bits_per_word > 8) {
521 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
522 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
524 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
525 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
528 slave_config.dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
529 slave_config.src_addr = (dma_addr_t)as->phybase + SPI_RDR;
530 slave_config.src_maxburst = 1;
531 slave_config.dst_maxburst = 1;
532 slave_config.device_fc = false;
535 * This driver uses fixed peripheral select mode (PS bit set to '0' in
536 * the Mode Register).
537 * So according to the datasheet, when FIFOs are available (and
538 * enabled), the Transmit FIFO operates in Multiple Data Mode.
539 * In this mode, up to 2 data, not 4, can be written into the Transmit
540 * Data Register in a single access.
541 * However, the first data has to be written into the lowest 16 bits and
542 * the second data into the highest 16 bits of the Transmit
543 * Data Register. For 8bit data (the most frequent case), it would
544 * require to rework tx_buf so each data would actually fit 16 bits.
545 * So we'd rather write only one data at the time. Hence the transmit
546 * path works the same whether FIFOs are available (and enabled) or not.
548 if (dmaengine_slave_config(host->dma_tx, &slave_config)) {
549 dev_err(&as->pdev->dev,
550 "failed to configure tx dma channel\n");
555 * This driver configures the spi controller for host mode (MSTR bit
556 * set to '1' in the Mode Register).
557 * So according to the datasheet, when FIFOs are available (and
558 * enabled), the Receive FIFO operates in Single Data Mode.
559 * So the receive path works the same whether FIFOs are available (and
562 if (dmaengine_slave_config(host->dma_rx, &slave_config)) {
563 dev_err(&as->pdev->dev,
564 "failed to configure rx dma channel\n");
571 static int atmel_spi_configure_dma(struct spi_controller *host,
572 struct atmel_spi *as)
574 struct device *dev = &as->pdev->dev;
577 host->dma_tx = dma_request_chan(dev, "tx");
578 if (IS_ERR(host->dma_tx)) {
579 err = PTR_ERR(host->dma_tx);
580 dev_dbg(dev, "No TX DMA channel, DMA is disabled\n");
584 host->dma_rx = dma_request_chan(dev, "rx");
585 if (IS_ERR(host->dma_rx)) {
586 err = PTR_ERR(host->dma_rx);
588 * No reason to check EPROBE_DEFER here since we have already
589 * requested tx channel.
591 dev_dbg(dev, "No RX DMA channel, DMA is disabled\n");
595 err = atmel_spi_dma_slave_config(as, 8);
599 dev_info(&as->pdev->dev,
600 "Using %s (tx) and %s (rx) for DMA transfers\n",
601 dma_chan_name(host->dma_tx),
602 dma_chan_name(host->dma_rx));
606 if (!IS_ERR(host->dma_rx))
607 dma_release_channel(host->dma_rx);
608 if (!IS_ERR(host->dma_tx))
609 dma_release_channel(host->dma_tx);
611 host->dma_tx = host->dma_rx = NULL;
615 static void atmel_spi_stop_dma(struct spi_controller *host)
618 dmaengine_terminate_all(host->dma_rx);
620 dmaengine_terminate_all(host->dma_tx);
623 static void atmel_spi_release_dma(struct spi_controller *host)
626 dma_release_channel(host->dma_rx);
630 dma_release_channel(host->dma_tx);
635 /* This function is called by the DMA driver from tasklet context */
636 static void dma_callback(void *data)
638 struct spi_controller *host = data;
639 struct atmel_spi *as = spi_controller_get_devdata(host);
641 if (is_vmalloc_addr(as->current_transfer->rx_buf) &&
642 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
643 memcpy(as->current_transfer->rx_buf, as->addr_rx_bbuf,
644 as->current_transfer->len);
646 complete(&as->xfer_completion);
650 * Next transfer using PIO without FIFO.
652 static void atmel_spi_next_xfer_single(struct spi_controller *host,
653 struct spi_transfer *xfer)
655 struct atmel_spi *as = spi_controller_get_devdata(host);
656 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
658 dev_vdbg(host->dev.parent, "atmel_spi_next_xfer_pio\n");
660 /* Make sure data is not remaining in RDR */
662 while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
667 if (xfer->bits_per_word > 8)
668 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
670 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
672 dev_dbg(host->dev.parent,
673 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
674 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
675 xfer->bits_per_word);
677 /* Enable relevant interrupts */
678 spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
682 * Next transfer using PIO with FIFO.
684 static void atmel_spi_next_xfer_fifo(struct spi_controller *host,
685 struct spi_transfer *xfer)
687 struct atmel_spi *as = spi_controller_get_devdata(host);
688 u32 current_remaining_data, num_data;
689 u32 offset = xfer->len - as->current_remaining_bytes;
690 const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset);
691 const u8 *bytes = (const u8 *)((u8 *)xfer->tx_buf + offset);
695 dev_vdbg(host->dev.parent, "atmel_spi_next_xfer_fifo\n");
697 /* Compute the number of data to transfer in the current iteration */
698 current_remaining_data = ((xfer->bits_per_word > 8) ?
699 ((u32)as->current_remaining_bytes >> 1) :
700 (u32)as->current_remaining_bytes);
701 num_data = min(current_remaining_data, as->fifo_size);
703 /* Flush RX and TX FIFOs */
704 spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR));
705 while (spi_readl(as, FLR))
708 /* Set RX FIFO Threshold to the number of data to transfer */
709 fifomr = spi_readl(as, FMR);
710 spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr));
712 /* Clear FIFO flags in the Status Register, especially RXFTHF */
713 (void)spi_readl(as, SR);
716 while (num_data >= 2) {
717 if (xfer->bits_per_word > 8) {
725 spi_writel(as, TDR, (td1 << 16) | td0);
730 if (xfer->bits_per_word > 8)
735 spi_writew(as, TDR, td0);
739 dev_dbg(host->dev.parent,
740 " start fifo xfer %p: len %u tx %p rx %p bitpw %d\n",
741 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
742 xfer->bits_per_word);
745 * Enable RX FIFO Threshold Flag interrupt to be notified about
746 * transfer completion.
748 spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES));
752 * Next transfer using PIO.
754 static void atmel_spi_next_xfer_pio(struct spi_controller *host,
755 struct spi_transfer *xfer)
757 struct atmel_spi *as = spi_controller_get_devdata(host);
760 atmel_spi_next_xfer_fifo(host, xfer);
762 atmel_spi_next_xfer_single(host, xfer);
766 * Submit next transfer for DMA.
768 static int atmel_spi_next_xfer_dma_submit(struct spi_controller *host,
769 struct spi_transfer *xfer,
772 struct atmel_spi *as = spi_controller_get_devdata(host);
773 struct dma_chan *rxchan = host->dma_rx;
774 struct dma_chan *txchan = host->dma_tx;
775 struct dma_async_tx_descriptor *rxdesc;
776 struct dma_async_tx_descriptor *txdesc;
779 dev_vdbg(host->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
781 /* Check that the channels are available */
782 if (!rxchan || !txchan)
788 if (atmel_spi_dma_slave_config(as, xfer->bits_per_word))
791 /* Send both scatterlists */
792 if (atmel_spi_is_vmalloc_xfer(xfer) &&
793 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
794 rxdesc = dmaengine_prep_slave_single(rxchan,
795 as->dma_addr_rx_bbuf,
801 rxdesc = dmaengine_prep_slave_sg(rxchan,
811 if (atmel_spi_is_vmalloc_xfer(xfer) &&
812 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
813 memcpy(as->addr_tx_bbuf, xfer->tx_buf, xfer->len);
814 txdesc = dmaengine_prep_slave_single(txchan,
815 as->dma_addr_tx_bbuf,
816 xfer->len, DMA_MEM_TO_DEV,
820 txdesc = dmaengine_prep_slave_sg(txchan,
830 dev_dbg(host->dev.parent,
831 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
832 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
833 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
835 /* Enable relevant interrupts */
836 spi_writel(as, IER, SPI_BIT(OVRES));
838 /* Put the callback on the RX transfer only, that should finish last */
839 rxdesc->callback = dma_callback;
840 rxdesc->callback_param = host;
842 /* Submit and fire RX and TX with TX last so we're ready to read! */
843 cookie = rxdesc->tx_submit(rxdesc);
844 if (dma_submit_error(cookie))
846 cookie = txdesc->tx_submit(txdesc);
847 if (dma_submit_error(cookie))
849 rxchan->device->device_issue_pending(rxchan);
850 txchan->device->device_issue_pending(txchan);
855 spi_writel(as, IDR, SPI_BIT(OVRES));
856 atmel_spi_stop_dma(host);
861 static void atmel_spi_next_xfer_data(struct spi_controller *host,
862 struct spi_transfer *xfer,
867 *rx_dma = xfer->rx_dma + xfer->len - *plen;
868 *tx_dma = xfer->tx_dma + xfer->len - *plen;
869 if (*plen > host->max_dma_len)
870 *plen = host->max_dma_len;
873 static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
874 struct spi_device *spi,
875 struct spi_transfer *xfer)
878 unsigned long bus_hz;
881 if (spi_get_csgpiod(spi, 0))
882 chip_select = as->native_cs_for_gpio;
884 chip_select = spi_get_chipselect(spi, 0);
886 /* v1 chips start out at half the peripheral bus speed. */
887 bus_hz = as->spi_clk;
888 if (!atmel_spi_is_v2(as))
892 * Calculate the lowest divider that satisfies the
893 * constraint, assuming div32/fdiv/mbz == 0.
895 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
898 * If the resulting divider doesn't fit into the
899 * register bitfield, we can't satisfy the constraint.
901 if (scbr >= (1 << SPI_SCBR_SIZE)) {
903 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
904 xfer->speed_hz, scbr, bus_hz/255);
909 "setup: %d Hz too high, scbr %u; max %ld Hz\n",
910 xfer->speed_hz, scbr, bus_hz);
913 csr = spi_readl(as, CSR0 + 4 * chip_select);
914 csr = SPI_BFINS(SCBR, scbr, csr);
915 spi_writel(as, CSR0 + 4 * chip_select, csr);
916 xfer->effective_speed_hz = bus_hz / scbr;
922 * Submit next transfer for PDC.
923 * lock is held, spi irq is blocked
925 static void atmel_spi_pdc_next_xfer(struct spi_controller *host,
926 struct spi_transfer *xfer)
928 struct atmel_spi *as = spi_controller_get_devdata(host);
930 dma_addr_t tx_dma, rx_dma;
932 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
934 len = as->current_remaining_bytes;
935 atmel_spi_next_xfer_data(host, xfer, &tx_dma, &rx_dma, &len);
936 as->current_remaining_bytes -= len;
938 spi_writel(as, RPR, rx_dma);
939 spi_writel(as, TPR, tx_dma);
941 if (xfer->bits_per_word > 8)
943 spi_writel(as, RCR, len);
944 spi_writel(as, TCR, len);
947 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
948 xfer, xfer->len, xfer->tx_buf,
949 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
950 (unsigned long long)xfer->rx_dma);
952 if (as->current_remaining_bytes) {
953 len = as->current_remaining_bytes;
954 atmel_spi_next_xfer_data(host, xfer, &tx_dma, &rx_dma, &len);
955 as->current_remaining_bytes -= len;
957 spi_writel(as, RNPR, rx_dma);
958 spi_writel(as, TNPR, tx_dma);
960 if (xfer->bits_per_word > 8)
962 spi_writel(as, RNCR, len);
963 spi_writel(as, TNCR, len);
966 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
967 xfer, xfer->len, xfer->tx_buf,
968 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
969 (unsigned long long)xfer->rx_dma);
972 /* REVISIT: We're waiting for RXBUFF before we start the next
973 * transfer because we need to handle some difficult timing
974 * issues otherwise. If we wait for TXBUFE in one transfer and
975 * then starts waiting for RXBUFF in the next, it's difficult
976 * to tell the difference between the RXBUFF interrupt we're
977 * actually waiting for and the RXBUFF interrupt of the
980 * It should be doable, though. Just not now...
982 spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));
983 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
987 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
988 * - The buffer is either valid for CPU access, else NULL
989 * - If the buffer is valid, so is its DMA address
991 * This driver manages the dma address unless message->is_dma_mapped.
994 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
996 struct device *dev = &as->pdev->dev;
998 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
1000 /* tx_buf is a const void* where we need a void * for the dma
1002 void *nonconst_tx = (void *)xfer->tx_buf;
1004 xfer->tx_dma = dma_map_single(dev,
1005 nonconst_tx, xfer->len,
1007 if (dma_mapping_error(dev, xfer->tx_dma))
1011 xfer->rx_dma = dma_map_single(dev,
1012 xfer->rx_buf, xfer->len,
1014 if (dma_mapping_error(dev, xfer->rx_dma)) {
1016 dma_unmap_single(dev,
1017 xfer->tx_dma, xfer->len,
1025 static void atmel_spi_dma_unmap_xfer(struct spi_controller *host,
1026 struct spi_transfer *xfer)
1028 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
1029 dma_unmap_single(host->dev.parent, xfer->tx_dma,
1030 xfer->len, DMA_TO_DEVICE);
1031 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
1032 dma_unmap_single(host->dev.parent, xfer->rx_dma,
1033 xfer->len, DMA_FROM_DEVICE);
1036 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
1038 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1042 atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer)
1046 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
1048 if (xfer->bits_per_word > 8) {
1049 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
1050 *rxp16 = spi_readl(as, RDR);
1052 rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
1053 *rxp = spi_readl(as, RDR);
1055 if (xfer->bits_per_word > 8) {
1056 if (as->current_remaining_bytes > 2)
1057 as->current_remaining_bytes -= 2;
1059 as->current_remaining_bytes = 0;
1061 as->current_remaining_bytes--;
1066 atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer)
1068 u32 fifolr = spi_readl(as, FLR);
1069 u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr);
1070 u32 offset = xfer->len - as->current_remaining_bytes;
1071 u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset);
1072 u8 *bytes = (u8 *)((u8 *)xfer->rx_buf + offset);
1073 u16 rd; /* RD field is the lowest 16 bits of RDR */
1075 /* Update the number of remaining bytes to transfer */
1076 num_bytes = ((xfer->bits_per_word > 8) ?
1080 if (as->current_remaining_bytes > num_bytes)
1081 as->current_remaining_bytes -= num_bytes;
1083 as->current_remaining_bytes = 0;
1085 /* Handle odd number of bytes when data are more than 8bit width */
1086 if (xfer->bits_per_word > 8)
1087 as->current_remaining_bytes &= ~0x1;
1091 rd = spi_readl(as, RDR);
1092 if (xfer->bits_per_word > 8)
1102 * Must update "current_remaining_bytes" to keep track of data
1106 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
1109 atmel_spi_pump_fifo_data(as, xfer);
1111 atmel_spi_pump_single_data(as, xfer);
1118 atmel_spi_pio_interrupt(int irq, void *dev_id)
1120 struct spi_controller *host = dev_id;
1121 struct atmel_spi *as = spi_controller_get_devdata(host);
1122 u32 status, pending, imr;
1123 struct spi_transfer *xfer;
1126 imr = spi_readl(as, IMR);
1127 status = spi_readl(as, SR);
1128 pending = status & imr;
1130 if (pending & SPI_BIT(OVRES)) {
1132 spi_writel(as, IDR, SPI_BIT(OVRES));
1133 dev_warn(host->dev.parent, "overrun\n");
1136 * When we get an overrun, we disregard the current
1137 * transfer. Data will not be copied back from any
1138 * bounce buffer and msg->actual_len will not be
1139 * updated with the last xfer.
1141 * We will also not process any remaning transfers in
1144 as->done_status = -EIO;
1147 /* Clear any overrun happening while cleaning up */
1150 complete(&as->xfer_completion);
1152 } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) {
1155 if (as->current_remaining_bytes) {
1157 xfer = as->current_transfer;
1158 atmel_spi_pump_pio_data(as, xfer);
1159 if (!as->current_remaining_bytes)
1160 spi_writel(as, IDR, pending);
1162 complete(&as->xfer_completion);
1165 atmel_spi_unlock(as);
1167 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
1169 spi_writel(as, IDR, pending);
1176 atmel_spi_pdc_interrupt(int irq, void *dev_id)
1178 struct spi_controller *host = dev_id;
1179 struct atmel_spi *as = spi_controller_get_devdata(host);
1180 u32 status, pending, imr;
1183 imr = spi_readl(as, IMR);
1184 status = spi_readl(as, SR);
1185 pending = status & imr;
1187 if (pending & SPI_BIT(OVRES)) {
1191 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
1194 /* Clear any overrun happening while cleaning up */
1197 as->done_status = -EIO;
1199 complete(&as->xfer_completion);
1201 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
1204 spi_writel(as, IDR, pending);
1206 complete(&as->xfer_completion);
1212 static int atmel_word_delay_csr(struct spi_device *spi, struct atmel_spi *as)
1214 struct spi_delay *delay = &spi->word_delay;
1215 u32 value = delay->value;
1217 switch (delay->unit) {
1218 case SPI_DELAY_UNIT_NSECS:
1221 case SPI_DELAY_UNIT_USECS:
1227 return (as->spi_clk / 1000000 * value) >> 5;
1230 static void initialize_native_cs_for_gpio(struct atmel_spi *as)
1233 struct spi_controller *host = platform_get_drvdata(as->pdev);
1235 if (!as->native_cs_free)
1236 return; /* already initialized */
1238 if (!host->cs_gpiods)
1239 return; /* No CS GPIO */
1242 * On the first version of the controller (AT91RM9200), CS0
1243 * can't be used associated with GPIO
1245 if (atmel_spi_is_v2(as))
1251 if (host->cs_gpiods[i])
1252 as->native_cs_free |= BIT(i);
1254 if (as->native_cs_free)
1255 as->native_cs_for_gpio = ffs(as->native_cs_free);
1258 static int atmel_spi_setup(struct spi_device *spi)
1260 struct atmel_spi *as;
1261 struct atmel_spi_device *asd;
1263 unsigned int bits = spi->bits_per_word;
1267 as = spi_controller_get_devdata(spi->controller);
1269 /* see notes above re chipselect */
1270 if (!spi_get_csgpiod(spi, 0) && (spi->mode & SPI_CS_HIGH)) {
1271 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
1275 /* Setup() is called during spi_register_controller(aka
1276 * spi_register_master) but after all membmers of the cs_gpiod
1277 * array have been filled, so we can looked for which native
1278 * CS will be free for using with GPIO
1280 initialize_native_cs_for_gpio(as);
1282 if (spi_get_csgpiod(spi, 0) && as->native_cs_free) {
1284 "No native CS available to support this GPIO CS\n");
1288 if (spi_get_csgpiod(spi, 0))
1289 chip_select = as->native_cs_for_gpio;
1291 chip_select = spi_get_chipselect(spi, 0);
1293 csr = SPI_BF(BITS, bits - 8);
1294 if (spi->mode & SPI_CPOL)
1295 csr |= SPI_BIT(CPOL);
1296 if (!(spi->mode & SPI_CPHA))
1297 csr |= SPI_BIT(NCPHA);
1299 if (!spi_get_csgpiod(spi, 0))
1300 csr |= SPI_BIT(CSAAT);
1301 csr |= SPI_BF(DLYBS, 0);
1303 word_delay_csr = atmel_word_delay_csr(spi, as);
1304 if (word_delay_csr < 0)
1305 return word_delay_csr;
1307 /* DLYBCT adds delays between words. This is useful for slow devices
1308 * that need a bit of time to setup the next transfer.
1310 csr |= SPI_BF(DLYBCT, word_delay_csr);
1312 asd = spi->controller_state;
1314 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1318 spi->controller_state = asd;
1324 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1325 bits, spi->mode, spi_get_chipselect(spi, 0), csr);
1327 if (!atmel_spi_is_v2(as))
1328 spi_writel(as, CSR0 + 4 * chip_select, csr);
1333 static void atmel_spi_set_cs(struct spi_device *spi, bool enable)
1335 struct atmel_spi *as = spi_controller_get_devdata(spi->controller);
1336 /* the core doesn't really pass us enable/disable, but CS HIGH vs CS LOW
1337 * since we already have routines for activate/deactivate translate
1338 * high/low to active/inactive
1340 enable = (!!(spi->mode & SPI_CS_HIGH) == enable);
1343 cs_activate(as, spi);
1345 cs_deactivate(as, spi);
1350 static int atmel_spi_one_transfer(struct spi_controller *host,
1351 struct spi_device *spi,
1352 struct spi_transfer *xfer)
1354 struct atmel_spi *as;
1357 struct atmel_spi_device *asd;
1360 unsigned int dma_timeout;
1363 as = spi_controller_get_devdata(host);
1365 asd = spi->controller_state;
1366 bits = (asd->csr >> 4) & 0xf;
1367 if (bits != xfer->bits_per_word - 8) {
1369 "you can't yet change bits_per_word in transfers\n");
1370 return -ENOPROTOOPT;
1374 * DMA map early, for performance (empties dcache ASAP) and
1375 * better fault reporting.
1377 if ((!host->cur_msg->is_dma_mapped)
1379 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1383 atmel_spi_set_xfer_speed(as, spi, xfer);
1385 as->done_status = 0;
1386 as->current_transfer = xfer;
1387 as->current_remaining_bytes = xfer->len;
1388 while (as->current_remaining_bytes) {
1389 reinit_completion(&as->xfer_completion);
1393 atmel_spi_pdc_next_xfer(host, xfer);
1394 atmel_spi_unlock(as);
1395 } else if (atmel_spi_use_dma(as, xfer)) {
1396 len = as->current_remaining_bytes;
1397 ret = atmel_spi_next_xfer_dma_submit(host,
1401 "unable to use DMA, fallback to PIO\n");
1402 as->done_status = ret;
1405 as->current_remaining_bytes -= len;
1406 if (as->current_remaining_bytes < 0)
1407 as->current_remaining_bytes = 0;
1411 atmel_spi_next_xfer_pio(host, xfer);
1412 atmel_spi_unlock(as);
1415 dma_timeout = msecs_to_jiffies(spi_controller_xfer_timeout(host, xfer));
1416 ret_timeout = wait_for_completion_timeout(&as->xfer_completion, dma_timeout);
1418 dev_err(&spi->dev, "spi transfer timeout\n");
1419 as->done_status = -EIO;
1422 if (as->done_status)
1426 if (as->done_status) {
1428 dev_warn(host->dev.parent,
1429 "overrun (%u/%u remaining)\n",
1430 spi_readl(as, TCR), spi_readl(as, RCR));
1433 * Clean up DMA registers and make sure the data
1434 * registers are empty.
1436 spi_writel(as, RNCR, 0);
1437 spi_writel(as, TNCR, 0);
1438 spi_writel(as, RCR, 0);
1439 spi_writel(as, TCR, 0);
1440 for (timeout = 1000; timeout; timeout--)
1441 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1444 dev_warn(host->dev.parent,
1445 "timeout waiting for TXEMPTY");
1446 while (spi_readl(as, SR) & SPI_BIT(RDRF))
1449 /* Clear any overrun happening while cleaning up */
1452 } else if (atmel_spi_use_dma(as, xfer)) {
1453 atmel_spi_stop_dma(host);
1457 if (!host->cur_msg->is_dma_mapped
1459 atmel_spi_dma_unmap_xfer(host, xfer);
1462 atmel_spi_disable_pdc_transfer(as);
1464 return as->done_status;
1467 static void atmel_spi_cleanup(struct spi_device *spi)
1469 struct atmel_spi_device *asd = spi->controller_state;
1474 spi->controller_state = NULL;
1478 static inline unsigned int atmel_get_version(struct atmel_spi *as)
1480 return spi_readl(as, VERSION) & 0x00000fff;
1483 static void atmel_get_caps(struct atmel_spi *as)
1485 unsigned int version;
1487 version = atmel_get_version(as);
1489 as->caps.is_spi2 = version > 0x121;
1490 as->caps.has_wdrbt = version >= 0x210;
1491 as->caps.has_dma_support = version >= 0x212;
1492 as->caps.has_pdc_support = version < 0x212;
1495 static void atmel_spi_init(struct atmel_spi *as)
1497 spi_writel(as, CR, SPI_BIT(SWRST));
1498 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1500 /* It is recommended to enable FIFOs first thing after reset */
1502 spi_writel(as, CR, SPI_BIT(FIFOEN));
1504 if (as->caps.has_wdrbt) {
1505 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1508 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1512 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1513 spi_writel(as, CR, SPI_BIT(SPIEN));
1516 static int atmel_spi_probe(struct platform_device *pdev)
1518 struct resource *regs;
1522 struct spi_controller *host;
1523 struct atmel_spi *as;
1525 /* Select default pin state */
1526 pinctrl_pm_select_default_state(&pdev->dev);
1528 irq = platform_get_irq(pdev, 0);
1532 clk = devm_clk_get(&pdev->dev, "spi_clk");
1534 return PTR_ERR(clk);
1536 /* setup spi core then atmel-specific driver state */
1537 host = spi_alloc_host(&pdev->dev, sizeof(*as));
1541 /* the spi->mode bits understood by this driver: */
1542 host->use_gpio_descriptors = true;
1543 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1544 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
1545 host->dev.of_node = pdev->dev.of_node;
1546 host->bus_num = pdev->id;
1547 host->num_chipselect = 4;
1548 host->setup = atmel_spi_setup;
1549 host->flags = (SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX |
1550 SPI_CONTROLLER_GPIO_SS);
1551 host->transfer_one = atmel_spi_one_transfer;
1552 host->set_cs = atmel_spi_set_cs;
1553 host->cleanup = atmel_spi_cleanup;
1554 host->auto_runtime_pm = true;
1555 host->max_dma_len = SPI_MAX_DMA_XFER;
1556 host->can_dma = atmel_spi_can_dma;
1557 platform_set_drvdata(pdev, host);
1559 as = spi_controller_get_devdata(host);
1561 spin_lock_init(&as->lock);
1564 as->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
1565 if (IS_ERR(as->regs)) {
1566 ret = PTR_ERR(as->regs);
1567 goto out_unmap_regs;
1569 as->phybase = regs->start;
1573 init_completion(&as->xfer_completion);
1577 as->use_dma = false;
1578 as->use_pdc = false;
1579 if (as->caps.has_dma_support) {
1580 ret = atmel_spi_configure_dma(host, as);
1583 } else if (ret == -EPROBE_DEFER) {
1584 goto out_unmap_regs;
1586 } else if (as->caps.has_pdc_support) {
1590 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
1591 as->addr_rx_bbuf = dma_alloc_coherent(&pdev->dev,
1593 &as->dma_addr_rx_bbuf,
1594 GFP_KERNEL | GFP_DMA);
1595 if (!as->addr_rx_bbuf) {
1596 as->use_dma = false;
1598 as->addr_tx_bbuf = dma_alloc_coherent(&pdev->dev,
1600 &as->dma_addr_tx_bbuf,
1601 GFP_KERNEL | GFP_DMA);
1602 if (!as->addr_tx_bbuf) {
1603 as->use_dma = false;
1604 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1606 as->dma_addr_rx_bbuf);
1610 dev_info(host->dev.parent,
1611 " can not allocate dma coherent memory\n");
1614 if (as->caps.has_dma_support && !as->use_dma)
1615 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1618 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1619 0, dev_name(&pdev->dev), host);
1621 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1622 0, dev_name(&pdev->dev), host);
1625 goto out_unmap_regs;
1627 /* Initialize the hardware */
1628 ret = clk_prepare_enable(clk);
1632 as->spi_clk = clk_get_rate(clk);
1635 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
1637 dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size);
1642 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1643 pm_runtime_use_autosuspend(&pdev->dev);
1644 pm_runtime_set_active(&pdev->dev);
1645 pm_runtime_enable(&pdev->dev);
1647 ret = devm_spi_register_controller(&pdev->dev, host);
1652 dev_info(&pdev->dev, "Atmel SPI Controller version 0x%x at 0x%08lx (irq %d)\n",
1653 atmel_get_version(as), (unsigned long)regs->start,
1659 pm_runtime_disable(&pdev->dev);
1660 pm_runtime_set_suspended(&pdev->dev);
1663 atmel_spi_release_dma(host);
1665 spi_writel(as, CR, SPI_BIT(SWRST));
1666 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1667 clk_disable_unprepare(clk);
1670 spi_controller_put(host);
1674 static void atmel_spi_remove(struct platform_device *pdev)
1676 struct spi_controller *host = platform_get_drvdata(pdev);
1677 struct atmel_spi *as = spi_controller_get_devdata(host);
1679 pm_runtime_get_sync(&pdev->dev);
1681 /* reset the hardware and block queue progress */
1683 atmel_spi_stop_dma(host);
1684 atmel_spi_release_dma(host);
1685 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
1686 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1688 as->dma_addr_tx_bbuf);
1689 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1691 as->dma_addr_rx_bbuf);
1695 spin_lock_irq(&as->lock);
1696 spi_writel(as, CR, SPI_BIT(SWRST));
1697 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1699 spin_unlock_irq(&as->lock);
1701 clk_disable_unprepare(as->clk);
1703 pm_runtime_put_noidle(&pdev->dev);
1704 pm_runtime_disable(&pdev->dev);
1707 static int atmel_spi_runtime_suspend(struct device *dev)
1709 struct spi_controller *host = dev_get_drvdata(dev);
1710 struct atmel_spi *as = spi_controller_get_devdata(host);
1712 clk_disable_unprepare(as->clk);
1713 pinctrl_pm_select_sleep_state(dev);
1718 static int atmel_spi_runtime_resume(struct device *dev)
1720 struct spi_controller *host = dev_get_drvdata(dev);
1721 struct atmel_spi *as = spi_controller_get_devdata(host);
1723 pinctrl_pm_select_default_state(dev);
1725 return clk_prepare_enable(as->clk);
1728 static int atmel_spi_suspend(struct device *dev)
1730 struct spi_controller *host = dev_get_drvdata(dev);
1733 /* Stop the queue running */
1734 ret = spi_controller_suspend(host);
1738 if (!pm_runtime_suspended(dev))
1739 atmel_spi_runtime_suspend(dev);
1744 static int atmel_spi_resume(struct device *dev)
1746 struct spi_controller *host = dev_get_drvdata(dev);
1747 struct atmel_spi *as = spi_controller_get_devdata(host);
1750 ret = clk_prepare_enable(as->clk);
1756 clk_disable_unprepare(as->clk);
1758 if (!pm_runtime_suspended(dev)) {
1759 ret = atmel_spi_runtime_resume(dev);
1764 /* Start the queue running */
1765 return spi_controller_resume(host);
1768 static const struct dev_pm_ops atmel_spi_pm_ops = {
1769 SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume)
1770 RUNTIME_PM_OPS(atmel_spi_runtime_suspend,
1771 atmel_spi_runtime_resume, NULL)
1774 static const struct of_device_id atmel_spi_dt_ids[] = {
1775 { .compatible = "atmel,at91rm9200-spi" },
1779 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1781 static struct platform_driver atmel_spi_driver = {
1783 .name = "atmel_spi",
1784 .pm = pm_ptr(&atmel_spi_pm_ops),
1785 .of_match_table = atmel_spi_dt_ids,
1787 .probe = atmel_spi_probe,
1788 .remove_new = atmel_spi_remove,
1790 module_platform_driver(atmel_spi_driver);
1792 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1793 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1794 MODULE_LICENSE("GPL");
1795 MODULE_ALIAS("platform:atmel_spi");