drivers/spi/spi-atmel.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for Atmel AT32 and AT91 SPI Controllers
   4  *
   5  * Copyright (C) 2006 Atmel Corporation
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/clk.h>
  10 #include <linux/module.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/delay.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/err.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/spi/spi.h>
  18 #include <linux/slab.h>
  19 #include <linux/platform_data/dma-atmel.h>
  20 #include <linux/of.h>
  21
  22 #include <linux/io.h>
  23 #include <linux/gpio/consumer.h>
  24 #include <linux/pinctrl/consumer.h>
  25 #include <linux/pm_runtime.h>
  26 #include <trace/events/spi.h>
  27
  28 /* SPI register offsets */
  29 #define SPI_CR                                  0x0000
  30 #define SPI_MR                                  0x0004
  31 #define SPI_RDR                                 0x0008
  32 #define SPI_TDR                                 0x000c
  33 #define SPI_SR                                  0x0010
  34 #define SPI_IER                                 0x0014
  35 #define SPI_IDR                                 0x0018
  36 #define SPI_IMR                                 0x001c
  37 #define SPI_CSR0                                0x0030
  38 #define SPI_CSR1                                0x0034
  39 #define SPI_CSR2                                0x0038
  40 #define SPI_CSR3                                0x003c
  41 #define SPI_FMR                                 0x0040
  42 #define SPI_FLR                                 0x0044
  43 #define SPI_VERSION                             0x00fc
  44 #define SPI_RPR                                 0x0100
  45 #define SPI_RCR                                 0x0104
  46 #define SPI_TPR                                 0x0108
  47 #define SPI_TCR                                 0x010c
  48 #define SPI_RNPR                                0x0110
  49 #define SPI_RNCR                                0x0114
  50 #define SPI_TNPR                                0x0118
  51 #define SPI_TNCR                                0x011c
  52 #define SPI_PTCR                                0x0120
  53 #define SPI_PTSR                                0x0124
  54
  55 /* Bitfields in CR */
  56 #define SPI_SPIEN_OFFSET                        0
  57 #define SPI_SPIEN_SIZE                          1
  58 #define SPI_SPIDIS_OFFSET                       1
  59 #define SPI_SPIDIS_SIZE                         1
  60 #define SPI_SWRST_OFFSET                        7
  61 #define SPI_SWRST_SIZE                          1
  62 #define SPI_LASTXFER_OFFSET                     24
  63 #define SPI_LASTXFER_SIZE                       1
  64 #define SPI_TXFCLR_OFFSET                       16
  65 #define SPI_TXFCLR_SIZE                         1
  66 #define SPI_RXFCLR_OFFSET                       17
  67 #define SPI_RXFCLR_SIZE                         1
  68 #define SPI_FIFOEN_OFFSET                       30
  69 #define SPI_FIFOEN_SIZE                         1
  70 #define SPI_FIFODIS_OFFSET                      31
  71 #define SPI_FIFODIS_SIZE                        1
  72
  73 /* Bitfields in MR */
  74 #define SPI_MSTR_OFFSET                         0
  75 #define SPI_MSTR_SIZE                           1
  76 #define SPI_PS_OFFSET                           1
  77 #define SPI_PS_SIZE                             1
  78 #define SPI_PCSDEC_OFFSET                       2
  79 #define SPI_PCSDEC_SIZE                         1
  80 #define SPI_FDIV_OFFSET                         3
  81 #define SPI_FDIV_SIZE                           1
  82 #define SPI_MODFDIS_OFFSET                      4
  83 #define SPI_MODFDIS_SIZE                        1
  84 #define SPI_WDRBT_OFFSET                        5
  85 #define SPI_WDRBT_SIZE                          1
  86 #define SPI_LLB_OFFSET                          7
  87 #define SPI_LLB_SIZE                            1
  88 #define SPI_PCS_OFFSET                          16
  89 #define SPI_PCS_SIZE                            4
  90 #define SPI_DLYBCS_OFFSET                       24
  91 #define SPI_DLYBCS_SIZE                         8
  92
  93 /* Bitfields in RDR */
  94 #define SPI_RD_OFFSET                           0
  95 #define SPI_RD_SIZE                             16
  96
  97 /* Bitfields in TDR */
  98 #define SPI_TD_OFFSET                           0
  99 #define SPI_TD_SIZE                             16
 100
 101 /* Bitfields in SR */
 102 #define SPI_RDRF_OFFSET                         0
 103 #define SPI_RDRF_SIZE                           1
 104 #define SPI_TDRE_OFFSET                         1
 105 #define SPI_TDRE_SIZE                           1
 106 #define SPI_MODF_OFFSET                         2
 107 #define SPI_MODF_SIZE                           1
 108 #define SPI_OVRES_OFFSET                        3
 109 #define SPI_OVRES_SIZE                          1
 110 #define SPI_ENDRX_OFFSET                        4
 111 #define SPI_ENDRX_SIZE                          1
 112 #define SPI_ENDTX_OFFSET                        5
 113 #define SPI_ENDTX_SIZE                          1
 114 #define SPI_RXBUFF_OFFSET                       6
 115 #define SPI_RXBUFF_SIZE                         1
 116 #define SPI_TXBUFE_OFFSET                       7
 117 #define SPI_TXBUFE_SIZE                         1
 118 #define SPI_NSSR_OFFSET                         8
 119 #define SPI_NSSR_SIZE                           1
 120 #define SPI_TXEMPTY_OFFSET                      9
 121 #define SPI_TXEMPTY_SIZE                        1
 122 #define SPI_SPIENS_OFFSET                       16
 123 #define SPI_SPIENS_SIZE                         1
 124 #define SPI_TXFEF_OFFSET                        24
 125 #define SPI_TXFEF_SIZE                          1
 126 #define SPI_TXFFF_OFFSET                        25
 127 #define SPI_TXFFF_SIZE                          1
 128 #define SPI_TXFTHF_OFFSET                       26
 129 #define SPI_TXFTHF_SIZE                         1
 130 #define SPI_RXFEF_OFFSET                        27
 131 #define SPI_RXFEF_SIZE                          1
 132 #define SPI_RXFFF_OFFSET                        28
 133 #define SPI_RXFFF_SIZE                          1
 134 #define SPI_RXFTHF_OFFSET                       29
 135 #define SPI_RXFTHF_SIZE                         1
 136 #define SPI_TXFPTEF_OFFSET                      30
 137 #define SPI_TXFPTEF_SIZE                        1
 138 #define SPI_RXFPTEF_OFFSET                      31
 139 #define SPI_RXFPTEF_SIZE                        1
 140
 141 /* Bitfields in CSR0 */
 142 #define SPI_CPOL_OFFSET                         0
 143 #define SPI_CPOL_SIZE                           1
 144 #define SPI_NCPHA_OFFSET                        1
 145 #define SPI_NCPHA_SIZE                          1
 146 #define SPI_CSAAT_OFFSET                        3
 147 #define SPI_CSAAT_SIZE                          1
 148 #define SPI_BITS_OFFSET                         4
 149 #define SPI_BITS_SIZE                           4
 150 #define SPI_SCBR_OFFSET                         8
 151 #define SPI_SCBR_SIZE                           8
 152 #define SPI_DLYBS_OFFSET                        16
 153 #define SPI_DLYBS_SIZE                          8
 154 #define SPI_DLYBCT_OFFSET                       24
 155 #define SPI_DLYBCT_SIZE                         8
 156
 157 /* Bitfields in RCR */
 158 #define SPI_RXCTR_OFFSET                        0
 159 #define SPI_RXCTR_SIZE                          16
 160
 161 /* Bitfields in TCR */
 162 #define SPI_TXCTR_OFFSET                        0
 163 #define SPI_TXCTR_SIZE                          16
 164
 165 /* Bitfields in RNCR */
 166 #define SPI_RXNCR_OFFSET                        0
 167 #define SPI_RXNCR_SIZE                          16
 168
 169 /* Bitfields in TNCR */
 170 #define SPI_TXNCR_OFFSET                        0
 171 #define SPI_TXNCR_SIZE                          16
 172
 173 /* Bitfields in PTCR */
 174 #define SPI_RXTEN_OFFSET                        0
 175 #define SPI_RXTEN_SIZE                          1
 176 #define SPI_RXTDIS_OFFSET                       1
 177 #define SPI_RXTDIS_SIZE                         1
 178 #define SPI_TXTEN_OFFSET                        8
 179 #define SPI_TXTEN_SIZE                          1
 180 #define SPI_TXTDIS_OFFSET                       9
 181 #define SPI_TXTDIS_SIZE                         1
 182
 183 /* Bitfields in FMR */
 184 #define SPI_TXRDYM_OFFSET                       0
 185 #define SPI_TXRDYM_SIZE                         2
 186 #define SPI_RXRDYM_OFFSET                       4
 187 #define SPI_RXRDYM_SIZE                         2
 188 #define SPI_TXFTHRES_OFFSET                     16
 189 #define SPI_TXFTHRES_SIZE                       6
 190 #define SPI_RXFTHRES_OFFSET                     24
 191 #define SPI_RXFTHRES_SIZE                       6
 192
 193 /* Bitfields in FLR */
 194 #define SPI_TXFL_OFFSET                         0
 195 #define SPI_TXFL_SIZE                           6
 196 #define SPI_RXFL_OFFSET                         16
 197 #define SPI_RXFL_SIZE                           6
 198
 199 /* Constants for BITS */
 200 #define SPI_BITS_8_BPT                          0
 201 #define SPI_BITS_9_BPT                          1
 202 #define SPI_BITS_10_BPT                         2
 203 #define SPI_BITS_11_BPT                         3
 204 #define SPI_BITS_12_BPT                         4
 205 #define SPI_BITS_13_BPT                         5
 206 #define SPI_BITS_14_BPT                         6
 207 #define SPI_BITS_15_BPT                         7
 208 #define SPI_BITS_16_BPT                         8
 209 #define SPI_ONE_DATA                            0
 210 #define SPI_TWO_DATA                            1
 211 #define SPI_FOUR_DATA                           2
 212
 213 /* Bit manipulation macros */
 214 #define SPI_BIT(name) \
 215         (1 << SPI_##name##_OFFSET)
 216 #define SPI_BF(name, value) \
 217         (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
 218 #define SPI_BFEXT(name, value) \
 219         (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
 220 #define SPI_BFINS(name, value, old) \
 221         (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
 222           | SPI_BF(name, value))
 223
 224 /* Register access macros */
 225 #define spi_readl(port, reg) \
 226         readl_relaxed((port)->regs + SPI_##reg)
 227 #define spi_writel(port, reg, value) \
 228         writel_relaxed((value), (port)->regs + SPI_##reg)
 229 #define spi_writew(port, reg, value) \
 230         writew_relaxed((value), (port)->regs + SPI_##reg)
 231
 232 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 233  * cache operations; better heuristics consider wordsize and bitrate.
 234  */
 235 #define DMA_MIN_BYTES   16
 236
 237 #define SPI_DMA_TIMEOUT         (msecs_to_jiffies(1000))
 238
 239 #define AUTOSUSPEND_TIMEOUT     2000
 240
 241 struct atmel_spi_caps {
 242         bool    is_spi2;
 243         bool    has_wdrbt;
 244         bool    has_dma_support;
 245         bool    has_pdc_support;
 246 };
 247
 248 /*
 249  * The core SPI transfer engine just talks to a register bank to set up
 250  * DMA transfers; transfer queue progress is driven by IRQs.  The clock
 251  * framework provides the base clock, subdivided for each spi_device.
 252  */
 253 struct atmel_spi {
 254         spinlock_t              lock;
 255         unsigned long           flags;
 256
 257         phys_addr_t             phybase;
 258         void __iomem            *regs;
 259         int                     irq;
 260         struct clk              *clk;
 261         struct platform_device  *pdev;
 262         unsigned long           spi_clk;
 263
 264         struct spi_transfer     *current_transfer;
 265         int                     current_remaining_bytes;
 266         int                     done_status;
 267         dma_addr_t              dma_addr_rx_bbuf;
 268         dma_addr_t              dma_addr_tx_bbuf;
 269         void                    *addr_rx_bbuf;
 270         void                    *addr_tx_bbuf;
 271
 272         struct completion       xfer_completion;
 273
 274         struct atmel_spi_caps   caps;
 275
 276         bool                    use_dma;
 277         bool                    use_pdc;
 278
 279         bool                    keep_cs;
 280
 281         u32                     fifo_size;
 282         u8                      native_cs_free;
 283         u8                      native_cs_for_gpio;
 284 };
 285
 286 /* Controller-specific per-slave state */
 287 struct atmel_spi_device {
 288         u32                     csr;
 289 };
 290
 291 #define SPI_MAX_DMA_XFER        65535 /* true for both PDC and DMA */
 292 #define INVALID_DMA_ADDRESS     0xffffffff
 293
 294 /*
 295  * Version 2 of the SPI controller has
 296  *  - CR.LASTXFER
 297  *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
 298  *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
 299  *  - SPI_CSRx.CSAAT
 300  *  - SPI_CSRx.SBCR allows faster clocking
 301  */
 302 static bool atmel_spi_is_v2(struct atmel_spi *as)
 303 {
 304         return as->caps.is_spi2;
 305 }
 306
 307 /*
 308  * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
 309  * they assume that spi slave device state will not change on deselect, so
 310  * that automagic deselection is OK.  ("NPCSx rises if no data is to be
 311  * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
 312  * controllers have CSAAT and friends.
 313  *
 314  * Even controller newer than ar91rm9200, using GPIOs can make sens as
 315  * it lets us support active-high chipselects despite the controller's
 316  * belief that only active-low devices/systems exists.
 317  *
 318  * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
 319  * right when driven with GPIO.  ("Mode Fault does not allow more than one
 320  * Master on Chip Select 0.")  No workaround exists for that ... so for
 321  * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
 322  * and (c) will trigger that first erratum in some cases.
 323  */
 324
 325 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
 326 {
 327         struct atmel_spi_device *asd = spi->controller_state;
 328         int chip_select;
 329         u32 mr;
 330
 331         if (spi->cs_gpiod)
 332                 chip_select = as->native_cs_for_gpio;
 333         else
 334                 chip_select = spi->chip_select;
 335
 336         if (atmel_spi_is_v2(as)) {
 337                 spi_writel(as, CSR0 + 4 * chip_select, asd->csr);
 338                 /* For the low SPI version, there is a issue that PDC transfer
 339                  * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
 340                  */
 341                 spi_writel(as, CSR0, asd->csr);
 342                 if (as->caps.has_wdrbt) {
 343                         spi_writel(as, MR,
 344                                         SPI_BF(PCS, ~(0x01 << chip_select))
 345                                         | SPI_BIT(WDRBT)
 346                                         | SPI_BIT(MODFDIS)
 347                                         | SPI_BIT(MSTR));
 348                 } else {
 349                         spi_writel(as, MR,
 350                                         SPI_BF(PCS, ~(0x01 << chip_select))
 351                                         | SPI_BIT(MODFDIS)
 352                                         | SPI_BIT(MSTR));
 353                 }
 354
 355                 mr = spi_readl(as, MR);
 356                 if (spi->cs_gpiod)
 357                         gpiod_set_value(spi->cs_gpiod, 1);
 358         } else {
 359                 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
 360                 int i;
 361                 u32 csr;
 362
 363                 /* Make sure clock polarity is correct */
 364                 for (i = 0; i < spi->master->num_chipselect; i++) {
 365                         csr = spi_readl(as, CSR0 + 4 * i);
 366                         if ((csr ^ cpol) & SPI_BIT(CPOL))
 367                                 spi_writel(as, CSR0 + 4 * i,
 368                                                 csr ^ SPI_BIT(CPOL));
 369                 }
 370
 371                 mr = spi_readl(as, MR);
 372                 mr = SPI_BFINS(PCS, ~(1 << chip_select), mr);
 373                 if (spi->cs_gpiod)
 374                         gpiod_set_value(spi->cs_gpiod, 1);
 375                 spi_writel(as, MR, mr);
 376         }
 377
 378         dev_dbg(&spi->dev, "activate NPCS, mr %08x\n", mr);
 379 }
 380
 381 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
 382 {
 383         int chip_select;
 384         u32 mr;
 385
 386         if (spi->cs_gpiod)
 387                 chip_select = as->native_cs_for_gpio;
 388         else
 389                 chip_select = spi->chip_select;
 390
 391         /* only deactivate *this* device; sometimes transfers to
 392          * another device may be active when this routine is called.
 393          */
 394         mr = spi_readl(as, MR);
 395         if (~SPI_BFEXT(PCS, mr) & (1 << chip_select)) {
 396                 mr = SPI_BFINS(PCS, 0xf, mr);
 397                 spi_writel(as, MR, mr);
 398         }
 399
 400         dev_dbg(&spi->dev, "DEactivate NPCS, mr %08x\n", mr);
 401
 402         if (!spi->cs_gpiod)
 403                 spi_writel(as, CR, SPI_BIT(LASTXFER));
 404         else
 405                 gpiod_set_value(spi->cs_gpiod, 0);
 406 }
 407
 408 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
 409 {
 410         spin_lock_irqsave(&as->lock, as->flags);
 411 }
 412
 413 static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
 414 {
 415         spin_unlock_irqrestore(&as->lock, as->flags);
 416 }
 417
 418 static inline bool atmel_spi_is_vmalloc_xfer(struct spi_transfer *xfer)
 419 {
 420         return is_vmalloc_addr(xfer->tx_buf) || is_vmalloc_addr(xfer->rx_buf);
 421 }
 422
 423 static inline bool atmel_spi_use_dma(struct atmel_spi *as,
 424                                 struct spi_transfer *xfer)
 425 {
 426         return as->use_dma && xfer->len >= DMA_MIN_BYTES;
 427 }
 428
 429 static bool atmel_spi_can_dma(struct spi_master *master,
 430                               struct spi_device *spi,
 431                               struct spi_transfer *xfer)
 432 {
 433         struct atmel_spi *as = spi_master_get_devdata(master);
 434
 435         if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5))
 436                 return atmel_spi_use_dma(as, xfer) &&
 437                         !atmel_spi_is_vmalloc_xfer(xfer);
 438         else
 439                 return atmel_spi_use_dma(as, xfer);
 440
 441 }
 442
 443 static int atmel_spi_dma_slave_config(struct atmel_spi *as,
 444                                 struct dma_slave_config *slave_config,
 445                                 u8 bits_per_word)
 446 {
 447         struct spi_master *master = platform_get_drvdata(as->pdev);
 448         int err = 0;
 449
 450         if (bits_per_word > 8) {
 451                 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 452                 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 453         } else {
 454                 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 455                 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 456         }
 457
 458         slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
 459         slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
 460         slave_config->src_maxburst = 1;
 461         slave_config->dst_maxburst = 1;
 462         slave_config->device_fc = false;
 463
 464         /*
 465          * This driver uses fixed peripheral select mode (PS bit set to '0' in
 466          * the Mode Register).
 467          * So according to the datasheet, when FIFOs are available (and
 468          * enabled), the Transmit FIFO operates in Multiple Data Mode.
 469          * In this mode, up to 2 data, not 4, can be written into the Transmit
 470          * Data Register in a single access.
 471          * However, the first data has to be written into the lowest 16 bits and
 472          * the second data into the highest 16 bits of the Transmit
 473          * Data Register. For 8bit data (the most frequent case), it would
 474          * require to rework tx_buf so each data would actualy fit 16 bits.
 475          * So we'd rather write only one data at the time. Hence the transmit
 476          * path works the same whether FIFOs are available (and enabled) or not.
 477          */
 478         slave_config->direction = DMA_MEM_TO_DEV;
 479         if (dmaengine_slave_config(master->dma_tx, slave_config)) {
 480                 dev_err(&as->pdev->dev,
 481                         "failed to configure tx dma channel\n");
 482                 err = -EINVAL;
 483         }
 484
 485         /*
 486          * This driver configures the spi controller for master mode (MSTR bit
 487          * set to '1' in the Mode Register).
 488          * So according to the datasheet, when FIFOs are available (and
 489          * enabled), the Receive FIFO operates in Single Data Mode.
 490          * So the receive path works the same whether FIFOs are available (and
 491          * enabled) or not.
 492          */
 493         slave_config->direction = DMA_DEV_TO_MEM;
 494         if (dmaengine_slave_config(master->dma_rx, slave_config)) {
 495                 dev_err(&as->pdev->dev,
 496                         "failed to configure rx dma channel\n");
 497                 err = -EINVAL;
 498         }
 499
 500         return err;
 501 }
 502
 503 static int atmel_spi_configure_dma(struct spi_master *master,
 504                                    struct atmel_spi *as)
 505 {
 506         struct dma_slave_config slave_config;
 507         struct device *dev = &as->pdev->dev;
 508         int err;
 509
 510         dma_cap_mask_t mask;
 511         dma_cap_zero(mask);
 512         dma_cap_set(DMA_SLAVE, mask);
 513
 514         master->dma_tx = dma_request_chan(dev, "tx");
 515         if (IS_ERR(master->dma_tx)) {
 516                 err = PTR_ERR(master->dma_tx);
 517                 if (err == -EPROBE_DEFER) {
 518                         dev_warn(dev, "no DMA channel available at the moment\n");
 519                         goto error_clear;
 520                 }
 521                 dev_err(dev,
 522                         "DMA TX channel not available, SPI unable to use DMA\n");
 523                 err = -EBUSY;
 524                 goto error_clear;
 525         }
 526
 527         /*
 528          * No reason to check EPROBE_DEFER here since we have already requested
 529          * tx channel. If it fails here, it's for another reason.
 530          */
 531         master->dma_rx = dma_request_slave_channel(dev, "rx");
 532
 533         if (!master->dma_rx) {
 534                 dev_err(dev,
 535                         "DMA RX channel not available, SPI unable to use DMA\n");
 536                 err = -EBUSY;
 537                 goto error;
 538         }
 539
 540         err = atmel_spi_dma_slave_config(as, &slave_config, 8);
 541         if (err)
 542                 goto error;
 543
 544         dev_info(&as->pdev->dev,
 545                         "Using %s (tx) and %s (rx) for DMA transfers\n",
 546                         dma_chan_name(master->dma_tx),
 547                         dma_chan_name(master->dma_rx));
 548
 549         return 0;
 550 error:
 551         if (master->dma_rx)
 552                 dma_release_channel(master->dma_rx);
 553         if (!IS_ERR(master->dma_tx))
 554                 dma_release_channel(master->dma_tx);
 555 error_clear:
 556         master->dma_tx = master->dma_rx = NULL;
 557         return err;
 558 }
 559
 560 static void atmel_spi_stop_dma(struct spi_master *master)
 561 {
 562         if (master->dma_rx)
 563                 dmaengine_terminate_all(master->dma_rx);
 564         if (master->dma_tx)
 565                 dmaengine_terminate_all(master->dma_tx);
 566 }
 567
 568 static void atmel_spi_release_dma(struct spi_master *master)
 569 {
 570         if (master->dma_rx) {
 571                 dma_release_channel(master->dma_rx);
 572                 master->dma_rx = NULL;
 573         }
 574         if (master->dma_tx) {
 575                 dma_release_channel(master->dma_tx);
 576                 master->dma_tx = NULL;
 577         }
 578 }
 579
 580 /* This function is called by the DMA driver from tasklet context */
 581 static void dma_callback(void *data)
 582 {
 583         struct spi_master       *master = data;
 584         struct atmel_spi        *as = spi_master_get_devdata(master);
 585
 586         if (is_vmalloc_addr(as->current_transfer->rx_buf) &&
 587             IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
 588                 memcpy(as->current_transfer->rx_buf, as->addr_rx_bbuf,
 589                        as->current_transfer->len);
 590         }
 591         complete(&as->xfer_completion);
 592 }
 593
 594 /*
 595  * Next transfer using PIO without FIFO.
 596  */
 597 static void atmel_spi_next_xfer_single(struct spi_master *master,
 598                                        struct spi_transfer *xfer)
 599 {
 600         struct atmel_spi        *as = spi_master_get_devdata(master);
 601         unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
 602
 603         dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
 604
 605         /* Make sure data is not remaining in RDR */
 606         spi_readl(as, RDR);
 607         while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
 608                 spi_readl(as, RDR);
 609                 cpu_relax();
 610         }
 611
 612         if (xfer->bits_per_word > 8)
 613                 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
 614         else
 615                 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
 616
 617         dev_dbg(master->dev.parent,
 618                 "  start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
 619                 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
 620                 xfer->bits_per_word);
 621
 622         /* Enable relevant interrupts */
 623         spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
 624 }
 625
 626 /*
 627  * Next transfer using PIO with FIFO.
 628  */
 629 static void atmel_spi_next_xfer_fifo(struct spi_master *master,
 630                                      struct spi_transfer *xfer)
 631 {
 632         struct atmel_spi *as = spi_master_get_devdata(master);
 633         u32 current_remaining_data, num_data;
 634         u32 offset = xfer->len - as->current_remaining_bytes;
 635         const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset);
 636         const u8  *bytes = (const u8  *)((u8 *)xfer->tx_buf + offset);
 637         u16 td0, td1;
 638         u32 fifomr;
 639
 640         dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_fifo\n");
 641
 642         /* Compute the number of data to transfer in the current iteration */
 643         current_remaining_data = ((xfer->bits_per_word > 8) ?
 644                                   ((u32)as->current_remaining_bytes >> 1) :
 645                                   (u32)as->current_remaining_bytes);
 646         num_data = min(current_remaining_data, as->fifo_size);
 647
 648         /* Flush RX and TX FIFOs */
 649         spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR));
 650         while (spi_readl(as, FLR))
 651                 cpu_relax();
 652
 653         /* Set RX FIFO Threshold to the number of data to transfer */
 654         fifomr = spi_readl(as, FMR);
 655         spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr));
 656
 657         /* Clear FIFO flags in the Status Register, especially RXFTHF */
 658         (void)spi_readl(as, SR);
 659
 660         /* Fill TX FIFO */
 661         while (num_data >= 2) {
 662                 if (xfer->bits_per_word > 8) {
 663                         td0 = *words++;
 664                         td1 = *words++;
 665                 } else {
 666                         td0 = *bytes++;
 667                         td1 = *bytes++;
 668                 }
 669
 670                 spi_writel(as, TDR, (td1 << 16) | td0);
 671                 num_data -= 2;
 672         }
 673
 674         if (num_data) {
 675                 if (xfer->bits_per_word > 8)
 676                         td0 = *words++;
 677                 else
 678                         td0 = *bytes++;
 679
 680                 spi_writew(as, TDR, td0);
 681                 num_data--;
 682         }
 683
 684         dev_dbg(master->dev.parent,
 685                 "  start fifo xfer %p: len %u tx %p rx %p bitpw %d\n",
 686                 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
 687                 xfer->bits_per_word);
 688
 689         /*
 690          * Enable RX FIFO Threshold Flag interrupt to be notified about
 691          * transfer completion.
 692          */
 693         spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES));
 694 }
 695
 696 /*
 697  * Next transfer using PIO.
 698  */
 699 static void atmel_spi_next_xfer_pio(struct spi_master *master,
 700                                     struct spi_transfer *xfer)
 701 {
 702         struct atmel_spi *as = spi_master_get_devdata(master);
 703
 704         if (as->fifo_size)
 705                 atmel_spi_next_xfer_fifo(master, xfer);
 706         else
 707                 atmel_spi_next_xfer_single(master, xfer);
 708 }
 709
 710 /*
 711  * Submit next transfer for DMA.
 712  */
 713 static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
 714                                 struct spi_transfer *xfer,
 715                                 u32 *plen)
 716 {
 717         struct atmel_spi        *as = spi_master_get_devdata(master);
 718         struct dma_chan         *rxchan = master->dma_rx;
 719         struct dma_chan         *txchan = master->dma_tx;
 720         struct dma_async_tx_descriptor *rxdesc;
 721         struct dma_async_tx_descriptor *txdesc;
 722         struct dma_slave_config slave_config;
 723         dma_cookie_t            cookie;
 724
 725         dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
 726
 727         /* Check that the channels are available */
 728         if (!rxchan || !txchan)
 729                 return -ENODEV;
 730
 731         /* release lock for DMA operations */
 732         atmel_spi_unlock(as);
 733
 734         *plen = xfer->len;
 735
 736         if (atmel_spi_dma_slave_config(as, &slave_config,
 737                                        xfer->bits_per_word))
 738                 goto err_exit;
 739
 740         /* Send both scatterlists */
 741         if (atmel_spi_is_vmalloc_xfer(xfer) &&
 742             IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
 743                 rxdesc = dmaengine_prep_slave_single(rxchan,
 744                                                      as->dma_addr_rx_bbuf,
 745                                                      xfer->len,
 746                                                      DMA_DEV_TO_MEM,
 747                                                      DMA_PREP_INTERRUPT |
 748                                                      DMA_CTRL_ACK);
 749         } else {
 750                 rxdesc = dmaengine_prep_slave_sg(rxchan,
 751                                                  xfer->rx_sg.sgl,
 752                                                  xfer->rx_sg.nents,
 753                                                  DMA_DEV_TO_MEM,
 754                                                  DMA_PREP_INTERRUPT |
 755                                                  DMA_CTRL_ACK);
 756         }
 757         if (!rxdesc)
 758                 goto err_dma;
 759
 760         if (atmel_spi_is_vmalloc_xfer(xfer) &&
 761             IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
 762                 memcpy(as->addr_tx_bbuf, xfer->tx_buf, xfer->len);
 763                 txdesc = dmaengine_prep_slave_single(txchan,
 764                                                      as->dma_addr_tx_bbuf,
 765                                                      xfer->len, DMA_MEM_TO_DEV,
 766                                                      DMA_PREP_INTERRUPT |
 767                                                      DMA_CTRL_ACK);
 768         } else {
 769                 txdesc = dmaengine_prep_slave_sg(txchan,
 770                                                  xfer->tx_sg.sgl,
 771                                                  xfer->tx_sg.nents,
 772                                                  DMA_MEM_TO_DEV,
 773                                                  DMA_PREP_INTERRUPT |
 774                                                  DMA_CTRL_ACK);
 775         }
 776         if (!txdesc)
 777                 goto err_dma;
 778
 779         dev_dbg(master->dev.parent,
 780                 "  start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 781                 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
 782                 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
 783
 784         /* Enable relevant interrupts */
 785         spi_writel(as, IER, SPI_BIT(OVRES));
 786
 787         /* Put the callback on the RX transfer only, that should finish last */
 788         rxdesc->callback = dma_callback;
 789         rxdesc->callback_param = master;
 790
 791         /* Submit and fire RX and TX with TX last so we're ready to read! */
 792         cookie = rxdesc->tx_submit(rxdesc);
 793         if (dma_submit_error(cookie))
 794                 goto err_dma;
 795         cookie = txdesc->tx_submit(txdesc);
 796         if (dma_submit_error(cookie))
 797                 goto err_dma;
 798         rxchan->device->device_issue_pending(rxchan);
 799         txchan->device->device_issue_pending(txchan);
 800
 801         /* take back lock */
 802         atmel_spi_lock(as);
 803         return 0;
 804
 805 err_dma:
 806         spi_writel(as, IDR, SPI_BIT(OVRES));
 807         atmel_spi_stop_dma(master);
 808 err_exit:
 809         atmel_spi_lock(as);
 810         return -ENOMEM;
 811 }
 812
 813 static void atmel_spi_next_xfer_data(struct spi_master *master,
 814                                 struct spi_transfer *xfer,
 815                                 dma_addr_t *tx_dma,
 816                                 dma_addr_t *rx_dma,
 817                                 u32 *plen)
 818 {
 819         *rx_dma = xfer->rx_dma + xfer->len - *plen;
 820         *tx_dma = xfer->tx_dma + xfer->len - *plen;
 821         if (*plen > master->max_dma_len)
 822                 *plen = master->max_dma_len;
 823 }
 824
 825 static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
 826                                     struct spi_device *spi,
 827                                     struct spi_transfer *xfer)
 828 {
 829         u32                     scbr, csr;
 830         unsigned long           bus_hz;
 831         int chip_select;
 832
 833         if (spi->cs_gpiod)
 834                 chip_select = as->native_cs_for_gpio;
 835         else
 836                 chip_select = spi->chip_select;
 837
 838         /* v1 chips start out at half the peripheral bus speed. */
 839         bus_hz = as->spi_clk;
 840         if (!atmel_spi_is_v2(as))
 841                 bus_hz /= 2;
 842
 843         /*
 844          * Calculate the lowest divider that satisfies the
 845          * constraint, assuming div32/fdiv/mbz == 0.
 846          */
 847         scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
 848
 849         /*
 850          * If the resulting divider doesn't fit into the
 851          * register bitfield, we can't satisfy the constraint.
 852          */
 853         if (scbr >= (1 << SPI_SCBR_SIZE)) {
 854                 dev_err(&spi->dev,
 855                         "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
 856                         xfer->speed_hz, scbr, bus_hz/255);
 857                 return -EINVAL;
 858         }
 859         if (scbr == 0) {
 860                 dev_err(&spi->dev,
 861                         "setup: %d Hz too high, scbr %u; max %ld Hz\n",
 862                         xfer->speed_hz, scbr, bus_hz);
 863                 return -EINVAL;
 864         }
 865         csr = spi_readl(as, CSR0 + 4 * chip_select);
 866         csr = SPI_BFINS(SCBR, scbr, csr);
 867         spi_writel(as, CSR0 + 4 * chip_select, csr);
 868
 869         return 0;
 870 }
 871
 872 /*
 873  * Submit next transfer for PDC.
 874  * lock is held, spi irq is blocked
 875  */
 876 static void atmel_spi_pdc_next_xfer(struct spi_master *master,
 877                                         struct spi_message *msg,
 878                                         struct spi_transfer *xfer)
 879 {
 880         struct atmel_spi        *as = spi_master_get_devdata(master);
 881         u32                     len;
 882         dma_addr_t              tx_dma, rx_dma;
 883
 884         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 885
 886         len = as->current_remaining_bytes;
 887         atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 888         as->current_remaining_bytes -= len;
 889
 890         spi_writel(as, RPR, rx_dma);
 891         spi_writel(as, TPR, tx_dma);
 892
 893         if (msg->spi->bits_per_word > 8)
 894                 len >>= 1;
 895         spi_writel(as, RCR, len);
 896         spi_writel(as, TCR, len);
 897
 898         dev_dbg(&msg->spi->dev,
 899                 "  start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 900                 xfer, xfer->len, xfer->tx_buf,
 901                 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
 902                 (unsigned long long)xfer->rx_dma);
 903
 904         if (as->current_remaining_bytes) {
 905                 len = as->current_remaining_bytes;
 906                 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 907                 as->current_remaining_bytes -= len;
 908
 909                 spi_writel(as, RNPR, rx_dma);
 910                 spi_writel(as, TNPR, tx_dma);
 911
 912                 if (msg->spi->bits_per_word > 8)
 913                         len >>= 1;
 914                 spi_writel(as, RNCR, len);
 915                 spi_writel(as, TNCR, len);
 916
 917                 dev_dbg(&msg->spi->dev,
 918                         "  next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 919                         xfer, xfer->len, xfer->tx_buf,
 920                         (unsigned long long)xfer->tx_dma, xfer->rx_buf,
 921                         (unsigned long long)xfer->rx_dma);
 922         }
 923
 924         /* REVISIT: We're waiting for RXBUFF before we start the next
 925          * transfer because we need to handle some difficult timing
 926          * issues otherwise. If we wait for TXBUFE in one transfer and
 927          * then starts waiting for RXBUFF in the next, it's difficult
 928          * to tell the difference between the RXBUFF interrupt we're
 929          * actually waiting for and the RXBUFF interrupt of the
 930          * previous transfer.
 931          *
 932          * It should be doable, though. Just not now...
 933          */
 934         spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));
 935         spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
 936 }
 937
 938 /*
 939  * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
 940  *  - The buffer is either valid for CPU access, else NULL
 941  *  - If the buffer is valid, so is its DMA address
 942  *
 943  * This driver manages the dma address unless message->is_dma_mapped.
 944  */
 945 static int
 946 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
 947 {
 948         struct device   *dev = &as->pdev->dev;
 949
 950         xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
 951         if (xfer->tx_buf) {
 952                 /* tx_buf is a const void* where we need a void * for the dma
 953                  * mapping */
 954                 void *nonconst_tx = (void *)xfer->tx_buf;
 955
 956                 xfer->tx_dma = dma_map_single(dev,
 957                                 nonconst_tx, xfer->len,
 958                                 DMA_TO_DEVICE);
 959                 if (dma_mapping_error(dev, xfer->tx_dma))
 960                         return -ENOMEM;
 961         }
 962         if (xfer->rx_buf) {
 963                 xfer->rx_dma = dma_map_single(dev,
 964                                 xfer->rx_buf, xfer->len,
 965                                 DMA_FROM_DEVICE);
 966                 if (dma_mapping_error(dev, xfer->rx_dma)) {
 967                         if (xfer->tx_buf)
 968                                 dma_unmap_single(dev,
 969                                                 xfer->tx_dma, xfer->len,
 970                                                 DMA_TO_DEVICE);
 971                         return -ENOMEM;
 972                 }
 973         }
 974         return 0;
 975 }
 976
 977 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
 978                                      struct spi_transfer *xfer)
 979 {
 980         if (xfer->tx_dma != INVALID_DMA_ADDRESS)
 981                 dma_unmap_single(master->dev.parent, xfer->tx_dma,
 982                                  xfer->len, DMA_TO_DEVICE);
 983         if (xfer->rx_dma != INVALID_DMA_ADDRESS)
 984                 dma_unmap_single(master->dev.parent, xfer->rx_dma,
 985                                  xfer->len, DMA_FROM_DEVICE);
 986 }
 987
 988 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
 989 {
 990         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 991 }
 992
 993 static void
 994 atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer)
 995 {
 996         u8              *rxp;
 997         u16             *rxp16;
 998         unsigned long   xfer_pos = xfer->len - as->current_remaining_bytes;
 999
1000         if (xfer->bits_per_word > 8) {
1001                 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
1002                 *rxp16 = spi_readl(as, RDR);
1003         } else {
1004                 rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
1005                 *rxp = spi_readl(as, RDR);
1006         }
1007         if (xfer->bits_per_word > 8) {
1008                 if (as->current_remaining_bytes > 2)
1009                         as->current_remaining_bytes -= 2;
1010                 else
1011                         as->current_remaining_bytes = 0;
1012         } else {
1013                 as->current_remaining_bytes--;
1014         }
1015 }
1016
1017 static void
1018 atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer)
1019 {
1020         u32 fifolr = spi_readl(as, FLR);
1021         u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr);
1022         u32 offset = xfer->len - as->current_remaining_bytes;
1023         u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset);
1024         u8  *bytes = (u8  *)((u8 *)xfer->rx_buf + offset);
1025         u16 rd; /* RD field is the lowest 16 bits of RDR */
1026
1027         /* Update the number of remaining bytes to transfer */
1028         num_bytes = ((xfer->bits_per_word > 8) ?
1029                      (num_data << 1) :
1030                      num_data);
1031
1032         if (as->current_remaining_bytes > num_bytes)
1033                 as->current_remaining_bytes -= num_bytes;
1034         else
1035                 as->current_remaining_bytes = 0;
1036
1037         /* Handle odd number of bytes when data are more than 8bit width */
1038         if (xfer->bits_per_word > 8)
1039                 as->current_remaining_bytes &= ~0x1;
1040
1041         /* Read data */
1042         while (num_data) {
1043                 rd = spi_readl(as, RDR);
1044                 if (xfer->bits_per_word > 8)
1045                         *words++ = rd;
1046                 else
1047                         *bytes++ = rd;
1048                 num_data--;
1049         }
1050 }
1051
1052 /* Called from IRQ
1053  *
1054  * Must update "current_remaining_bytes" to keep track of data
1055  * to transfer.
1056  */
1057 static void
1058 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
1059 {
1060         if (as->fifo_size)
1061                 atmel_spi_pump_fifo_data(as, xfer);
1062         else
1063                 atmel_spi_pump_single_data(as, xfer);
1064 }
1065
1066 /* Interrupt
1067  *
1068  * No need for locking in this Interrupt handler: done_status is the
1069  * only information modified.
1070  */
1071 static irqreturn_t
1072 atmel_spi_pio_interrupt(int irq, void *dev_id)
1073 {
1074         struct spi_master       *master = dev_id;
1075         struct atmel_spi        *as = spi_master_get_devdata(master);
1076         u32                     status, pending, imr;
1077         struct spi_transfer     *xfer;
1078         int                     ret = IRQ_NONE;
1079
1080         imr = spi_readl(as, IMR);
1081         status = spi_readl(as, SR);
1082         pending = status & imr;
1083
1084         if (pending & SPI_BIT(OVRES)) {
1085                 ret = IRQ_HANDLED;
1086                 spi_writel(as, IDR, SPI_BIT(OVRES));
1087                 dev_warn(master->dev.parent, "overrun\n");
1088
1089                 /*
1090                  * When we get an overrun, we disregard the current
1091                  * transfer. Data will not be copied back from any
1092                  * bounce buffer and msg->actual_len will not be
1093                  * updated with the last xfer.
1094                  *
1095                  * We will also not process any remaning transfers in
1096                  * the message.
1097                  */
1098                 as->done_status = -EIO;
1099                 smp_wmb();
1100
1101                 /* Clear any overrun happening while cleaning up */
1102                 spi_readl(as, SR);
1103
1104                 complete(&as->xfer_completion);
1105
1106         } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) {
1107                 atmel_spi_lock(as);
1108
1109                 if (as->current_remaining_bytes) {
1110                         ret = IRQ_HANDLED;
1111                         xfer = as->current_transfer;
1112                         atmel_spi_pump_pio_data(as, xfer);
1113                         if (!as->current_remaining_bytes)
1114                                 spi_writel(as, IDR, pending);
1115
1116                         complete(&as->xfer_completion);
1117                 }
1118
1119                 atmel_spi_unlock(as);
1120         } else {
1121                 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
1122                 ret = IRQ_HANDLED;
1123                 spi_writel(as, IDR, pending);
1124         }
1125
1126         return ret;
1127 }
1128
1129 static irqreturn_t
1130 atmel_spi_pdc_interrupt(int irq, void *dev_id)
1131 {
1132         struct spi_master       *master = dev_id;
1133         struct atmel_spi        *as = spi_master_get_devdata(master);
1134         u32                     status, pending, imr;
1135         int                     ret = IRQ_NONE;
1136
1137         imr = spi_readl(as, IMR);
1138         status = spi_readl(as, SR);
1139         pending = status & imr;
1140
1141         if (pending & SPI_BIT(OVRES)) {
1142
1143                 ret = IRQ_HANDLED;
1144
1145                 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
1146                                      | SPI_BIT(OVRES)));
1147
1148                 /* Clear any overrun happening while cleaning up */
1149                 spi_readl(as, SR);
1150
1151                 as->done_status = -EIO;
1152
1153                 complete(&as->xfer_completion);
1154
1155         } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
1156                 ret = IRQ_HANDLED;
1157
1158                 spi_writel(as, IDR, pending);
1159
1160                 complete(&as->xfer_completion);
1161         }
1162
1163         return ret;
1164 }
1165
1166 static int atmel_word_delay_csr(struct spi_device *spi, struct atmel_spi *as)
1167 {
1168         struct spi_delay *delay = &spi->word_delay;
1169         u32 value = delay->value;
1170
1171         switch (delay->unit) {
1172         case SPI_DELAY_UNIT_NSECS:
1173                 value /= 1000;
1174                 break;
1175         case SPI_DELAY_UNIT_USECS:
1176                 break;
1177         default:
1178                 return -EINVAL;
1179         }
1180
1181         return (as->spi_clk / 1000000 * value) >> 5;
1182 }
1183
1184 static void initialize_native_cs_for_gpio(struct atmel_spi *as)
1185 {
1186         int i;
1187         struct spi_master *master = platform_get_drvdata(as->pdev);
1188
1189         if (!as->native_cs_free)
1190                 return; /* already initialized */
1191
1192         if (!master->cs_gpiods)
1193                 return; /* No CS GPIO */
1194
1195         /*
1196          * On the first version of the controller (AT91RM9200), CS0
1197          * can't be used associated with GPIO
1198          */
1199         if (atmel_spi_is_v2(as))
1200                 i = 0;
1201         else
1202                 i = 1;
1203
1204         for (; i < 4; i++)
1205                 if (master->cs_gpiods[i])
1206                         as->native_cs_free |= BIT(i);
1207
1208         if (as->native_cs_free)
1209                 as->native_cs_for_gpio = ffs(as->native_cs_free);
1210 }
1211
1212 static int atmel_spi_setup(struct spi_device *spi)
1213 {
1214         struct atmel_spi        *as;
1215         struct atmel_spi_device *asd;
1216         u32                     csr;
1217         unsigned int            bits = spi->bits_per_word;
1218         int chip_select;
1219         int                     word_delay_csr;
1220
1221         as = spi_master_get_devdata(spi->master);
1222
1223         /* see notes above re chipselect */
1224         if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH)) {
1225                 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
1226                 return -EINVAL;
1227         }
1228
1229         /* Setup() is called during spi_register_controller(aka
1230          * spi_register_master) but after all membmers of the cs_gpiod
1231          * array have been filled, so we can looked for which native
1232          * CS will be free for using with GPIO
1233          */
1234         initialize_native_cs_for_gpio(as);
1235
1236         if (spi->cs_gpiod && as->native_cs_free) {
1237                 dev_err(&spi->dev,
1238                         "No native CS available to support this GPIO CS\n");
1239                 return -EBUSY;
1240         }
1241
1242         if (spi->cs_gpiod)
1243                 chip_select = as->native_cs_for_gpio;
1244         else
1245                 chip_select = spi->chip_select;
1246
1247         csr = SPI_BF(BITS, bits - 8);
1248         if (spi->mode & SPI_CPOL)
1249                 csr |= SPI_BIT(CPOL);
1250         if (!(spi->mode & SPI_CPHA))
1251                 csr |= SPI_BIT(NCPHA);
1252
1253         if (!spi->cs_gpiod)
1254                 csr |= SPI_BIT(CSAAT);
1255         csr |= SPI_BF(DLYBS, 0);
1256
1257         word_delay_csr = atmel_word_delay_csr(spi, as);
1258         if (word_delay_csr < 0)
1259                 return word_delay_csr;
1260
1261         /* DLYBCT adds delays between words.  This is useful for slow devices
1262          * that need a bit of time to setup the next transfer.
1263          */
1264         csr |= SPI_BF(DLYBCT, word_delay_csr);
1265
1266         asd = spi->controller_state;
1267         if (!asd) {
1268                 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1269                 if (!asd)
1270                         return -ENOMEM;
1271
1272                 spi->controller_state = asd;
1273         }
1274
1275         asd->csr = csr;
1276
1277         dev_dbg(&spi->dev,
1278                 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1279                 bits, spi->mode, spi->chip_select, csr);
1280
1281         if (!atmel_spi_is_v2(as))
1282                 spi_writel(as, CSR0 + 4 * chip_select, csr);
1283
1284         return 0;
1285 }
1286
1287 static int atmel_spi_one_transfer(struct spi_master *master,
1288                                         struct spi_message *msg,
1289                                         struct spi_transfer *xfer)
1290 {
1291         struct atmel_spi        *as;
1292         struct spi_device       *spi = msg->spi;
1293         u8                      bits;
1294         u32                     len;
1295         struct atmel_spi_device *asd;
1296         int                     timeout;
1297         int                     ret;
1298         unsigned long           dma_timeout;
1299
1300         as = spi_master_get_devdata(master);
1301
1302         if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1303                 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1304                 return -EINVAL;
1305         }
1306
1307         asd = spi->controller_state;
1308         bits = (asd->csr >> 4) & 0xf;
1309         if (bits != xfer->bits_per_word - 8) {
1310                 dev_dbg(&spi->dev,
1311                         "you can't yet change bits_per_word in transfers\n");
1312                 return -ENOPROTOOPT;
1313         }
1314
1315         /*
1316          * DMA map early, for performance (empties dcache ASAP) and
1317          * better fault reporting.
1318          */
1319         if ((!msg->is_dma_mapped)
1320                 && as->use_pdc) {
1321                 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1322                         return -ENOMEM;
1323         }
1324
1325         atmel_spi_set_xfer_speed(as, msg->spi, xfer);
1326
1327         as->done_status = 0;
1328         as->current_transfer = xfer;
1329         as->current_remaining_bytes = xfer->len;
1330         while (as->current_remaining_bytes) {
1331                 reinit_completion(&as->xfer_completion);
1332
1333                 if (as->use_pdc) {
1334                         atmel_spi_pdc_next_xfer(master, msg, xfer);
1335                 } else if (atmel_spi_use_dma(as, xfer)) {
1336                         len = as->current_remaining_bytes;
1337                         ret = atmel_spi_next_xfer_dma_submit(master,
1338                                                                 xfer, &len);
1339                         if (ret) {
1340                                 dev_err(&spi->dev,
1341                                         "unable to use DMA, fallback to PIO\n");
1342                                 atmel_spi_next_xfer_pio(master, xfer);
1343                         } else {
1344                                 as->current_remaining_bytes -= len;
1345                                 if (as->current_remaining_bytes < 0)
1346                                         as->current_remaining_bytes = 0;
1347                         }
1348                 } else {
1349                         atmel_spi_next_xfer_pio(master, xfer);
1350                 }
1351
1352                 /* interrupts are disabled, so free the lock for schedule */
1353                 atmel_spi_unlock(as);
1354                 dma_timeout = wait_for_completion_timeout(&as->xfer_completion,
1355                                                           SPI_DMA_TIMEOUT);
1356                 atmel_spi_lock(as);
1357                 if (WARN_ON(dma_timeout == 0)) {
1358                         dev_err(&spi->dev, "spi transfer timeout\n");
1359                         as->done_status = -EIO;
1360                 }
1361
1362                 if (as->done_status)
1363                         break;
1364         }
1365
1366         if (as->done_status) {
1367                 if (as->use_pdc) {
1368                         dev_warn(master->dev.parent,
1369                                 "overrun (%u/%u remaining)\n",
1370                                 spi_readl(as, TCR), spi_readl(as, RCR));
1371
1372                         /*
1373                          * Clean up DMA registers and make sure the data
1374                          * registers are empty.
1375                          */
1376                         spi_writel(as, RNCR, 0);
1377                         spi_writel(as, TNCR, 0);
1378                         spi_writel(as, RCR, 0);
1379                         spi_writel(as, TCR, 0);
1380                         for (timeout = 1000; timeout; timeout--)
1381                                 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1382                                         break;
1383                         if (!timeout)
1384                                 dev_warn(master->dev.parent,
1385                                          "timeout waiting for TXEMPTY");
1386                         while (spi_readl(as, SR) & SPI_BIT(RDRF))
1387                                 spi_readl(as, RDR);
1388
1389                         /* Clear any overrun happening while cleaning up */
1390                         spi_readl(as, SR);
1391
1392                 } else if (atmel_spi_use_dma(as, xfer)) {
1393                         atmel_spi_stop_dma(master);
1394                 }
1395
1396                 if (!msg->is_dma_mapped
1397                         && as->use_pdc)
1398                         atmel_spi_dma_unmap_xfer(master, xfer);
1399
1400                 return 0;
1401
1402         } else {
1403                 /* only update length if no error */
1404                 msg->actual_length += xfer->len;
1405         }
1406
1407         if (!msg->is_dma_mapped
1408                 && as->use_pdc)
1409                 atmel_spi_dma_unmap_xfer(master, xfer);
1410
1411         spi_transfer_delay_exec(xfer);
1412
1413         if (xfer->cs_change) {
1414                 if (list_is_last(&xfer->transfer_list,
1415                                  &msg->transfers)) {
1416                         as->keep_cs = true;
1417                 } else {
1418                         cs_deactivate(as, msg->spi);
1419                         udelay(10);
1420                         cs_activate(as, msg->spi);
1421                 }
1422         }
1423
1424         return 0;
1425 }
1426
1427 static int atmel_spi_transfer_one_message(struct spi_master *master,
1428                                                 struct spi_message *msg)
1429 {
1430         struct atmel_spi *as;
1431         struct spi_transfer *xfer;
1432         struct spi_device *spi = msg->spi;
1433         int ret = 0;
1434
1435         as = spi_master_get_devdata(master);
1436
1437         dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1438                                         msg, dev_name(&spi->dev));
1439
1440         atmel_spi_lock(as);
1441         cs_activate(as, spi);
1442
1443         as->keep_cs = false;
1444
1445         msg->status = 0;
1446         msg->actual_length = 0;
1447
1448         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1449                 trace_spi_transfer_start(msg, xfer);
1450
1451                 ret = atmel_spi_one_transfer(master, msg, xfer);
1452                 if (ret)
1453                         goto msg_done;
1454
1455                 trace_spi_transfer_stop(msg, xfer);
1456         }
1457
1458         if (as->use_pdc)
1459                 atmel_spi_disable_pdc_transfer(as);
1460
1461         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1462                 dev_dbg(&spi->dev,
1463                         "  xfer %p: len %u tx %p/%pad rx %p/%pad\n",
1464                         xfer, xfer->len,
1465                         xfer->tx_buf, &xfer->tx_dma,
1466                         xfer->rx_buf, &xfer->rx_dma);
1467         }
1468
1469 msg_done:
1470         if (!as->keep_cs)
1471                 cs_deactivate(as, msg->spi);
1472
1473         atmel_spi_unlock(as);
1474
1475         msg->status = as->done_status;
1476         spi_finalize_current_message(spi->master);
1477
1478         return ret;
1479 }
1480
1481 static void atmel_spi_cleanup(struct spi_device *spi)
1482 {
1483         struct atmel_spi_device *asd = spi->controller_state;
1484
1485         if (!asd)
1486                 return;
1487
1488         spi->controller_state = NULL;
1489         kfree(asd);
1490 }
1491
1492 static inline unsigned int atmel_get_version(struct atmel_spi *as)
1493 {
1494         return spi_readl(as, VERSION) & 0x00000fff;
1495 }
1496
1497 static void atmel_get_caps(struct atmel_spi *as)
1498 {
1499         unsigned int version;
1500
1501         version = atmel_get_version(as);
1502
1503         as->caps.is_spi2 = version > 0x121;
1504         as->caps.has_wdrbt = version >= 0x210;
1505         as->caps.has_dma_support = version >= 0x212;
1506         as->caps.has_pdc_support = version < 0x212;
1507 }
1508
1509 static void atmel_spi_init(struct atmel_spi *as)
1510 {
1511         spi_writel(as, CR, SPI_BIT(SWRST));
1512         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1513
1514         /* It is recommended to enable FIFOs first thing after reset */
1515         if (as->fifo_size)
1516                 spi_writel(as, CR, SPI_BIT(FIFOEN));
1517
1518         if (as->caps.has_wdrbt) {
1519                 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1520                                 | SPI_BIT(MSTR));
1521         } else {
1522                 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1523         }
1524
1525         if (as->use_pdc)
1526                 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1527         spi_writel(as, CR, SPI_BIT(SPIEN));
1528 }
1529
1530 static int atmel_spi_probe(struct platform_device *pdev)
1531 {
1532         struct resource         *regs;
1533         int                     irq;
1534         struct clk              *clk;
1535         int                     ret;
1536         struct spi_master       *master;
1537         struct atmel_spi        *as;
1538
1539         /* Select default pin state */
1540         pinctrl_pm_select_default_state(&pdev->dev);
1541
1542         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1543         if (!regs)
1544                 return -ENXIO;
1545
1546         irq = platform_get_irq(pdev, 0);
1547         if (irq < 0)
1548                 return irq;
1549
1550         clk = devm_clk_get(&pdev->dev, "spi_clk");
1551         if (IS_ERR(clk))
1552                 return PTR_ERR(clk);
1553
1554         /* setup spi core then atmel-specific driver state */
1555         ret = -ENOMEM;
1556         master = spi_alloc_master(&pdev->dev, sizeof(*as));
1557         if (!master)
1558                 goto out_free;
1559
1560         /* the spi->mode bits understood by this driver: */
1561         master->use_gpio_descriptors = true;
1562         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1563         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
1564         master->dev.of_node = pdev->dev.of_node;
1565         master->bus_num = pdev->id;
1566         master->num_chipselect = 4;
1567         master->setup = atmel_spi_setup;
1568         master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
1569         master->transfer_one_message = atmel_spi_transfer_one_message;
1570         master->cleanup = atmel_spi_cleanup;
1571         master->auto_runtime_pm = true;
1572         master->max_dma_len = SPI_MAX_DMA_XFER;
1573         master->can_dma = atmel_spi_can_dma;
1574         platform_set_drvdata(pdev, master);
1575
1576         as = spi_master_get_devdata(master);
1577
1578         spin_lock_init(&as->lock);
1579
1580         as->pdev = pdev;
1581         as->regs = devm_ioremap_resource(&pdev->dev, regs);
1582         if (IS_ERR(as->regs)) {
1583                 ret = PTR_ERR(as->regs);
1584                 goto out_unmap_regs;
1585         }
1586         as->phybase = regs->start;
1587         as->irq = irq;
1588         as->clk = clk;
1589
1590         init_completion(&as->xfer_completion);
1591
1592         atmel_get_caps(as);
1593
1594         as->use_dma = false;
1595         as->use_pdc = false;
1596         if (as->caps.has_dma_support) {
1597                 ret = atmel_spi_configure_dma(master, as);
1598                 if (ret == 0) {
1599                         as->use_dma = true;
1600                 } else if (ret == -EPROBE_DEFER) {
1601                         return ret;
1602                 }
1603         } else if (as->caps.has_pdc_support) {
1604                 as->use_pdc = true;
1605         }
1606
1607         if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
1608                 as->addr_rx_bbuf = dma_alloc_coherent(&pdev->dev,
1609                                                       SPI_MAX_DMA_XFER,
1610                                                       &as->dma_addr_rx_bbuf,
1611                                                       GFP_KERNEL | GFP_DMA);
1612                 if (!as->addr_rx_bbuf) {
1613                         as->use_dma = false;
1614                 } else {
1615                         as->addr_tx_bbuf = dma_alloc_coherent(&pdev->dev,
1616                                         SPI_MAX_DMA_XFER,
1617                                         &as->dma_addr_tx_bbuf,
1618                                         GFP_KERNEL | GFP_DMA);
1619                         if (!as->addr_tx_bbuf) {
1620                                 as->use_dma = false;
1621                                 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1622                                                   as->addr_rx_bbuf,
1623                                                   as->dma_addr_rx_bbuf);
1624                         }
1625                 }
1626                 if (!as->use_dma)
1627                         dev_info(master->dev.parent,
1628                                  "  can not allocate dma coherent memory\n");
1629         }
1630
1631         if (as->caps.has_dma_support && !as->use_dma)
1632                 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1633
1634         if (as->use_pdc) {
1635                 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1636                                         0, dev_name(&pdev->dev), master);
1637         } else {
1638                 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1639                                         0, dev_name(&pdev->dev), master);
1640         }
1641         if (ret)
1642                 goto out_unmap_regs;
1643
1644         /* Initialize the hardware */
1645         ret = clk_prepare_enable(clk);
1646         if (ret)
1647                 goto out_free_irq;
1648
1649         as->spi_clk = clk_get_rate(clk);
1650
1651         as->fifo_size = 0;
1652         if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
1653                                   &as->fifo_size)) {
1654                 dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size);
1655         }
1656
1657         atmel_spi_init(as);
1658
1659         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1660         pm_runtime_use_autosuspend(&pdev->dev);
1661         pm_runtime_set_active(&pdev->dev);
1662         pm_runtime_enable(&pdev->dev);
1663
1664         ret = devm_spi_register_master(&pdev->dev, master);
1665         if (ret)
1666                 goto out_free_dma;
1667
1668         /* go! */
1669         dev_info(&pdev->dev, "Atmel SPI Controller version 0x%x at 0x%08lx (irq %d)\n",
1670                         atmel_get_version(as), (unsigned long)regs->start,
1671                         irq);
1672
1673         return 0;
1674
1675 out_free_dma:
1676         pm_runtime_disable(&pdev->dev);
1677         pm_runtime_set_suspended(&pdev->dev);
1678
1679         if (as->use_dma)
1680                 atmel_spi_release_dma(master);
1681
1682         spi_writel(as, CR, SPI_BIT(SWRST));
1683         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1684         clk_disable_unprepare(clk);
1685 out_free_irq:
1686 out_unmap_regs:
1687 out_free:
1688         spi_master_put(master);
1689         return ret;
1690 }
1691
1692 static int atmel_spi_remove(struct platform_device *pdev)
1693 {
1694         struct spi_master       *master = platform_get_drvdata(pdev);
1695         struct atmel_spi        *as = spi_master_get_devdata(master);
1696
1697         pm_runtime_get_sync(&pdev->dev);
1698
1699         /* reset the hardware and block queue progress */
1700         if (as->use_dma) {
1701                 atmel_spi_stop_dma(master);
1702                 atmel_spi_release_dma(master);
1703                 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
1704                         dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1705                                           as->addr_tx_bbuf,
1706                                           as->dma_addr_tx_bbuf);
1707                         dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1708                                           as->addr_rx_bbuf,
1709                                           as->dma_addr_rx_bbuf);
1710                 }
1711         }
1712
1713         spin_lock_irq(&as->lock);
1714         spi_writel(as, CR, SPI_BIT(SWRST));
1715         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1716         spi_readl(as, SR);
1717         spin_unlock_irq(&as->lock);
1718
1719         clk_disable_unprepare(as->clk);
1720
1721         pm_runtime_put_noidle(&pdev->dev);
1722         pm_runtime_disable(&pdev->dev);
1723
1724         return 0;
1725 }
1726
1727 #ifdef CONFIG_PM
1728 static int atmel_spi_runtime_suspend(struct device *dev)
1729 {
1730         struct spi_master *master = dev_get_drvdata(dev);
1731         struct atmel_spi *as = spi_master_get_devdata(master);
1732
1733         clk_disable_unprepare(as->clk);
1734         pinctrl_pm_select_sleep_state(dev);
1735
1736         return 0;
1737 }
1738
1739 static int atmel_spi_runtime_resume(struct device *dev)
1740 {
1741         struct spi_master *master = dev_get_drvdata(dev);
1742         struct atmel_spi *as = spi_master_get_devdata(master);
1743
1744         pinctrl_pm_select_default_state(dev);
1745
1746         return clk_prepare_enable(as->clk);
1747 }
1748
1749 #ifdef CONFIG_PM_SLEEP
1750 static int atmel_spi_suspend(struct device *dev)
1751 {
1752         struct spi_master *master = dev_get_drvdata(dev);
1753         int ret;
1754
1755         /* Stop the queue running */
1756         ret = spi_master_suspend(master);
1757         if (ret)
1758                 return ret;
1759
1760         if (!pm_runtime_suspended(dev))
1761                 atmel_spi_runtime_suspend(dev);
1762
1763         return 0;
1764 }
1765
1766 static int atmel_spi_resume(struct device *dev)
1767 {
1768         struct spi_master *master = dev_get_drvdata(dev);
1769         struct atmel_spi *as = spi_master_get_devdata(master);
1770         int ret;
1771
1772         ret = clk_prepare_enable(as->clk);
1773         if (ret)
1774                 return ret;
1775
1776         atmel_spi_init(as);
1777
1778         clk_disable_unprepare(as->clk);
1779
1780         if (!pm_runtime_suspended(dev)) {
1781                 ret = atmel_spi_runtime_resume(dev);
1782                 if (ret)
1783                         return ret;
1784         }
1785
1786         /* Start the queue running */
1787         return spi_master_resume(master);
1788 }
1789 #endif
1790
1791 static const struct dev_pm_ops atmel_spi_pm_ops = {
1792         SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume)
1793         SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend,
1794                            atmel_spi_runtime_resume, NULL)
1795 };
1796 #define ATMEL_SPI_PM_OPS        (&atmel_spi_pm_ops)
1797 #else
1798 #define ATMEL_SPI_PM_OPS        NULL
1799 #endif
1800
1801 static const struct of_device_id atmel_spi_dt_ids[] = {
1802         { .compatible = "atmel,at91rm9200-spi" },
1803         { /* sentinel */ }
1804 };
1805
1806 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1807
1808 static struct platform_driver atmel_spi_driver = {
1809         .driver         = {
1810                 .name   = "atmel_spi",
1811                 .pm     = ATMEL_SPI_PM_OPS,
1812                 .of_match_table = atmel_spi_dt_ids,
1813         },
1814         .probe          = atmel_spi_probe,
1815         .remove         = atmel_spi_remove,
1816 };
1817 module_platform_driver(atmel_spi_driver);
1818
1819 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1820 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1821 MODULE_LICENSE("GPL");
1822 MODULE_ALIAS("platform:atmel_spi");