1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for Atmel AT32 and AT91 SPI Controllers
5 * Copyright (C) 2006 Atmel Corporation
8 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/delay.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/dmaengine.h>
15 #include <linux/err.h>
16 #include <linux/interrupt.h>
17 #include <linux/spi/spi.h>
18 #include <linux/slab.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pm_runtime.h>
25 #include <trace/events/spi.h>
27 /* SPI register offsets */
30 #define SPI_RDR 0x0008
31 #define SPI_TDR 0x000c
33 #define SPI_IER 0x0014
34 #define SPI_IDR 0x0018
35 #define SPI_IMR 0x001c
36 #define SPI_CSR0 0x0030
37 #define SPI_CSR1 0x0034
38 #define SPI_CSR2 0x0038
39 #define SPI_CSR3 0x003c
40 #define SPI_FMR 0x0040
41 #define SPI_FLR 0x0044
42 #define SPI_VERSION 0x00fc
43 #define SPI_RPR 0x0100
44 #define SPI_RCR 0x0104
45 #define SPI_TPR 0x0108
46 #define SPI_TCR 0x010c
47 #define SPI_RNPR 0x0110
48 #define SPI_RNCR 0x0114
49 #define SPI_TNPR 0x0118
50 #define SPI_TNCR 0x011c
51 #define SPI_PTCR 0x0120
52 #define SPI_PTSR 0x0124
55 #define SPI_SPIEN_OFFSET 0
56 #define SPI_SPIEN_SIZE 1
57 #define SPI_SPIDIS_OFFSET 1
58 #define SPI_SPIDIS_SIZE 1
59 #define SPI_SWRST_OFFSET 7
60 #define SPI_SWRST_SIZE 1
61 #define SPI_LASTXFER_OFFSET 24
62 #define SPI_LASTXFER_SIZE 1
63 #define SPI_TXFCLR_OFFSET 16
64 #define SPI_TXFCLR_SIZE 1
65 #define SPI_RXFCLR_OFFSET 17
66 #define SPI_RXFCLR_SIZE 1
67 #define SPI_FIFOEN_OFFSET 30
68 #define SPI_FIFOEN_SIZE 1
69 #define SPI_FIFODIS_OFFSET 31
70 #define SPI_FIFODIS_SIZE 1
73 #define SPI_MSTR_OFFSET 0
74 #define SPI_MSTR_SIZE 1
75 #define SPI_PS_OFFSET 1
77 #define SPI_PCSDEC_OFFSET 2
78 #define SPI_PCSDEC_SIZE 1
79 #define SPI_FDIV_OFFSET 3
80 #define SPI_FDIV_SIZE 1
81 #define SPI_MODFDIS_OFFSET 4
82 #define SPI_MODFDIS_SIZE 1
83 #define SPI_WDRBT_OFFSET 5
84 #define SPI_WDRBT_SIZE 1
85 #define SPI_LLB_OFFSET 7
86 #define SPI_LLB_SIZE 1
87 #define SPI_PCS_OFFSET 16
88 #define SPI_PCS_SIZE 4
89 #define SPI_DLYBCS_OFFSET 24
90 #define SPI_DLYBCS_SIZE 8
92 /* Bitfields in RDR */
93 #define SPI_RD_OFFSET 0
94 #define SPI_RD_SIZE 16
96 /* Bitfields in TDR */
97 #define SPI_TD_OFFSET 0
98 #define SPI_TD_SIZE 16
100 /* Bitfields in SR */
101 #define SPI_RDRF_OFFSET 0
102 #define SPI_RDRF_SIZE 1
103 #define SPI_TDRE_OFFSET 1
104 #define SPI_TDRE_SIZE 1
105 #define SPI_MODF_OFFSET 2
106 #define SPI_MODF_SIZE 1
107 #define SPI_OVRES_OFFSET 3
108 #define SPI_OVRES_SIZE 1
109 #define SPI_ENDRX_OFFSET 4
110 #define SPI_ENDRX_SIZE 1
111 #define SPI_ENDTX_OFFSET 5
112 #define SPI_ENDTX_SIZE 1
113 #define SPI_RXBUFF_OFFSET 6
114 #define SPI_RXBUFF_SIZE 1
115 #define SPI_TXBUFE_OFFSET 7
116 #define SPI_TXBUFE_SIZE 1
117 #define SPI_NSSR_OFFSET 8
118 #define SPI_NSSR_SIZE 1
119 #define SPI_TXEMPTY_OFFSET 9
120 #define SPI_TXEMPTY_SIZE 1
121 #define SPI_SPIENS_OFFSET 16
122 #define SPI_SPIENS_SIZE 1
123 #define SPI_TXFEF_OFFSET 24
124 #define SPI_TXFEF_SIZE 1
125 #define SPI_TXFFF_OFFSET 25
126 #define SPI_TXFFF_SIZE 1
127 #define SPI_TXFTHF_OFFSET 26
128 #define SPI_TXFTHF_SIZE 1
129 #define SPI_RXFEF_OFFSET 27
130 #define SPI_RXFEF_SIZE 1
131 #define SPI_RXFFF_OFFSET 28
132 #define SPI_RXFFF_SIZE 1
133 #define SPI_RXFTHF_OFFSET 29
134 #define SPI_RXFTHF_SIZE 1
135 #define SPI_TXFPTEF_OFFSET 30
136 #define SPI_TXFPTEF_SIZE 1
137 #define SPI_RXFPTEF_OFFSET 31
138 #define SPI_RXFPTEF_SIZE 1
140 /* Bitfields in CSR0 */
141 #define SPI_CPOL_OFFSET 0
142 #define SPI_CPOL_SIZE 1
143 #define SPI_NCPHA_OFFSET 1
144 #define SPI_NCPHA_SIZE 1
145 #define SPI_CSAAT_OFFSET 3
146 #define SPI_CSAAT_SIZE 1
147 #define SPI_BITS_OFFSET 4
148 #define SPI_BITS_SIZE 4
149 #define SPI_SCBR_OFFSET 8
150 #define SPI_SCBR_SIZE 8
151 #define SPI_DLYBS_OFFSET 16
152 #define SPI_DLYBS_SIZE 8
153 #define SPI_DLYBCT_OFFSET 24
154 #define SPI_DLYBCT_SIZE 8
156 /* Bitfields in RCR */
157 #define SPI_RXCTR_OFFSET 0
158 #define SPI_RXCTR_SIZE 16
160 /* Bitfields in TCR */
161 #define SPI_TXCTR_OFFSET 0
162 #define SPI_TXCTR_SIZE 16
164 /* Bitfields in RNCR */
165 #define SPI_RXNCR_OFFSET 0
166 #define SPI_RXNCR_SIZE 16
168 /* Bitfields in TNCR */
169 #define SPI_TXNCR_OFFSET 0
170 #define SPI_TXNCR_SIZE 16
172 /* Bitfields in PTCR */
173 #define SPI_RXTEN_OFFSET 0
174 #define SPI_RXTEN_SIZE 1
175 #define SPI_RXTDIS_OFFSET 1
176 #define SPI_RXTDIS_SIZE 1
177 #define SPI_TXTEN_OFFSET 8
178 #define SPI_TXTEN_SIZE 1
179 #define SPI_TXTDIS_OFFSET 9
180 #define SPI_TXTDIS_SIZE 1
182 /* Bitfields in FMR */
183 #define SPI_TXRDYM_OFFSET 0
184 #define SPI_TXRDYM_SIZE 2
185 #define SPI_RXRDYM_OFFSET 4
186 #define SPI_RXRDYM_SIZE 2
187 #define SPI_TXFTHRES_OFFSET 16
188 #define SPI_TXFTHRES_SIZE 6
189 #define SPI_RXFTHRES_OFFSET 24
190 #define SPI_RXFTHRES_SIZE 6
192 /* Bitfields in FLR */
193 #define SPI_TXFL_OFFSET 0
194 #define SPI_TXFL_SIZE 6
195 #define SPI_RXFL_OFFSET 16
196 #define SPI_RXFL_SIZE 6
198 /* Constants for BITS */
199 #define SPI_BITS_8_BPT 0
200 #define SPI_BITS_9_BPT 1
201 #define SPI_BITS_10_BPT 2
202 #define SPI_BITS_11_BPT 3
203 #define SPI_BITS_12_BPT 4
204 #define SPI_BITS_13_BPT 5
205 #define SPI_BITS_14_BPT 6
206 #define SPI_BITS_15_BPT 7
207 #define SPI_BITS_16_BPT 8
208 #define SPI_ONE_DATA 0
209 #define SPI_TWO_DATA 1
210 #define SPI_FOUR_DATA 2
212 /* Bit manipulation macros */
213 #define SPI_BIT(name) \
214 (1 << SPI_##name##_OFFSET)
215 #define SPI_BF(name, value) \
216 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
217 #define SPI_BFEXT(name, value) \
218 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
219 #define SPI_BFINS(name, value, old) \
220 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
221 | SPI_BF(name, value))
223 /* Register access macros */
224 #define spi_readl(port, reg) \
225 readl_relaxed((port)->regs + SPI_##reg)
226 #define spi_writel(port, reg, value) \
227 writel_relaxed((value), (port)->regs + SPI_##reg)
228 #define spi_writew(port, reg, value) \
229 writew_relaxed((value), (port)->regs + SPI_##reg)
231 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
232 * cache operations; better heuristics consider wordsize and bitrate.
234 #define DMA_MIN_BYTES 16
236 #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
238 #define AUTOSUSPEND_TIMEOUT 2000
240 struct atmel_spi_caps {
243 bool has_dma_support;
244 bool has_pdc_support;
248 * The core SPI transfer engine just talks to a register bank to set up
249 * DMA transfers; transfer queue progress is driven by IRQs. The clock
250 * framework provides the base clock, subdivided for each spi_device.
260 struct platform_device *pdev;
261 unsigned long spi_clk;
263 struct spi_transfer *current_transfer;
264 int current_remaining_bytes;
266 dma_addr_t dma_addr_rx_bbuf;
267 dma_addr_t dma_addr_tx_bbuf;
271 struct completion xfer_completion;
273 struct atmel_spi_caps caps;
282 u8 native_cs_for_gpio;
285 /* Controller-specific per-slave state */
286 struct atmel_spi_device {
290 #define SPI_MAX_DMA_XFER 65535 /* true for both PDC and DMA */
291 #define INVALID_DMA_ADDRESS 0xffffffff
294 * Version 2 of the SPI controller has
296 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
297 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
299 * - SPI_CSRx.SBCR allows faster clocking
301 static bool atmel_spi_is_v2(struct atmel_spi *as)
303 return as->caps.is_spi2;
307 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
308 * they assume that spi slave device state will not change on deselect, so
309 * that automagic deselection is OK. ("NPCSx rises if no data is to be
310 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
311 * controllers have CSAAT and friends.
313 * Even controller newer than ar91rm9200, using GPIOs can make sens as
314 * it lets us support active-high chipselects despite the controller's
315 * belief that only active-low devices/systems exists.
317 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
318 * right when driven with GPIO. ("Mode Fault does not allow more than one
319 * Master on Chip Select 0.") No workaround exists for that ... so for
320 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
321 * and (c) will trigger that first erratum in some cases.
324 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
326 struct atmel_spi_device *asd = spi->controller_state;
331 chip_select = as->native_cs_for_gpio;
333 chip_select = spi->chip_select;
335 if (atmel_spi_is_v2(as)) {
336 spi_writel(as, CSR0 + 4 * chip_select, asd->csr);
337 /* For the low SPI version, there is a issue that PDC transfer
338 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
340 spi_writel(as, CSR0, asd->csr);
341 if (as->caps.has_wdrbt) {
343 SPI_BF(PCS, ~(0x01 << chip_select))
349 SPI_BF(PCS, ~(0x01 << chip_select))
354 mr = spi_readl(as, MR);
356 gpiod_set_value(spi->cs_gpiod, 1);
358 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
362 /* Make sure clock polarity is correct */
363 for (i = 0; i < spi->master->num_chipselect; i++) {
364 csr = spi_readl(as, CSR0 + 4 * i);
365 if ((csr ^ cpol) & SPI_BIT(CPOL))
366 spi_writel(as, CSR0 + 4 * i,
367 csr ^ SPI_BIT(CPOL));
370 mr = spi_readl(as, MR);
371 mr = SPI_BFINS(PCS, ~(1 << chip_select), mr);
373 gpiod_set_value(spi->cs_gpiod, 1);
374 spi_writel(as, MR, mr);
377 dev_dbg(&spi->dev, "activate NPCS, mr %08x\n", mr);
380 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
386 chip_select = as->native_cs_for_gpio;
388 chip_select = spi->chip_select;
390 /* only deactivate *this* device; sometimes transfers to
391 * another device may be active when this routine is called.
393 mr = spi_readl(as, MR);
394 if (~SPI_BFEXT(PCS, mr) & (1 << chip_select)) {
395 mr = SPI_BFINS(PCS, 0xf, mr);
396 spi_writel(as, MR, mr);
399 dev_dbg(&spi->dev, "DEactivate NPCS, mr %08x\n", mr);
402 spi_writel(as, CR, SPI_BIT(LASTXFER));
404 gpiod_set_value(spi->cs_gpiod, 0);
407 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
409 spin_lock_irqsave(&as->lock, as->flags);
412 static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
414 spin_unlock_irqrestore(&as->lock, as->flags);
417 static inline bool atmel_spi_is_vmalloc_xfer(struct spi_transfer *xfer)
419 return is_vmalloc_addr(xfer->tx_buf) || is_vmalloc_addr(xfer->rx_buf);
422 static inline bool atmel_spi_use_dma(struct atmel_spi *as,
423 struct spi_transfer *xfer)
425 return as->use_dma && xfer->len >= DMA_MIN_BYTES;
428 static bool atmel_spi_can_dma(struct spi_master *master,
429 struct spi_device *spi,
430 struct spi_transfer *xfer)
432 struct atmel_spi *as = spi_master_get_devdata(master);
434 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5))
435 return atmel_spi_use_dma(as, xfer) &&
436 !atmel_spi_is_vmalloc_xfer(xfer);
438 return atmel_spi_use_dma(as, xfer);
442 static int atmel_spi_dma_slave_config(struct atmel_spi *as,
443 struct dma_slave_config *slave_config,
446 struct spi_master *master = platform_get_drvdata(as->pdev);
449 if (bits_per_word > 8) {
450 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
451 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
453 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
454 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
457 slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
458 slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
459 slave_config->src_maxburst = 1;
460 slave_config->dst_maxburst = 1;
461 slave_config->device_fc = false;
464 * This driver uses fixed peripheral select mode (PS bit set to '0' in
465 * the Mode Register).
466 * So according to the datasheet, when FIFOs are available (and
467 * enabled), the Transmit FIFO operates in Multiple Data Mode.
468 * In this mode, up to 2 data, not 4, can be written into the Transmit
469 * Data Register in a single access.
470 * However, the first data has to be written into the lowest 16 bits and
471 * the second data into the highest 16 bits of the Transmit
472 * Data Register. For 8bit data (the most frequent case), it would
473 * require to rework tx_buf so each data would actualy fit 16 bits.
474 * So we'd rather write only one data at the time. Hence the transmit
475 * path works the same whether FIFOs are available (and enabled) or not.
477 slave_config->direction = DMA_MEM_TO_DEV;
478 if (dmaengine_slave_config(master->dma_tx, slave_config)) {
479 dev_err(&as->pdev->dev,
480 "failed to configure tx dma channel\n");
485 * This driver configures the spi controller for master mode (MSTR bit
486 * set to '1' in the Mode Register).
487 * So according to the datasheet, when FIFOs are available (and
488 * enabled), the Receive FIFO operates in Single Data Mode.
489 * So the receive path works the same whether FIFOs are available (and
492 slave_config->direction = DMA_DEV_TO_MEM;
493 if (dmaengine_slave_config(master->dma_rx, slave_config)) {
494 dev_err(&as->pdev->dev,
495 "failed to configure rx dma channel\n");
502 static int atmel_spi_configure_dma(struct spi_master *master,
503 struct atmel_spi *as)
505 struct dma_slave_config slave_config;
506 struct device *dev = &as->pdev->dev;
509 master->dma_tx = dma_request_chan(dev, "tx");
510 if (IS_ERR(master->dma_tx)) {
511 err = PTR_ERR(master->dma_tx);
512 dev_dbg(dev, "No TX DMA channel, DMA is disabled\n");
516 master->dma_rx = dma_request_chan(dev, "rx");
517 if (IS_ERR(master->dma_rx)) {
518 err = PTR_ERR(master->dma_rx);
520 * No reason to check EPROBE_DEFER here since we have already
521 * requested tx channel.
523 dev_dbg(dev, "No RX DMA channel, DMA is disabled\n");
527 err = atmel_spi_dma_slave_config(as, &slave_config, 8);
531 dev_info(&as->pdev->dev,
532 "Using %s (tx) and %s (rx) for DMA transfers\n",
533 dma_chan_name(master->dma_tx),
534 dma_chan_name(master->dma_rx));
538 if (!IS_ERR(master->dma_rx))
539 dma_release_channel(master->dma_rx);
540 if (!IS_ERR(master->dma_tx))
541 dma_release_channel(master->dma_tx);
543 master->dma_tx = master->dma_rx = NULL;
547 static void atmel_spi_stop_dma(struct spi_master *master)
550 dmaengine_terminate_all(master->dma_rx);
552 dmaengine_terminate_all(master->dma_tx);
555 static void atmel_spi_release_dma(struct spi_master *master)
557 if (master->dma_rx) {
558 dma_release_channel(master->dma_rx);
559 master->dma_rx = NULL;
561 if (master->dma_tx) {
562 dma_release_channel(master->dma_tx);
563 master->dma_tx = NULL;
567 /* This function is called by the DMA driver from tasklet context */
568 static void dma_callback(void *data)
570 struct spi_master *master = data;
571 struct atmel_spi *as = spi_master_get_devdata(master);
573 if (is_vmalloc_addr(as->current_transfer->rx_buf) &&
574 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
575 memcpy(as->current_transfer->rx_buf, as->addr_rx_bbuf,
576 as->current_transfer->len);
578 complete(&as->xfer_completion);
582 * Next transfer using PIO without FIFO.
584 static void atmel_spi_next_xfer_single(struct spi_master *master,
585 struct spi_transfer *xfer)
587 struct atmel_spi *as = spi_master_get_devdata(master);
588 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
590 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
592 /* Make sure data is not remaining in RDR */
594 while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
599 if (xfer->bits_per_word > 8)
600 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
602 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
604 dev_dbg(master->dev.parent,
605 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
606 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
607 xfer->bits_per_word);
609 /* Enable relevant interrupts */
610 spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
614 * Next transfer using PIO with FIFO.
616 static void atmel_spi_next_xfer_fifo(struct spi_master *master,
617 struct spi_transfer *xfer)
619 struct atmel_spi *as = spi_master_get_devdata(master);
620 u32 current_remaining_data, num_data;
621 u32 offset = xfer->len - as->current_remaining_bytes;
622 const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset);
623 const u8 *bytes = (const u8 *)((u8 *)xfer->tx_buf + offset);
627 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_fifo\n");
629 /* Compute the number of data to transfer in the current iteration */
630 current_remaining_data = ((xfer->bits_per_word > 8) ?
631 ((u32)as->current_remaining_bytes >> 1) :
632 (u32)as->current_remaining_bytes);
633 num_data = min(current_remaining_data, as->fifo_size);
635 /* Flush RX and TX FIFOs */
636 spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR));
637 while (spi_readl(as, FLR))
640 /* Set RX FIFO Threshold to the number of data to transfer */
641 fifomr = spi_readl(as, FMR);
642 spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr));
644 /* Clear FIFO flags in the Status Register, especially RXFTHF */
645 (void)spi_readl(as, SR);
648 while (num_data >= 2) {
649 if (xfer->bits_per_word > 8) {
657 spi_writel(as, TDR, (td1 << 16) | td0);
662 if (xfer->bits_per_word > 8)
667 spi_writew(as, TDR, td0);
671 dev_dbg(master->dev.parent,
672 " start fifo xfer %p: len %u tx %p rx %p bitpw %d\n",
673 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
674 xfer->bits_per_word);
677 * Enable RX FIFO Threshold Flag interrupt to be notified about
678 * transfer completion.
680 spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES));
684 * Next transfer using PIO.
686 static void atmel_spi_next_xfer_pio(struct spi_master *master,
687 struct spi_transfer *xfer)
689 struct atmel_spi *as = spi_master_get_devdata(master);
692 atmel_spi_next_xfer_fifo(master, xfer);
694 atmel_spi_next_xfer_single(master, xfer);
698 * Submit next transfer for DMA.
700 static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
701 struct spi_transfer *xfer,
704 struct atmel_spi *as = spi_master_get_devdata(master);
705 struct dma_chan *rxchan = master->dma_rx;
706 struct dma_chan *txchan = master->dma_tx;
707 struct dma_async_tx_descriptor *rxdesc;
708 struct dma_async_tx_descriptor *txdesc;
709 struct dma_slave_config slave_config;
712 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
714 /* Check that the channels are available */
715 if (!rxchan || !txchan)
721 if (atmel_spi_dma_slave_config(as, &slave_config,
722 xfer->bits_per_word))
725 /* Send both scatterlists */
726 if (atmel_spi_is_vmalloc_xfer(xfer) &&
727 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
728 rxdesc = dmaengine_prep_slave_single(rxchan,
729 as->dma_addr_rx_bbuf,
735 rxdesc = dmaengine_prep_slave_sg(rxchan,
745 if (atmel_spi_is_vmalloc_xfer(xfer) &&
746 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
747 memcpy(as->addr_tx_bbuf, xfer->tx_buf, xfer->len);
748 txdesc = dmaengine_prep_slave_single(txchan,
749 as->dma_addr_tx_bbuf,
750 xfer->len, DMA_MEM_TO_DEV,
754 txdesc = dmaengine_prep_slave_sg(txchan,
764 dev_dbg(master->dev.parent,
765 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
766 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
767 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
769 /* Enable relevant interrupts */
770 spi_writel(as, IER, SPI_BIT(OVRES));
772 /* Put the callback on the RX transfer only, that should finish last */
773 rxdesc->callback = dma_callback;
774 rxdesc->callback_param = master;
776 /* Submit and fire RX and TX with TX last so we're ready to read! */
777 cookie = rxdesc->tx_submit(rxdesc);
778 if (dma_submit_error(cookie))
780 cookie = txdesc->tx_submit(txdesc);
781 if (dma_submit_error(cookie))
783 rxchan->device->device_issue_pending(rxchan);
784 txchan->device->device_issue_pending(txchan);
789 spi_writel(as, IDR, SPI_BIT(OVRES));
790 atmel_spi_stop_dma(master);
795 static void atmel_spi_next_xfer_data(struct spi_master *master,
796 struct spi_transfer *xfer,
801 *rx_dma = xfer->rx_dma + xfer->len - *plen;
802 *tx_dma = xfer->tx_dma + xfer->len - *plen;
803 if (*plen > master->max_dma_len)
804 *plen = master->max_dma_len;
807 static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
808 struct spi_device *spi,
809 struct spi_transfer *xfer)
812 unsigned long bus_hz;
816 chip_select = as->native_cs_for_gpio;
818 chip_select = spi->chip_select;
820 /* v1 chips start out at half the peripheral bus speed. */
821 bus_hz = as->spi_clk;
822 if (!atmel_spi_is_v2(as))
826 * Calculate the lowest divider that satisfies the
827 * constraint, assuming div32/fdiv/mbz == 0.
829 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
832 * If the resulting divider doesn't fit into the
833 * register bitfield, we can't satisfy the constraint.
835 if (scbr >= (1 << SPI_SCBR_SIZE)) {
837 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
838 xfer->speed_hz, scbr, bus_hz/255);
843 "setup: %d Hz too high, scbr %u; max %ld Hz\n",
844 xfer->speed_hz, scbr, bus_hz);
847 csr = spi_readl(as, CSR0 + 4 * chip_select);
848 csr = SPI_BFINS(SCBR, scbr, csr);
849 spi_writel(as, CSR0 + 4 * chip_select, csr);
850 xfer->effective_speed_hz = bus_hz / scbr;
856 * Submit next transfer for PDC.
857 * lock is held, spi irq is blocked
859 static void atmel_spi_pdc_next_xfer(struct spi_master *master,
860 struct spi_transfer *xfer)
862 struct atmel_spi *as = spi_master_get_devdata(master);
864 dma_addr_t tx_dma, rx_dma;
866 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
868 len = as->current_remaining_bytes;
869 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
870 as->current_remaining_bytes -= len;
872 spi_writel(as, RPR, rx_dma);
873 spi_writel(as, TPR, tx_dma);
875 if (xfer->bits_per_word > 8)
877 spi_writel(as, RCR, len);
878 spi_writel(as, TCR, len);
880 dev_dbg(&master->dev,
881 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
882 xfer, xfer->len, xfer->tx_buf,
883 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
884 (unsigned long long)xfer->rx_dma);
886 if (as->current_remaining_bytes) {
887 len = as->current_remaining_bytes;
888 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
889 as->current_remaining_bytes -= len;
891 spi_writel(as, RNPR, rx_dma);
892 spi_writel(as, TNPR, tx_dma);
894 if (xfer->bits_per_word > 8)
896 spi_writel(as, RNCR, len);
897 spi_writel(as, TNCR, len);
899 dev_dbg(&master->dev,
900 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
901 xfer, xfer->len, xfer->tx_buf,
902 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
903 (unsigned long long)xfer->rx_dma);
906 /* REVISIT: We're waiting for RXBUFF before we start the next
907 * transfer because we need to handle some difficult timing
908 * issues otherwise. If we wait for TXBUFE in one transfer and
909 * then starts waiting for RXBUFF in the next, it's difficult
910 * to tell the difference between the RXBUFF interrupt we're
911 * actually waiting for and the RXBUFF interrupt of the
914 * It should be doable, though. Just not now...
916 spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));
917 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
921 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
922 * - The buffer is either valid for CPU access, else NULL
923 * - If the buffer is valid, so is its DMA address
925 * This driver manages the dma address unless message->is_dma_mapped.
928 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
930 struct device *dev = &as->pdev->dev;
932 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
934 /* tx_buf is a const void* where we need a void * for the dma
936 void *nonconst_tx = (void *)xfer->tx_buf;
938 xfer->tx_dma = dma_map_single(dev,
939 nonconst_tx, xfer->len,
941 if (dma_mapping_error(dev, xfer->tx_dma))
945 xfer->rx_dma = dma_map_single(dev,
946 xfer->rx_buf, xfer->len,
948 if (dma_mapping_error(dev, xfer->rx_dma)) {
950 dma_unmap_single(dev,
951 xfer->tx_dma, xfer->len,
959 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
960 struct spi_transfer *xfer)
962 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
963 dma_unmap_single(master->dev.parent, xfer->tx_dma,
964 xfer->len, DMA_TO_DEVICE);
965 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
966 dma_unmap_single(master->dev.parent, xfer->rx_dma,
967 xfer->len, DMA_FROM_DEVICE);
970 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
972 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
976 atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer)
980 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
982 if (xfer->bits_per_word > 8) {
983 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
984 *rxp16 = spi_readl(as, RDR);
986 rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
987 *rxp = spi_readl(as, RDR);
989 if (xfer->bits_per_word > 8) {
990 if (as->current_remaining_bytes > 2)
991 as->current_remaining_bytes -= 2;
993 as->current_remaining_bytes = 0;
995 as->current_remaining_bytes--;
1000 atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer)
1002 u32 fifolr = spi_readl(as, FLR);
1003 u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr);
1004 u32 offset = xfer->len - as->current_remaining_bytes;
1005 u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset);
1006 u8 *bytes = (u8 *)((u8 *)xfer->rx_buf + offset);
1007 u16 rd; /* RD field is the lowest 16 bits of RDR */
1009 /* Update the number of remaining bytes to transfer */
1010 num_bytes = ((xfer->bits_per_word > 8) ?
1014 if (as->current_remaining_bytes > num_bytes)
1015 as->current_remaining_bytes -= num_bytes;
1017 as->current_remaining_bytes = 0;
1019 /* Handle odd number of bytes when data are more than 8bit width */
1020 if (xfer->bits_per_word > 8)
1021 as->current_remaining_bytes &= ~0x1;
1025 rd = spi_readl(as, RDR);
1026 if (xfer->bits_per_word > 8)
1036 * Must update "current_remaining_bytes" to keep track of data
1040 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
1043 atmel_spi_pump_fifo_data(as, xfer);
1045 atmel_spi_pump_single_data(as, xfer);
1052 atmel_spi_pio_interrupt(int irq, void *dev_id)
1054 struct spi_master *master = dev_id;
1055 struct atmel_spi *as = spi_master_get_devdata(master);
1056 u32 status, pending, imr;
1057 struct spi_transfer *xfer;
1060 imr = spi_readl(as, IMR);
1061 status = spi_readl(as, SR);
1062 pending = status & imr;
1064 if (pending & SPI_BIT(OVRES)) {
1066 spi_writel(as, IDR, SPI_BIT(OVRES));
1067 dev_warn(master->dev.parent, "overrun\n");
1070 * When we get an overrun, we disregard the current
1071 * transfer. Data will not be copied back from any
1072 * bounce buffer and msg->actual_len will not be
1073 * updated with the last xfer.
1075 * We will also not process any remaning transfers in
1078 as->done_status = -EIO;
1081 /* Clear any overrun happening while cleaning up */
1084 complete(&as->xfer_completion);
1086 } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) {
1089 if (as->current_remaining_bytes) {
1091 xfer = as->current_transfer;
1092 atmel_spi_pump_pio_data(as, xfer);
1093 if (!as->current_remaining_bytes)
1094 spi_writel(as, IDR, pending);
1096 complete(&as->xfer_completion);
1099 atmel_spi_unlock(as);
1101 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
1103 spi_writel(as, IDR, pending);
1110 atmel_spi_pdc_interrupt(int irq, void *dev_id)
1112 struct spi_master *master = dev_id;
1113 struct atmel_spi *as = spi_master_get_devdata(master);
1114 u32 status, pending, imr;
1117 imr = spi_readl(as, IMR);
1118 status = spi_readl(as, SR);
1119 pending = status & imr;
1121 if (pending & SPI_BIT(OVRES)) {
1125 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
1128 /* Clear any overrun happening while cleaning up */
1131 as->done_status = -EIO;
1133 complete(&as->xfer_completion);
1135 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
1138 spi_writel(as, IDR, pending);
1140 complete(&as->xfer_completion);
1146 static int atmel_word_delay_csr(struct spi_device *spi, struct atmel_spi *as)
1148 struct spi_delay *delay = &spi->word_delay;
1149 u32 value = delay->value;
1151 switch (delay->unit) {
1152 case SPI_DELAY_UNIT_NSECS:
1155 case SPI_DELAY_UNIT_USECS:
1161 return (as->spi_clk / 1000000 * value) >> 5;
1164 static void initialize_native_cs_for_gpio(struct atmel_spi *as)
1167 struct spi_master *master = platform_get_drvdata(as->pdev);
1169 if (!as->native_cs_free)
1170 return; /* already initialized */
1172 if (!master->cs_gpiods)
1173 return; /* No CS GPIO */
1176 * On the first version of the controller (AT91RM9200), CS0
1177 * can't be used associated with GPIO
1179 if (atmel_spi_is_v2(as))
1185 if (master->cs_gpiods[i])
1186 as->native_cs_free |= BIT(i);
1188 if (as->native_cs_free)
1189 as->native_cs_for_gpio = ffs(as->native_cs_free);
1192 static int atmel_spi_setup(struct spi_device *spi)
1194 struct atmel_spi *as;
1195 struct atmel_spi_device *asd;
1197 unsigned int bits = spi->bits_per_word;
1201 as = spi_master_get_devdata(spi->master);
1203 /* see notes above re chipselect */
1204 if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH)) {
1205 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
1209 /* Setup() is called during spi_register_controller(aka
1210 * spi_register_master) but after all membmers of the cs_gpiod
1211 * array have been filled, so we can looked for which native
1212 * CS will be free for using with GPIO
1214 initialize_native_cs_for_gpio(as);
1216 if (spi->cs_gpiod && as->native_cs_free) {
1218 "No native CS available to support this GPIO CS\n");
1223 chip_select = as->native_cs_for_gpio;
1225 chip_select = spi->chip_select;
1227 csr = SPI_BF(BITS, bits - 8);
1228 if (spi->mode & SPI_CPOL)
1229 csr |= SPI_BIT(CPOL);
1230 if (!(spi->mode & SPI_CPHA))
1231 csr |= SPI_BIT(NCPHA);
1234 csr |= SPI_BIT(CSAAT);
1235 csr |= SPI_BF(DLYBS, 0);
1237 word_delay_csr = atmel_word_delay_csr(spi, as);
1238 if (word_delay_csr < 0)
1239 return word_delay_csr;
1241 /* DLYBCT adds delays between words. This is useful for slow devices
1242 * that need a bit of time to setup the next transfer.
1244 csr |= SPI_BF(DLYBCT, word_delay_csr);
1246 asd = spi->controller_state;
1248 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1252 spi->controller_state = asd;
1258 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1259 bits, spi->mode, spi->chip_select, csr);
1261 if (!atmel_spi_is_v2(as))
1262 spi_writel(as, CSR0 + 4 * chip_select, csr);
1267 static void atmel_spi_set_cs(struct spi_device *spi, bool enable)
1269 struct atmel_spi *as = spi_master_get_devdata(spi->master);
1270 /* the core doesn't really pass us enable/disable, but CS HIGH vs CS LOW
1271 * since we already have routines for activate/deactivate translate
1272 * high/low to active/inactive
1274 enable = (!!(spi->mode & SPI_CS_HIGH) == enable);
1277 cs_activate(as, spi);
1279 cs_deactivate(as, spi);
1284 static int atmel_spi_one_transfer(struct spi_master *master,
1285 struct spi_device *spi,
1286 struct spi_transfer *xfer)
1288 struct atmel_spi *as;
1291 struct atmel_spi_device *asd;
1294 unsigned long dma_timeout;
1296 as = spi_master_get_devdata(master);
1298 asd = spi->controller_state;
1299 bits = (asd->csr >> 4) & 0xf;
1300 if (bits != xfer->bits_per_word - 8) {
1302 "you can't yet change bits_per_word in transfers\n");
1303 return -ENOPROTOOPT;
1307 * DMA map early, for performance (empties dcache ASAP) and
1308 * better fault reporting.
1310 if ((!master->cur_msg_mapped)
1312 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1316 atmel_spi_set_xfer_speed(as, spi, xfer);
1318 as->done_status = 0;
1319 as->current_transfer = xfer;
1320 as->current_remaining_bytes = xfer->len;
1321 while (as->current_remaining_bytes) {
1322 reinit_completion(&as->xfer_completion);
1326 atmel_spi_pdc_next_xfer(master, xfer);
1327 atmel_spi_unlock(as);
1328 } else if (atmel_spi_use_dma(as, xfer)) {
1329 len = as->current_remaining_bytes;
1330 ret = atmel_spi_next_xfer_dma_submit(master,
1334 "unable to use DMA, fallback to PIO\n");
1335 as->done_status = ret;
1338 as->current_remaining_bytes -= len;
1339 if (as->current_remaining_bytes < 0)
1340 as->current_remaining_bytes = 0;
1344 atmel_spi_next_xfer_pio(master, xfer);
1345 atmel_spi_unlock(as);
1348 dma_timeout = wait_for_completion_timeout(&as->xfer_completion,
1350 if (WARN_ON(dma_timeout == 0)) {
1351 dev_err(&spi->dev, "spi transfer timeout\n");
1352 as->done_status = -EIO;
1355 if (as->done_status)
1359 if (as->done_status) {
1361 dev_warn(master->dev.parent,
1362 "overrun (%u/%u remaining)\n",
1363 spi_readl(as, TCR), spi_readl(as, RCR));
1366 * Clean up DMA registers and make sure the data
1367 * registers are empty.
1369 spi_writel(as, RNCR, 0);
1370 spi_writel(as, TNCR, 0);
1371 spi_writel(as, RCR, 0);
1372 spi_writel(as, TCR, 0);
1373 for (timeout = 1000; timeout; timeout--)
1374 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1377 dev_warn(master->dev.parent,
1378 "timeout waiting for TXEMPTY");
1379 while (spi_readl(as, SR) & SPI_BIT(RDRF))
1382 /* Clear any overrun happening while cleaning up */
1385 } else if (atmel_spi_use_dma(as, xfer)) {
1386 atmel_spi_stop_dma(master);
1390 if (!master->cur_msg_mapped
1392 atmel_spi_dma_unmap_xfer(master, xfer);
1395 atmel_spi_disable_pdc_transfer(as);
1397 return as->done_status;
1400 static void atmel_spi_cleanup(struct spi_device *spi)
1402 struct atmel_spi_device *asd = spi->controller_state;
1407 spi->controller_state = NULL;
1411 static inline unsigned int atmel_get_version(struct atmel_spi *as)
1413 return spi_readl(as, VERSION) & 0x00000fff;
1416 static void atmel_get_caps(struct atmel_spi *as)
1418 unsigned int version;
1420 version = atmel_get_version(as);
1422 as->caps.is_spi2 = version > 0x121;
1423 as->caps.has_wdrbt = version >= 0x210;
1424 as->caps.has_dma_support = version >= 0x212;
1425 as->caps.has_pdc_support = version < 0x212;
1428 static void atmel_spi_init(struct atmel_spi *as)
1430 spi_writel(as, CR, SPI_BIT(SWRST));
1431 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1433 /* It is recommended to enable FIFOs first thing after reset */
1435 spi_writel(as, CR, SPI_BIT(FIFOEN));
1437 if (as->caps.has_wdrbt) {
1438 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1441 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1445 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1446 spi_writel(as, CR, SPI_BIT(SPIEN));
1449 static int atmel_spi_probe(struct platform_device *pdev)
1451 struct resource *regs;
1455 struct spi_master *master;
1456 struct atmel_spi *as;
1458 /* Select default pin state */
1459 pinctrl_pm_select_default_state(&pdev->dev);
1461 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1465 irq = platform_get_irq(pdev, 0);
1469 clk = devm_clk_get(&pdev->dev, "spi_clk");
1471 return PTR_ERR(clk);
1473 /* setup spi core then atmel-specific driver state */
1474 master = spi_alloc_master(&pdev->dev, sizeof(*as));
1478 /* the spi->mode bits understood by this driver: */
1479 master->use_gpio_descriptors = true;
1480 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1481 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
1482 master->dev.of_node = pdev->dev.of_node;
1483 master->bus_num = pdev->id;
1484 master->num_chipselect = 4;
1485 master->setup = atmel_spi_setup;
1486 master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
1487 master->transfer_one = atmel_spi_one_transfer;
1488 master->set_cs = atmel_spi_set_cs;
1489 master->cleanup = atmel_spi_cleanup;
1490 master->auto_runtime_pm = true;
1491 master->max_dma_len = SPI_MAX_DMA_XFER;
1492 master->can_dma = atmel_spi_can_dma;
1493 platform_set_drvdata(pdev, master);
1495 as = spi_master_get_devdata(master);
1497 spin_lock_init(&as->lock);
1500 as->regs = devm_ioremap_resource(&pdev->dev, regs);
1501 if (IS_ERR(as->regs)) {
1502 ret = PTR_ERR(as->regs);
1503 goto out_unmap_regs;
1505 as->phybase = regs->start;
1509 init_completion(&as->xfer_completion);
1513 as->use_dma = false;
1514 as->use_pdc = false;
1515 if (as->caps.has_dma_support) {
1516 ret = atmel_spi_configure_dma(master, as);
1519 } else if (ret == -EPROBE_DEFER) {
1520 goto out_unmap_regs;
1522 } else if (as->caps.has_pdc_support) {
1526 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
1527 as->addr_rx_bbuf = dma_alloc_coherent(&pdev->dev,
1529 &as->dma_addr_rx_bbuf,
1530 GFP_KERNEL | GFP_DMA);
1531 if (!as->addr_rx_bbuf) {
1532 as->use_dma = false;
1534 as->addr_tx_bbuf = dma_alloc_coherent(&pdev->dev,
1536 &as->dma_addr_tx_bbuf,
1537 GFP_KERNEL | GFP_DMA);
1538 if (!as->addr_tx_bbuf) {
1539 as->use_dma = false;
1540 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1542 as->dma_addr_rx_bbuf);
1546 dev_info(master->dev.parent,
1547 " can not allocate dma coherent memory\n");
1550 if (as->caps.has_dma_support && !as->use_dma)
1551 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1554 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1555 0, dev_name(&pdev->dev), master);
1557 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1558 0, dev_name(&pdev->dev), master);
1561 goto out_unmap_regs;
1563 /* Initialize the hardware */
1564 ret = clk_prepare_enable(clk);
1568 as->spi_clk = clk_get_rate(clk);
1571 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
1573 dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size);
1578 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1579 pm_runtime_use_autosuspend(&pdev->dev);
1580 pm_runtime_set_active(&pdev->dev);
1581 pm_runtime_enable(&pdev->dev);
1583 ret = devm_spi_register_master(&pdev->dev, master);
1588 dev_info(&pdev->dev, "Atmel SPI Controller version 0x%x at 0x%08lx (irq %d)\n",
1589 atmel_get_version(as), (unsigned long)regs->start,
1595 pm_runtime_disable(&pdev->dev);
1596 pm_runtime_set_suspended(&pdev->dev);
1599 atmel_spi_release_dma(master);
1601 spi_writel(as, CR, SPI_BIT(SWRST));
1602 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1603 clk_disable_unprepare(clk);
1606 spi_master_put(master);
1610 static int atmel_spi_remove(struct platform_device *pdev)
1612 struct spi_master *master = platform_get_drvdata(pdev);
1613 struct atmel_spi *as = spi_master_get_devdata(master);
1615 pm_runtime_get_sync(&pdev->dev);
1617 /* reset the hardware and block queue progress */
1619 atmel_spi_stop_dma(master);
1620 atmel_spi_release_dma(master);
1621 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
1622 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1624 as->dma_addr_tx_bbuf);
1625 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1627 as->dma_addr_rx_bbuf);
1631 spin_lock_irq(&as->lock);
1632 spi_writel(as, CR, SPI_BIT(SWRST));
1633 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1635 spin_unlock_irq(&as->lock);
1637 clk_disable_unprepare(as->clk);
1639 pm_runtime_put_noidle(&pdev->dev);
1640 pm_runtime_disable(&pdev->dev);
1646 static int atmel_spi_runtime_suspend(struct device *dev)
1648 struct spi_master *master = dev_get_drvdata(dev);
1649 struct atmel_spi *as = spi_master_get_devdata(master);
1651 clk_disable_unprepare(as->clk);
1652 pinctrl_pm_select_sleep_state(dev);
1657 static int atmel_spi_runtime_resume(struct device *dev)
1659 struct spi_master *master = dev_get_drvdata(dev);
1660 struct atmel_spi *as = spi_master_get_devdata(master);
1662 pinctrl_pm_select_default_state(dev);
1664 return clk_prepare_enable(as->clk);
1667 #ifdef CONFIG_PM_SLEEP
1668 static int atmel_spi_suspend(struct device *dev)
1670 struct spi_master *master = dev_get_drvdata(dev);
1673 /* Stop the queue running */
1674 ret = spi_master_suspend(master);
1678 if (!pm_runtime_suspended(dev))
1679 atmel_spi_runtime_suspend(dev);
1684 static int atmel_spi_resume(struct device *dev)
1686 struct spi_master *master = dev_get_drvdata(dev);
1687 struct atmel_spi *as = spi_master_get_devdata(master);
1690 ret = clk_prepare_enable(as->clk);
1696 clk_disable_unprepare(as->clk);
1698 if (!pm_runtime_suspended(dev)) {
1699 ret = atmel_spi_runtime_resume(dev);
1704 /* Start the queue running */
1705 return spi_master_resume(master);
1709 static const struct dev_pm_ops atmel_spi_pm_ops = {
1710 SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume)
1711 SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend,
1712 atmel_spi_runtime_resume, NULL)
1714 #define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops)
1716 #define ATMEL_SPI_PM_OPS NULL
1719 static const struct of_device_id atmel_spi_dt_ids[] = {
1720 { .compatible = "atmel,at91rm9200-spi" },
1724 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1726 static struct platform_driver atmel_spi_driver = {
1728 .name = "atmel_spi",
1729 .pm = ATMEL_SPI_PM_OPS,
1730 .of_match_table = atmel_spi_dt_ids,
1732 .probe = atmel_spi_probe,
1733 .remove = atmel_spi_remove,
1735 module_platform_driver(atmel_spi_driver);
1737 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1738 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1739 MODULE_LICENSE("GPL");
1740 MODULE_ALIAS("platform:atmel_spi");