drivers/spi/spi-at91-usart.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Driver for AT91 USART Controllers as SPI
   4 //
   5 // Copyright (C) 2018 Microchip Technology Inc.
   6 //
   7 // Author: Radu Pirea <radu.pirea@microchip.com>
   8
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of_gpio.h>
  15 #include <linux/pinctrl/consumer.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm_runtime.h>
  18
  19 #include <linux/spi/spi.h>
  20
  21 #define US_CR                   0x00
  22 #define US_MR                   0x04
  23 #define US_IER                  0x08
  24 #define US_IDR                  0x0C
  25 #define US_CSR                  0x14
  26 #define US_RHR                  0x18
  27 #define US_THR                  0x1C
  28 #define US_BRGR                 0x20
  29 #define US_VERSION              0xFC
  30
  31 #define US_CR_RSTRX             BIT(2)
  32 #define US_CR_RSTTX             BIT(3)
  33 #define US_CR_RXEN              BIT(4)
  34 #define US_CR_RXDIS             BIT(5)
  35 #define US_CR_TXEN              BIT(6)
  36 #define US_CR_TXDIS             BIT(7)
  37
  38 #define US_MR_SPI_MASTER        0x0E
  39 #define US_MR_CHRL              GENMASK(7, 6)
  40 #define US_MR_CPHA              BIT(8)
  41 #define US_MR_CPOL              BIT(16)
  42 #define US_MR_CLKO              BIT(18)
  43 #define US_MR_WRDBT             BIT(20)
  44 #define US_MR_LOOP              BIT(15)
  45
  46 #define US_IR_RXRDY             BIT(0)
  47 #define US_IR_TXRDY             BIT(1)
  48 #define US_IR_OVRE              BIT(5)
  49
  50 #define US_BRGR_SIZE            BIT(16)
  51
  52 #define US_MIN_CLK_DIV          0x06
  53 #define US_MAX_CLK_DIV          BIT(16)
  54
  55 #define US_RESET                (US_CR_RSTRX | US_CR_RSTTX)
  56 #define US_DISABLE              (US_CR_RXDIS | US_CR_TXDIS)
  57 #define US_ENABLE               (US_CR_RXEN | US_CR_TXEN)
  58 #define US_OVRE_RXRDY_IRQS      (US_IR_OVRE | US_IR_RXRDY)
  59
  60 #define US_INIT \
  61         (US_MR_SPI_MASTER | US_MR_CHRL | US_MR_CLKO | US_MR_WRDBT)
  62
  63 /* Register access macros */
  64 #define at91_usart_spi_readl(port, reg) \
  65         readl_relaxed((port)->regs + US_##reg)
  66 #define at91_usart_spi_writel(port, reg, value) \
  67         writel_relaxed((value), (port)->regs + US_##reg)
  68
  69 #define at91_usart_spi_readb(port, reg) \
  70         readb_relaxed((port)->regs + US_##reg)
  71 #define at91_usart_spi_writeb(port, reg, value) \
  72         writeb_relaxed((value), (port)->regs + US_##reg)
  73
  74 struct at91_usart_spi {
  75         struct spi_transfer     *current_transfer;
  76         void __iomem            *regs;
  77         struct device           *dev;
  78         struct clk              *clk;
  79
  80         /*used in interrupt to protect data reading*/
  81         spinlock_t              lock;
  82
  83         int                     irq;
  84         unsigned int            current_tx_remaining_bytes;
  85         unsigned int            current_rx_remaining_bytes;
  86
  87         u32                     spi_clk;
  88         u32                     status;
  89
  90         bool                    xfer_failed;
  91 };
  92
  93 static inline u32 at91_usart_spi_tx_ready(struct at91_usart_spi *aus)
  94 {
  95         return aus->status & US_IR_TXRDY;
  96 }
  97
  98 static inline u32 at91_usart_spi_rx_ready(struct at91_usart_spi *aus)
  99 {
 100         return aus->status & US_IR_RXRDY;
 101 }
 102
 103 static inline u32 at91_usart_spi_check_overrun(struct at91_usart_spi *aus)
 104 {
 105         return aus->status & US_IR_OVRE;
 106 }
 107
 108 static inline u32 at91_usart_spi_read_status(struct at91_usart_spi *aus)
 109 {
 110         aus->status = at91_usart_spi_readl(aus, CSR);
 111         return aus->status;
 112 }
 113
 114 static inline void at91_usart_spi_tx(struct at91_usart_spi *aus)
 115 {
 116         unsigned int len = aus->current_transfer->len;
 117         unsigned int remaining = aus->current_tx_remaining_bytes;
 118         const u8  *tx_buf = aus->current_transfer->tx_buf;
 119
 120         if (!remaining)
 121                 return;
 122
 123         if (at91_usart_spi_tx_ready(aus)) {
 124                 at91_usart_spi_writeb(aus, THR, tx_buf[len - remaining]);
 125                 aus->current_tx_remaining_bytes--;
 126         }
 127 }
 128
 129 static inline void at91_usart_spi_rx(struct at91_usart_spi *aus)
 130 {
 131         int len = aus->current_transfer->len;
 132         int remaining = aus->current_rx_remaining_bytes;
 133         u8  *rx_buf = aus->current_transfer->rx_buf;
 134
 135         if (!remaining)
 136                 return;
 137
 138         rx_buf[len - remaining] = at91_usart_spi_readb(aus, RHR);
 139         aus->current_rx_remaining_bytes--;
 140 }
 141
 142 static inline void
 143 at91_usart_spi_set_xfer_speed(struct at91_usart_spi *aus,
 144                               struct spi_transfer *xfer)
 145 {
 146         at91_usart_spi_writel(aus, BRGR,
 147                               DIV_ROUND_UP(aus->spi_clk, xfer->speed_hz));
 148 }
 149
 150 static irqreturn_t at91_usart_spi_interrupt(int irq, void *dev_id)
 151 {
 152         struct spi_controller *controller = dev_id;
 153         struct at91_usart_spi *aus = spi_master_get_devdata(controller);
 154
 155         spin_lock(&aus->lock);
 156         at91_usart_spi_read_status(aus);
 157
 158         if (at91_usart_spi_check_overrun(aus)) {
 159                 aus->xfer_failed = true;
 160                 at91_usart_spi_writel(aus, IDR, US_IR_OVRE | US_IR_RXRDY);
 161                 spin_unlock(&aus->lock);
 162                 return IRQ_HANDLED;
 163         }
 164
 165         if (at91_usart_spi_rx_ready(aus)) {
 166                 at91_usart_spi_rx(aus);
 167                 spin_unlock(&aus->lock);
 168                 return IRQ_HANDLED;
 169         }
 170
 171         spin_unlock(&aus->lock);
 172
 173         return IRQ_NONE;
 174 }
 175
 176 static int at91_usart_spi_setup(struct spi_device *spi)
 177 {
 178         struct at91_usart_spi *aus = spi_master_get_devdata(spi->controller);
 179         u32 *ausd = spi->controller_state;
 180         unsigned int mr = at91_usart_spi_readl(aus, MR);
 181
 182         if (spi->mode & SPI_CPOL)
 183                 mr |= US_MR_CPOL;
 184         else
 185                 mr &= ~US_MR_CPOL;
 186
 187         if (spi->mode & SPI_CPHA)
 188                 mr |= US_MR_CPHA;
 189         else
 190                 mr &= ~US_MR_CPHA;
 191
 192         if (spi->mode & SPI_LOOP)
 193                 mr |= US_MR_LOOP;
 194         else
 195                 mr &= ~US_MR_LOOP;
 196
 197         if (!ausd) {
 198                 ausd = kzalloc(sizeof(*ausd), GFP_KERNEL);
 199                 if (!ausd)
 200                         return -ENOMEM;
 201
 202                 spi->controller_state = ausd;
 203         }
 204
 205         *ausd = mr;
 206
 207         dev_dbg(&spi->dev,
 208                 "setup: bpw %u mode 0x%x -> mr %d %08x\n",
 209                 spi->bits_per_word, spi->mode, spi->chip_select, mr);
 210
 211         return 0;
 212 }
 213
 214 static int at91_usart_spi_transfer_one(struct spi_controller *ctlr,
 215                                        struct spi_device *spi,
 216                                        struct spi_transfer *xfer)
 217 {
 218         struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
 219
 220         at91_usart_spi_set_xfer_speed(aus, xfer);
 221         aus->xfer_failed = false;
 222         aus->current_transfer = xfer;
 223         aus->current_tx_remaining_bytes = xfer->len;
 224         aus->current_rx_remaining_bytes = xfer->len;
 225
 226         while ((aus->current_tx_remaining_bytes ||
 227                 aus->current_rx_remaining_bytes) && !aus->xfer_failed) {
 228                 at91_usart_spi_read_status(aus);
 229                 at91_usart_spi_tx(aus);
 230                 cpu_relax();
 231         }
 232
 233         if (aus->xfer_failed) {
 234                 dev_err(aus->dev, "Overrun!\n");
 235                 return -EIO;
 236         }
 237
 238         return 0;
 239 }
 240
 241 static int at91_usart_spi_prepare_message(struct spi_controller *ctlr,
 242                                           struct spi_message *message)
 243 {
 244         struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
 245         struct spi_device *spi = message->spi;
 246         u32 *ausd = spi->controller_state;
 247
 248         at91_usart_spi_writel(aus, CR, US_ENABLE);
 249         at91_usart_spi_writel(aus, IER, US_OVRE_RXRDY_IRQS);
 250         at91_usart_spi_writel(aus, MR, *ausd);
 251
 252         return 0;
 253 }
 254
 255 static int at91_usart_spi_unprepare_message(struct spi_controller *ctlr,
 256                                             struct spi_message *message)
 257 {
 258         struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
 259
 260         at91_usart_spi_writel(aus, CR, US_RESET | US_DISABLE);
 261         at91_usart_spi_writel(aus, IDR, US_OVRE_RXRDY_IRQS);
 262
 263         return 0;
 264 }
 265
 266 static void at91_usart_spi_cleanup(struct spi_device *spi)
 267 {
 268         struct at91_usart_spi_device *ausd = spi->controller_state;
 269
 270         spi->controller_state = NULL;
 271         kfree(ausd);
 272 }
 273
 274 static void at91_usart_spi_init(struct at91_usart_spi *aus)
 275 {
 276         at91_usart_spi_writel(aus, MR, US_INIT);
 277         at91_usart_spi_writel(aus, CR, US_RESET | US_DISABLE);
 278 }
 279
 280 static int at91_usart_gpio_setup(struct platform_device *pdev)
 281 {
 282         struct device_node *np = pdev->dev.parent->of_node;
 283         int i;
 284         int ret;
 285         int nb;
 286
 287         if (!np)
 288                 return -EINVAL;
 289
 290         nb = of_gpio_named_count(np, "cs-gpios");
 291         for (i = 0; i < nb; i++) {
 292                 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
 293
 294                 if (cs_gpio < 0)
 295                         return cs_gpio;
 296
 297                 if (gpio_is_valid(cs_gpio)) {
 298                         ret = devm_gpio_request_one(&pdev->dev, cs_gpio,
 299                                                     GPIOF_DIR_OUT,
 300                                                     dev_name(&pdev->dev));
 301                         if (ret)
 302                                 return ret;
 303                 }
 304         }
 305
 306         return 0;
 307 }
 308
 309 static int at91_usart_spi_probe(struct platform_device *pdev)
 310 {
 311         struct resource *regs;
 312         struct spi_controller *controller;
 313         struct at91_usart_spi *aus;
 314         struct clk *clk;
 315         int irq;
 316         int ret;
 317
 318         regs = platform_get_resource(to_platform_device(pdev->dev.parent),
 319                                      IORESOURCE_MEM, 0);
 320         if (!regs)
 321                 return -EINVAL;
 322
 323         irq = platform_get_irq(to_platform_device(pdev->dev.parent), 0);
 324         if (irq < 0)
 325                 return irq;
 326
 327         clk = devm_clk_get(pdev->dev.parent, "usart");
 328         if (IS_ERR(clk))
 329                 return PTR_ERR(clk);
 330
 331         ret = -ENOMEM;
 332         controller = spi_alloc_master(&pdev->dev, sizeof(*aus));
 333         if (!controller)
 334                 goto at91_usart_spi_probe_fail;
 335
 336         ret = at91_usart_gpio_setup(pdev);
 337         if (ret)
 338                 goto at91_usart_spi_probe_fail;
 339
 340         controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH;
 341         controller->dev.of_node = pdev->dev.parent->of_node;
 342         controller->bits_per_word_mask = SPI_BPW_MASK(8);
 343         controller->setup = at91_usart_spi_setup;
 344         controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
 345         controller->transfer_one = at91_usart_spi_transfer_one;
 346         controller->prepare_message = at91_usart_spi_prepare_message;
 347         controller->unprepare_message = at91_usart_spi_unprepare_message;
 348         controller->cleanup = at91_usart_spi_cleanup;
 349         controller->max_speed_hz = DIV_ROUND_UP(clk_get_rate(clk),
 350                                                 US_MIN_CLK_DIV);
 351         controller->min_speed_hz = DIV_ROUND_UP(clk_get_rate(clk),
 352                                                 US_MAX_CLK_DIV);
 353         platform_set_drvdata(pdev, controller);
 354
 355         aus = spi_master_get_devdata(controller);
 356
 357         aus->dev = &pdev->dev;
 358         aus->regs = devm_ioremap_resource(&pdev->dev, regs);
 359         if (IS_ERR(aus->regs)) {
 360                 ret = PTR_ERR(aus->regs);
 361                 goto at91_usart_spi_probe_fail;
 362         }
 363
 364         aus->irq = irq;
 365         aus->clk = clk;
 366
 367         ret = devm_request_irq(&pdev->dev, irq, at91_usart_spi_interrupt, 0,
 368                                dev_name(&pdev->dev), controller);
 369         if (ret)
 370                 goto at91_usart_spi_probe_fail;
 371
 372         ret = clk_prepare_enable(clk);
 373         if (ret)
 374                 goto at91_usart_spi_probe_fail;
 375
 376         aus->spi_clk = clk_get_rate(clk);
 377         at91_usart_spi_init(aus);
 378
 379         spin_lock_init(&aus->lock);
 380         ret = devm_spi_register_master(&pdev->dev, controller);
 381         if (ret)
 382                 goto at91_usart_fail_register_master;
 383
 384         dev_info(&pdev->dev,
 385                  "AT91 USART SPI Controller version 0x%x at %pa (irq %d)\n",
 386                  at91_usart_spi_readl(aus, VERSION),
 387                  &regs->start, irq);
 388
 389         return 0;
 390
 391 at91_usart_fail_register_master:
 392         clk_disable_unprepare(clk);
 393 at91_usart_spi_probe_fail:
 394         spi_master_put(controller);
 395         return ret;
 396 }
 397
 398 __maybe_unused static int at91_usart_spi_runtime_suspend(struct device *dev)
 399 {
 400         struct spi_controller *ctlr = dev_get_drvdata(dev);
 401         struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
 402
 403         clk_disable_unprepare(aus->clk);
 404         pinctrl_pm_select_sleep_state(dev);
 405
 406         return 0;
 407 }
 408
 409 __maybe_unused static int at91_usart_spi_runtime_resume(struct device *dev)
 410 {
 411         struct spi_controller *ctrl = dev_get_drvdata(dev);
 412         struct at91_usart_spi *aus = spi_master_get_devdata(ctrl);
 413
 414         pinctrl_pm_select_default_state(dev);
 415
 416         return clk_prepare_enable(aus->clk);
 417 }
 418
 419 __maybe_unused static int at91_usart_spi_suspend(struct device *dev)
 420 {
 421         struct spi_controller *ctrl = dev_get_drvdata(dev);
 422         int ret;
 423
 424         ret = spi_controller_suspend(ctrl);
 425         if (ret)
 426                 return ret;
 427
 428         if (!pm_runtime_suspended(dev))
 429                 at91_usart_spi_runtime_suspend(dev);
 430
 431         return 0;
 432 }
 433
 434 __maybe_unused static int at91_usart_spi_resume(struct device *dev)
 435 {
 436         struct spi_controller *ctrl = dev_get_drvdata(dev);
 437         struct at91_usart_spi *aus = spi_master_get_devdata(ctrl);
 438         int ret;
 439
 440         if (!pm_runtime_suspended(dev)) {
 441                 ret = at91_usart_spi_runtime_resume(dev);
 442                 if (ret)
 443                         return ret;
 444         }
 445
 446         at91_usart_spi_init(aus);
 447
 448         return spi_controller_resume(ctrl);
 449 }
 450
 451 static int at91_usart_spi_remove(struct platform_device *pdev)
 452 {
 453         struct spi_controller *ctlr = platform_get_drvdata(pdev);
 454         struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
 455
 456         clk_disable_unprepare(aus->clk);
 457
 458         return 0;
 459 }
 460
 461 static const struct dev_pm_ops at91_usart_spi_pm_ops = {
 462         SET_SYSTEM_SLEEP_PM_OPS(at91_usart_spi_suspend, at91_usart_spi_resume)
 463         SET_RUNTIME_PM_OPS(at91_usart_spi_runtime_suspend,
 464                            at91_usart_spi_runtime_resume, NULL)
 465 };
 466
 467 static const struct of_device_id at91_usart_spi_dt_ids[] = {
 468         { .compatible = "microchip,at91sam9g45-usart-spi"},
 469         { /* sentinel */}
 470 };
 471
 472 MODULE_DEVICE_TABLE(of, at91_usart_spi_dt_ids);
 473
 474 static struct platform_driver at91_usart_spi_driver = {
 475         .driver = {
 476                 .name = "at91_usart_spi",
 477                 .pm = &at91_usart_spi_pm_ops,
 478         },
 479         .probe = at91_usart_spi_probe,
 480         .remove = at91_usart_spi_remove,
 481 };
 482
 483 module_platform_driver(at91_usart_spi_driver);
 484
 485 MODULE_DESCRIPTION("Microchip AT91 USART SPI Controller driver");
 486 MODULE_AUTHOR("Radu Pirea <radu.pirea@microchip.com>");
 487 MODULE_LICENSE("GPL v2");
 488 MODULE_ALIAS("platform:at91_usart_spi");