drivers/spi/spi-amd.c

   1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2 //
   3 // AMD SPI controller driver
   4 //
   5 // Copyright (c) 2020, Advanced Micro Devices, Inc.
   6 //
   7 // Author: Sanjay R Mehta <sanju.mehta@amd.com>
   8
   9 #include <linux/acpi.h>
  10 #include <linux/init.h>
  11 #include <linux/module.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/delay.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/iopoll.h>
  16
  17 #define AMD_SPI_CTRL0_REG       0x00
  18 #define AMD_SPI_EXEC_CMD        BIT(16)
  19 #define AMD_SPI_FIFO_CLEAR      BIT(20)
  20 #define AMD_SPI_BUSY            BIT(31)
  21
  22 #define AMD_SPI_OPCODE_REG      0x45
  23 #define AMD_SPI_CMD_TRIGGER_REG 0x47
  24 #define AMD_SPI_TRIGGER_CMD     BIT(7)
  25
  26 #define AMD_SPI_OPCODE_MASK     0xFF
  27
  28 #define AMD_SPI_ALT_CS_REG      0x1D
  29 #define AMD_SPI_ALT_CS_MASK     0x3
  30
  31 #define AMD_SPI_FIFO_BASE       0x80
  32 #define AMD_SPI_TX_COUNT_REG    0x48
  33 #define AMD_SPI_RX_COUNT_REG    0x4B
  34 #define AMD_SPI_STATUS_REG      0x4C
  35
  36 #define AMD_SPI_FIFO_SIZE       70
  37 #define AMD_SPI_MEM_SIZE        200
  38
  39 #define AMD_SPI_ENA_REG         0x20
  40 #define AMD_SPI_ALT_SPD_SHIFT   20
  41 #define AMD_SPI_ALT_SPD_MASK    GENMASK(23, AMD_SPI_ALT_SPD_SHIFT)
  42 #define AMD_SPI_SPI100_SHIFT    0
  43 #define AMD_SPI_SPI100_MASK     GENMASK(AMD_SPI_SPI100_SHIFT, AMD_SPI_SPI100_SHIFT)
  44 #define AMD_SPI_SPEED_REG       0x6C
  45 #define AMD_SPI_SPD7_SHIFT      8
  46 #define AMD_SPI_SPD7_MASK       GENMASK(13, AMD_SPI_SPD7_SHIFT)
  47
  48 #define AMD_SPI_MAX_HZ          100000000
  49 #define AMD_SPI_MIN_HZ          800000
  50
  51 /**
  52  * enum amd_spi_versions - SPI controller versions
  53  * @AMD_SPI_V1:         AMDI0061 hardware version
  54  * @AMD_SPI_V2:         AMDI0062 hardware version
  55  */
  56 enum amd_spi_versions {
  57         AMD_SPI_V1 = 1,
  58         AMD_SPI_V2,
  59 };
  60
  61 enum amd_spi_speed {
  62         F_66_66MHz,
  63         F_33_33MHz,
  64         F_22_22MHz,
  65         F_16_66MHz,
  66         F_100MHz,
  67         F_800KHz,
  68         SPI_SPD7 = 0x7,
  69         F_50MHz = 0x4,
  70         F_4MHz = 0x32,
  71         F_3_17MHz = 0x3F
  72 };
  73
  74 /**
  75  * struct amd_spi_freq - Matches device speed with values to write in regs
  76  * @speed_hz: Device frequency
  77  * @enable_val: Value to be written to "enable register"
  78  * @spd7_val: Some frequencies requires to have a value written at SPISPEED register
  79  */
  80 struct amd_spi_freq {
  81         u32 speed_hz;
  82         u32 enable_val;
  83         u32 spd7_val;
  84 };
  85
  86 /**
  87  * struct amd_spi - SPI driver instance
  88  * @io_remap_addr:      Start address of the SPI controller registers
  89  * @version:            SPI controller hardware version
  90  * @speed_hz:           Device frequency
  91  */
  92 struct amd_spi {
  93         void __iomem *io_remap_addr;
  94         enum amd_spi_versions version;
  95         unsigned int speed_hz;
  96 };
  97
  98 static inline u8 amd_spi_readreg8(struct amd_spi *amd_spi, int idx)
  99 {
 100         return ioread8((u8 __iomem *)amd_spi->io_remap_addr + idx);
 101 }
 102
 103 static inline void amd_spi_writereg8(struct amd_spi *amd_spi, int idx, u8 val)
 104 {
 105         iowrite8(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
 106 }
 107
 108 static void amd_spi_setclear_reg8(struct amd_spi *amd_spi, int idx, u8 set, u8 clear)
 109 {
 110         u8 tmp = amd_spi_readreg8(amd_spi, idx);
 111
 112         tmp = (tmp & ~clear) | set;
 113         amd_spi_writereg8(amd_spi, idx, tmp);
 114 }
 115
 116 static inline u32 amd_spi_readreg32(struct amd_spi *amd_spi, int idx)
 117 {
 118         return ioread32((u8 __iomem *)amd_spi->io_remap_addr + idx);
 119 }
 120
 121 static inline void amd_spi_writereg32(struct amd_spi *amd_spi, int idx, u32 val)
 122 {
 123         iowrite32(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
 124 }
 125
 126 static inline void amd_spi_setclear_reg32(struct amd_spi *amd_spi, int idx, u32 set, u32 clear)
 127 {
 128         u32 tmp = amd_spi_readreg32(amd_spi, idx);
 129
 130         tmp = (tmp & ~clear) | set;
 131         amd_spi_writereg32(amd_spi, idx, tmp);
 132 }
 133
 134 static void amd_spi_select_chip(struct amd_spi *amd_spi, u8 cs)
 135 {
 136         amd_spi_setclear_reg8(amd_spi, AMD_SPI_ALT_CS_REG, cs, AMD_SPI_ALT_CS_MASK);
 137 }
 138
 139 static inline void amd_spi_clear_chip(struct amd_spi *amd_spi, u8 chip_select)
 140 {
 141         amd_spi_writereg8(amd_spi, AMD_SPI_ALT_CS_REG, chip_select & ~AMD_SPI_ALT_CS_MASK);
 142 }
 143
 144 static void amd_spi_clear_fifo_ptr(struct amd_spi *amd_spi)
 145 {
 146         amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR, AMD_SPI_FIFO_CLEAR);
 147 }
 148
 149 static int amd_spi_set_opcode(struct amd_spi *amd_spi, u8 cmd_opcode)
 150 {
 151         switch (amd_spi->version) {
 152         case AMD_SPI_V1:
 153                 amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, cmd_opcode,
 154                                        AMD_SPI_OPCODE_MASK);
 155                 return 0;
 156         case AMD_SPI_V2:
 157                 amd_spi_writereg8(amd_spi, AMD_SPI_OPCODE_REG, cmd_opcode);
 158                 return 0;
 159         default:
 160                 return -ENODEV;
 161         }
 162 }
 163
 164 static inline void amd_spi_set_rx_count(struct amd_spi *amd_spi, u8 rx_count)
 165 {
 166         amd_spi_setclear_reg8(amd_spi, AMD_SPI_RX_COUNT_REG, rx_count, 0xff);
 167 }
 168
 169 static inline void amd_spi_set_tx_count(struct amd_spi *amd_spi, u8 tx_count)
 170 {
 171         amd_spi_setclear_reg8(amd_spi, AMD_SPI_TX_COUNT_REG, tx_count, 0xff);
 172 }
 173
 174 static int amd_spi_busy_wait(struct amd_spi *amd_spi)
 175 {
 176         u32 val;
 177         int reg;
 178
 179         switch (amd_spi->version) {
 180         case AMD_SPI_V1:
 181                 reg = AMD_SPI_CTRL0_REG;
 182                 break;
 183         case AMD_SPI_V2:
 184                 reg = AMD_SPI_STATUS_REG;
 185                 break;
 186         default:
 187                 return -ENODEV;
 188         }
 189
 190         return readl_poll_timeout(amd_spi->io_remap_addr + reg, val,
 191                                   !(val & AMD_SPI_BUSY), 20, 2000000);
 192 }
 193
 194 static int amd_spi_execute_opcode(struct amd_spi *amd_spi)
 195 {
 196         int ret;
 197
 198         ret = amd_spi_busy_wait(amd_spi);
 199         if (ret)
 200                 return ret;
 201
 202         switch (amd_spi->version) {
 203         case AMD_SPI_V1:
 204                 /* Set ExecuteOpCode bit in the CTRL0 register */
 205                 amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD,
 206                                        AMD_SPI_EXEC_CMD);
 207                 return 0;
 208         case AMD_SPI_V2:
 209                 /* Trigger the command execution */
 210                 amd_spi_setclear_reg8(amd_spi, AMD_SPI_CMD_TRIGGER_REG,
 211                                       AMD_SPI_TRIGGER_CMD, AMD_SPI_TRIGGER_CMD);
 212                 return 0;
 213         default:
 214                 return -ENODEV;
 215         }
 216 }
 217
 218 static int amd_spi_host_setup(struct spi_device *spi)
 219 {
 220         struct amd_spi *amd_spi = spi_controller_get_devdata(spi->controller);
 221
 222         amd_spi_clear_fifo_ptr(amd_spi);
 223
 224         return 0;
 225 }
 226
 227 static const struct amd_spi_freq amd_spi_freq[] = {
 228         { AMD_SPI_MAX_HZ,   F_100MHz,         0},
 229         {       66660000, F_66_66MHz,         0},
 230         {       50000000,   SPI_SPD7,   F_50MHz},
 231         {       33330000, F_33_33MHz,         0},
 232         {       22220000, F_22_22MHz,         0},
 233         {       16660000, F_16_66MHz,         0},
 234         {        4000000,   SPI_SPD7,    F_4MHz},
 235         {        3170000,   SPI_SPD7, F_3_17MHz},
 236         { AMD_SPI_MIN_HZ,   F_800KHz,         0},
 237 };
 238
 239 static int amd_set_spi_freq(struct amd_spi *amd_spi, u32 speed_hz)
 240 {
 241         unsigned int i, spd7_val, alt_spd;
 242
 243         if (speed_hz < AMD_SPI_MIN_HZ)
 244                 return -EINVAL;
 245
 246         for (i = 0; i < ARRAY_SIZE(amd_spi_freq); i++)
 247                 if (speed_hz >= amd_spi_freq[i].speed_hz)
 248                         break;
 249
 250         if (amd_spi->speed_hz == amd_spi_freq[i].speed_hz)
 251                 return 0;
 252
 253         amd_spi->speed_hz = amd_spi_freq[i].speed_hz;
 254
 255         alt_spd = (amd_spi_freq[i].enable_val << AMD_SPI_ALT_SPD_SHIFT)
 256                    & AMD_SPI_ALT_SPD_MASK;
 257         amd_spi_setclear_reg32(amd_spi, AMD_SPI_ENA_REG, alt_spd,
 258                                AMD_SPI_ALT_SPD_MASK);
 259
 260         if (amd_spi->speed_hz == AMD_SPI_MAX_HZ)
 261                 amd_spi_setclear_reg32(amd_spi, AMD_SPI_ENA_REG, 1,
 262                                        AMD_SPI_SPI100_MASK);
 263
 264         if (amd_spi_freq[i].spd7_val) {
 265                 spd7_val = (amd_spi_freq[i].spd7_val << AMD_SPI_SPD7_SHIFT)
 266                             & AMD_SPI_SPD7_MASK;
 267                 amd_spi_setclear_reg32(amd_spi, AMD_SPI_SPEED_REG, spd7_val,
 268                                        AMD_SPI_SPD7_MASK);
 269         }
 270
 271         return 0;
 272 }
 273
 274 static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi,
 275                                     struct spi_controller *host,
 276                                     struct spi_message *message)
 277 {
 278         struct spi_transfer *xfer = NULL;
 279         struct spi_device *spi = message->spi;
 280         u8 cmd_opcode = 0, fifo_pos = AMD_SPI_FIFO_BASE;
 281         u8 *buf = NULL;
 282         u32 i = 0;
 283         u32 tx_len = 0, rx_len = 0;
 284
 285         list_for_each_entry(xfer, &message->transfers,
 286                             transfer_list) {
 287                 if (xfer->speed_hz)
 288                         amd_set_spi_freq(amd_spi, xfer->speed_hz);
 289                 else
 290                         amd_set_spi_freq(amd_spi, spi->max_speed_hz);
 291
 292                 if (xfer->tx_buf) {
 293                         buf = (u8 *)xfer->tx_buf;
 294                         if (!tx_len) {
 295                                 cmd_opcode = *(u8 *)xfer->tx_buf;
 296                                 buf++;
 297                                 xfer->len--;
 298                         }
 299                         tx_len += xfer->len;
 300
 301                         /* Write data into the FIFO. */
 302                         for (i = 0; i < xfer->len; i++)
 303                                 amd_spi_writereg8(amd_spi, fifo_pos + i, buf[i]);
 304
 305                         fifo_pos += xfer->len;
 306                 }
 307
 308                 /* Store no. of bytes to be received from FIFO */
 309                 if (xfer->rx_buf)
 310                         rx_len += xfer->len;
 311         }
 312
 313         if (!buf) {
 314                 message->status = -EINVAL;
 315                 goto fin_msg;
 316         }
 317
 318         amd_spi_set_opcode(amd_spi, cmd_opcode);
 319         amd_spi_set_tx_count(amd_spi, tx_len);
 320         amd_spi_set_rx_count(amd_spi, rx_len);
 321
 322         /* Execute command */
 323         message->status = amd_spi_execute_opcode(amd_spi);
 324         if (message->status)
 325                 goto fin_msg;
 326
 327         if (rx_len) {
 328                 message->status = amd_spi_busy_wait(amd_spi);
 329                 if (message->status)
 330                         goto fin_msg;
 331
 332                 list_for_each_entry(xfer, &message->transfers, transfer_list)
 333                         if (xfer->rx_buf) {
 334                                 buf = (u8 *)xfer->rx_buf;
 335                                 /* Read data from FIFO to receive buffer */
 336                                 for (i = 0; i < xfer->len; i++)
 337                                         buf[i] = amd_spi_readreg8(amd_spi, fifo_pos + i);
 338                                 fifo_pos += xfer->len;
 339                         }
 340         }
 341
 342         /* Update statistics */
 343         message->actual_length = tx_len + rx_len + 1;
 344
 345 fin_msg:
 346         switch (amd_spi->version) {
 347         case AMD_SPI_V1:
 348                 break;
 349         case AMD_SPI_V2:
 350                 amd_spi_clear_chip(amd_spi, spi_get_chipselect(message->spi, 0));
 351                 break;
 352         default:
 353                 return -ENODEV;
 354         }
 355
 356         spi_finalize_current_message(host);
 357
 358         return message->status;
 359 }
 360
 361 static int amd_spi_host_transfer(struct spi_controller *host,
 362                                    struct spi_message *msg)
 363 {
 364         struct amd_spi *amd_spi = spi_controller_get_devdata(host);
 365         struct spi_device *spi = msg->spi;
 366
 367         amd_spi_select_chip(amd_spi, spi_get_chipselect(spi, 0));
 368
 369         /*
 370          * Extract spi_transfers from the spi message and
 371          * program the controller.
 372          */
 373         return amd_spi_fifo_xfer(amd_spi, host, msg);
 374 }
 375
 376 static size_t amd_spi_max_transfer_size(struct spi_device *spi)
 377 {
 378         return AMD_SPI_FIFO_SIZE;
 379 }
 380
 381 static int amd_spi_probe(struct platform_device *pdev)
 382 {
 383         struct device *dev = &pdev->dev;
 384         struct spi_controller *host;
 385         struct amd_spi *amd_spi;
 386         int err;
 387
 388         /* Allocate storage for host and driver private data */
 389         host = devm_spi_alloc_host(dev, sizeof(struct amd_spi));
 390         if (!host)
 391                 return dev_err_probe(dev, -ENOMEM, "Error allocating SPI host\n");
 392
 393         amd_spi = spi_controller_get_devdata(host);
 394         amd_spi->io_remap_addr = devm_platform_ioremap_resource(pdev, 0);
 395         if (IS_ERR(amd_spi->io_remap_addr))
 396                 return dev_err_probe(dev, PTR_ERR(amd_spi->io_remap_addr),
 397                                      "ioremap of SPI registers failed\n");
 398
 399         dev_dbg(dev, "io_remap_address: %p\n", amd_spi->io_remap_addr);
 400
 401         amd_spi->version = (uintptr_t) device_get_match_data(dev);
 402
 403         /* Initialize the spi_controller fields */
 404         host->bus_num = 0;
 405         host->num_chipselect = 4;
 406         host->mode_bits = 0;
 407         host->flags = SPI_CONTROLLER_HALF_DUPLEX;
 408         host->max_speed_hz = AMD_SPI_MAX_HZ;
 409         host->min_speed_hz = AMD_SPI_MIN_HZ;
 410         host->setup = amd_spi_host_setup;
 411         host->transfer_one_message = amd_spi_host_transfer;
 412         host->max_transfer_size = amd_spi_max_transfer_size;
 413         host->max_message_size = amd_spi_max_transfer_size;
 414
 415         /* Register the controller with SPI framework */
 416         err = devm_spi_register_controller(dev, host);
 417         if (err)
 418                 return dev_err_probe(dev, err, "error registering SPI controller\n");
 419
 420         return 0;
 421 }
 422
 423 #ifdef CONFIG_ACPI
 424 static const struct acpi_device_id spi_acpi_match[] = {
 425         { "AMDI0061", AMD_SPI_V1 },
 426         { "AMDI0062", AMD_SPI_V2 },
 427         {},
 428 };
 429 MODULE_DEVICE_TABLE(acpi, spi_acpi_match);
 430 #endif
 431
 432 static struct platform_driver amd_spi_driver = {
 433         .driver = {
 434                 .name = "amd_spi",
 435                 .acpi_match_table = ACPI_PTR(spi_acpi_match),
 436         },
 437         .probe = amd_spi_probe,
 438 };
 439
 440 module_platform_driver(amd_spi_driver);
 441
 442 MODULE_LICENSE("Dual BSD/GPL");
 443 MODULE_AUTHOR("Sanjay Mehta <sanju.mehta@amd.com>");
 444 MODULE_DESCRIPTION("AMD SPI Master Controller Driver");