drivers/soundwire/qcom.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2019, Linaro Limited
   3
   4 #include <linux/clk.h>
   5 #include <linux/completion.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/io.h>
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/debugfs.h>
  11 #include <linux/of.h>
  12 #include <linux/of_irq.h>
  13 #include <linux/of_device.h>
  14 #include <linux/regmap.h>
  15 #include <linux/slab.h>
  16 #include <linux/slimbus.h>
  17 #include <linux/soundwire/sdw.h>
  18 #include <linux/soundwire/sdw_registers.h>
  19 #include <sound/pcm_params.h>
  20 #include <sound/soc.h>
  21 #include "bus.h"
  22
  23 #define SWRM_COMP_HW_VERSION                                    0x00
  24 #define SWRM_COMP_CFG_ADDR                                      0x04
  25 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK                    BIT(1)
  26 #define SWRM_COMP_CFG_ENABLE_MSK                                BIT(0)
  27 #define SWRM_COMP_PARAMS                                        0x100
  28 #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH                          GENMASK(14, 10)
  29 #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH                          GENMASK(19, 15)
  30 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK                        GENMASK(4, 0)
  31 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK                         GENMASK(9, 5)
  32 #define SWRM_INTERRUPT_STATUS                                   0x200
  33 #define SWRM_INTERRUPT_STATUS_RMSK                              GENMASK(16, 0)
  34 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ                    BIT(0)
  35 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED                BIT(1)
  36 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS          BIT(2)
  37 #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET                  BIT(3)
  38 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW                  BIT(4)
  39 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW                 BIT(5)
  40 #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW              BIT(6)
  41 #define SWRM_INTERRUPT_STATUS_CMD_ERROR                         BIT(7)
  42 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION               BIT(8)
  43 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH         BIT(9)
  44 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED           BIT(10)
  45 #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2             BIT(13)
  46 #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2              BIT(14)
  47 #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP               BIT(16)
  48 #define SWRM_INTERRUPT_MAX                                      17
  49 #define SWRM_INTERRUPT_MASK_ADDR                                0x204
  50 #define SWRM_INTERRUPT_CLEAR                                    0x208
  51 #define SWRM_INTERRUPT_CPU_EN                                   0x210
  52 #define SWRM_CMD_FIFO_WR_CMD                                    0x300
  53 #define SWRM_CMD_FIFO_RD_CMD                                    0x304
  54 #define SWRM_CMD_FIFO_CMD                                       0x308
  55 #define SWRM_CMD_FIFO_FLUSH                                     0x1
  56 #define SWRM_CMD_FIFO_STATUS                                    0x30C
  57 #define SWRM_RD_CMD_FIFO_CNT_MASK                               GENMASK(20, 16)
  58 #define SWRM_WR_CMD_FIFO_CNT_MASK                               GENMASK(12, 8)
  59 #define SWRM_CMD_FIFO_CFG_ADDR                                  0x314
  60 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE                        BIT(31)
  61 #define SWRM_RD_WR_CMD_RETRIES                                  0x7
  62 #define SWRM_CMD_FIFO_RD_FIFO_ADDR                              0x318
  63 #define SWRM_RD_FIFO_CMD_ID_MASK                                GENMASK(11, 8)
  64 #define SWRM_ENUMERATOR_CFG_ADDR                                0x500
  65 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m)               (0x530 + 0x8 * (m))
  66 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m)               (0x534 + 0x8 * (m))
  67 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m)                (0x101C + 0x40 * (m))
  68 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK                  GENMASK(2, 0)
  69 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK                  GENMASK(7, 3)
  70 #define SWRM_MCP_BUS_CTRL                                       0x1044
  71 #define SWRM_MCP_BUS_CLK_START                                  BIT(1)
  72 #define SWRM_MCP_CFG_ADDR                                       0x1048
  73 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK               GENMASK(21, 17)
  74 #define SWRM_DEF_CMD_NO_PINGS                                   0x1f
  75 #define SWRM_MCP_STATUS                                         0x104C
  76 #define SWRM_MCP_STATUS_BANK_NUM_MASK                           BIT(0)
  77 #define SWRM_MCP_SLV_STATUS                                     0x1090
  78 #define SWRM_MCP_SLV_STATUS_MASK                                GENMASK(1, 0)
  79 #define SWRM_MCP_SLV_STATUS_SZ                                  2
  80 #define SWRM_DP_PORT_CTRL_BANK(n, m)    (0x1124 + 0x100 * (n - 1) + 0x40 * m)
  81 #define SWRM_DP_PORT_CTRL_2_BANK(n, m)  (0x1128 + 0x100 * (n - 1) + 0x40 * m)
  82 #define SWRM_DP_BLOCK_CTRL_1(n)         (0x112C + 0x100 * (n - 1))
  83 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m)  (0x1130 + 0x100 * (n - 1) + 0x40 * m)
  84 #define SWRM_DP_PORT_HCTRL_BANK(n, m)   (0x1134 + 0x100 * (n - 1) + 0x40 * m)
  85 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m)  (0x1138 + 0x100 * (n - 1) + 0x40 * m)
  86 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n)   (0x1054 + 0x100 * (n - 1))
  87 #define SWR_MSTR_MAX_REG_ADDR           (0x1740)
  88
  89 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT                          0x18
  90 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT                          0x10
  91 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT                          0x08
  92 #define SWRM_AHB_BRIDGE_WR_DATA_0                               0xc85
  93 #define SWRM_AHB_BRIDGE_WR_ADDR_0                               0xc89
  94 #define SWRM_AHB_BRIDGE_RD_ADDR_0                               0xc8d
  95 #define SWRM_AHB_BRIDGE_RD_DATA_0                               0xc91
  96
  97 #define SWRM_REG_VAL_PACK(data, dev, id, reg)   \
  98                         ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
  99
 100 #define SWRM_SPECIAL_CMD_ID     0xF
 101 #define MAX_FREQ_NUM            1
 102 #define TIMEOUT_MS              (2 * HZ)
 103 #define QCOM_SWRM_MAX_RD_LEN    0x1
 104 #define QCOM_SDW_MAX_PORTS      14
 105 #define DEFAULT_CLK_FREQ        9600000
 106 #define SWRM_MAX_DAIS           0xF
 107 #define SWR_INVALID_PARAM 0xFF
 108 #define SWR_HSTOP_MAX_VAL 0xF
 109 #define SWR_HSTART_MIN_VAL 0x0
 110 #define SWR_BROADCAST_CMD_ID    0x0F
 111 #define SWR_MAX_CMD_ID  14
 112 #define MAX_FIFO_RD_RETRY 3
 113 #define SWR_OVERFLOW_RETRY_COUNT 30
 114
 115 struct qcom_swrm_port_config {
 116         u8 si;
 117         u8 off1;
 118         u8 off2;
 119         u8 bp_mode;
 120         u8 hstart;
 121         u8 hstop;
 122         u8 word_length;
 123         u8 blk_group_count;
 124         u8 lane_control;
 125 };
 126
 127 struct qcom_swrm_ctrl {
 128         struct sdw_bus bus;
 129         struct device *dev;
 130         struct regmap *regmap;
 131         void __iomem *mmio;
 132 #ifdef CONFIG_DEBUG_FS
 133         struct dentry *debugfs;
 134 #endif
 135         struct completion broadcast;
 136         struct completion enumeration;
 137         struct work_struct slave_work;
 138         /* Port alloc/free lock */
 139         struct mutex port_lock;
 140         struct clk *hclk;
 141         u8 wr_cmd_id;
 142         u8 rd_cmd_id;
 143         int irq;
 144         unsigned int version;
 145         int num_din_ports;
 146         int num_dout_ports;
 147         int cols_index;
 148         int rows_index;
 149         unsigned long dout_port_mask;
 150         unsigned long din_port_mask;
 151         u32 intr_mask;
 152         u8 rcmd_id;
 153         u8 wcmd_id;
 154         struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS];
 155         struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
 156         enum sdw_slave_status status[SDW_MAX_DEVICES];
 157         int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
 158         int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
 159         u32 slave_status;
 160         u32 wr_fifo_depth;
 161         u32 rd_fifo_depth;
 162 };
 163
 164 struct qcom_swrm_data {
 165         u32 default_cols;
 166         u32 default_rows;
 167 };
 168
 169 static struct qcom_swrm_data swrm_v1_3_data = {
 170         .default_rows = 48,
 171         .default_cols = 16,
 172 };
 173
 174 static struct qcom_swrm_data swrm_v1_5_data = {
 175         .default_rows = 50,
 176         .default_cols = 16,
 177 };
 178
 179 #define to_qcom_sdw(b)  container_of(b, struct qcom_swrm_ctrl, bus)
 180
 181 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
 182                                   u32 *val)
 183 {
 184         struct regmap *wcd_regmap = ctrl->regmap;
 185         int ret;
 186
 187         /* pg register + offset */
 188         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0,
 189                           (u8 *)&reg, 4);
 190         if (ret < 0)
 191                 return SDW_CMD_FAIL;
 192
 193         ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0,
 194                                val, 4);
 195         if (ret < 0)
 196                 return SDW_CMD_FAIL;
 197
 198         return SDW_CMD_OK;
 199 }
 200
 201 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
 202                                    int reg, int val)
 203 {
 204         struct regmap *wcd_regmap = ctrl->regmap;
 205         int ret;
 206         /* pg register + offset */
 207         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0,
 208                           (u8 *)&val, 4);
 209         if (ret)
 210                 return SDW_CMD_FAIL;
 211
 212         /* write address register */
 213         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0,
 214                           (u8 *)&reg, 4);
 215         if (ret)
 216                 return SDW_CMD_FAIL;
 217
 218         return SDW_CMD_OK;
 219 }
 220
 221 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
 222                                   u32 *val)
 223 {
 224         *val = readl(ctrl->mmio + reg);
 225         return SDW_CMD_OK;
 226 }
 227
 228 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
 229                                    int val)
 230 {
 231         writel(val, ctrl->mmio + reg);
 232         return SDW_CMD_OK;
 233 }
 234
 235 static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
 236                                    u8 dev_addr, u16 reg_addr)
 237 {
 238         u32 val;
 239         u8 id = *cmd_id;
 240
 241         if (id != SWR_BROADCAST_CMD_ID) {
 242                 if (id < SWR_MAX_CMD_ID)
 243                         id += 1;
 244                 else
 245                         id = 0;
 246                 *cmd_id = id;
 247         }
 248         val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
 249
 250         return val;
 251 }
 252
 253 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm)
 254 {
 255         u32 fifo_outstanding_data, value;
 256         int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 257
 258         do {
 259                 /* Check for fifo underflow during read */
 260                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 261                 fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
 262
 263                 /* Check if read data is available in read fifo */
 264                 if (fifo_outstanding_data > 0)
 265                         return 0;
 266
 267                 usleep_range(500, 510);
 268         } while (fifo_retry_count--);
 269
 270         if (fifo_outstanding_data == 0) {
 271                 dev_err_ratelimited(swrm->dev, "%s err read underflow\n", __func__);
 272                 return -EIO;
 273         }
 274
 275         return 0;
 276 }
 277
 278 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *swrm)
 279 {
 280         u32 fifo_outstanding_cmds, value;
 281         int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 282
 283         do {
 284                 /* Check for fifo overflow during write */
 285                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 286                 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
 287
 288                 /* Check for space in write fifo before writing */
 289                 if (fifo_outstanding_cmds < swrm->wr_fifo_depth)
 290                         return 0;
 291
 292                 usleep_range(500, 510);
 293         } while (fifo_retry_count--);
 294
 295         if (fifo_outstanding_cmds == swrm->wr_fifo_depth) {
 296                 dev_err_ratelimited(swrm->dev, "%s err write overflow\n", __func__);
 297                 return -EIO;
 298         }
 299
 300         return 0;
 301 }
 302
 303 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data,
 304                                      u8 dev_addr, u16 reg_addr)
 305 {
 306
 307         u32 val;
 308         int ret = 0;
 309         u8 cmd_id = 0x0;
 310
 311         if (dev_addr == SDW_BROADCAST_DEV_NUM) {
 312                 cmd_id = SWR_BROADCAST_CMD_ID;
 313                 val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
 314                                               dev_addr, reg_addr);
 315         } else {
 316                 val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data,
 317                                               dev_addr, reg_addr);
 318         }
 319
 320         if (swrm_wait_for_wr_fifo_avail(swrm))
 321                 return SDW_CMD_FAIL_OTHER;
 322
 323         /* Its assumed that write is okay as we do not get any status back */
 324         swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val);
 325
 326         /* version 1.3 or less */
 327         if (swrm->version <= 0x01030000)
 328                 usleep_range(150, 155);
 329
 330         if (cmd_id == SWR_BROADCAST_CMD_ID) {
 331                 /*
 332                  * sleep for 10ms for MSM soundwire variant to allow broadcast
 333                  * command to complete.
 334                  */
 335                 ret = wait_for_completion_timeout(&swrm->broadcast,
 336                                                   msecs_to_jiffies(TIMEOUT_MS));
 337                 if (!ret)
 338                         ret = SDW_CMD_IGNORED;
 339                 else
 340                         ret = SDW_CMD_OK;
 341
 342         } else {
 343                 ret = SDW_CMD_OK;
 344         }
 345         return ret;
 346 }
 347
 348 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm,
 349                                      u8 dev_addr, u16 reg_addr,
 350                                      u32 len, u8 *rval)
 351 {
 352         u32 cmd_data, cmd_id, val, retry_attempt = 0;
 353
 354         val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr);
 355
 356         /* wait for FIFO RD to complete to avoid overflow */
 357         usleep_range(100, 105);
 358         swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
 359         /* wait for FIFO RD CMD complete to avoid overflow */
 360         usleep_range(250, 255);
 361
 362         if (swrm_wait_for_rd_fifo_avail(swrm))
 363                 return SDW_CMD_FAIL_OTHER;
 364
 365         do {
 366                 swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data);
 367                 rval[0] = cmd_data & 0xFF;
 368                 cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data);
 369
 370                 if (cmd_id != swrm->rcmd_id) {
 371                         if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) {
 372                                 /* wait 500 us before retry on fifo read failure */
 373                                 usleep_range(500, 505);
 374                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD,
 375                                                 SWRM_CMD_FIFO_FLUSH);
 376                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
 377                         }
 378                         retry_attempt++;
 379                 } else {
 380                         return SDW_CMD_OK;
 381                 }
 382
 383         } while (retry_attempt < MAX_FIFO_RD_RETRY);
 384
 385         dev_err(swrm->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
 386                 dev_num: 0x%x, cmd_data: 0x%x\n",
 387                 reg_addr, swrm->rcmd_id, dev_addr, cmd_data);
 388
 389         return SDW_CMD_IGNORED;
 390 }
 391
 392 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl)
 393 {
 394         u32 val, status;
 395         int dev_num;
 396
 397         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
 398
 399         for (dev_num = 0; dev_num < SDW_MAX_DEVICES; dev_num++) {
 400                 status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ));
 401
 402                 if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) {
 403                         ctrl->status[dev_num] = status;
 404                         return dev_num;
 405                 }
 406         }
 407
 408         return -EINVAL;
 409 }
 410
 411 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
 412 {
 413         u32 val;
 414         int i;
 415
 416         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
 417         ctrl->slave_status = val;
 418
 419         for (i = 0; i < SDW_MAX_DEVICES; i++) {
 420                 u32 s;
 421
 422                 s = (val >> (i * 2));
 423                 s &= SWRM_MCP_SLV_STATUS_MASK;
 424                 ctrl->status[i] = s;
 425         }
 426 }
 427
 428 static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus,
 429                                         struct sdw_slave *slave, int devnum)
 430 {
 431         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 432         u32 status;
 433
 434         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status);
 435         status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ));
 436         status &= SWRM_MCP_SLV_STATUS_MASK;
 437
 438         if (status == SDW_SLAVE_ATTACHED) {
 439                 if (slave)
 440                         slave->dev_num = devnum;
 441                 mutex_lock(&bus->bus_lock);
 442                 set_bit(devnum, bus->assigned);
 443                 mutex_unlock(&bus->bus_lock);
 444         }
 445 }
 446
 447 static int qcom_swrm_enumerate(struct sdw_bus *bus)
 448 {
 449         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 450         struct sdw_slave *slave, *_s;
 451         struct sdw_slave_id id;
 452         u32 val1, val2;
 453         bool found;
 454         u64 addr;
 455         int i;
 456         char *buf1 = (char *)&val1, *buf2 = (char *)&val2;
 457
 458         for (i = 1; i <= SDW_MAX_DEVICES; i++) {
 459                 /*SCP_Devid5 - Devid 4*/
 460                 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1);
 461
 462                 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/
 463                 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2);
 464
 465                 if (!val1 && !val2)
 466                         break;
 467
 468                 addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) |
 469                         ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) |
 470                         ((u64)buf1[0] << 40);
 471
 472                 sdw_extract_slave_id(bus, addr, &id);
 473                 found = false;
 474                 /* Now compare with entries */
 475                 list_for_each_entry_safe(slave, _s, &bus->slaves, node) {
 476                         if (sdw_compare_devid(slave, id) == 0) {
 477                                 qcom_swrm_set_slave_dev_num(bus, slave, i);
 478                                 found = true;
 479                                 break;
 480                         }
 481                 }
 482
 483                 if (!found) {
 484                         qcom_swrm_set_slave_dev_num(bus, NULL, i);
 485                         sdw_slave_add(bus, &id, NULL);
 486                 }
 487         }
 488
 489         complete(&ctrl->enumeration);
 490         return 0;
 491 }
 492
 493 static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
 494 {
 495         struct qcom_swrm_ctrl *swrm = dev_id;
 496         u32 value, intr_sts, intr_sts_masked, slave_status;
 497         u32 i;
 498         int devnum;
 499         int ret = IRQ_HANDLED;
 500
 501         swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
 502         intr_sts_masked = intr_sts & swrm->intr_mask;
 503
 504         do {
 505                 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
 506                         value = intr_sts_masked & BIT(i);
 507                         if (!value)
 508                                 continue;
 509
 510                         switch (value) {
 511                         case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
 512                                 devnum = qcom_swrm_get_alert_slave_dev_num(swrm);
 513                                 if (devnum < 0) {
 514                                         dev_err_ratelimited(swrm->dev,
 515                                             "no slave alert found.spurious interrupt\n");
 516                                 } else {
 517                                         sdw_handle_slave_status(&swrm->bus, swrm->status);
 518                                 }
 519
 520                                 break;
 521                         case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
 522                         case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
 523                                 dev_err_ratelimited(swrm->dev, "%s: SWR new slave attached\n",
 524                                         __func__);
 525                                 swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status);
 526                                 if (swrm->slave_status == slave_status) {
 527                                         dev_err(swrm->dev, "Slave status not changed %x\n",
 528                                                 slave_status);
 529                                 } else {
 530                                         qcom_swrm_get_device_status(swrm);
 531                                         qcom_swrm_enumerate(&swrm->bus);
 532                                         sdw_handle_slave_status(&swrm->bus, swrm->status);
 533                                 }
 534                                 break;
 535                         case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
 536                                 dev_err_ratelimited(swrm->dev,
 537                                                 "%s: SWR bus clsh detected\n",
 538                                                 __func__);
 539                                 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
 540                                 swrm->reg_write(swrm, SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
 541                                 break;
 542                         case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
 543                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 544                                 dev_err_ratelimited(swrm->dev,
 545                                         "%s: SWR read FIFO overflow fifo status 0x%x\n",
 546                                         __func__, value);
 547                                 break;
 548                         case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
 549                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 550                                 dev_err_ratelimited(swrm->dev,
 551                                         "%s: SWR read FIFO underflow fifo status 0x%x\n",
 552                                         __func__, value);
 553                                 break;
 554                         case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
 555                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 556                                 dev_err(swrm->dev,
 557                                         "%s: SWR write FIFO overflow fifo status %x\n",
 558                                         __func__, value);
 559                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
 560                                 break;
 561                         case SWRM_INTERRUPT_STATUS_CMD_ERROR:
 562                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 563                                 dev_err_ratelimited(swrm->dev,
 564                                         "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n",
 565                                         __func__, value);
 566                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
 567                                 break;
 568                         case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
 569                                 dev_err_ratelimited(swrm->dev,
 570                                                 "%s: SWR Port collision detected\n",
 571                                                 __func__);
 572                                 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
 573                                 swrm->reg_write(swrm,
 574                                         SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
 575                                 break;
 576                         case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
 577                                 dev_err_ratelimited(swrm->dev,
 578                                         "%s: SWR read enable valid mismatch\n",
 579                                         __func__);
 580                                 swrm->intr_mask &=
 581                                         ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
 582                                 swrm->reg_write(swrm,
 583                                         SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
 584                                 break;
 585                         case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
 586                                 complete(&swrm->broadcast);
 587                                 break;
 588                         case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2:
 589                                 break;
 590                         case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2:
 591                                 break;
 592                         case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP:
 593                                 break;
 594                         default:
 595                                 dev_err_ratelimited(swrm->dev,
 596                                                 "%s: SWR unknown interrupt value: %d\n",
 597                                                 __func__, value);
 598                                 ret = IRQ_NONE;
 599                                 break;
 600                         }
 601                 }
 602                 swrm->reg_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts);
 603                 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
 604                 intr_sts_masked = intr_sts & swrm->intr_mask;
 605         } while (intr_sts_masked);
 606
 607         return ret;
 608 }
 609
 610 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
 611 {
 612         u32 val;
 613
 614         /* Clear Rows and Cols */
 615         val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
 616         val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
 617
 618         ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
 619
 620         /* Enable Auto enumeration */
 621         ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
 622
 623         ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK;
 624         /* Mask soundwire interrupts */
 625         ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR,
 626                         SWRM_INTERRUPT_STATUS_RMSK);
 627
 628         /* Configure No pings */
 629         ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
 630         u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
 631         ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
 632
 633         ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
 634         /* Configure number of retries of a read/write cmd */
 635         if (ctrl->version > 0x01050001) {
 636                 /* Only for versions >= 1.5.1 */
 637                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
 638                                 SWRM_RD_WR_CMD_RETRIES |
 639                                 SWRM_CONTINUE_EXEC_ON_CMD_IGNORE);
 640         } else {
 641                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
 642                                 SWRM_RD_WR_CMD_RETRIES);
 643         }
 644
 645         /* Set IRQ to PULSE */
 646         ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
 647                         SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
 648                         SWRM_COMP_CFG_ENABLE_MSK);
 649
 650         /* enable CPU IRQs */
 651         if (ctrl->mmio) {
 652                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN,
 653                                 SWRM_INTERRUPT_STATUS_RMSK);
 654         }
 655         ctrl->slave_status = 0;
 656         ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
 657         ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val);
 658         ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);
 659
 660         return 0;
 661 }
 662
 663 static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus,
 664                                                     struct sdw_msg *msg)
 665 {
 666         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 667         int ret, i, len;
 668
 669         if (msg->flags == SDW_MSG_FLAG_READ) {
 670                 for (i = 0; i < msg->len;) {
 671                         if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN)
 672                                 len = msg->len - i;
 673                         else
 674                                 len = QCOM_SWRM_MAX_RD_LEN;
 675
 676                         ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
 677                                                         msg->addr + i, len,
 678                                                        &msg->buf[i]);
 679                         if (ret)
 680                                 return ret;
 681
 682                         i = i + len;
 683                 }
 684         } else if (msg->flags == SDW_MSG_FLAG_WRITE) {
 685                 for (i = 0; i < msg->len; i++) {
 686                         ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
 687                                                         msg->dev_num,
 688                                                        msg->addr + i);
 689                         if (ret)
 690                                 return SDW_CMD_IGNORED;
 691                 }
 692         }
 693
 694         return SDW_CMD_OK;
 695 }
 696
 697 static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus)
 698 {
 699         u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);
 700         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 701         u32 val;
 702
 703         ctrl->reg_read(ctrl, reg, &val);
 704
 705         u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
 706         u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
 707
 708         return ctrl->reg_write(ctrl, reg, val);
 709 }
 710
 711 static int qcom_swrm_port_params(struct sdw_bus *bus,
 712                                  struct sdw_port_params *p_params,
 713                                  unsigned int bank)
 714 {
 715         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 716
 717         return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),
 718                                p_params->bps - 1);
 719
 720 }
 721
 722 static int qcom_swrm_transport_params(struct sdw_bus *bus,
 723                                       struct sdw_transport_params *params,
 724                                       enum sdw_reg_bank bank)
 725 {
 726         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 727         struct qcom_swrm_port_config *pcfg;
 728         u32 value;
 729         int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank);
 730         int ret;
 731
 732         pcfg = &ctrl->pconfig[params->port_num];
 733
 734         value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
 735         value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
 736         value |= pcfg->si;
 737
 738         ret = ctrl->reg_write(ctrl, reg, value);
 739         if (ret)
 740                 goto err;
 741
 742         if (pcfg->lane_control != SWR_INVALID_PARAM) {
 743                 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank);
 744                 value = pcfg->lane_control;
 745                 ret = ctrl->reg_write(ctrl, reg, value);
 746                 if (ret)
 747                         goto err;
 748         }
 749
 750         if (pcfg->blk_group_count != SWR_INVALID_PARAM) {
 751                 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank);
 752                 value = pcfg->blk_group_count;
 753                 ret = ctrl->reg_write(ctrl, reg, value);
 754                 if (ret)
 755                         goto err;
 756         }
 757
 758         if (pcfg->hstart != SWR_INVALID_PARAM
 759                         && pcfg->hstop != SWR_INVALID_PARAM) {
 760                 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
 761                 value = (pcfg->hstop << 4) | pcfg->hstart;
 762                 ret = ctrl->reg_write(ctrl, reg, value);
 763         } else {
 764                 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
 765                 value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;
 766                 ret = ctrl->reg_write(ctrl, reg, value);
 767         }
 768
 769         if (ret)
 770                 goto err;
 771
 772         if (pcfg->bp_mode != SWR_INVALID_PARAM) {
 773                 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank);
 774                 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
 775         }
 776
 777 err:
 778         return ret;
 779 }
 780
 781 static int qcom_swrm_port_enable(struct sdw_bus *bus,
 782                                  struct sdw_enable_ch *enable_ch,
 783                                  unsigned int bank)
 784 {
 785         u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);
 786         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 787         u32 val;
 788
 789         ctrl->reg_read(ctrl, reg, &val);
 790
 791         if (enable_ch->enable)
 792                 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
 793         else
 794                 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
 795
 796         return ctrl->reg_write(ctrl, reg, val);
 797 }
 798
 799 static const struct sdw_master_port_ops qcom_swrm_port_ops = {
 800         .dpn_set_port_params = qcom_swrm_port_params,
 801         .dpn_set_port_transport_params = qcom_swrm_transport_params,
 802         .dpn_port_enable_ch = qcom_swrm_port_enable,
 803 };
 804
 805 static const struct sdw_master_ops qcom_swrm_ops = {
 806         .xfer_msg = qcom_swrm_xfer_msg,
 807         .pre_bank_switch = qcom_swrm_pre_bank_switch,
 808 };
 809
 810 static int qcom_swrm_compute_params(struct sdw_bus *bus)
 811 {
 812         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 813         struct sdw_master_runtime *m_rt;
 814         struct sdw_slave_runtime *s_rt;
 815         struct sdw_port_runtime *p_rt;
 816         struct qcom_swrm_port_config *pcfg;
 817         struct sdw_slave *slave;
 818         unsigned int m_port;
 819         int i = 1;
 820
 821         list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
 822                 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
 823                         pcfg = &ctrl->pconfig[p_rt->num];
 824                         p_rt->transport_params.port_num = p_rt->num;
 825                         if (pcfg->word_length != SWR_INVALID_PARAM) {
 826                                 sdw_fill_port_params(&p_rt->port_params,
 827                                              p_rt->num,  pcfg->word_length + 1,
 828                                              SDW_PORT_FLOW_MODE_ISOCH,
 829                                              SDW_PORT_DATA_MODE_NORMAL);
 830                         }
 831
 832                 }
 833
 834                 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
 835                         slave = s_rt->slave;
 836                         list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
 837                                 m_port = slave->m_port_map[p_rt->num];
 838                                 /* port config starts at offset 0 so -1 from actual port number */
 839                                 if (m_port)
 840                                         pcfg = &ctrl->pconfig[m_port];
 841                                 else
 842                                         pcfg = &ctrl->pconfig[i];
 843                                 p_rt->transport_params.port_num = p_rt->num;
 844                                 p_rt->transport_params.sample_interval =
 845                                         pcfg->si + 1;
 846                                 p_rt->transport_params.offset1 = pcfg->off1;
 847                                 p_rt->transport_params.offset2 = pcfg->off2;
 848                                 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;
 849                                 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count;
 850
 851                                 p_rt->transport_params.hstart = pcfg->hstart;
 852                                 p_rt->transport_params.hstop = pcfg->hstop;
 853                                 p_rt->transport_params.lane_ctrl = pcfg->lane_control;
 854                                 if (pcfg->word_length != SWR_INVALID_PARAM) {
 855                                         sdw_fill_port_params(&p_rt->port_params,
 856                                                      p_rt->num,
 857                                                      pcfg->word_length + 1,
 858                                                      SDW_PORT_FLOW_MODE_ISOCH,
 859                                                      SDW_PORT_DATA_MODE_NORMAL);
 860                                 }
 861                                 i++;
 862                         }
 863                 }
 864         }
 865
 866         return 0;
 867 }
 868
 869 static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
 870         DEFAULT_CLK_FREQ,
 871 };
 872
 873 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
 874                                         struct sdw_stream_runtime *stream)
 875 {
 876         struct sdw_master_runtime *m_rt;
 877         struct sdw_port_runtime *p_rt;
 878         unsigned long *port_mask;
 879
 880         mutex_lock(&ctrl->port_lock);
 881
 882         list_for_each_entry(m_rt, &stream->master_list, stream_node) {
 883                 if (m_rt->direction == SDW_DATA_DIR_RX)
 884                         port_mask = &ctrl->dout_port_mask;
 885                 else
 886                         port_mask = &ctrl->din_port_mask;
 887
 888                 list_for_each_entry(p_rt, &m_rt->port_list, port_node)
 889                         clear_bit(p_rt->num, port_mask);
 890         }
 891
 892         mutex_unlock(&ctrl->port_lock);
 893 }
 894
 895 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
 896                                         struct sdw_stream_runtime *stream,
 897                                        struct snd_pcm_hw_params *params,
 898                                        int direction)
 899 {
 900         struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS];
 901         struct sdw_stream_config sconfig;
 902         struct sdw_master_runtime *m_rt;
 903         struct sdw_slave_runtime *s_rt;
 904         struct sdw_port_runtime *p_rt;
 905         struct sdw_slave *slave;
 906         unsigned long *port_mask;
 907         int i, maxport, pn, nports = 0, ret = 0;
 908         unsigned int m_port;
 909
 910         mutex_lock(&ctrl->port_lock);
 911         list_for_each_entry(m_rt, &stream->master_list, stream_node) {
 912                 if (m_rt->direction == SDW_DATA_DIR_RX) {
 913                         maxport = ctrl->num_dout_ports;
 914                         port_mask = &ctrl->dout_port_mask;
 915                 } else {
 916                         maxport = ctrl->num_din_ports;
 917                         port_mask = &ctrl->din_port_mask;
 918                 }
 919
 920                 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
 921                         slave = s_rt->slave;
 922                         list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
 923                                 m_port = slave->m_port_map[p_rt->num];
 924                                 /* Port numbers start from 1 - 14*/
 925                                 if (m_port)
 926                                         pn = m_port;
 927                                 else
 928                                         pn = find_first_zero_bit(port_mask, maxport);
 929
 930                                 if (pn > maxport) {
 931                                         dev_err(ctrl->dev, "All ports busy\n");
 932                                         ret = -EBUSY;
 933                                         goto err;
 934                                 }
 935                                 set_bit(pn, port_mask);
 936                                 pconfig[nports].num = pn;
 937                                 pconfig[nports].ch_mask = p_rt->ch_mask;
 938                                 nports++;
 939                         }
 940                 }
 941         }
 942
 943         if (direction == SNDRV_PCM_STREAM_CAPTURE)
 944                 sconfig.direction = SDW_DATA_DIR_TX;
 945         else
 946                 sconfig.direction = SDW_DATA_DIR_RX;
 947
 948         /* hw parameters wil be ignored as we only support PDM */
 949         sconfig.ch_count = 1;
 950         sconfig.frame_rate = params_rate(params);
 951         sconfig.type = stream->type;
 952         sconfig.bps = 1;
 953         sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
 954                               nports, stream);
 955 err:
 956         if (ret) {
 957                 for (i = 0; i < nports; i++)
 958                         clear_bit(pconfig[i].num, port_mask);
 959         }
 960
 961         mutex_unlock(&ctrl->port_lock);
 962
 963         return ret;
 964 }
 965
 966 static int qcom_swrm_hw_params(struct snd_pcm_substream *substream,
 967                                struct snd_pcm_hw_params *params,
 968                               struct snd_soc_dai *dai)
 969 {
 970         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
 971         struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
 972         int ret;
 973
 974         ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
 975                                            substream->stream);
 976         if (ret)
 977                 qcom_swrm_stream_free_ports(ctrl, sruntime);
 978
 979         return ret;
 980 }
 981
 982 static int qcom_swrm_hw_free(struct snd_pcm_substream *substream,
 983                              struct snd_soc_dai *dai)
 984 {
 985         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
 986         struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
 987
 988         qcom_swrm_stream_free_ports(ctrl, sruntime);
 989         sdw_stream_remove_master(&ctrl->bus, sruntime);
 990
 991         return 0;
 992 }
 993
 994 static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai,
 995                                     void *stream, int direction)
 996 {
 997         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
 998
 999         ctrl->sruntime[dai->id] = stream;
1000
1001         return 0;
1002 }
1003
1004 static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction)
1005 {
1006         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1007
1008         return ctrl->sruntime[dai->id];
1009 }
1010
1011 static int qcom_swrm_startup(struct snd_pcm_substream *substream,
1012                              struct snd_soc_dai *dai)
1013 {
1014         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1015         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1016         struct sdw_stream_runtime *sruntime;
1017         struct snd_soc_dai *codec_dai;
1018         int ret, i;
1019
1020         sruntime = sdw_alloc_stream(dai->name);
1021         if (!sruntime)
1022                 return -ENOMEM;
1023
1024         ctrl->sruntime[dai->id] = sruntime;
1025
1026         for_each_rtd_codec_dais(rtd, i, codec_dai) {
1027                 ret = snd_soc_dai_set_stream(codec_dai, sruntime,
1028                                              substream->stream);
1029                 if (ret < 0 && ret != -ENOTSUPP) {
1030                         dev_err(dai->dev, "Failed to set sdw stream on %s\n",
1031                                 codec_dai->name);
1032                         sdw_release_stream(sruntime);
1033                         return ret;
1034                 }
1035         }
1036
1037         return 0;
1038 }
1039
1040 static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
1041                                struct snd_soc_dai *dai)
1042 {
1043         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1044
1045         sdw_release_stream(ctrl->sruntime[dai->id]);
1046         ctrl->sruntime[dai->id] = NULL;
1047 }
1048
1049 static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
1050         .hw_params = qcom_swrm_hw_params,
1051         .hw_free = qcom_swrm_hw_free,
1052         .startup = qcom_swrm_startup,
1053         .shutdown = qcom_swrm_shutdown,
1054         .set_stream = qcom_swrm_set_sdw_stream,
1055         .get_stream = qcom_swrm_get_sdw_stream,
1056 };
1057
1058 static const struct snd_soc_component_driver qcom_swrm_dai_component = {
1059         .name = "soundwire",
1060 };
1061
1062 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
1063 {
1064         int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
1065         struct snd_soc_dai_driver *dais;
1066         struct snd_soc_pcm_stream *stream;
1067         struct device *dev = ctrl->dev;
1068         int i;
1069
1070         /* PDM dais are only tested for now */
1071         dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
1072         if (!dais)
1073                 return -ENOMEM;
1074
1075         for (i = 0; i < num_dais; i++) {
1076                 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i);
1077                 if (!dais[i].name)
1078                         return -ENOMEM;
1079
1080                 if (i < ctrl->num_dout_ports)
1081                         stream = &dais[i].playback;
1082                 else
1083                         stream = &dais[i].capture;
1084
1085                 stream->channels_min = 1;
1086                 stream->channels_max = 1;
1087                 stream->rates = SNDRV_PCM_RATE_48000;
1088                 stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
1089
1090                 dais[i].ops = &qcom_swrm_pdm_dai_ops;
1091                 dais[i].id = i;
1092         }
1093
1094         return devm_snd_soc_register_component(ctrl->dev,
1095                                                 &qcom_swrm_dai_component,
1096                                                 dais, num_dais);
1097 }
1098
1099 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
1100 {
1101         struct device_node *np = ctrl->dev->of_node;
1102         u8 off1[QCOM_SDW_MAX_PORTS];
1103         u8 off2[QCOM_SDW_MAX_PORTS];
1104         u8 si[QCOM_SDW_MAX_PORTS];
1105         u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, };
1106         u8 hstart[QCOM_SDW_MAX_PORTS];
1107         u8 hstop[QCOM_SDW_MAX_PORTS];
1108         u8 word_length[QCOM_SDW_MAX_PORTS];
1109         u8 blk_group_count[QCOM_SDW_MAX_PORTS];
1110         u8 lane_control[QCOM_SDW_MAX_PORTS];
1111         int i, ret, nports, val;
1112
1113         ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
1114
1115         ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
1116         ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
1117
1118         ret = of_property_read_u32(np, "qcom,din-ports", &val);
1119         if (ret)
1120                 return ret;
1121
1122         if (val > ctrl->num_din_ports)
1123                 return -EINVAL;
1124
1125         ctrl->num_din_ports = val;
1126
1127         ret = of_property_read_u32(np, "qcom,dout-ports", &val);
1128         if (ret)
1129                 return ret;
1130
1131         if (val > ctrl->num_dout_ports)
1132                 return -EINVAL;
1133
1134         ctrl->num_dout_ports = val;
1135
1136         nports = ctrl->num_dout_ports + ctrl->num_din_ports;
1137         /* Valid port numbers are from 1-14, so mask out port 0 explicitly */
1138         set_bit(0, &ctrl->dout_port_mask);
1139         set_bit(0, &ctrl->din_port_mask);
1140
1141         ret = of_property_read_u8_array(np, "qcom,ports-offset1",
1142                                         off1, nports);
1143         if (ret)
1144                 return ret;
1145
1146         ret = of_property_read_u8_array(np, "qcom,ports-offset2",
1147                                         off2, nports);
1148         if (ret)
1149                 return ret;
1150
1151         ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low",
1152                                         si, nports);
1153         if (ret)
1154                 return ret;
1155
1156         ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode",
1157                                         bp_mode, nports);
1158         if (ret) {
1159                 if (ctrl->version <= 0x01030000)
1160                         memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1161                 else
1162                         return ret;
1163         }
1164
1165         memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1166         of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports);
1167
1168         memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1169         of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports);
1170
1171         memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1172         of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports);
1173
1174         memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1175         of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports);
1176
1177         memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1178         of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports);
1179
1180         for (i = 0; i < nports; i++) {
1181                 /* Valid port number range is from 1-14 */
1182                 ctrl->pconfig[i + 1].si = si[i];
1183                 ctrl->pconfig[i + 1].off1 = off1[i];
1184                 ctrl->pconfig[i + 1].off2 = off2[i];
1185                 ctrl->pconfig[i + 1].bp_mode = bp_mode[i];
1186                 ctrl->pconfig[i + 1].hstart = hstart[i];
1187                 ctrl->pconfig[i + 1].hstop = hstop[i];
1188                 ctrl->pconfig[i + 1].word_length = word_length[i];
1189                 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i];
1190                 ctrl->pconfig[i + 1].lane_control = lane_control[i];
1191         }
1192
1193         return 0;
1194 }
1195
1196 #ifdef CONFIG_DEBUG_FS
1197 static int swrm_reg_show(struct seq_file *s_file, void *data)
1198 {
1199         struct qcom_swrm_ctrl *swrm = s_file->private;
1200         int reg, reg_val;
1201
1202         for (reg = 0; reg <= SWR_MSTR_MAX_REG_ADDR; reg += 4) {
1203                 swrm->reg_read(swrm, reg, &reg_val);
1204                 seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val);
1205         }
1206
1207         return 0;
1208 }
1209 DEFINE_SHOW_ATTRIBUTE(swrm_reg);
1210 #endif
1211
1212 static int qcom_swrm_probe(struct platform_device *pdev)
1213 {
1214         struct device *dev = &pdev->dev;
1215         struct sdw_master_prop *prop;
1216         struct sdw_bus_params *params;
1217         struct qcom_swrm_ctrl *ctrl;
1218         const struct qcom_swrm_data *data;
1219         int ret;
1220         u32 val;
1221
1222         ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1223         if (!ctrl)
1224                 return -ENOMEM;
1225
1226         data = of_device_get_match_data(dev);
1227         ctrl->rows_index = sdw_find_row_index(data->default_rows);
1228         ctrl->cols_index = sdw_find_col_index(data->default_cols);
1229 #if IS_REACHABLE(CONFIG_SLIMBUS)
1230         if (dev->parent->bus == &slimbus_bus) {
1231 #else
1232         if (false) {
1233 #endif
1234                 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1235                 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1236                 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1237                 if (!ctrl->regmap)
1238                         return -EINVAL;
1239         } else {
1240                 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1241                 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1242                 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1243                 if (IS_ERR(ctrl->mmio))
1244                         return PTR_ERR(ctrl->mmio);
1245         }
1246
1247         ctrl->irq = of_irq_get(dev->of_node, 0);
1248         if (ctrl->irq < 0) {
1249                 ret = ctrl->irq;
1250                 goto err_init;
1251         }
1252
1253         ctrl->hclk = devm_clk_get(dev, "iface");
1254         if (IS_ERR(ctrl->hclk)) {
1255                 ret = PTR_ERR(ctrl->hclk);
1256                 goto err_init;
1257         }
1258
1259         clk_prepare_enable(ctrl->hclk);
1260
1261         ctrl->dev = dev;
1262         dev_set_drvdata(&pdev->dev, ctrl);
1263         mutex_init(&ctrl->port_lock);
1264         init_completion(&ctrl->broadcast);
1265         init_completion(&ctrl->enumeration);
1266
1267         ctrl->bus.ops = &qcom_swrm_ops;
1268         ctrl->bus.port_ops = &qcom_swrm_port_ops;
1269         ctrl->bus.compute_params = &qcom_swrm_compute_params;
1270
1271         ret = qcom_swrm_get_port_config(ctrl);
1272         if (ret)
1273                 goto err_clk;
1274
1275         params = &ctrl->bus.params;
1276         params->max_dr_freq = DEFAULT_CLK_FREQ;
1277         params->curr_dr_freq = DEFAULT_CLK_FREQ;
1278         params->col = data->default_cols;
1279         params->row = data->default_rows;
1280         ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1281         params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
1282         params->next_bank = !params->curr_bank;
1283
1284         prop = &ctrl->bus.prop;
1285         prop->max_clk_freq = DEFAULT_CLK_FREQ;
1286         prop->num_clk_gears = 0;
1287         prop->num_clk_freq = MAX_FREQ_NUM;
1288         prop->clk_freq = &qcom_swrm_freq_tbl[0];
1289         prop->default_col = data->default_cols;
1290         prop->default_row = data->default_rows;
1291
1292         ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1293
1294         ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1295                                         qcom_swrm_irq_handler,
1296                                         IRQF_TRIGGER_RISING |
1297                                         IRQF_ONESHOT,
1298                                         "soundwire", ctrl);
1299         if (ret) {
1300                 dev_err(dev, "Failed to request soundwire irq\n");
1301                 goto err_clk;
1302         }
1303
1304         ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1305         if (ret) {
1306                 dev_err(dev, "Failed to register Soundwire controller (%d)\n",
1307                         ret);
1308                 goto err_clk;
1309         }
1310
1311         qcom_swrm_init(ctrl);
1312         wait_for_completion_timeout(&ctrl->enumeration,
1313                                     msecs_to_jiffies(TIMEOUT_MS));
1314         ret = qcom_swrm_register_dais(ctrl);
1315         if (ret)
1316                 goto err_master_add;
1317
1318         dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n",
1319                  (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1320                  ctrl->version & 0xffff);
1321
1322 #ifdef CONFIG_DEBUG_FS
1323         ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1324         debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1325                             &swrm_reg_fops);
1326 #endif
1327
1328         return 0;
1329
1330 err_master_add:
1331         sdw_bus_master_delete(&ctrl->bus);
1332 err_clk:
1333         clk_disable_unprepare(ctrl->hclk);
1334 err_init:
1335         return ret;
1336 }
1337
1338 static int qcom_swrm_remove(struct platform_device *pdev)
1339 {
1340         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1341
1342         sdw_bus_master_delete(&ctrl->bus);
1343         clk_disable_unprepare(ctrl->hclk);
1344
1345         return 0;
1346 }
1347
1348 static const struct of_device_id qcom_swrm_of_match[] = {
1349         { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
1350         { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
1351         {/* sentinel */},
1352 };
1353
1354 MODULE_DEVICE_TABLE(of, qcom_swrm_of_match);
1355
1356 static struct platform_driver qcom_swrm_driver = {
1357         .probe  = &qcom_swrm_probe,
1358         .remove = &qcom_swrm_remove,
1359         .driver = {
1360                 .name   = "qcom-soundwire",
1361                 .of_match_table = qcom_swrm_of_match,
1362         }
1363 };
1364 module_platform_driver(qcom_swrm_driver);
1365
1366 MODULE_DESCRIPTION("Qualcomm soundwire driver");
1367 MODULE_LICENSE("GPL v2");