1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2019, Linaro Limited
5 #include <linux/completion.h>
6 #include <linux/interrupt.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/debugfs.h>
12 #include <linux/of_irq.h>
13 #include <linux/of_device.h>
14 #include <linux/regmap.h>
15 #include <linux/slab.h>
16 #include <linux/slimbus.h>
17 #include <linux/soundwire/sdw.h>
18 #include <linux/soundwire/sdw_registers.h>
19 #include <sound/pcm_params.h>
20 #include <sound/soc.h>
23 #define SWRM_COMP_HW_VERSION 0x00
24 #define SWRM_COMP_CFG_ADDR 0x04
25 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1)
26 #define SWRM_COMP_CFG_ENABLE_MSK BIT(0)
27 #define SWRM_COMP_PARAMS 0x100
28 #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH GENMASK(14, 10)
29 #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH GENMASK(19, 15)
30 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0)
31 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5)
32 #define SWRM_INTERRUPT_STATUS 0x200
33 #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0)
34 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0)
35 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1)
36 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS BIT(2)
37 #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET BIT(3)
38 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW BIT(4)
39 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW BIT(5)
40 #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW BIT(6)
41 #define SWRM_INTERRUPT_STATUS_CMD_ERROR BIT(7)
42 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION BIT(8)
43 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH BIT(9)
44 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10)
45 #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13)
46 #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14)
47 #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16)
48 #define SWRM_INTERRUPT_MAX 17
49 #define SWRM_INTERRUPT_MASK_ADDR 0x204
50 #define SWRM_INTERRUPT_CLEAR 0x208
51 #define SWRM_INTERRUPT_CPU_EN 0x210
52 #define SWRM_CMD_FIFO_WR_CMD 0x300
53 #define SWRM_CMD_FIFO_RD_CMD 0x304
54 #define SWRM_CMD_FIFO_CMD 0x308
55 #define SWRM_CMD_FIFO_FLUSH 0x1
56 #define SWRM_CMD_FIFO_STATUS 0x30C
57 #define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16)
58 #define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8)
59 #define SWRM_CMD_FIFO_CFG_ADDR 0x314
60 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31)
61 #define SWRM_RD_WR_CMD_RETRIES 0x7
62 #define SWRM_CMD_FIFO_RD_FIFO_ADDR 0x318
63 #define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8)
64 #define SWRM_ENUMERATOR_CFG_ADDR 0x500
65 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m))
66 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m) (0x534 + 0x8 * (m))
67 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m))
68 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0)
69 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK GENMASK(7, 3)
70 #define SWRM_MCP_BUS_CTRL 0x1044
71 #define SWRM_MCP_BUS_CLK_START BIT(1)
72 #define SWRM_MCP_CFG_ADDR 0x1048
73 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK GENMASK(21, 17)
74 #define SWRM_DEF_CMD_NO_PINGS 0x1f
75 #define SWRM_MCP_STATUS 0x104C
76 #define SWRM_MCP_STATUS_BANK_NUM_MASK BIT(0)
77 #define SWRM_MCP_SLV_STATUS 0x1090
78 #define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0)
79 #define SWRM_MCP_SLV_STATUS_SZ 2
80 #define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m)
81 #define SWRM_DP_PORT_CTRL_2_BANK(n, m) (0x1128 + 0x100 * (n - 1) + 0x40 * m)
82 #define SWRM_DP_BLOCK_CTRL_1(n) (0x112C + 0x100 * (n - 1))
83 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m)
84 #define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m)
85 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m)
86 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1))
87 #define SWR_MSTR_MAX_REG_ADDR (0x1740)
89 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18
90 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10
91 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08
92 #define SWRM_AHB_BRIDGE_WR_DATA_0 0xc85
93 #define SWRM_AHB_BRIDGE_WR_ADDR_0 0xc89
94 #define SWRM_AHB_BRIDGE_RD_ADDR_0 0xc8d
95 #define SWRM_AHB_BRIDGE_RD_DATA_0 0xc91
97 #define SWRM_REG_VAL_PACK(data, dev, id, reg) \
98 ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
100 #define SWRM_SPECIAL_CMD_ID 0xF
101 #define MAX_FREQ_NUM 1
102 #define TIMEOUT_MS (2 * HZ)
103 #define QCOM_SWRM_MAX_RD_LEN 0x1
104 #define QCOM_SDW_MAX_PORTS 14
105 #define DEFAULT_CLK_FREQ 9600000
106 #define SWRM_MAX_DAIS 0xF
107 #define SWR_INVALID_PARAM 0xFF
108 #define SWR_HSTOP_MAX_VAL 0xF
109 #define SWR_HSTART_MIN_VAL 0x0
110 #define SWR_BROADCAST_CMD_ID 0x0F
111 #define SWR_MAX_CMD_ID 14
112 #define MAX_FIFO_RD_RETRY 3
113 #define SWR_OVERFLOW_RETRY_COUNT 30
115 struct qcom_swrm_port_config {
127 struct qcom_swrm_ctrl {
130 struct regmap *regmap;
132 #ifdef CONFIG_DEBUG_FS
133 struct dentry *debugfs;
135 struct completion broadcast;
136 struct completion enumeration;
137 struct work_struct slave_work;
138 /* Port alloc/free lock */
139 struct mutex port_lock;
144 unsigned int version;
149 unsigned long dout_port_mask;
150 unsigned long din_port_mask;
154 struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS];
155 struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
156 enum sdw_slave_status status[SDW_MAX_DEVICES];
157 int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
158 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
164 struct qcom_swrm_data {
169 static struct qcom_swrm_data swrm_v1_3_data = {
174 static struct qcom_swrm_data swrm_v1_5_data = {
179 #define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus)
181 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
184 struct regmap *wcd_regmap = ctrl->regmap;
187 /* pg register + offset */
188 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0,
193 ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0,
201 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
204 struct regmap *wcd_regmap = ctrl->regmap;
206 /* pg register + offset */
207 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0,
212 /* write address register */
213 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0,
221 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
224 *val = readl(ctrl->mmio + reg);
228 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
231 writel(val, ctrl->mmio + reg);
235 static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
236 u8 dev_addr, u16 reg_addr)
241 if (id != SWR_BROADCAST_CMD_ID) {
242 if (id < SWR_MAX_CMD_ID)
248 val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
253 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm)
255 u32 fifo_outstanding_data, value;
256 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
259 /* Check for fifo underflow during read */
260 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
261 fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
263 /* Check if read data is available in read fifo */
264 if (fifo_outstanding_data > 0)
267 usleep_range(500, 510);
268 } while (fifo_retry_count--);
270 if (fifo_outstanding_data == 0) {
271 dev_err_ratelimited(swrm->dev, "%s err read underflow\n", __func__);
278 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *swrm)
280 u32 fifo_outstanding_cmds, value;
281 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
284 /* Check for fifo overflow during write */
285 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
286 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
288 /* Check for space in write fifo before writing */
289 if (fifo_outstanding_cmds < swrm->wr_fifo_depth)
292 usleep_range(500, 510);
293 } while (fifo_retry_count--);
295 if (fifo_outstanding_cmds == swrm->wr_fifo_depth) {
296 dev_err_ratelimited(swrm->dev, "%s err write overflow\n", __func__);
303 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data,
304 u8 dev_addr, u16 reg_addr)
311 if (dev_addr == SDW_BROADCAST_DEV_NUM) {
312 cmd_id = SWR_BROADCAST_CMD_ID;
313 val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
316 val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data,
320 if (swrm_wait_for_wr_fifo_avail(swrm))
321 return SDW_CMD_FAIL_OTHER;
323 /* Its assumed that write is okay as we do not get any status back */
324 swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val);
326 /* version 1.3 or less */
327 if (swrm->version <= 0x01030000)
328 usleep_range(150, 155);
330 if (cmd_id == SWR_BROADCAST_CMD_ID) {
332 * sleep for 10ms for MSM soundwire variant to allow broadcast
333 * command to complete.
335 ret = wait_for_completion_timeout(&swrm->broadcast,
336 msecs_to_jiffies(TIMEOUT_MS));
338 ret = SDW_CMD_IGNORED;
348 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm,
349 u8 dev_addr, u16 reg_addr,
352 u32 cmd_data, cmd_id, val, retry_attempt = 0;
354 val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr);
356 /* wait for FIFO RD to complete to avoid overflow */
357 usleep_range(100, 105);
358 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
359 /* wait for FIFO RD CMD complete to avoid overflow */
360 usleep_range(250, 255);
362 if (swrm_wait_for_rd_fifo_avail(swrm))
363 return SDW_CMD_FAIL_OTHER;
366 swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data);
367 rval[0] = cmd_data & 0xFF;
368 cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data);
370 if (cmd_id != swrm->rcmd_id) {
371 if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) {
372 /* wait 500 us before retry on fifo read failure */
373 usleep_range(500, 505);
374 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD,
375 SWRM_CMD_FIFO_FLUSH);
376 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
383 } while (retry_attempt < MAX_FIFO_RD_RETRY);
385 dev_err(swrm->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
386 dev_num: 0x%x, cmd_data: 0x%x\n",
387 reg_addr, swrm->rcmd_id, dev_addr, cmd_data);
389 return SDW_CMD_IGNORED;
392 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl)
397 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
399 for (dev_num = 0; dev_num < SDW_MAX_DEVICES; dev_num++) {
400 status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ));
402 if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) {
403 ctrl->status[dev_num] = status;
411 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
416 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
417 ctrl->slave_status = val;
419 for (i = 0; i < SDW_MAX_DEVICES; i++) {
422 s = (val >> (i * 2));
423 s &= SWRM_MCP_SLV_STATUS_MASK;
428 static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus,
429 struct sdw_slave *slave, int devnum)
431 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
434 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status);
435 status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ));
436 status &= SWRM_MCP_SLV_STATUS_MASK;
438 if (status == SDW_SLAVE_ATTACHED) {
440 slave->dev_num = devnum;
441 mutex_lock(&bus->bus_lock);
442 set_bit(devnum, bus->assigned);
443 mutex_unlock(&bus->bus_lock);
447 static int qcom_swrm_enumerate(struct sdw_bus *bus)
449 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
450 struct sdw_slave *slave, *_s;
451 struct sdw_slave_id id;
456 char *buf1 = (char *)&val1, *buf2 = (char *)&val2;
458 for (i = 1; i <= SDW_MAX_DEVICES; i++) {
459 /*SCP_Devid5 - Devid 4*/
460 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1);
462 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/
463 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2);
468 addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) |
469 ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) |
470 ((u64)buf1[0] << 40);
472 sdw_extract_slave_id(bus, addr, &id);
474 /* Now compare with entries */
475 list_for_each_entry_safe(slave, _s, &bus->slaves, node) {
476 if (sdw_compare_devid(slave, id) == 0) {
477 qcom_swrm_set_slave_dev_num(bus, slave, i);
484 qcom_swrm_set_slave_dev_num(bus, NULL, i);
485 sdw_slave_add(bus, &id, NULL);
489 complete(&ctrl->enumeration);
493 static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
495 struct qcom_swrm_ctrl *swrm = dev_id;
496 u32 value, intr_sts, intr_sts_masked, slave_status;
499 int ret = IRQ_HANDLED;
501 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
502 intr_sts_masked = intr_sts & swrm->intr_mask;
505 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
506 value = intr_sts_masked & BIT(i);
511 case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
512 devnum = qcom_swrm_get_alert_slave_dev_num(swrm);
514 dev_err_ratelimited(swrm->dev,
515 "no slave alert found.spurious interrupt\n");
517 sdw_handle_slave_status(&swrm->bus, swrm->status);
521 case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
522 case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
523 dev_err_ratelimited(swrm->dev, "%s: SWR new slave attached\n",
525 swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status);
526 if (swrm->slave_status == slave_status) {
527 dev_err(swrm->dev, "Slave status not changed %x\n",
530 qcom_swrm_get_device_status(swrm);
531 qcom_swrm_enumerate(&swrm->bus);
532 sdw_handle_slave_status(&swrm->bus, swrm->status);
535 case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
536 dev_err_ratelimited(swrm->dev,
537 "%s: SWR bus clsh detected\n",
539 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
540 swrm->reg_write(swrm, SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
542 case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
543 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
544 dev_err_ratelimited(swrm->dev,
545 "%s: SWR read FIFO overflow fifo status 0x%x\n",
548 case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
549 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
550 dev_err_ratelimited(swrm->dev,
551 "%s: SWR read FIFO underflow fifo status 0x%x\n",
554 case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
555 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
557 "%s: SWR write FIFO overflow fifo status %x\n",
559 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
561 case SWRM_INTERRUPT_STATUS_CMD_ERROR:
562 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
563 dev_err_ratelimited(swrm->dev,
564 "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n",
566 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
568 case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
569 dev_err_ratelimited(swrm->dev,
570 "%s: SWR Port collision detected\n",
572 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
573 swrm->reg_write(swrm,
574 SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
576 case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
577 dev_err_ratelimited(swrm->dev,
578 "%s: SWR read enable valid mismatch\n",
581 ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
582 swrm->reg_write(swrm,
583 SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
585 case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
586 complete(&swrm->broadcast);
588 case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2:
590 case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2:
592 case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP:
595 dev_err_ratelimited(swrm->dev,
596 "%s: SWR unknown interrupt value: %d\n",
602 swrm->reg_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts);
603 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
604 intr_sts_masked = intr_sts & swrm->intr_mask;
605 } while (intr_sts_masked);
610 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
614 /* Clear Rows and Cols */
615 val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
616 val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
618 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
620 /* Enable Auto enumeration */
621 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
623 ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK;
624 /* Mask soundwire interrupts */
625 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR,
626 SWRM_INTERRUPT_STATUS_RMSK);
628 /* Configure No pings */
629 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
630 u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
631 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
633 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
634 /* Configure number of retries of a read/write cmd */
635 if (ctrl->version > 0x01050001) {
636 /* Only for versions >= 1.5.1 */
637 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
638 SWRM_RD_WR_CMD_RETRIES |
639 SWRM_CONTINUE_EXEC_ON_CMD_IGNORE);
641 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
642 SWRM_RD_WR_CMD_RETRIES);
645 /* Set IRQ to PULSE */
646 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
647 SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
648 SWRM_COMP_CFG_ENABLE_MSK);
650 /* enable CPU IRQs */
652 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN,
653 SWRM_INTERRUPT_STATUS_RMSK);
655 ctrl->slave_status = 0;
656 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
657 ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val);
658 ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);
663 static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus,
666 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
669 if (msg->flags == SDW_MSG_FLAG_READ) {
670 for (i = 0; i < msg->len;) {
671 if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN)
674 len = QCOM_SWRM_MAX_RD_LEN;
676 ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
684 } else if (msg->flags == SDW_MSG_FLAG_WRITE) {
685 for (i = 0; i < msg->len; i++) {
686 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
690 return SDW_CMD_IGNORED;
697 static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus)
699 u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);
700 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
703 ctrl->reg_read(ctrl, reg, &val);
705 u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
706 u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
708 return ctrl->reg_write(ctrl, reg, val);
711 static int qcom_swrm_port_params(struct sdw_bus *bus,
712 struct sdw_port_params *p_params,
715 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
717 return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),
722 static int qcom_swrm_transport_params(struct sdw_bus *bus,
723 struct sdw_transport_params *params,
724 enum sdw_reg_bank bank)
726 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
727 struct qcom_swrm_port_config *pcfg;
729 int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank);
732 pcfg = &ctrl->pconfig[params->port_num];
734 value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
735 value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
738 ret = ctrl->reg_write(ctrl, reg, value);
742 if (pcfg->lane_control != SWR_INVALID_PARAM) {
743 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank);
744 value = pcfg->lane_control;
745 ret = ctrl->reg_write(ctrl, reg, value);
750 if (pcfg->blk_group_count != SWR_INVALID_PARAM) {
751 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank);
752 value = pcfg->blk_group_count;
753 ret = ctrl->reg_write(ctrl, reg, value);
758 if (pcfg->hstart != SWR_INVALID_PARAM
759 && pcfg->hstop != SWR_INVALID_PARAM) {
760 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
761 value = (pcfg->hstop << 4) | pcfg->hstart;
762 ret = ctrl->reg_write(ctrl, reg, value);
764 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
765 value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;
766 ret = ctrl->reg_write(ctrl, reg, value);
772 if (pcfg->bp_mode != SWR_INVALID_PARAM) {
773 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank);
774 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
781 static int qcom_swrm_port_enable(struct sdw_bus *bus,
782 struct sdw_enable_ch *enable_ch,
785 u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);
786 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
789 ctrl->reg_read(ctrl, reg, &val);
791 if (enable_ch->enable)
792 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
794 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
796 return ctrl->reg_write(ctrl, reg, val);
799 static const struct sdw_master_port_ops qcom_swrm_port_ops = {
800 .dpn_set_port_params = qcom_swrm_port_params,
801 .dpn_set_port_transport_params = qcom_swrm_transport_params,
802 .dpn_port_enable_ch = qcom_swrm_port_enable,
805 static const struct sdw_master_ops qcom_swrm_ops = {
806 .xfer_msg = qcom_swrm_xfer_msg,
807 .pre_bank_switch = qcom_swrm_pre_bank_switch,
810 static int qcom_swrm_compute_params(struct sdw_bus *bus)
812 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
813 struct sdw_master_runtime *m_rt;
814 struct sdw_slave_runtime *s_rt;
815 struct sdw_port_runtime *p_rt;
816 struct qcom_swrm_port_config *pcfg;
817 struct sdw_slave *slave;
821 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
822 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
823 pcfg = &ctrl->pconfig[p_rt->num];
824 p_rt->transport_params.port_num = p_rt->num;
825 if (pcfg->word_length != SWR_INVALID_PARAM) {
826 sdw_fill_port_params(&p_rt->port_params,
827 p_rt->num, pcfg->word_length + 1,
828 SDW_PORT_FLOW_MODE_ISOCH,
829 SDW_PORT_DATA_MODE_NORMAL);
834 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
836 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
837 m_port = slave->m_port_map[p_rt->num];
838 /* port config starts at offset 0 so -1 from actual port number */
840 pcfg = &ctrl->pconfig[m_port];
842 pcfg = &ctrl->pconfig[i];
843 p_rt->transport_params.port_num = p_rt->num;
844 p_rt->transport_params.sample_interval =
846 p_rt->transport_params.offset1 = pcfg->off1;
847 p_rt->transport_params.offset2 = pcfg->off2;
848 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;
849 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count;
851 p_rt->transport_params.hstart = pcfg->hstart;
852 p_rt->transport_params.hstop = pcfg->hstop;
853 p_rt->transport_params.lane_ctrl = pcfg->lane_control;
854 if (pcfg->word_length != SWR_INVALID_PARAM) {
855 sdw_fill_port_params(&p_rt->port_params,
857 pcfg->word_length + 1,
858 SDW_PORT_FLOW_MODE_ISOCH,
859 SDW_PORT_DATA_MODE_NORMAL);
869 static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
873 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
874 struct sdw_stream_runtime *stream)
876 struct sdw_master_runtime *m_rt;
877 struct sdw_port_runtime *p_rt;
878 unsigned long *port_mask;
880 mutex_lock(&ctrl->port_lock);
882 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
883 if (m_rt->direction == SDW_DATA_DIR_RX)
884 port_mask = &ctrl->dout_port_mask;
886 port_mask = &ctrl->din_port_mask;
888 list_for_each_entry(p_rt, &m_rt->port_list, port_node)
889 clear_bit(p_rt->num, port_mask);
892 mutex_unlock(&ctrl->port_lock);
895 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
896 struct sdw_stream_runtime *stream,
897 struct snd_pcm_hw_params *params,
900 struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS];
901 struct sdw_stream_config sconfig;
902 struct sdw_master_runtime *m_rt;
903 struct sdw_slave_runtime *s_rt;
904 struct sdw_port_runtime *p_rt;
905 struct sdw_slave *slave;
906 unsigned long *port_mask;
907 int i, maxport, pn, nports = 0, ret = 0;
910 mutex_lock(&ctrl->port_lock);
911 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
912 if (m_rt->direction == SDW_DATA_DIR_RX) {
913 maxport = ctrl->num_dout_ports;
914 port_mask = &ctrl->dout_port_mask;
916 maxport = ctrl->num_din_ports;
917 port_mask = &ctrl->din_port_mask;
920 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
922 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
923 m_port = slave->m_port_map[p_rt->num];
924 /* Port numbers start from 1 - 14*/
928 pn = find_first_zero_bit(port_mask, maxport);
931 dev_err(ctrl->dev, "All ports busy\n");
935 set_bit(pn, port_mask);
936 pconfig[nports].num = pn;
937 pconfig[nports].ch_mask = p_rt->ch_mask;
943 if (direction == SNDRV_PCM_STREAM_CAPTURE)
944 sconfig.direction = SDW_DATA_DIR_TX;
946 sconfig.direction = SDW_DATA_DIR_RX;
948 /* hw parameters wil be ignored as we only support PDM */
949 sconfig.ch_count = 1;
950 sconfig.frame_rate = params_rate(params);
951 sconfig.type = stream->type;
953 sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
957 for (i = 0; i < nports; i++)
958 clear_bit(pconfig[i].num, port_mask);
961 mutex_unlock(&ctrl->port_lock);
966 static int qcom_swrm_hw_params(struct snd_pcm_substream *substream,
967 struct snd_pcm_hw_params *params,
968 struct snd_soc_dai *dai)
970 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
971 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
974 ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
977 qcom_swrm_stream_free_ports(ctrl, sruntime);
982 static int qcom_swrm_hw_free(struct snd_pcm_substream *substream,
983 struct snd_soc_dai *dai)
985 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
986 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
988 qcom_swrm_stream_free_ports(ctrl, sruntime);
989 sdw_stream_remove_master(&ctrl->bus, sruntime);
994 static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai,
995 void *stream, int direction)
997 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
999 ctrl->sruntime[dai->id] = stream;
1004 static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction)
1006 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1008 return ctrl->sruntime[dai->id];
1011 static int qcom_swrm_startup(struct snd_pcm_substream *substream,
1012 struct snd_soc_dai *dai)
1014 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1015 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1016 struct sdw_stream_runtime *sruntime;
1017 struct snd_soc_dai *codec_dai;
1020 sruntime = sdw_alloc_stream(dai->name);
1024 ctrl->sruntime[dai->id] = sruntime;
1026 for_each_rtd_codec_dais(rtd, i, codec_dai) {
1027 ret = snd_soc_dai_set_sdw_stream(codec_dai, sruntime,
1029 if (ret < 0 && ret != -ENOTSUPP) {
1030 dev_err(dai->dev, "Failed to set sdw stream on %s\n",
1032 sdw_release_stream(sruntime);
1040 static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
1041 struct snd_soc_dai *dai)
1043 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1045 sdw_release_stream(ctrl->sruntime[dai->id]);
1046 ctrl->sruntime[dai->id] = NULL;
1049 static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
1050 .hw_params = qcom_swrm_hw_params,
1051 .hw_free = qcom_swrm_hw_free,
1052 .startup = qcom_swrm_startup,
1053 .shutdown = qcom_swrm_shutdown,
1054 .set_sdw_stream = qcom_swrm_set_sdw_stream,
1055 .get_sdw_stream = qcom_swrm_get_sdw_stream,
1058 static const struct snd_soc_component_driver qcom_swrm_dai_component = {
1059 .name = "soundwire",
1062 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
1064 int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
1065 struct snd_soc_dai_driver *dais;
1066 struct snd_soc_pcm_stream *stream;
1067 struct device *dev = ctrl->dev;
1070 /* PDM dais are only tested for now */
1071 dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
1075 for (i = 0; i < num_dais; i++) {
1076 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i);
1080 if (i < ctrl->num_dout_ports)
1081 stream = &dais[i].playback;
1083 stream = &dais[i].capture;
1085 stream->channels_min = 1;
1086 stream->channels_max = 1;
1087 stream->rates = SNDRV_PCM_RATE_48000;
1088 stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
1090 dais[i].ops = &qcom_swrm_pdm_dai_ops;
1094 return devm_snd_soc_register_component(ctrl->dev,
1095 &qcom_swrm_dai_component,
1099 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
1101 struct device_node *np = ctrl->dev->of_node;
1102 u8 off1[QCOM_SDW_MAX_PORTS];
1103 u8 off2[QCOM_SDW_MAX_PORTS];
1104 u8 si[QCOM_SDW_MAX_PORTS];
1105 u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, };
1106 u8 hstart[QCOM_SDW_MAX_PORTS];
1107 u8 hstop[QCOM_SDW_MAX_PORTS];
1108 u8 word_length[QCOM_SDW_MAX_PORTS];
1109 u8 blk_group_count[QCOM_SDW_MAX_PORTS];
1110 u8 lane_control[QCOM_SDW_MAX_PORTS];
1111 int i, ret, nports, val;
1113 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
1115 ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
1116 ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
1118 ret = of_property_read_u32(np, "qcom,din-ports", &val);
1122 if (val > ctrl->num_din_ports)
1125 ctrl->num_din_ports = val;
1127 ret = of_property_read_u32(np, "qcom,dout-ports", &val);
1131 if (val > ctrl->num_dout_ports)
1134 ctrl->num_dout_ports = val;
1136 nports = ctrl->num_dout_ports + ctrl->num_din_ports;
1137 /* Valid port numbers are from 1-14, so mask out port 0 explicitly */
1138 set_bit(0, &ctrl->dout_port_mask);
1139 set_bit(0, &ctrl->din_port_mask);
1141 ret = of_property_read_u8_array(np, "qcom,ports-offset1",
1146 ret = of_property_read_u8_array(np, "qcom,ports-offset2",
1151 ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low",
1156 ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode",
1161 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &version);
1163 if (version <= 0x01030000)
1164 memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1169 memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1170 of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports);
1172 memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1173 of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports);
1175 memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1176 of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports);
1178 memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1179 of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports);
1181 memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1182 of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports);
1184 for (i = 0; i < nports; i++) {
1185 /* Valid port number range is from 1-14 */
1186 ctrl->pconfig[i + 1].si = si[i];
1187 ctrl->pconfig[i + 1].off1 = off1[i];
1188 ctrl->pconfig[i + 1].off2 = off2[i];
1189 ctrl->pconfig[i + 1].bp_mode = bp_mode[i];
1190 ctrl->pconfig[i + 1].hstart = hstart[i];
1191 ctrl->pconfig[i + 1].hstop = hstop[i];
1192 ctrl->pconfig[i + 1].word_length = word_length[i];
1193 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i];
1194 ctrl->pconfig[i + 1].lane_control = lane_control[i];
1200 #ifdef CONFIG_DEBUG_FS
1201 static int swrm_reg_show(struct seq_file *s_file, void *data)
1203 struct qcom_swrm_ctrl *swrm = s_file->private;
1206 for (reg = 0; reg <= SWR_MSTR_MAX_REG_ADDR; reg += 4) {
1207 swrm->reg_read(swrm, reg, ®_val);
1208 seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val);
1213 DEFINE_SHOW_ATTRIBUTE(swrm_reg);
1216 static int qcom_swrm_probe(struct platform_device *pdev)
1218 struct device *dev = &pdev->dev;
1219 struct sdw_master_prop *prop;
1220 struct sdw_bus_params *params;
1221 struct qcom_swrm_ctrl *ctrl;
1222 const struct qcom_swrm_data *data;
1226 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1230 data = of_device_get_match_data(dev);
1231 ctrl->rows_index = sdw_find_row_index(data->default_rows);
1232 ctrl->cols_index = sdw_find_col_index(data->default_cols);
1233 #if IS_REACHABLE(CONFIG_SLIMBUS)
1234 if (dev->parent->bus == &slimbus_bus) {
1238 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1239 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1240 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1244 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1245 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1246 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1247 if (IS_ERR(ctrl->mmio))
1248 return PTR_ERR(ctrl->mmio);
1251 ctrl->irq = of_irq_get(dev->of_node, 0);
1252 if (ctrl->irq < 0) {
1257 ctrl->hclk = devm_clk_get(dev, "iface");
1258 if (IS_ERR(ctrl->hclk)) {
1259 ret = PTR_ERR(ctrl->hclk);
1263 clk_prepare_enable(ctrl->hclk);
1266 dev_set_drvdata(&pdev->dev, ctrl);
1267 mutex_init(&ctrl->port_lock);
1268 init_completion(&ctrl->broadcast);
1269 init_completion(&ctrl->enumeration);
1271 ctrl->bus.ops = &qcom_swrm_ops;
1272 ctrl->bus.port_ops = &qcom_swrm_port_ops;
1273 ctrl->bus.compute_params = &qcom_swrm_compute_params;
1275 ret = qcom_swrm_get_port_config(ctrl);
1279 params = &ctrl->bus.params;
1280 params->max_dr_freq = DEFAULT_CLK_FREQ;
1281 params->curr_dr_freq = DEFAULT_CLK_FREQ;
1282 params->col = data->default_cols;
1283 params->row = data->default_rows;
1284 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1285 params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
1286 params->next_bank = !params->curr_bank;
1288 prop = &ctrl->bus.prop;
1289 prop->max_clk_freq = DEFAULT_CLK_FREQ;
1290 prop->num_clk_gears = 0;
1291 prop->num_clk_freq = MAX_FREQ_NUM;
1292 prop->clk_freq = &qcom_swrm_freq_tbl[0];
1293 prop->default_col = data->default_cols;
1294 prop->default_row = data->default_rows;
1296 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1298 ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1299 qcom_swrm_irq_handler,
1300 IRQF_TRIGGER_RISING |
1304 dev_err(dev, "Failed to request soundwire irq\n");
1308 ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1310 dev_err(dev, "Failed to register Soundwire controller (%d)\n",
1315 qcom_swrm_init(ctrl);
1316 wait_for_completion_timeout(&ctrl->enumeration,
1317 msecs_to_jiffies(TIMEOUT_MS));
1318 ret = qcom_swrm_register_dais(ctrl);
1320 goto err_master_add;
1322 dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n",
1323 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1324 ctrl->version & 0xffff);
1326 #ifdef CONFIG_DEBUG_FS
1327 ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1328 debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1335 sdw_bus_master_delete(&ctrl->bus);
1337 clk_disable_unprepare(ctrl->hclk);
1342 static int qcom_swrm_remove(struct platform_device *pdev)
1344 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1346 sdw_bus_master_delete(&ctrl->bus);
1347 clk_disable_unprepare(ctrl->hclk);
1352 static const struct of_device_id qcom_swrm_of_match[] = {
1353 { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
1354 { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
1358 MODULE_DEVICE_TABLE(of, qcom_swrm_of_match);
1360 static struct platform_driver qcom_swrm_driver = {
1361 .probe = &qcom_swrm_probe,
1362 .remove = &qcom_swrm_remove,
1364 .name = "qcom-soundwire",
1365 .of_match_table = qcom_swrm_of_match,
1368 module_platform_driver(qcom_swrm_driver);
1370 MODULE_DESCRIPTION("Qualcomm soundwire driver");
1371 MODULE_LICENSE("GPL v2");