drivers/soundwire/qcom.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2019, Linaro Limited
   3
   4 #include <linux/clk.h>
   5 #include <linux/completion.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/io.h>
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/debugfs.h>
  11 #include <linux/of.h>
  12 #include <linux/of_irq.h>
  13 #include <linux/of_device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/regmap.h>
  16 #include <linux/slab.h>
  17 #include <linux/slimbus.h>
  18 #include <linux/soundwire/sdw.h>
  19 #include <linux/soundwire/sdw_registers.h>
  20 #include <sound/pcm_params.h>
  21 #include <sound/soc.h>
  22 #include "bus.h"
  23
  24 #define SWRM_COMP_SW_RESET                                      0x008
  25 #define SWRM_COMP_STATUS                                        0x014
  26 #define SWRM_FRM_GEN_ENABLED                                    BIT(0)
  27 #define SWRM_COMP_HW_VERSION                                    0x00
  28 #define SWRM_COMP_CFG_ADDR                                      0x04
  29 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK                    BIT(1)
  30 #define SWRM_COMP_CFG_ENABLE_MSK                                BIT(0)
  31 #define SWRM_COMP_PARAMS                                        0x100
  32 #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH                          GENMASK(14, 10)
  33 #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH                          GENMASK(19, 15)
  34 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK                        GENMASK(4, 0)
  35 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK                         GENMASK(9, 5)
  36 #define SWRM_COMP_MASTER_ID                                     0x104
  37 #define SWRM_INTERRUPT_STATUS                                   0x200
  38 #define SWRM_INTERRUPT_STATUS_RMSK                              GENMASK(16, 0)
  39 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ                    BIT(0)
  40 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED                BIT(1)
  41 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS          BIT(2)
  42 #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET                  BIT(3)
  43 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW                  BIT(4)
  44 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW                 BIT(5)
  45 #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW              BIT(6)
  46 #define SWRM_INTERRUPT_STATUS_CMD_ERROR                         BIT(7)
  47 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION               BIT(8)
  48 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH         BIT(9)
  49 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED           BIT(10)
  50 #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2             BIT(13)
  51 #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2              BIT(14)
  52 #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP               BIT(16)
  53 #define SWRM_INTERRUPT_MAX                                      17
  54 #define SWRM_INTERRUPT_MASK_ADDR                                0x204
  55 #define SWRM_INTERRUPT_CLEAR                                    0x208
  56 #define SWRM_INTERRUPT_CPU_EN                                   0x210
  57 #define SWRM_CMD_FIFO_WR_CMD                                    0x300
  58 #define SWRM_CMD_FIFO_RD_CMD                                    0x304
  59 #define SWRM_CMD_FIFO_CMD                                       0x308
  60 #define SWRM_CMD_FIFO_FLUSH                                     0x1
  61 #define SWRM_CMD_FIFO_STATUS                                    0x30C
  62 #define SWRM_RD_CMD_FIFO_CNT_MASK                               GENMASK(20, 16)
  63 #define SWRM_WR_CMD_FIFO_CNT_MASK                               GENMASK(12, 8)
  64 #define SWRM_CMD_FIFO_CFG_ADDR                                  0x314
  65 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE                        BIT(31)
  66 #define SWRM_RD_WR_CMD_RETRIES                                  0x7
  67 #define SWRM_CMD_FIFO_RD_FIFO_ADDR                              0x318
  68 #define SWRM_RD_FIFO_CMD_ID_MASK                                GENMASK(11, 8)
  69 #define SWRM_ENUMERATOR_CFG_ADDR                                0x500
  70 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m)               (0x530 + 0x8 * (m))
  71 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m)               (0x534 + 0x8 * (m))
  72 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m)                (0x101C + 0x40 * (m))
  73 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK                  GENMASK(2, 0)
  74 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK                  GENMASK(7, 3)
  75 #define SWRM_MCP_BUS_CTRL                                       0x1044
  76 #define SWRM_MCP_BUS_CLK_START                                  BIT(1)
  77 #define SWRM_MCP_CFG_ADDR                                       0x1048
  78 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK               GENMASK(21, 17)
  79 #define SWRM_DEF_CMD_NO_PINGS                                   0x1f
  80 #define SWRM_MCP_STATUS                                         0x104C
  81 #define SWRM_MCP_STATUS_BANK_NUM_MASK                           BIT(0)
  82 #define SWRM_MCP_SLV_STATUS                                     0x1090
  83 #define SWRM_MCP_SLV_STATUS_MASK                                GENMASK(1, 0)
  84 #define SWRM_MCP_SLV_STATUS_SZ                                  2
  85 #define SWRM_DP_PORT_CTRL_BANK(n, m)    (0x1124 + 0x100 * (n - 1) + 0x40 * m)
  86 #define SWRM_DP_PORT_CTRL_2_BANK(n, m)  (0x1128 + 0x100 * (n - 1) + 0x40 * m)
  87 #define SWRM_DP_BLOCK_CTRL_1(n)         (0x112C + 0x100 * (n - 1))
  88 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m)  (0x1130 + 0x100 * (n - 1) + 0x40 * m)
  89 #define SWRM_DP_PORT_HCTRL_BANK(n, m)   (0x1134 + 0x100 * (n - 1) + 0x40 * m)
  90 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m)  (0x1138 + 0x100 * (n - 1) + 0x40 * m)
  91 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n)   (0x1054 + 0x100 * (n - 1))
  92 #define SWR_MSTR_MAX_REG_ADDR           (0x1740)
  93
  94 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT                          0x18
  95 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT                          0x10
  96 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT                          0x08
  97 #define SWRM_AHB_BRIDGE_WR_DATA_0                               0xc85
  98 #define SWRM_AHB_BRIDGE_WR_ADDR_0                               0xc89
  99 #define SWRM_AHB_BRIDGE_RD_ADDR_0                               0xc8d
 100 #define SWRM_AHB_BRIDGE_RD_DATA_0                               0xc91
 101
 102 #define SWRM_REG_VAL_PACK(data, dev, id, reg)   \
 103                         ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
 104
 105 #define SWRM_SPECIAL_CMD_ID     0xF
 106 #define MAX_FREQ_NUM            1
 107 #define TIMEOUT_MS              (2 * HZ)
 108 #define QCOM_SWRM_MAX_RD_LEN    0x1
 109 #define QCOM_SDW_MAX_PORTS      14
 110 #define DEFAULT_CLK_FREQ        9600000
 111 #define SWRM_MAX_DAIS           0xF
 112 #define SWR_INVALID_PARAM 0xFF
 113 #define SWR_HSTOP_MAX_VAL 0xF
 114 #define SWR_HSTART_MIN_VAL 0x0
 115 #define SWR_BROADCAST_CMD_ID    0x0F
 116 #define SWR_MAX_CMD_ID  14
 117 #define MAX_FIFO_RD_RETRY 3
 118 #define SWR_OVERFLOW_RETRY_COUNT 30
 119 #define SWRM_LINK_STATUS_RETRY_CNT 100
 120
 121 enum {
 122         MASTER_ID_WSA = 1,
 123         MASTER_ID_RX,
 124         MASTER_ID_TX
 125 };
 126
 127 struct qcom_swrm_port_config {
 128         u8 si;
 129         u8 off1;
 130         u8 off2;
 131         u8 bp_mode;
 132         u8 hstart;
 133         u8 hstop;
 134         u8 word_length;
 135         u8 blk_group_count;
 136         u8 lane_control;
 137 };
 138
 139 struct qcom_swrm_ctrl {
 140         struct sdw_bus bus;
 141         struct device *dev;
 142         struct regmap *regmap;
 143         void __iomem *mmio;
 144 #ifdef CONFIG_DEBUG_FS
 145         struct dentry *debugfs;
 146 #endif
 147         struct completion broadcast;
 148         struct completion enumeration;
 149         struct work_struct slave_work;
 150         /* Port alloc/free lock */
 151         struct mutex port_lock;
 152         struct clk *hclk;
 153         u8 wr_cmd_id;
 154         u8 rd_cmd_id;
 155         int irq;
 156         unsigned int version;
 157         int num_din_ports;
 158         int num_dout_ports;
 159         int cols_index;
 160         int rows_index;
 161         unsigned long dout_port_mask;
 162         unsigned long din_port_mask;
 163         u32 intr_mask;
 164         u8 rcmd_id;
 165         u8 wcmd_id;
 166         struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS];
 167         struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
 168         enum sdw_slave_status status[SDW_MAX_DEVICES];
 169         int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
 170         int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
 171         u32 slave_status;
 172         u32 wr_fifo_depth;
 173         u32 rd_fifo_depth;
 174         bool clock_stop_not_supported;
 175 };
 176
 177 struct qcom_swrm_data {
 178         u32 default_cols;
 179         u32 default_rows;
 180 };
 181
 182 static struct qcom_swrm_data swrm_v1_3_data = {
 183         .default_rows = 48,
 184         .default_cols = 16,
 185 };
 186
 187 static struct qcom_swrm_data swrm_v1_5_data = {
 188         .default_rows = 50,
 189         .default_cols = 16,
 190 };
 191
 192 #define to_qcom_sdw(b)  container_of(b, struct qcom_swrm_ctrl, bus)
 193
 194 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
 195                                   u32 *val)
 196 {
 197         struct regmap *wcd_regmap = ctrl->regmap;
 198         int ret;
 199
 200         /* pg register + offset */
 201         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0,
 202                           (u8 *)&reg, 4);
 203         if (ret < 0)
 204                 return SDW_CMD_FAIL;
 205
 206         ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0,
 207                                val, 4);
 208         if (ret < 0)
 209                 return SDW_CMD_FAIL;
 210
 211         return SDW_CMD_OK;
 212 }
 213
 214 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
 215                                    int reg, int val)
 216 {
 217         struct regmap *wcd_regmap = ctrl->regmap;
 218         int ret;
 219         /* pg register + offset */
 220         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0,
 221                           (u8 *)&val, 4);
 222         if (ret)
 223                 return SDW_CMD_FAIL;
 224
 225         /* write address register */
 226         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0,
 227                           (u8 *)&reg, 4);
 228         if (ret)
 229                 return SDW_CMD_FAIL;
 230
 231         return SDW_CMD_OK;
 232 }
 233
 234 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
 235                                   u32 *val)
 236 {
 237         *val = readl(ctrl->mmio + reg);
 238         return SDW_CMD_OK;
 239 }
 240
 241 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
 242                                    int val)
 243 {
 244         writel(val, ctrl->mmio + reg);
 245         return SDW_CMD_OK;
 246 }
 247
 248 static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
 249                                    u8 dev_addr, u16 reg_addr)
 250 {
 251         u32 val;
 252         u8 id = *cmd_id;
 253
 254         if (id != SWR_BROADCAST_CMD_ID) {
 255                 if (id < SWR_MAX_CMD_ID)
 256                         id += 1;
 257                 else
 258                         id = 0;
 259                 *cmd_id = id;
 260         }
 261         val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
 262
 263         return val;
 264 }
 265
 266 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm)
 267 {
 268         u32 fifo_outstanding_data, value;
 269         int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 270
 271         do {
 272                 /* Check for fifo underflow during read */
 273                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 274                 fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
 275
 276                 /* Check if read data is available in read fifo */
 277                 if (fifo_outstanding_data > 0)
 278                         return 0;
 279
 280                 usleep_range(500, 510);
 281         } while (fifo_retry_count--);
 282
 283         if (fifo_outstanding_data == 0) {
 284                 dev_err_ratelimited(swrm->dev, "%s err read underflow\n", __func__);
 285                 return -EIO;
 286         }
 287
 288         return 0;
 289 }
 290
 291 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *swrm)
 292 {
 293         u32 fifo_outstanding_cmds, value;
 294         int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 295
 296         do {
 297                 /* Check for fifo overflow during write */
 298                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 299                 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
 300
 301                 /* Check for space in write fifo before writing */
 302                 if (fifo_outstanding_cmds < swrm->wr_fifo_depth)
 303                         return 0;
 304
 305                 usleep_range(500, 510);
 306         } while (fifo_retry_count--);
 307
 308         if (fifo_outstanding_cmds == swrm->wr_fifo_depth) {
 309                 dev_err_ratelimited(swrm->dev, "%s err write overflow\n", __func__);
 310                 return -EIO;
 311         }
 312
 313         return 0;
 314 }
 315
 316 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data,
 317                                      u8 dev_addr, u16 reg_addr)
 318 {
 319
 320         u32 val;
 321         int ret = 0;
 322         u8 cmd_id = 0x0;
 323
 324         if (dev_addr == SDW_BROADCAST_DEV_NUM) {
 325                 cmd_id = SWR_BROADCAST_CMD_ID;
 326                 val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
 327                                               dev_addr, reg_addr);
 328         } else {
 329                 val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data,
 330                                               dev_addr, reg_addr);
 331         }
 332
 333         if (swrm_wait_for_wr_fifo_avail(swrm))
 334                 return SDW_CMD_FAIL_OTHER;
 335
 336         /* Its assumed that write is okay as we do not get any status back */
 337         swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val);
 338
 339         /* version 1.3 or less */
 340         if (swrm->version <= 0x01030000)
 341                 usleep_range(150, 155);
 342
 343         if (cmd_id == SWR_BROADCAST_CMD_ID) {
 344                 /*
 345                  * sleep for 10ms for MSM soundwire variant to allow broadcast
 346                  * command to complete.
 347                  */
 348                 ret = wait_for_completion_timeout(&swrm->broadcast,
 349                                                   msecs_to_jiffies(TIMEOUT_MS));
 350                 if (!ret)
 351                         ret = SDW_CMD_IGNORED;
 352                 else
 353                         ret = SDW_CMD_OK;
 354
 355         } else {
 356                 ret = SDW_CMD_OK;
 357         }
 358         return ret;
 359 }
 360
 361 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm,
 362                                      u8 dev_addr, u16 reg_addr,
 363                                      u32 len, u8 *rval)
 364 {
 365         u32 cmd_data, cmd_id, val, retry_attempt = 0;
 366
 367         val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr);
 368
 369         /* wait for FIFO RD to complete to avoid overflow */
 370         usleep_range(100, 105);
 371         swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
 372         /* wait for FIFO RD CMD complete to avoid overflow */
 373         usleep_range(250, 255);
 374
 375         if (swrm_wait_for_rd_fifo_avail(swrm))
 376                 return SDW_CMD_FAIL_OTHER;
 377
 378         do {
 379                 swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data);
 380                 rval[0] = cmd_data & 0xFF;
 381                 cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data);
 382
 383                 if (cmd_id != swrm->rcmd_id) {
 384                         if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) {
 385                                 /* wait 500 us before retry on fifo read failure */
 386                                 usleep_range(500, 505);
 387                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD,
 388                                                 SWRM_CMD_FIFO_FLUSH);
 389                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
 390                         }
 391                         retry_attempt++;
 392                 } else {
 393                         return SDW_CMD_OK;
 394                 }
 395
 396         } while (retry_attempt < MAX_FIFO_RD_RETRY);
 397
 398         dev_err(swrm->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
 399                 dev_num: 0x%x, cmd_data: 0x%x\n",
 400                 reg_addr, swrm->rcmd_id, dev_addr, cmd_data);
 401
 402         return SDW_CMD_IGNORED;
 403 }
 404
 405 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl)
 406 {
 407         u32 val, status;
 408         int dev_num;
 409
 410         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
 411
 412         for (dev_num = 0; dev_num < SDW_MAX_DEVICES; dev_num++) {
 413                 status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ));
 414
 415                 if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) {
 416                         ctrl->status[dev_num] = status;
 417                         return dev_num;
 418                 }
 419         }
 420
 421         return -EINVAL;
 422 }
 423
 424 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
 425 {
 426         u32 val;
 427         int i;
 428
 429         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
 430         ctrl->slave_status = val;
 431
 432         for (i = 0; i < SDW_MAX_DEVICES; i++) {
 433                 u32 s;
 434
 435                 s = (val >> (i * 2));
 436                 s &= SWRM_MCP_SLV_STATUS_MASK;
 437                 ctrl->status[i] = s;
 438         }
 439 }
 440
 441 static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus,
 442                                         struct sdw_slave *slave, int devnum)
 443 {
 444         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 445         u32 status;
 446
 447         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status);
 448         status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ));
 449         status &= SWRM_MCP_SLV_STATUS_MASK;
 450
 451         if (status == SDW_SLAVE_ATTACHED) {
 452                 if (slave)
 453                         slave->dev_num = devnum;
 454                 mutex_lock(&bus->bus_lock);
 455                 set_bit(devnum, bus->assigned);
 456                 mutex_unlock(&bus->bus_lock);
 457         }
 458 }
 459
 460 static int qcom_swrm_enumerate(struct sdw_bus *bus)
 461 {
 462         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 463         struct sdw_slave *slave, *_s;
 464         struct sdw_slave_id id;
 465         u32 val1, val2;
 466         bool found;
 467         u64 addr;
 468         int i;
 469         char *buf1 = (char *)&val1, *buf2 = (char *)&val2;
 470
 471         for (i = 1; i <= SDW_MAX_DEVICES; i++) {
 472                 /*SCP_Devid5 - Devid 4*/
 473                 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1);
 474
 475                 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/
 476                 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2);
 477
 478                 if (!val1 && !val2)
 479                         break;
 480
 481                 addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) |
 482                         ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) |
 483                         ((u64)buf1[0] << 40);
 484
 485                 sdw_extract_slave_id(bus, addr, &id);
 486                 found = false;
 487                 /* Now compare with entries */
 488                 list_for_each_entry_safe(slave, _s, &bus->slaves, node) {
 489                         if (sdw_compare_devid(slave, id) == 0) {
 490                                 qcom_swrm_set_slave_dev_num(bus, slave, i);
 491                                 found = true;
 492                                 break;
 493                         }
 494                 }
 495
 496                 if (!found) {
 497                         qcom_swrm_set_slave_dev_num(bus, NULL, i);
 498                         sdw_slave_add(bus, &id, NULL);
 499                 }
 500         }
 501
 502         complete(&ctrl->enumeration);
 503         return 0;
 504 }
 505
 506 static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
 507 {
 508         struct qcom_swrm_ctrl *swrm = dev_id;
 509         u32 value, intr_sts, intr_sts_masked, slave_status;
 510         u32 i;
 511         int devnum;
 512         int ret = IRQ_HANDLED;
 513         clk_prepare_enable(swrm->hclk);
 514
 515         swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
 516         intr_sts_masked = intr_sts & swrm->intr_mask;
 517
 518         do {
 519                 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
 520                         value = intr_sts_masked & BIT(i);
 521                         if (!value)
 522                                 continue;
 523
 524                         switch (value) {
 525                         case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
 526                                 devnum = qcom_swrm_get_alert_slave_dev_num(swrm);
 527                                 if (devnum < 0) {
 528                                         dev_err_ratelimited(swrm->dev,
 529                                             "no slave alert found.spurious interrupt\n");
 530                                 } else {
 531                                         sdw_handle_slave_status(&swrm->bus, swrm->status);
 532                                 }
 533
 534                                 break;
 535                         case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
 536                         case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
 537                                 dev_err_ratelimited(swrm->dev, "%s: SWR new slave attached\n",
 538                                         __func__);
 539                                 swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status);
 540                                 if (swrm->slave_status == slave_status) {
 541                                         dev_err(swrm->dev, "Slave status not changed %x\n",
 542                                                 slave_status);
 543                                 } else {
 544                                         qcom_swrm_get_device_status(swrm);
 545                                         qcom_swrm_enumerate(&swrm->bus);
 546                                         sdw_handle_slave_status(&swrm->bus, swrm->status);
 547                                 }
 548                                 break;
 549                         case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
 550                                 dev_err_ratelimited(swrm->dev,
 551                                                 "%s: SWR bus clsh detected\n",
 552                                                 __func__);
 553                                 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
 554                                 swrm->reg_write(swrm, SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
 555                                 break;
 556                         case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
 557                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 558                                 dev_err_ratelimited(swrm->dev,
 559                                         "%s: SWR read FIFO overflow fifo status 0x%x\n",
 560                                         __func__, value);
 561                                 break;
 562                         case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
 563                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 564                                 dev_err_ratelimited(swrm->dev,
 565                                         "%s: SWR read FIFO underflow fifo status 0x%x\n",
 566                                         __func__, value);
 567                                 break;
 568                         case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
 569                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 570                                 dev_err(swrm->dev,
 571                                         "%s: SWR write FIFO overflow fifo status %x\n",
 572                                         __func__, value);
 573                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
 574                                 break;
 575                         case SWRM_INTERRUPT_STATUS_CMD_ERROR:
 576                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 577                                 dev_err_ratelimited(swrm->dev,
 578                                         "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n",
 579                                         __func__, value);
 580                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
 581                                 break;
 582                         case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
 583                                 dev_err_ratelimited(swrm->dev,
 584                                                 "%s: SWR Port collision detected\n",
 585                                                 __func__);
 586                                 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
 587                                 swrm->reg_write(swrm,
 588                                         SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
 589                                 break;
 590                         case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
 591                                 dev_err_ratelimited(swrm->dev,
 592                                         "%s: SWR read enable valid mismatch\n",
 593                                         __func__);
 594                                 swrm->intr_mask &=
 595                                         ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
 596                                 swrm->reg_write(swrm,
 597                                         SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
 598                                 break;
 599                         case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
 600                                 complete(&swrm->broadcast);
 601                                 break;
 602                         case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2:
 603                                 break;
 604                         case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2:
 605                                 break;
 606                         case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP:
 607                                 break;
 608                         default:
 609                                 dev_err_ratelimited(swrm->dev,
 610                                                 "%s: SWR unknown interrupt value: %d\n",
 611                                                 __func__, value);
 612                                 ret = IRQ_NONE;
 613                                 break;
 614                         }
 615                 }
 616                 swrm->reg_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts);
 617                 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
 618                 intr_sts_masked = intr_sts & swrm->intr_mask;
 619         } while (intr_sts_masked);
 620
 621         clk_disable_unprepare(swrm->hclk);
 622         return ret;
 623 }
 624
 625 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
 626 {
 627         u32 val;
 628
 629         /* Clear Rows and Cols */
 630         val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
 631         val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
 632
 633         ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
 634
 635         /* Enable Auto enumeration */
 636         ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
 637
 638         ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK;
 639         /* Mask soundwire interrupts */
 640         ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR,
 641                         SWRM_INTERRUPT_STATUS_RMSK);
 642
 643         /* Configure No pings */
 644         ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
 645         u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
 646         ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
 647
 648         ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
 649         /* Configure number of retries of a read/write cmd */
 650         if (ctrl->version > 0x01050001) {
 651                 /* Only for versions >= 1.5.1 */
 652                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
 653                                 SWRM_RD_WR_CMD_RETRIES |
 654                                 SWRM_CONTINUE_EXEC_ON_CMD_IGNORE);
 655         } else {
 656                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
 657                                 SWRM_RD_WR_CMD_RETRIES);
 658         }
 659
 660         /* Set IRQ to PULSE */
 661         ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
 662                         SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
 663                         SWRM_COMP_CFG_ENABLE_MSK);
 664
 665         /* enable CPU IRQs */
 666         if (ctrl->mmio) {
 667                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN,
 668                                 SWRM_INTERRUPT_STATUS_RMSK);
 669         }
 670         ctrl->slave_status = 0;
 671         ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
 672         ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val);
 673         ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);
 674
 675         return 0;
 676 }
 677
 678 static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus,
 679                                                     struct sdw_msg *msg)
 680 {
 681         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 682         int ret, i, len;
 683
 684         if (msg->flags == SDW_MSG_FLAG_READ) {
 685                 for (i = 0; i < msg->len;) {
 686                         if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN)
 687                                 len = msg->len - i;
 688                         else
 689                                 len = QCOM_SWRM_MAX_RD_LEN;
 690
 691                         ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
 692                                                         msg->addr + i, len,
 693                                                        &msg->buf[i]);
 694                         if (ret)
 695                                 return ret;
 696
 697                         i = i + len;
 698                 }
 699         } else if (msg->flags == SDW_MSG_FLAG_WRITE) {
 700                 for (i = 0; i < msg->len; i++) {
 701                         ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
 702                                                         msg->dev_num,
 703                                                        msg->addr + i);
 704                         if (ret)
 705                                 return SDW_CMD_IGNORED;
 706                 }
 707         }
 708
 709         return SDW_CMD_OK;
 710 }
 711
 712 static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus)
 713 {
 714         u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);
 715         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 716         u32 val;
 717
 718         ctrl->reg_read(ctrl, reg, &val);
 719
 720         u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
 721         u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
 722
 723         return ctrl->reg_write(ctrl, reg, val);
 724 }
 725
 726 static int qcom_swrm_port_params(struct sdw_bus *bus,
 727                                  struct sdw_port_params *p_params,
 728                                  unsigned int bank)
 729 {
 730         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 731
 732         return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),
 733                                p_params->bps - 1);
 734
 735 }
 736
 737 static int qcom_swrm_transport_params(struct sdw_bus *bus,
 738                                       struct sdw_transport_params *params,
 739                                       enum sdw_reg_bank bank)
 740 {
 741         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 742         struct qcom_swrm_port_config *pcfg;
 743         u32 value;
 744         int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank);
 745         int ret;
 746
 747         pcfg = &ctrl->pconfig[params->port_num];
 748
 749         value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
 750         value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
 751         value |= pcfg->si;
 752
 753         ret = ctrl->reg_write(ctrl, reg, value);
 754         if (ret)
 755                 goto err;
 756
 757         if (pcfg->lane_control != SWR_INVALID_PARAM) {
 758                 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank);
 759                 value = pcfg->lane_control;
 760                 ret = ctrl->reg_write(ctrl, reg, value);
 761                 if (ret)
 762                         goto err;
 763         }
 764
 765         if (pcfg->blk_group_count != SWR_INVALID_PARAM) {
 766                 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank);
 767                 value = pcfg->blk_group_count;
 768                 ret = ctrl->reg_write(ctrl, reg, value);
 769                 if (ret)
 770                         goto err;
 771         }
 772
 773         if (pcfg->hstart != SWR_INVALID_PARAM
 774                         && pcfg->hstop != SWR_INVALID_PARAM) {
 775                 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
 776                 value = (pcfg->hstop << 4) | pcfg->hstart;
 777                 ret = ctrl->reg_write(ctrl, reg, value);
 778         } else {
 779                 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
 780                 value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;
 781                 ret = ctrl->reg_write(ctrl, reg, value);
 782         }
 783
 784         if (ret)
 785                 goto err;
 786
 787         if (pcfg->bp_mode != SWR_INVALID_PARAM) {
 788                 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank);
 789                 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
 790         }
 791
 792 err:
 793         return ret;
 794 }
 795
 796 static int qcom_swrm_port_enable(struct sdw_bus *bus,
 797                                  struct sdw_enable_ch *enable_ch,
 798                                  unsigned int bank)
 799 {
 800         u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);
 801         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 802         u32 val;
 803
 804         ctrl->reg_read(ctrl, reg, &val);
 805
 806         if (enable_ch->enable)
 807                 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
 808         else
 809                 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
 810
 811         return ctrl->reg_write(ctrl, reg, val);
 812 }
 813
 814 static const struct sdw_master_port_ops qcom_swrm_port_ops = {
 815         .dpn_set_port_params = qcom_swrm_port_params,
 816         .dpn_set_port_transport_params = qcom_swrm_transport_params,
 817         .dpn_port_enable_ch = qcom_swrm_port_enable,
 818 };
 819
 820 static const struct sdw_master_ops qcom_swrm_ops = {
 821         .xfer_msg = qcom_swrm_xfer_msg,
 822         .pre_bank_switch = qcom_swrm_pre_bank_switch,
 823 };
 824
 825 static int qcom_swrm_compute_params(struct sdw_bus *bus)
 826 {
 827         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 828         struct sdw_master_runtime *m_rt;
 829         struct sdw_slave_runtime *s_rt;
 830         struct sdw_port_runtime *p_rt;
 831         struct qcom_swrm_port_config *pcfg;
 832         struct sdw_slave *slave;
 833         unsigned int m_port;
 834         int i = 1;
 835
 836         list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
 837                 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
 838                         pcfg = &ctrl->pconfig[p_rt->num];
 839                         p_rt->transport_params.port_num = p_rt->num;
 840                         if (pcfg->word_length != SWR_INVALID_PARAM) {
 841                                 sdw_fill_port_params(&p_rt->port_params,
 842                                              p_rt->num,  pcfg->word_length + 1,
 843                                              SDW_PORT_FLOW_MODE_ISOCH,
 844                                              SDW_PORT_DATA_MODE_NORMAL);
 845                         }
 846
 847                 }
 848
 849                 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
 850                         slave = s_rt->slave;
 851                         list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
 852                                 m_port = slave->m_port_map[p_rt->num];
 853                                 /* port config starts at offset 0 so -1 from actual port number */
 854                                 if (m_port)
 855                                         pcfg = &ctrl->pconfig[m_port];
 856                                 else
 857                                         pcfg = &ctrl->pconfig[i];
 858                                 p_rt->transport_params.port_num = p_rt->num;
 859                                 p_rt->transport_params.sample_interval =
 860                                         pcfg->si + 1;
 861                                 p_rt->transport_params.offset1 = pcfg->off1;
 862                                 p_rt->transport_params.offset2 = pcfg->off2;
 863                                 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;
 864                                 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count;
 865
 866                                 p_rt->transport_params.hstart = pcfg->hstart;
 867                                 p_rt->transport_params.hstop = pcfg->hstop;
 868                                 p_rt->transport_params.lane_ctrl = pcfg->lane_control;
 869                                 if (pcfg->word_length != SWR_INVALID_PARAM) {
 870                                         sdw_fill_port_params(&p_rt->port_params,
 871                                                      p_rt->num,
 872                                                      pcfg->word_length + 1,
 873                                                      SDW_PORT_FLOW_MODE_ISOCH,
 874                                                      SDW_PORT_DATA_MODE_NORMAL);
 875                                 }
 876                                 i++;
 877                         }
 878                 }
 879         }
 880
 881         return 0;
 882 }
 883
 884 static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
 885         DEFAULT_CLK_FREQ,
 886 };
 887
 888 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
 889                                         struct sdw_stream_runtime *stream)
 890 {
 891         struct sdw_master_runtime *m_rt;
 892         struct sdw_port_runtime *p_rt;
 893         unsigned long *port_mask;
 894
 895         mutex_lock(&ctrl->port_lock);
 896
 897         list_for_each_entry(m_rt, &stream->master_list, stream_node) {
 898                 if (m_rt->direction == SDW_DATA_DIR_RX)
 899                         port_mask = &ctrl->dout_port_mask;
 900                 else
 901                         port_mask = &ctrl->din_port_mask;
 902
 903                 list_for_each_entry(p_rt, &m_rt->port_list, port_node)
 904                         clear_bit(p_rt->num, port_mask);
 905         }
 906
 907         mutex_unlock(&ctrl->port_lock);
 908 }
 909
 910 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
 911                                         struct sdw_stream_runtime *stream,
 912                                        struct snd_pcm_hw_params *params,
 913                                        int direction)
 914 {
 915         struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS];
 916         struct sdw_stream_config sconfig;
 917         struct sdw_master_runtime *m_rt;
 918         struct sdw_slave_runtime *s_rt;
 919         struct sdw_port_runtime *p_rt;
 920         struct sdw_slave *slave;
 921         unsigned long *port_mask;
 922         int i, maxport, pn, nports = 0, ret = 0;
 923         unsigned int m_port;
 924
 925         mutex_lock(&ctrl->port_lock);
 926         list_for_each_entry(m_rt, &stream->master_list, stream_node) {
 927                 if (m_rt->direction == SDW_DATA_DIR_RX) {
 928                         maxport = ctrl->num_dout_ports;
 929                         port_mask = &ctrl->dout_port_mask;
 930                 } else {
 931                         maxport = ctrl->num_din_ports;
 932                         port_mask = &ctrl->din_port_mask;
 933                 }
 934
 935                 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
 936                         slave = s_rt->slave;
 937                         list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
 938                                 m_port = slave->m_port_map[p_rt->num];
 939                                 /* Port numbers start from 1 - 14*/
 940                                 if (m_port)
 941                                         pn = m_port;
 942                                 else
 943                                         pn = find_first_zero_bit(port_mask, maxport);
 944
 945                                 if (pn > maxport) {
 946                                         dev_err(ctrl->dev, "All ports busy\n");
 947                                         ret = -EBUSY;
 948                                         goto err;
 949                                 }
 950                                 set_bit(pn, port_mask);
 951                                 pconfig[nports].num = pn;
 952                                 pconfig[nports].ch_mask = p_rt->ch_mask;
 953                                 nports++;
 954                         }
 955                 }
 956         }
 957
 958         if (direction == SNDRV_PCM_STREAM_CAPTURE)
 959                 sconfig.direction = SDW_DATA_DIR_TX;
 960         else
 961                 sconfig.direction = SDW_DATA_DIR_RX;
 962
 963         /* hw parameters wil be ignored as we only support PDM */
 964         sconfig.ch_count = 1;
 965         sconfig.frame_rate = params_rate(params);
 966         sconfig.type = stream->type;
 967         sconfig.bps = 1;
 968         sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
 969                               nports, stream);
 970 err:
 971         if (ret) {
 972                 for (i = 0; i < nports; i++)
 973                         clear_bit(pconfig[i].num, port_mask);
 974         }
 975
 976         mutex_unlock(&ctrl->port_lock);
 977
 978         return ret;
 979 }
 980
 981 static int qcom_swrm_hw_params(struct snd_pcm_substream *substream,
 982                                struct snd_pcm_hw_params *params,
 983                               struct snd_soc_dai *dai)
 984 {
 985         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
 986         struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
 987         int ret;
 988
 989         ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
 990                                            substream->stream);
 991         if (ret)
 992                 qcom_swrm_stream_free_ports(ctrl, sruntime);
 993
 994         return ret;
 995 }
 996
 997 static int qcom_swrm_hw_free(struct snd_pcm_substream *substream,
 998                              struct snd_soc_dai *dai)
 999 {
1000         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1001         struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1002
1003         qcom_swrm_stream_free_ports(ctrl, sruntime);
1004         sdw_stream_remove_master(&ctrl->bus, sruntime);
1005
1006         return 0;
1007 }
1008
1009 static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai,
1010                                     void *stream, int direction)
1011 {
1012         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1013
1014         ctrl->sruntime[dai->id] = stream;
1015
1016         return 0;
1017 }
1018
1019 static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction)
1020 {
1021         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1022
1023         return ctrl->sruntime[dai->id];
1024 }
1025
1026 static int qcom_swrm_startup(struct snd_pcm_substream *substream,
1027                              struct snd_soc_dai *dai)
1028 {
1029         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1030         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1031         struct sdw_stream_runtime *sruntime;
1032         struct snd_soc_dai *codec_dai;
1033         int ret, i;
1034
1035         ret = pm_runtime_get_sync(ctrl->dev);
1036         if (ret < 0 && ret != -EACCES) {
1037                 dev_err_ratelimited(ctrl->dev,
1038                                     "pm_runtime_get_sync failed in %s, ret %d\n",
1039                                     __func__, ret);
1040                 pm_runtime_put_noidle(ctrl->dev);
1041                 return ret;
1042         }
1043
1044         sruntime = sdw_alloc_stream(dai->name);
1045         if (!sruntime)
1046                 return -ENOMEM;
1047
1048         ctrl->sruntime[dai->id] = sruntime;
1049
1050         for_each_rtd_codec_dais(rtd, i, codec_dai) {
1051                 ret = snd_soc_dai_set_stream(codec_dai, sruntime,
1052                                              substream->stream);
1053                 if (ret < 0 && ret != -ENOTSUPP) {
1054                         dev_err(dai->dev, "Failed to set sdw stream on %s\n",
1055                                 codec_dai->name);
1056                         sdw_release_stream(sruntime);
1057                         return ret;
1058                 }
1059         }
1060
1061         return 0;
1062 }
1063
1064 static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
1065                                struct snd_soc_dai *dai)
1066 {
1067         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1068
1069         sdw_release_stream(ctrl->sruntime[dai->id]);
1070         ctrl->sruntime[dai->id] = NULL;
1071         pm_runtime_mark_last_busy(ctrl->dev);
1072         pm_runtime_put_autosuspend(ctrl->dev);
1073
1074 }
1075
1076 static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
1077         .hw_params = qcom_swrm_hw_params,
1078         .hw_free = qcom_swrm_hw_free,
1079         .startup = qcom_swrm_startup,
1080         .shutdown = qcom_swrm_shutdown,
1081         .set_stream = qcom_swrm_set_sdw_stream,
1082         .get_stream = qcom_swrm_get_sdw_stream,
1083 };
1084
1085 static const struct snd_soc_component_driver qcom_swrm_dai_component = {
1086         .name = "soundwire",
1087 };
1088
1089 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
1090 {
1091         int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
1092         struct snd_soc_dai_driver *dais;
1093         struct snd_soc_pcm_stream *stream;
1094         struct device *dev = ctrl->dev;
1095         int i;
1096
1097         /* PDM dais are only tested for now */
1098         dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
1099         if (!dais)
1100                 return -ENOMEM;
1101
1102         for (i = 0; i < num_dais; i++) {
1103                 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i);
1104                 if (!dais[i].name)
1105                         return -ENOMEM;
1106
1107                 if (i < ctrl->num_dout_ports)
1108                         stream = &dais[i].playback;
1109                 else
1110                         stream = &dais[i].capture;
1111
1112                 stream->channels_min = 1;
1113                 stream->channels_max = 1;
1114                 stream->rates = SNDRV_PCM_RATE_48000;
1115                 stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
1116
1117                 dais[i].ops = &qcom_swrm_pdm_dai_ops;
1118                 dais[i].id = i;
1119         }
1120
1121         return devm_snd_soc_register_component(ctrl->dev,
1122                                                 &qcom_swrm_dai_component,
1123                                                 dais, num_dais);
1124 }
1125
1126 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
1127 {
1128         struct device_node *np = ctrl->dev->of_node;
1129         u8 off1[QCOM_SDW_MAX_PORTS];
1130         u8 off2[QCOM_SDW_MAX_PORTS];
1131         u8 si[QCOM_SDW_MAX_PORTS];
1132         u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, };
1133         u8 hstart[QCOM_SDW_MAX_PORTS];
1134         u8 hstop[QCOM_SDW_MAX_PORTS];
1135         u8 word_length[QCOM_SDW_MAX_PORTS];
1136         u8 blk_group_count[QCOM_SDW_MAX_PORTS];
1137         u8 lane_control[QCOM_SDW_MAX_PORTS];
1138         int i, ret, nports, val;
1139
1140         ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
1141
1142         ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
1143         ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
1144
1145         ret = of_property_read_u32(np, "qcom,din-ports", &val);
1146         if (ret)
1147                 return ret;
1148
1149         if (val > ctrl->num_din_ports)
1150                 return -EINVAL;
1151
1152         ctrl->num_din_ports = val;
1153
1154         ret = of_property_read_u32(np, "qcom,dout-ports", &val);
1155         if (ret)
1156                 return ret;
1157
1158         if (val > ctrl->num_dout_ports)
1159                 return -EINVAL;
1160
1161         ctrl->num_dout_ports = val;
1162
1163         nports = ctrl->num_dout_ports + ctrl->num_din_ports;
1164         /* Valid port numbers are from 1-14, so mask out port 0 explicitly */
1165         set_bit(0, &ctrl->dout_port_mask);
1166         set_bit(0, &ctrl->din_port_mask);
1167
1168         ret = of_property_read_u8_array(np, "qcom,ports-offset1",
1169                                         off1, nports);
1170         if (ret)
1171                 return ret;
1172
1173         ret = of_property_read_u8_array(np, "qcom,ports-offset2",
1174                                         off2, nports);
1175         if (ret)
1176                 return ret;
1177
1178         ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low",
1179                                         si, nports);
1180         if (ret)
1181                 return ret;
1182
1183         ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode",
1184                                         bp_mode, nports);
1185         if (ret) {
1186                 if (ctrl->version <= 0x01030000)
1187                         memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1188                 else
1189                         return ret;
1190         }
1191
1192         memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1193         of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports);
1194
1195         memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1196         of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports);
1197
1198         memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1199         of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports);
1200
1201         memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1202         of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports);
1203
1204         memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1205         of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports);
1206
1207         for (i = 0; i < nports; i++) {
1208                 /* Valid port number range is from 1-14 */
1209                 ctrl->pconfig[i + 1].si = si[i];
1210                 ctrl->pconfig[i + 1].off1 = off1[i];
1211                 ctrl->pconfig[i + 1].off2 = off2[i];
1212                 ctrl->pconfig[i + 1].bp_mode = bp_mode[i];
1213                 ctrl->pconfig[i + 1].hstart = hstart[i];
1214                 ctrl->pconfig[i + 1].hstop = hstop[i];
1215                 ctrl->pconfig[i + 1].word_length = word_length[i];
1216                 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i];
1217                 ctrl->pconfig[i + 1].lane_control = lane_control[i];
1218         }
1219
1220         return 0;
1221 }
1222
1223 #ifdef CONFIG_DEBUG_FS
1224 static int swrm_reg_show(struct seq_file *s_file, void *data)
1225 {
1226         struct qcom_swrm_ctrl *swrm = s_file->private;
1227         int reg, reg_val, ret;
1228
1229         ret = pm_runtime_get_sync(swrm->dev);
1230         if (ret < 0 && ret != -EACCES) {
1231                 dev_err_ratelimited(swrm->dev,
1232                                     "pm_runtime_get_sync failed in %s, ret %d\n",
1233                                     __func__, ret);
1234                 pm_runtime_put_noidle(swrm->dev);
1235         }
1236
1237         for (reg = 0; reg <= SWR_MSTR_MAX_REG_ADDR; reg += 4) {
1238                 swrm->reg_read(swrm, reg, &reg_val);
1239                 seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val);
1240         }
1241         pm_runtime_mark_last_busy(swrm->dev);
1242         pm_runtime_put_autosuspend(swrm->dev);
1243
1244
1245         return 0;
1246 }
1247 DEFINE_SHOW_ATTRIBUTE(swrm_reg);
1248 #endif
1249
1250 static int qcom_swrm_probe(struct platform_device *pdev)
1251 {
1252         struct device *dev = &pdev->dev;
1253         struct sdw_master_prop *prop;
1254         struct sdw_bus_params *params;
1255         struct qcom_swrm_ctrl *ctrl;
1256         const struct qcom_swrm_data *data;
1257         int ret;
1258         u32 val;
1259
1260         ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1261         if (!ctrl)
1262                 return -ENOMEM;
1263
1264         data = of_device_get_match_data(dev);
1265         ctrl->rows_index = sdw_find_row_index(data->default_rows);
1266         ctrl->cols_index = sdw_find_col_index(data->default_cols);
1267 #if IS_REACHABLE(CONFIG_SLIMBUS)
1268         if (dev->parent->bus == &slimbus_bus) {
1269 #else
1270         if (false) {
1271 #endif
1272                 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1273                 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1274                 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1275                 if (!ctrl->regmap)
1276                         return -EINVAL;
1277         } else {
1278                 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1279                 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1280                 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1281                 if (IS_ERR(ctrl->mmio))
1282                         return PTR_ERR(ctrl->mmio);
1283         }
1284
1285         ctrl->irq = of_irq_get(dev->of_node, 0);
1286         if (ctrl->irq < 0) {
1287                 ret = ctrl->irq;
1288                 goto err_init;
1289         }
1290
1291         ctrl->hclk = devm_clk_get(dev, "iface");
1292         if (IS_ERR(ctrl->hclk)) {
1293                 ret = PTR_ERR(ctrl->hclk);
1294                 goto err_init;
1295         }
1296
1297         clk_prepare_enable(ctrl->hclk);
1298
1299         ctrl->dev = dev;
1300         dev_set_drvdata(&pdev->dev, ctrl);
1301         mutex_init(&ctrl->port_lock);
1302         init_completion(&ctrl->broadcast);
1303         init_completion(&ctrl->enumeration);
1304
1305         ctrl->bus.ops = &qcom_swrm_ops;
1306         ctrl->bus.port_ops = &qcom_swrm_port_ops;
1307         ctrl->bus.compute_params = &qcom_swrm_compute_params;
1308         ctrl->bus.clk_stop_timeout = 300;
1309
1310         ret = qcom_swrm_get_port_config(ctrl);
1311         if (ret)
1312                 goto err_clk;
1313
1314         params = &ctrl->bus.params;
1315         params->max_dr_freq = DEFAULT_CLK_FREQ;
1316         params->curr_dr_freq = DEFAULT_CLK_FREQ;
1317         params->col = data->default_cols;
1318         params->row = data->default_rows;
1319         ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1320         params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
1321         params->next_bank = !params->curr_bank;
1322
1323         prop = &ctrl->bus.prop;
1324         prop->max_clk_freq = DEFAULT_CLK_FREQ;
1325         prop->num_clk_gears = 0;
1326         prop->num_clk_freq = MAX_FREQ_NUM;
1327         prop->clk_freq = &qcom_swrm_freq_tbl[0];
1328         prop->default_col = data->default_cols;
1329         prop->default_row = data->default_rows;
1330
1331         ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1332
1333         ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1334                                         qcom_swrm_irq_handler,
1335                                         IRQF_TRIGGER_RISING |
1336                                         IRQF_ONESHOT,
1337                                         "soundwire", ctrl);
1338         if (ret) {
1339                 dev_err(dev, "Failed to request soundwire irq\n");
1340                 goto err_clk;
1341         }
1342
1343         ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1344         if (ret) {
1345                 dev_err(dev, "Failed to register Soundwire controller (%d)\n",
1346                         ret);
1347                 goto err_clk;
1348         }
1349
1350         qcom_swrm_init(ctrl);
1351         wait_for_completion_timeout(&ctrl->enumeration,
1352                                     msecs_to_jiffies(TIMEOUT_MS));
1353         ret = qcom_swrm_register_dais(ctrl);
1354         if (ret)
1355                 goto err_master_add;
1356
1357         dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n",
1358                  (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1359                  ctrl->version & 0xffff);
1360
1361         pm_runtime_set_autosuspend_delay(dev, 3000);
1362         pm_runtime_use_autosuspend(dev);
1363         pm_runtime_mark_last_busy(dev);
1364         pm_runtime_set_active(dev);
1365         pm_runtime_enable(dev);
1366
1367         /* Clk stop is not supported on WSA Soundwire masters */
1368         if (ctrl->version <= 0x01030000) {
1369                 ctrl->clock_stop_not_supported = true;
1370         } else {
1371                 ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val);
1372                 if (val == MASTER_ID_WSA)
1373                         ctrl->clock_stop_not_supported = true;
1374         }
1375
1376 #ifdef CONFIG_DEBUG_FS
1377         ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1378         debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1379                             &swrm_reg_fops);
1380 #endif
1381
1382         return 0;
1383
1384 err_master_add:
1385         sdw_bus_master_delete(&ctrl->bus);
1386 err_clk:
1387         clk_disable_unprepare(ctrl->hclk);
1388 err_init:
1389         return ret;
1390 }
1391
1392 static int qcom_swrm_remove(struct platform_device *pdev)
1393 {
1394         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1395
1396         sdw_bus_master_delete(&ctrl->bus);
1397         clk_disable_unprepare(ctrl->hclk);
1398
1399         return 0;
1400 }
1401
1402 static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *swrm)
1403 {
1404         int retry = SWRM_LINK_STATUS_RETRY_CNT;
1405         int comp_sts;
1406
1407         do {
1408                 swrm->reg_read(swrm, SWRM_COMP_STATUS, &comp_sts);
1409
1410                 if (comp_sts & SWRM_FRM_GEN_ENABLED)
1411                         return true;
1412
1413                 usleep_range(500, 510);
1414         } while (retry--);
1415
1416         dev_err(swrm->dev, "%s: link status not %s\n", __func__,
1417                 comp_sts && SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected");
1418
1419         return false;
1420 }
1421
1422 static int swrm_runtime_resume(struct device *dev)
1423 {
1424         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1425         int ret;
1426
1427         clk_prepare_enable(ctrl->hclk);
1428
1429         if (ctrl->clock_stop_not_supported) {
1430                 reinit_completion(&ctrl->enumeration);
1431                 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1432                 usleep_range(100, 105);
1433
1434                 qcom_swrm_init(ctrl);
1435
1436                 usleep_range(100, 105);
1437                 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1438                         dev_err(ctrl->dev, "link failed to connect\n");
1439
1440                 /* wait for hw enumeration to complete */
1441                 wait_for_completion_timeout(&ctrl->enumeration,
1442                                             msecs_to_jiffies(TIMEOUT_MS));
1443                 qcom_swrm_get_device_status(ctrl);
1444                 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
1445         } else {
1446                 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1447                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR,
1448                         SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET);
1449
1450                 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1451                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);
1452                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
1453
1454                 usleep_range(100, 105);
1455                 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1456                         dev_err(ctrl->dev, "link failed to connect\n");
1457
1458                 ret = sdw_bus_exit_clk_stop(&ctrl->bus);
1459                 if (ret < 0)
1460                         dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
1461         }
1462
1463         return 0;
1464 }
1465
1466 static int __maybe_unused swrm_runtime_suspend(struct device *dev)
1467 {
1468         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1469         int ret;
1470
1471         if (!ctrl->clock_stop_not_supported) {
1472                 /* Mask bus clash interrupt */
1473                 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1474                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);
1475                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
1476                 /* Prepare slaves for clock stop */
1477                 ret = sdw_bus_prep_clk_stop(&ctrl->bus);
1478                 if (ret < 0 && ret != -ENODATA) {
1479                         dev_err(dev, "prepare clock stop failed %d", ret);
1480                         return ret;
1481                 }
1482
1483                 ret = sdw_bus_clk_stop(&ctrl->bus);
1484                 if (ret < 0 && ret != -ENODATA) {
1485                         dev_err(dev, "bus clock stop failed %d", ret);
1486                         return ret;
1487                 }
1488         }
1489
1490         clk_disable_unprepare(ctrl->hclk);
1491
1492         usleep_range(300, 305);
1493
1494         return 0;
1495 }
1496
1497 static const struct dev_pm_ops swrm_dev_pm_ops = {
1498         SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL)
1499 };
1500
1501 static const struct of_device_id qcom_swrm_of_match[] = {
1502         { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
1503         { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
1504         {/* sentinel */},
1505 };
1506
1507 MODULE_DEVICE_TABLE(of, qcom_swrm_of_match);
1508
1509 static struct platform_driver qcom_swrm_driver = {
1510         .probe  = &qcom_swrm_probe,
1511         .remove = &qcom_swrm_remove,
1512         .driver = {
1513                 .name   = "qcom-soundwire",
1514                 .of_match_table = qcom_swrm_of_match,
1515                 .pm = &swrm_dev_pm_ops,
1516         }
1517 };
1518 module_platform_driver(qcom_swrm_driver);
1519
1520 MODULE_DESCRIPTION("Qualcomm soundwire driver");
1521 MODULE_LICENSE("GPL v2");