drivers/soundwire/intel.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
   2 // Copyright(c) 2015-17 Intel Corporation.
   3
   4 /*
   5  * Soundwire Intel Master Driver
   6  */
   7
   8 #include <linux/acpi.h>
   9 #include <linux/debugfs.h>
  10 #include <linux/delay.h>
  11 #include <linux/module.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/auxiliary_bus.h>
  15 #include <sound/pcm_params.h>
  16 #include <linux/pm_runtime.h>
  17 #include <sound/soc.h>
  18 #include <linux/soundwire/sdw_registers.h>
  19 #include <linux/soundwire/sdw.h>
  20 #include <linux/soundwire/sdw_intel.h>
  21 #include "cadence_master.h"
  22 #include "bus.h"
  23 #include "intel.h"
  24
  25 #define INTEL_MASTER_SUSPEND_DELAY_MS   3000
  26 #define INTEL_MASTER_RESET_ITERATIONS   10
  27
  28 /*
  29  * debug/config flags for the Intel SoundWire Master.
  30  *
  31  * Since we may have multiple masters active, we can have up to 8
  32  * flags reused in each byte, with master0 using the ls-byte, etc.
  33  */
  34
  35 #define SDW_INTEL_MASTER_DISABLE_PM_RUNTIME             BIT(0)
  36 #define SDW_INTEL_MASTER_DISABLE_CLOCK_STOP             BIT(1)
  37 #define SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE        BIT(2)
  38 #define SDW_INTEL_MASTER_DISABLE_MULTI_LINK             BIT(3)
  39
  40 static int md_flags;
  41 module_param_named(sdw_md_flags, md_flags, int, 0444);
  42 MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags (0x0 all off)");
  43
  44 enum intel_pdi_type {
  45         INTEL_PDI_IN = 0,
  46         INTEL_PDI_OUT = 1,
  47         INTEL_PDI_BD = 2,
  48 };
  49
  50 #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns)
  51
  52 /*
  53  * Read, write helpers for HW registers
  54  */
  55 static inline int intel_readl(void __iomem *base, int offset)
  56 {
  57         return readl(base + offset);
  58 }
  59
  60 static inline void intel_writel(void __iomem *base, int offset, int value)
  61 {
  62         writel(value, base + offset);
  63 }
  64
  65 static inline u16 intel_readw(void __iomem *base, int offset)
  66 {
  67         return readw(base + offset);
  68 }
  69
  70 static inline void intel_writew(void __iomem *base, int offset, u16 value)
  71 {
  72         writew(value, base + offset);
  73 }
  74
  75 static int intel_wait_bit(void __iomem *base, int offset, u32 mask, u32 target)
  76 {
  77         int timeout = 10;
  78         u32 reg_read;
  79
  80         do {
  81                 reg_read = readl(base + offset);
  82                 if ((reg_read & mask) == target)
  83                         return 0;
  84
  85                 timeout--;
  86                 usleep_range(50, 100);
  87         } while (timeout != 0);
  88
  89         return -EAGAIN;
  90 }
  91
  92 static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask)
  93 {
  94         writel(value, base + offset);
  95         return intel_wait_bit(base, offset, mask, 0);
  96 }
  97
  98 static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask)
  99 {
 100         writel(value, base + offset);
 101         return intel_wait_bit(base, offset, mask, mask);
 102 }
 103
 104 /*
 105  * debugfs
 106  */
 107 #ifdef CONFIG_DEBUG_FS
 108
 109 #define RD_BUF (2 * PAGE_SIZE)
 110
 111 static ssize_t intel_sprintf(void __iomem *mem, bool l,
 112                              char *buf, size_t pos, unsigned int reg)
 113 {
 114         int value;
 115
 116         if (l)
 117                 value = intel_readl(mem, reg);
 118         else
 119                 value = intel_readw(mem, reg);
 120
 121         return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value);
 122 }
 123
 124 static int intel_reg_show(struct seq_file *s_file, void *data)
 125 {
 126         struct sdw_intel *sdw = s_file->private;
 127         void __iomem *s = sdw->link_res->shim;
 128         void __iomem *a = sdw->link_res->alh;
 129         char *buf;
 130         ssize_t ret;
 131         int i, j;
 132         unsigned int links, reg;
 133
 134         buf = kzalloc(RD_BUF, GFP_KERNEL);
 135         if (!buf)
 136                 return -ENOMEM;
 137
 138         links = intel_readl(s, SDW_SHIM_LCAP) & GENMASK(2, 0);
 139
 140         ret = scnprintf(buf, RD_BUF, "Register  Value\n");
 141         ret += scnprintf(buf + ret, RD_BUF - ret, "\nShim\n");
 142
 143         for (i = 0; i < links; i++) {
 144                 reg = SDW_SHIM_LCAP + i * 4;
 145                 ret += intel_sprintf(s, true, buf, ret, reg);
 146         }
 147
 148         for (i = 0; i < links; i++) {
 149                 ret += scnprintf(buf + ret, RD_BUF - ret, "\nLink%d\n", i);
 150                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLSCAP(i));
 151                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS0CM(i));
 152                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS1CM(i));
 153                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS2CM(i));
 154                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS3CM(i));
 155                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PCMSCAP(i));
 156
 157                 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PCMSyCH registers\n");
 158
 159                 /*
 160                  * the value 10 is the number of PDIs. We will need a
 161                  * cleanup to remove hard-coded Intel configurations
 162                  * from cadence_master.c
 163                  */
 164                 for (j = 0; j < 10; j++) {
 165                         ret += intel_sprintf(s, false, buf, ret,
 166                                         SDW_SHIM_PCMSYCHM(i, j));
 167                         ret += intel_sprintf(s, false, buf, ret,
 168                                         SDW_SHIM_PCMSYCHC(i, j));
 169                 }
 170                 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PDMSCAP, IOCTL, CTMCTL\n");
 171
 172                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PDMSCAP(i));
 173                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_IOCTL(i));
 174                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTMCTL(i));
 175         }
 176
 177         ret += scnprintf(buf + ret, RD_BUF - ret, "\nWake registers\n");
 178         ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKEEN);
 179         ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKESTS);
 180
 181         ret += scnprintf(buf + ret, RD_BUF - ret, "\nALH STRMzCFG\n");
 182         for (i = 0; i < SDW_ALH_NUM_STREAMS; i++)
 183                 ret += intel_sprintf(a, true, buf, ret, SDW_ALH_STRMZCFG(i));
 184
 185         seq_printf(s_file, "%s", buf);
 186         kfree(buf);
 187
 188         return 0;
 189 }
 190 DEFINE_SHOW_ATTRIBUTE(intel_reg);
 191
 192 static int intel_set_m_datamode(void *data, u64 value)
 193 {
 194         struct sdw_intel *sdw = data;
 195         struct sdw_bus *bus = &sdw->cdns.bus;
 196
 197         if (value > SDW_PORT_DATA_MODE_STATIC_1)
 198                 return -EINVAL;
 199
 200         /* Userspace changed the hardware state behind the kernel's back */
 201         add_taint(TAINT_USER, LOCKDEP_STILL_OK);
 202
 203         bus->params.m_data_mode = value;
 204
 205         return 0;
 206 }
 207 DEFINE_DEBUGFS_ATTRIBUTE(intel_set_m_datamode_fops, NULL,
 208                          intel_set_m_datamode, "%llu\n");
 209
 210 static int intel_set_s_datamode(void *data, u64 value)
 211 {
 212         struct sdw_intel *sdw = data;
 213         struct sdw_bus *bus = &sdw->cdns.bus;
 214
 215         if (value > SDW_PORT_DATA_MODE_STATIC_1)
 216                 return -EINVAL;
 217
 218         /* Userspace changed the hardware state behind the kernel's back */
 219         add_taint(TAINT_USER, LOCKDEP_STILL_OK);
 220
 221         bus->params.s_data_mode = value;
 222
 223         return 0;
 224 }
 225 DEFINE_DEBUGFS_ATTRIBUTE(intel_set_s_datamode_fops, NULL,
 226                          intel_set_s_datamode, "%llu\n");
 227
 228 static void intel_debugfs_init(struct sdw_intel *sdw)
 229 {
 230         struct dentry *root = sdw->cdns.bus.debugfs;
 231
 232         if (!root)
 233                 return;
 234
 235         sdw->debugfs = debugfs_create_dir("intel-sdw", root);
 236
 237         debugfs_create_file("intel-registers", 0400, sdw->debugfs, sdw,
 238                             &intel_reg_fops);
 239
 240         debugfs_create_file("intel-m-datamode", 0200, sdw->debugfs, sdw,
 241                             &intel_set_m_datamode_fops);
 242
 243         debugfs_create_file("intel-s-datamode", 0200, sdw->debugfs, sdw,
 244                             &intel_set_s_datamode_fops);
 245
 246         sdw_cdns_debugfs_init(&sdw->cdns, sdw->debugfs);
 247 }
 248
 249 static void intel_debugfs_exit(struct sdw_intel *sdw)
 250 {
 251         debugfs_remove_recursive(sdw->debugfs);
 252 }
 253 #else
 254 static void intel_debugfs_init(struct sdw_intel *sdw) {}
 255 static void intel_debugfs_exit(struct sdw_intel *sdw) {}
 256 #endif /* CONFIG_DEBUG_FS */
 257
 258 /*
 259  * shim ops
 260  */
 261
 262 static int intel_link_power_up(struct sdw_intel *sdw)
 263 {
 264         unsigned int link_id = sdw->instance;
 265         void __iomem *shim = sdw->link_res->shim;
 266         u32 *shim_mask = sdw->link_res->shim_mask;
 267         struct sdw_bus *bus = &sdw->cdns.bus;
 268         struct sdw_master_prop *prop = &bus->prop;
 269         u32 spa_mask, cpa_mask;
 270         u32 link_control;
 271         int ret = 0;
 272         u32 syncprd;
 273         u32 sync_reg;
 274
 275         mutex_lock(sdw->link_res->shim_lock);
 276
 277         /*
 278          * The hardware relies on an internal counter, typically 4kHz,
 279          * to generate the SoundWire SSP - which defines a 'safe'
 280          * synchronization point between commands and audio transport
 281          * and allows for multi link synchronization. The SYNCPRD value
 282          * is only dependent on the oscillator clock provided to
 283          * the IP, so adjust based on _DSD properties reported in DSDT
 284          * tables. The values reported are based on either 24MHz
 285          * (CNL/CML) or 38.4 MHz (ICL/TGL+).
 286          */
 287         if (prop->mclk_freq % 6000000)
 288                 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;
 289         else
 290                 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24;
 291
 292         if (!*shim_mask) {
 293                 dev_dbg(sdw->cdns.dev, "%s: powering up all links\n", __func__);
 294
 295                 /* we first need to program the SyncPRD/CPU registers */
 296                 dev_dbg(sdw->cdns.dev,
 297                         "%s: first link up, programming SYNCPRD\n", __func__);
 298
 299                 /* set SyncPRD period */
 300                 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
 301                 u32p_replace_bits(&sync_reg, syncprd, SDW_SHIM_SYNC_SYNCPRD);
 302
 303                 /* Set SyncCPU bit */
 304                 sync_reg |= SDW_SHIM_SYNC_SYNCCPU;
 305                 intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
 306
 307                 /* Link power up sequence */
 308                 link_control = intel_readl(shim, SDW_SHIM_LCTL);
 309
 310                 /* only power-up enabled links */
 311                 spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, sdw->link_res->link_mask);
 312                 cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask);
 313
 314                 link_control |=  spa_mask;
 315
 316                 ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
 317                 if (ret < 0) {
 318                         dev_err(sdw->cdns.dev, "Failed to power up link: %d\n", ret);
 319                         goto out;
 320                 }
 321
 322                 /* SyncCPU will change once link is active */
 323                 ret = intel_wait_bit(shim, SDW_SHIM_SYNC,
 324                                      SDW_SHIM_SYNC_SYNCCPU, 0);
 325                 if (ret < 0) {
 326                         dev_err(sdw->cdns.dev,
 327                                 "Failed to set SHIM_SYNC: %d\n", ret);
 328                         goto out;
 329                 }
 330         }
 331
 332         *shim_mask |= BIT(link_id);
 333
 334         sdw->cdns.link_up = true;
 335 out:
 336         mutex_unlock(sdw->link_res->shim_lock);
 337
 338         return ret;
 339 }
 340
 341 /* this needs to be called with shim_lock */
 342 static void intel_shim_glue_to_master_ip(struct sdw_intel *sdw)
 343 {
 344         void __iomem *shim = sdw->link_res->shim;
 345         unsigned int link_id = sdw->instance;
 346         u16 ioctl;
 347
 348         /* Switch to MIP from Glue logic */
 349         ioctl = intel_readw(shim,  SDW_SHIM_IOCTL(link_id));
 350
 351         ioctl &= ~(SDW_SHIM_IOCTL_DOE);
 352         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 353         usleep_range(10, 15);
 354
 355         ioctl &= ~(SDW_SHIM_IOCTL_DO);
 356         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 357         usleep_range(10, 15);
 358
 359         ioctl |= (SDW_SHIM_IOCTL_MIF);
 360         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 361         usleep_range(10, 15);
 362
 363         ioctl &= ~(SDW_SHIM_IOCTL_BKE);
 364         ioctl &= ~(SDW_SHIM_IOCTL_COE);
 365         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 366         usleep_range(10, 15);
 367
 368         /* at this point Master IP has full control of the I/Os */
 369 }
 370
 371 /* this needs to be called with shim_lock */
 372 static void intel_shim_master_ip_to_glue(struct sdw_intel *sdw)
 373 {
 374         unsigned int link_id = sdw->instance;
 375         void __iomem *shim = sdw->link_res->shim;
 376         u16 ioctl;
 377
 378         /* Glue logic */
 379         ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
 380         ioctl |= SDW_SHIM_IOCTL_BKE;
 381         ioctl |= SDW_SHIM_IOCTL_COE;
 382         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 383         usleep_range(10, 15);
 384
 385         ioctl &= ~(SDW_SHIM_IOCTL_MIF);
 386         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 387         usleep_range(10, 15);
 388
 389         /* at this point Integration Glue has full control of the I/Os */
 390 }
 391
 392 static int intel_shim_init(struct sdw_intel *sdw, bool clock_stop)
 393 {
 394         void __iomem *shim = sdw->link_res->shim;
 395         unsigned int link_id = sdw->instance;
 396         int ret = 0;
 397         u16 ioctl = 0, act = 0;
 398
 399         mutex_lock(sdw->link_res->shim_lock);
 400
 401         /* Initialize Shim */
 402         ioctl |= SDW_SHIM_IOCTL_BKE;
 403         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 404         usleep_range(10, 15);
 405
 406         ioctl |= SDW_SHIM_IOCTL_WPDD;
 407         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 408         usleep_range(10, 15);
 409
 410         ioctl |= SDW_SHIM_IOCTL_DO;
 411         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 412         usleep_range(10, 15);
 413
 414         ioctl |= SDW_SHIM_IOCTL_DOE;
 415         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 416         usleep_range(10, 15);
 417
 418         intel_shim_glue_to_master_ip(sdw);
 419
 420         u16p_replace_bits(&act, 0x1, SDW_SHIM_CTMCTL_DOAIS);
 421         act |= SDW_SHIM_CTMCTL_DACTQE;
 422         act |= SDW_SHIM_CTMCTL_DODS;
 423         intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act);
 424         usleep_range(10, 15);
 425
 426         mutex_unlock(sdw->link_res->shim_lock);
 427
 428         return ret;
 429 }
 430
 431 static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable)
 432 {
 433         void __iomem *shim = sdw->link_res->shim;
 434         unsigned int link_id = sdw->instance;
 435         u16 wake_en, wake_sts;
 436
 437         mutex_lock(sdw->link_res->shim_lock);
 438         wake_en = intel_readw(shim, SDW_SHIM_WAKEEN);
 439
 440         if (wake_enable) {
 441                 /* Enable the wakeup */
 442                 wake_en |= (SDW_SHIM_WAKEEN_ENABLE << link_id);
 443                 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
 444         } else {
 445                 /* Disable the wake up interrupt */
 446                 wake_en &= ~(SDW_SHIM_WAKEEN_ENABLE << link_id);
 447                 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
 448
 449                 /* Clear wake status */
 450                 wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);
 451                 wake_sts |= (SDW_SHIM_WAKEEN_ENABLE << link_id);
 452                 intel_writew(shim, SDW_SHIM_WAKESTS_STATUS, wake_sts);
 453         }
 454         mutex_unlock(sdw->link_res->shim_lock);
 455 }
 456
 457 static int intel_link_power_down(struct sdw_intel *sdw)
 458 {
 459         u32 link_control, spa_mask, cpa_mask;
 460         unsigned int link_id = sdw->instance;
 461         void __iomem *shim = sdw->link_res->shim;
 462         u32 *shim_mask = sdw->link_res->shim_mask;
 463         int ret = 0;
 464
 465         mutex_lock(sdw->link_res->shim_lock);
 466
 467         if (!(*shim_mask & BIT(link_id)))
 468                 dev_err(sdw->cdns.dev,
 469                         "%s: Unbalanced power-up/down calls\n", __func__);
 470
 471         sdw->cdns.link_up = false;
 472
 473         intel_shim_master_ip_to_glue(sdw);
 474
 475         *shim_mask &= ~BIT(link_id);
 476
 477         if (!*shim_mask) {
 478
 479                 dev_dbg(sdw->cdns.dev, "%s: powering down all links\n", __func__);
 480
 481                 /* Link power down sequence */
 482                 link_control = intel_readl(shim, SDW_SHIM_LCTL);
 483
 484                 /* only power-down enabled links */
 485                 spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, ~sdw->link_res->link_mask);
 486                 cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask);
 487
 488                 link_control &=  spa_mask;
 489
 490                 ret = intel_clear_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
 491                 if (ret < 0) {
 492                         dev_err(sdw->cdns.dev, "%s: could not power down link\n", __func__);
 493
 494                         /*
 495                          * we leave the sdw->cdns.link_up flag as false since we've disabled
 496                          * the link at this point and cannot handle interrupts any longer.
 497                          */
 498                 }
 499         }
 500
 501         mutex_unlock(sdw->link_res->shim_lock);
 502
 503         return ret;
 504 }
 505
 506 static void intel_shim_sync_arm(struct sdw_intel *sdw)
 507 {
 508         void __iomem *shim = sdw->link_res->shim;
 509         u32 sync_reg;
 510
 511         mutex_lock(sdw->link_res->shim_lock);
 512
 513         /* update SYNC register */
 514         sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
 515         sync_reg |= (SDW_SHIM_SYNC_CMDSYNC << sdw->instance);
 516         intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
 517
 518         mutex_unlock(sdw->link_res->shim_lock);
 519 }
 520
 521 static int intel_shim_sync_go_unlocked(struct sdw_intel *sdw)
 522 {
 523         void __iomem *shim = sdw->link_res->shim;
 524         u32 sync_reg;
 525         int ret;
 526
 527         /* Read SYNC register */
 528         sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
 529
 530         /*
 531          * Set SyncGO bit to synchronously trigger a bank switch for
 532          * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all
 533          * the Masters.
 534          */
 535         sync_reg |= SDW_SHIM_SYNC_SYNCGO;
 536
 537         ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
 538                               SDW_SHIM_SYNC_SYNCGO);
 539
 540         if (ret < 0)
 541                 dev_err(sdw->cdns.dev, "SyncGO clear failed: %d\n", ret);
 542
 543         return ret;
 544 }
 545
 546 static int intel_shim_sync_go(struct sdw_intel *sdw)
 547 {
 548         int ret;
 549
 550         mutex_lock(sdw->link_res->shim_lock);
 551
 552         ret = intel_shim_sync_go_unlocked(sdw);
 553
 554         mutex_unlock(sdw->link_res->shim_lock);
 555
 556         return ret;
 557 }
 558
 559 /*
 560  * PDI routines
 561  */
 562 static void intel_pdi_init(struct sdw_intel *sdw,
 563                            struct sdw_cdns_stream_config *config)
 564 {
 565         void __iomem *shim = sdw->link_res->shim;
 566         unsigned int link_id = sdw->instance;
 567         int pcm_cap;
 568
 569         /* PCM Stream Capability */
 570         pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id));
 571
 572         config->pcm_bd = FIELD_GET(SDW_SHIM_PCMSCAP_BSS, pcm_cap);
 573         config->pcm_in = FIELD_GET(SDW_SHIM_PCMSCAP_ISS, pcm_cap);
 574         config->pcm_out = FIELD_GET(SDW_SHIM_PCMSCAP_OSS, pcm_cap);
 575
 576         dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n",
 577                 config->pcm_bd, config->pcm_in, config->pcm_out);
 578 }
 579
 580 static int
 581 intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num)
 582 {
 583         void __iomem *shim = sdw->link_res->shim;
 584         unsigned int link_id = sdw->instance;
 585         int count;
 586
 587         count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num));
 588
 589         /*
 590          * WORKAROUND: on all existing Intel controllers, pdi
 591          * number 2 reports channel count as 1 even though it
 592          * supports 8 channels. Performing hardcoding for pdi
 593          * number 2.
 594          */
 595         if (pdi_num == 2)
 596                 count = 7;
 597
 598         /* zero based values for channel count in register */
 599         count++;
 600
 601         return count;
 602 }
 603
 604 static int intel_pdi_get_ch_update(struct sdw_intel *sdw,
 605                                    struct sdw_cdns_pdi *pdi,
 606                                    unsigned int num_pdi,
 607                                    unsigned int *num_ch)
 608 {
 609         int i, ch_count = 0;
 610
 611         for (i = 0; i < num_pdi; i++) {
 612                 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num);
 613                 ch_count += pdi->ch_count;
 614                 pdi++;
 615         }
 616
 617         *num_ch = ch_count;
 618         return 0;
 619 }
 620
 621 static int intel_pdi_stream_ch_update(struct sdw_intel *sdw,
 622                                       struct sdw_cdns_streams *stream)
 623 {
 624         intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
 625                                 &stream->num_ch_bd);
 626
 627         intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
 628                                 &stream->num_ch_in);
 629
 630         intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
 631                                 &stream->num_ch_out);
 632
 633         return 0;
 634 }
 635
 636 static int intel_pdi_ch_update(struct sdw_intel *sdw)
 637 {
 638         intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm);
 639
 640         return 0;
 641 }
 642
 643 static void
 644 intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
 645 {
 646         void __iomem *shim = sdw->link_res->shim;
 647         unsigned int link_id = sdw->instance;
 648         int pdi_conf = 0;
 649
 650         /* the Bulk and PCM streams are not contiguous */
 651         pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
 652         if (pdi->num >= 2)
 653                 pdi->intel_alh_id += 2;
 654
 655         /*
 656          * Program stream parameters to stream SHIM register
 657          * This is applicable for PCM stream only.
 658          */
 659         if (pdi->type != SDW_STREAM_PCM)
 660                 return;
 661
 662         if (pdi->dir == SDW_DATA_DIR_RX)
 663                 pdi_conf |= SDW_SHIM_PCMSYCM_DIR;
 664         else
 665                 pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR);
 666
 667         u32p_replace_bits(&pdi_conf, pdi->intel_alh_id, SDW_SHIM_PCMSYCM_STREAM);
 668         u32p_replace_bits(&pdi_conf, pdi->l_ch_num, SDW_SHIM_PCMSYCM_LCHN);
 669         u32p_replace_bits(&pdi_conf, pdi->h_ch_num, SDW_SHIM_PCMSYCM_HCHN);
 670
 671         intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf);
 672 }
 673
 674 static void
 675 intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
 676 {
 677         void __iomem *alh = sdw->link_res->alh;
 678         unsigned int link_id = sdw->instance;
 679         unsigned int conf;
 680
 681         /* the Bulk and PCM streams are not contiguous */
 682         pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
 683         if (pdi->num >= 2)
 684                 pdi->intel_alh_id += 2;
 685
 686         /* Program Stream config ALH register */
 687         conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id));
 688
 689         u32p_replace_bits(&conf, SDW_ALH_STRMZCFG_DMAT_VAL, SDW_ALH_STRMZCFG_DMAT);
 690         u32p_replace_bits(&conf, pdi->ch_count - 1, SDW_ALH_STRMZCFG_CHN);
 691
 692         intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf);
 693 }
 694
 695 static int intel_params_stream(struct sdw_intel *sdw,
 696                                int stream,
 697                                struct snd_soc_dai *dai,
 698                                struct snd_pcm_hw_params *hw_params,
 699                                int link_id, int alh_stream_id)
 700 {
 701         struct sdw_intel_link_res *res = sdw->link_res;
 702         struct sdw_intel_stream_params_data params_data;
 703
 704         params_data.stream = stream; /* direction */
 705         params_data.dai = dai;
 706         params_data.hw_params = hw_params;
 707         params_data.link_id = link_id;
 708         params_data.alh_stream_id = alh_stream_id;
 709
 710         if (res->ops && res->ops->params_stream && res->dev)
 711                 return res->ops->params_stream(res->dev,
 712                                                &params_data);
 713         return -EIO;
 714 }
 715
 716 static int intel_free_stream(struct sdw_intel *sdw,
 717                              int stream,
 718                              struct snd_soc_dai *dai,
 719                              int link_id)
 720 {
 721         struct sdw_intel_link_res *res = sdw->link_res;
 722         struct sdw_intel_stream_free_data free_data;
 723
 724         free_data.stream = stream; /* direction */
 725         free_data.dai = dai;
 726         free_data.link_id = link_id;
 727
 728         if (res->ops && res->ops->free_stream && res->dev)
 729                 return res->ops->free_stream(res->dev,
 730                                              &free_data);
 731
 732         return 0;
 733 }
 734
 735 /*
 736  * bank switch routines
 737  */
 738
 739 static int intel_pre_bank_switch(struct sdw_bus *bus)
 740 {
 741         struct sdw_cdns *cdns = bus_to_cdns(bus);
 742         struct sdw_intel *sdw = cdns_to_intel(cdns);
 743
 744         /* Write to register only for multi-link */
 745         if (!bus->multi_link)
 746                 return 0;
 747
 748         intel_shim_sync_arm(sdw);
 749
 750         return 0;
 751 }
 752
 753 static int intel_post_bank_switch(struct sdw_bus *bus)
 754 {
 755         struct sdw_cdns *cdns = bus_to_cdns(bus);
 756         struct sdw_intel *sdw = cdns_to_intel(cdns);
 757         void __iomem *shim = sdw->link_res->shim;
 758         int sync_reg, ret;
 759
 760         /* Write to register only for multi-link */
 761         if (!bus->multi_link)
 762                 return 0;
 763
 764         mutex_lock(sdw->link_res->shim_lock);
 765
 766         /* Read SYNC register */
 767         sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
 768
 769         /*
 770          * post_bank_switch() ops is called from the bus in loop for
 771          * all the Masters in the steam with the expectation that
 772          * we trigger the bankswitch for the only first Master in the list
 773          * and do nothing for the other Masters
 774          *
 775          * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master.
 776          */
 777         if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK)) {
 778                 ret = 0;
 779                 goto unlock;
 780         }
 781
 782         ret = intel_shim_sync_go_unlocked(sdw);
 783 unlock:
 784         mutex_unlock(sdw->link_res->shim_lock);
 785
 786         if (ret < 0)
 787                 dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret);
 788
 789         return ret;
 790 }
 791
 792 /*
 793  * DAI routines
 794  */
 795
 796 static int intel_startup(struct snd_pcm_substream *substream,
 797                          struct snd_soc_dai *dai)
 798 {
 799         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
 800         int ret;
 801
 802         ret = pm_runtime_get_sync(cdns->dev);
 803         if (ret < 0 && ret != -EACCES) {
 804                 dev_err_ratelimited(cdns->dev,
 805                                     "pm_runtime_get_sync failed in %s, ret %d\n",
 806                                     __func__, ret);
 807                 pm_runtime_put_noidle(cdns->dev);
 808                 return ret;
 809         }
 810         return 0;
 811 }
 812
 813 static int intel_hw_params(struct snd_pcm_substream *substream,
 814                            struct snd_pcm_hw_params *params,
 815                            struct snd_soc_dai *dai)
 816 {
 817         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
 818         struct sdw_intel *sdw = cdns_to_intel(cdns);
 819         struct sdw_cdns_dma_data *dma;
 820         struct sdw_cdns_pdi *pdi;
 821         struct sdw_stream_config sconfig;
 822         struct sdw_port_config *pconfig;
 823         int ch, dir;
 824         int ret;
 825
 826         dma = snd_soc_dai_get_dma_data(dai, substream);
 827         if (!dma)
 828                 return -EIO;
 829
 830         ch = params_channels(params);
 831         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 832                 dir = SDW_DATA_DIR_RX;
 833         else
 834                 dir = SDW_DATA_DIR_TX;
 835
 836         pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id);
 837
 838         if (!pdi) {
 839                 ret = -EINVAL;
 840                 goto error;
 841         }
 842
 843         /* do run-time configurations for SHIM, ALH and PDI/PORT */
 844         intel_pdi_shim_configure(sdw, pdi);
 845         intel_pdi_alh_configure(sdw, pdi);
 846         sdw_cdns_config_stream(cdns, ch, dir, pdi);
 847
 848         /* store pdi and hw_params, may be needed in prepare step */
 849         dma->paused = false;
 850         dma->suspended = false;
 851         dma->pdi = pdi;
 852         dma->hw_params = params;
 853
 854         /* Inform DSP about PDI stream number */
 855         ret = intel_params_stream(sdw, substream->stream, dai, params,
 856                                   sdw->instance,
 857                                   pdi->intel_alh_id);
 858         if (ret)
 859                 goto error;
 860
 861         sconfig.direction = dir;
 862         sconfig.ch_count = ch;
 863         sconfig.frame_rate = params_rate(params);
 864         sconfig.type = dma->stream_type;
 865
 866         sconfig.bps = snd_pcm_format_width(params_format(params));
 867
 868         /* Port configuration */
 869         pconfig = kzalloc(sizeof(*pconfig), GFP_KERNEL);
 870         if (!pconfig) {
 871                 ret =  -ENOMEM;
 872                 goto error;
 873         }
 874
 875         pconfig->num = pdi->num;
 876         pconfig->ch_mask = (1 << ch) - 1;
 877
 878         ret = sdw_stream_add_master(&cdns->bus, &sconfig,
 879                                     pconfig, 1, dma->stream);
 880         if (ret)
 881                 dev_err(cdns->dev, "add master to stream failed:%d\n", ret);
 882
 883         kfree(pconfig);
 884 error:
 885         return ret;
 886 }
 887
 888 static int intel_prepare(struct snd_pcm_substream *substream,
 889                          struct snd_soc_dai *dai)
 890 {
 891         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
 892         struct sdw_intel *sdw = cdns_to_intel(cdns);
 893         struct sdw_cdns_dma_data *dma;
 894         int ch, dir;
 895         int ret = 0;
 896
 897         dma = snd_soc_dai_get_dma_data(dai, substream);
 898         if (!dma) {
 899                 dev_err(dai->dev, "failed to get dma data in %s\n",
 900                         __func__);
 901                 return -EIO;
 902         }
 903
 904         if (dma->suspended) {
 905                 dma->suspended = false;
 906
 907                 /*
 908                  * .prepare() is called after system resume, where we
 909                  * need to reinitialize the SHIM/ALH/Cadence IP.
 910                  * .prepare() is also called to deal with underflows,
 911                  * but in those cases we cannot touch ALH/SHIM
 912                  * registers
 913                  */
 914
 915                 /* configure stream */
 916                 ch = params_channels(dma->hw_params);
 917                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 918                         dir = SDW_DATA_DIR_RX;
 919                 else
 920                         dir = SDW_DATA_DIR_TX;
 921
 922                 intel_pdi_shim_configure(sdw, dma->pdi);
 923                 intel_pdi_alh_configure(sdw, dma->pdi);
 924                 sdw_cdns_config_stream(cdns, ch, dir, dma->pdi);
 925
 926                 /* Inform DSP about PDI stream number */
 927                 ret = intel_params_stream(sdw, substream->stream, dai,
 928                                           dma->hw_params,
 929                                           sdw->instance,
 930                                           dma->pdi->intel_alh_id);
 931         }
 932
 933         return ret;
 934 }
 935
 936 static int
 937 intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
 938 {
 939         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
 940         struct sdw_intel *sdw = cdns_to_intel(cdns);
 941         struct sdw_cdns_dma_data *dma;
 942         int ret;
 943
 944         dma = snd_soc_dai_get_dma_data(dai, substream);
 945         if (!dma)
 946                 return -EIO;
 947
 948         /*
 949          * The sdw stream state will transition to RELEASED when stream->
 950          * master_list is empty. So the stream state will transition to
 951          * DEPREPARED for the first cpu-dai and to RELEASED for the last
 952          * cpu-dai.
 953          */
 954         ret = sdw_stream_remove_master(&cdns->bus, dma->stream);
 955         if (ret < 0) {
 956                 dev_err(dai->dev, "remove master from stream %s failed: %d\n",
 957                         dma->stream->name, ret);
 958                 return ret;
 959         }
 960
 961         ret = intel_free_stream(sdw, substream->stream, dai, sdw->instance);
 962         if (ret < 0) {
 963                 dev_err(dai->dev, "intel_free_stream: failed %d\n", ret);
 964                 return ret;
 965         }
 966
 967         dma->hw_params = NULL;
 968         dma->pdi = NULL;
 969
 970         return 0;
 971 }
 972
 973 static void intel_shutdown(struct snd_pcm_substream *substream,
 974                            struct snd_soc_dai *dai)
 975 {
 976         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
 977
 978         pm_runtime_mark_last_busy(cdns->dev);
 979         pm_runtime_put_autosuspend(cdns->dev);
 980 }
 981
 982 static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai,
 983                                     void *stream, int direction)
 984 {
 985         return cdns_set_sdw_stream(dai, stream, direction);
 986 }
 987
 988 static void *intel_get_sdw_stream(struct snd_soc_dai *dai,
 989                                   int direction)
 990 {
 991         struct sdw_cdns_dma_data *dma;
 992
 993         if (direction == SNDRV_PCM_STREAM_PLAYBACK)
 994                 dma = dai->playback_dma_data;
 995         else
 996                 dma = dai->capture_dma_data;
 997
 998         if (!dma)
 999                 return ERR_PTR(-EINVAL);
1000
1001         return dma->stream;
1002 }
1003
1004 static int intel_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
1005 {
1006         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
1007         struct sdw_intel *sdw = cdns_to_intel(cdns);
1008         struct sdw_cdns_dma_data *dma;
1009         int ret = 0;
1010
1011         dma = snd_soc_dai_get_dma_data(dai, substream);
1012         if (!dma) {
1013                 dev_err(dai->dev, "failed to get dma data in %s\n",
1014                         __func__);
1015                 return -EIO;
1016         }
1017
1018         switch (cmd) {
1019         case SNDRV_PCM_TRIGGER_SUSPEND:
1020
1021                 /*
1022                  * The .prepare callback is used to deal with xruns and resume operations.
1023                  * In the case of xruns, the DMAs and SHIM registers cannot be touched,
1024                  * but for resume operations the DMAs and SHIM registers need to be initialized.
1025                  * the .trigger callback is used to track the suspend case only.
1026                  */
1027
1028                 dma->suspended = true;
1029
1030                 ret = intel_free_stream(sdw, substream->stream, dai, sdw->instance);
1031                 break;
1032
1033         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1034                 dma->paused = true;
1035                 break;
1036         case SNDRV_PCM_TRIGGER_STOP:
1037         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1038                 dma->paused = false;
1039                 break;
1040         default:
1041                 break;
1042         }
1043
1044         return ret;
1045 }
1046
1047 static int intel_component_dais_suspend(struct snd_soc_component *component)
1048 {
1049         struct snd_soc_dai *dai;
1050
1051         /*
1052          * In the corner case where a SUSPEND happens during a PAUSE, the ALSA core
1053          * does not throw the TRIGGER_SUSPEND. This leaves the DAIs in an unbalanced state.
1054          * Since the component suspend is called last, we can trap this corner case
1055          * and force the DAIs to release their resources.
1056          */
1057         for_each_component_dais(component, dai) {
1058                 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
1059                 struct sdw_intel *sdw = cdns_to_intel(cdns);
1060                 struct sdw_cdns_dma_data *dma;
1061                 int stream;
1062                 int ret;
1063
1064                 dma = dai->playback_dma_data;
1065                 stream = SNDRV_PCM_STREAM_PLAYBACK;
1066                 if (!dma) {
1067                         dma = dai->capture_dma_data;
1068                         stream = SNDRV_PCM_STREAM_CAPTURE;
1069                 }
1070
1071                 if (!dma)
1072                         continue;
1073
1074                 if (dma->suspended)
1075                         continue;
1076
1077                 if (dma->paused) {
1078                         dma->suspended = true;
1079
1080                         ret = intel_free_stream(sdw, stream, dai, sdw->instance);
1081                         if (ret < 0)
1082                                 return ret;
1083                 }
1084         }
1085
1086         return 0;
1087 }
1088
1089 static const struct snd_soc_dai_ops intel_pcm_dai_ops = {
1090         .startup = intel_startup,
1091         .hw_params = intel_hw_params,
1092         .prepare = intel_prepare,
1093         .hw_free = intel_hw_free,
1094         .trigger = intel_trigger,
1095         .shutdown = intel_shutdown,
1096         .set_stream = intel_pcm_set_sdw_stream,
1097         .get_stream = intel_get_sdw_stream,
1098 };
1099
1100 static const struct snd_soc_component_driver dai_component = {
1101         .name           = "soundwire",
1102         .suspend        = intel_component_dais_suspend
1103 };
1104
1105 static int intel_create_dai(struct sdw_cdns *cdns,
1106                             struct snd_soc_dai_driver *dais,
1107                             enum intel_pdi_type type,
1108                             u32 num, u32 off, u32 max_ch)
1109 {
1110         int i;
1111
1112         if (num == 0)
1113                 return 0;
1114
1115          /* TODO: Read supported rates/formats from hardware */
1116         for (i = off; i < (off + num); i++) {
1117                 dais[i].name = devm_kasprintf(cdns->dev, GFP_KERNEL,
1118                                               "SDW%d Pin%d",
1119                                               cdns->instance, i);
1120                 if (!dais[i].name)
1121                         return -ENOMEM;
1122
1123                 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) {
1124                         dais[i].playback.channels_min = 1;
1125                         dais[i].playback.channels_max = max_ch;
1126                         dais[i].playback.rates = SNDRV_PCM_RATE_48000;
1127                         dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
1128                 }
1129
1130                 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) {
1131                         dais[i].capture.channels_min = 1;
1132                         dais[i].capture.channels_max = max_ch;
1133                         dais[i].capture.rates = SNDRV_PCM_RATE_48000;
1134                         dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
1135                 }
1136
1137                 dais[i].ops = &intel_pcm_dai_ops;
1138         }
1139
1140         return 0;
1141 }
1142
1143 static int intel_register_dai(struct sdw_intel *sdw)
1144 {
1145         struct sdw_cdns *cdns = &sdw->cdns;
1146         struct sdw_cdns_streams *stream;
1147         struct snd_soc_dai_driver *dais;
1148         int num_dai, ret, off = 0;
1149
1150         /* DAIs are created based on total number of PDIs supported */
1151         num_dai = cdns->pcm.num_pdi;
1152
1153         dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
1154         if (!dais)
1155                 return -ENOMEM;
1156
1157         /* Create PCM DAIs */
1158         stream = &cdns->pcm;
1159
1160         ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in,
1161                                off, stream->num_ch_in);
1162         if (ret)
1163                 return ret;
1164
1165         off += cdns->pcm.num_in;
1166         ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,
1167                                off, stream->num_ch_out);
1168         if (ret)
1169                 return ret;
1170
1171         off += cdns->pcm.num_out;
1172         ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,
1173                                off, stream->num_ch_bd);
1174         if (ret)
1175                 return ret;
1176
1177         return snd_soc_register_component(cdns->dev, &dai_component,
1178                                           dais, num_dai);
1179 }
1180
1181 static int sdw_master_read_intel_prop(struct sdw_bus *bus)
1182 {
1183         struct sdw_master_prop *prop = &bus->prop;
1184         struct fwnode_handle *link;
1185         char name[32];
1186         u32 quirk_mask;
1187
1188         /* Find master handle */
1189         snprintf(name, sizeof(name),
1190                  "mipi-sdw-link-%d-subproperties", bus->link_id);
1191
1192         link = device_get_named_child_node(bus->dev, name);
1193         if (!link) {
1194                 dev_err(bus->dev, "Master node %s not found\n", name);
1195                 return -EIO;
1196         }
1197
1198         fwnode_property_read_u32(link,
1199                                  "intel-sdw-ip-clock",
1200                                  &prop->mclk_freq);
1201
1202         /* the values reported by BIOS are the 2x clock, not the bus clock */
1203         prop->mclk_freq /= 2;
1204
1205         fwnode_property_read_u32(link,
1206                                  "intel-quirk-mask",
1207                                  &quirk_mask);
1208
1209         if (quirk_mask & SDW_INTEL_QUIRK_MASK_BUS_DISABLE)
1210                 prop->hw_disabled = true;
1211
1212         prop->quirks = SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH |
1213                 SDW_MASTER_QUIRKS_CLEAR_INITIAL_PARITY;
1214
1215         return 0;
1216 }
1217
1218 static int intel_prop_read(struct sdw_bus *bus)
1219 {
1220         /* Initialize with default handler to read all DisCo properties */
1221         sdw_master_read_prop(bus);
1222
1223         /* read Intel-specific properties */
1224         sdw_master_read_intel_prop(bus);
1225
1226         return 0;
1227 }
1228
1229 static struct sdw_master_ops sdw_intel_ops = {
1230         .read_prop = sdw_master_read_prop,
1231         .override_adr = sdw_dmi_override_adr,
1232         .xfer_msg = cdns_xfer_msg,
1233         .xfer_msg_defer = cdns_xfer_msg_defer,
1234         .reset_page_addr = cdns_reset_page_addr,
1235         .set_bus_conf = cdns_bus_conf,
1236         .pre_bank_switch = intel_pre_bank_switch,
1237         .post_bank_switch = intel_post_bank_switch,
1238 };
1239
1240 static int intel_init(struct sdw_intel *sdw)
1241 {
1242         bool clock_stop;
1243
1244         /* Initialize shim and controller */
1245         intel_link_power_up(sdw);
1246
1247         clock_stop = sdw_cdns_is_clock_stop(&sdw->cdns);
1248
1249         intel_shim_init(sdw, clock_stop);
1250
1251         return 0;
1252 }
1253
1254 /*
1255  * probe and init (aux_dev_id argument is required by function prototype but not used)
1256  */
1257 static int intel_link_probe(struct auxiliary_device *auxdev,
1258                             const struct auxiliary_device_id *aux_dev_id)
1259
1260 {
1261         struct device *dev = &auxdev->dev;
1262         struct sdw_intel_link_dev *ldev = auxiliary_dev_to_sdw_intel_link_dev(auxdev);
1263         struct sdw_intel *sdw;
1264         struct sdw_cdns *cdns;
1265         struct sdw_bus *bus;
1266         int ret;
1267
1268         sdw = devm_kzalloc(dev, sizeof(*sdw), GFP_KERNEL);
1269         if (!sdw)
1270                 return -ENOMEM;
1271
1272         cdns = &sdw->cdns;
1273         bus = &cdns->bus;
1274
1275         sdw->instance = auxdev->id;
1276         sdw->link_res = &ldev->link_res;
1277         cdns->dev = dev;
1278         cdns->registers = sdw->link_res->registers;
1279         cdns->instance = sdw->instance;
1280         cdns->msg_count = 0;
1281
1282         bus->link_id = auxdev->id;
1283
1284         sdw_cdns_probe(cdns);
1285
1286         /* Set property read ops */
1287         sdw_intel_ops.read_prop = intel_prop_read;
1288         bus->ops = &sdw_intel_ops;
1289
1290         /* set driver data, accessed by snd_soc_dai_get_drvdata() */
1291         auxiliary_set_drvdata(auxdev, cdns);
1292
1293         /* use generic bandwidth allocation algorithm */
1294         sdw->cdns.bus.compute_params = sdw_compute_params;
1295
1296         ret = sdw_bus_master_add(bus, dev, dev->fwnode);
1297         if (ret) {
1298                 dev_err(dev, "sdw_bus_master_add fail: %d\n", ret);
1299                 return ret;
1300         }
1301
1302         if (bus->prop.hw_disabled)
1303                 dev_info(dev,
1304                          "SoundWire master %d is disabled, will be ignored\n",
1305                          bus->link_id);
1306         /*
1307          * Ignore BIOS err_threshold, it's a really bad idea when dealing
1308          * with multiple hardware synchronized links
1309          */
1310         bus->prop.err_threshold = 0;
1311
1312         return 0;
1313 }
1314
1315 int intel_link_startup(struct auxiliary_device *auxdev)
1316 {
1317         struct sdw_cdns_stream_config config;
1318         struct device *dev = &auxdev->dev;
1319         struct sdw_cdns *cdns = auxiliary_get_drvdata(auxdev);
1320         struct sdw_intel *sdw = cdns_to_intel(cdns);
1321         struct sdw_bus *bus = &cdns->bus;
1322         int link_flags;
1323         bool multi_link;
1324         u32 clock_stop_quirks;
1325         int ret;
1326
1327         if (bus->prop.hw_disabled) {
1328                 dev_info(dev,
1329                          "SoundWire master %d is disabled, ignoring\n",
1330                          sdw->instance);
1331                 return 0;
1332         }
1333
1334         link_flags = md_flags >> (bus->link_id * 8);
1335         multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK);
1336         if (!multi_link) {
1337                 dev_dbg(dev, "Multi-link is disabled\n");
1338                 bus->multi_link = false;
1339         } else {
1340                 /*
1341                  * hardware-based synchronization is required regardless
1342                  * of the number of segments used by a stream: SSP-based
1343                  * synchronization is gated by gsync when the multi-master
1344                  * mode is set.
1345                  */
1346                 bus->multi_link = true;
1347                 bus->hw_sync_min_links = 1;
1348         }
1349
1350         /* Initialize shim, controller */
1351         ret = intel_init(sdw);
1352         if (ret)
1353                 goto err_init;
1354
1355         /* Read the PDI config and initialize cadence PDI */
1356         intel_pdi_init(sdw, &config);
1357         ret = sdw_cdns_pdi_init(cdns, config);
1358         if (ret)
1359                 goto err_init;
1360
1361         intel_pdi_ch_update(sdw);
1362
1363         ret = sdw_cdns_enable_interrupt(cdns, true);
1364         if (ret < 0) {
1365                 dev_err(dev, "cannot enable interrupts\n");
1366                 goto err_init;
1367         }
1368
1369         /*
1370          * follow recommended programming flows to avoid timeouts when
1371          * gsync is enabled
1372          */
1373         if (multi_link)
1374                 intel_shim_sync_arm(sdw);
1375
1376         ret = sdw_cdns_init(cdns);
1377         if (ret < 0) {
1378                 dev_err(dev, "unable to initialize Cadence IP\n");
1379                 goto err_interrupt;
1380         }
1381
1382         ret = sdw_cdns_exit_reset(cdns);
1383         if (ret < 0) {
1384                 dev_err(dev, "unable to exit bus reset sequence\n");
1385                 goto err_interrupt;
1386         }
1387
1388         if (multi_link) {
1389                 ret = intel_shim_sync_go(sdw);
1390                 if (ret < 0) {
1391                         dev_err(dev, "sync go failed: %d\n", ret);
1392                         goto err_interrupt;
1393                 }
1394         }
1395         sdw_cdns_check_self_clearing_bits(cdns, __func__,
1396                                           true, INTEL_MASTER_RESET_ITERATIONS);
1397
1398         /* Register DAIs */
1399         ret = intel_register_dai(sdw);
1400         if (ret) {
1401                 dev_err(dev, "DAI registration failed: %d\n", ret);
1402                 snd_soc_unregister_component(dev);
1403                 goto err_interrupt;
1404         }
1405
1406         intel_debugfs_init(sdw);
1407
1408         /* Enable runtime PM */
1409         if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME)) {
1410                 pm_runtime_set_autosuspend_delay(dev,
1411                                                  INTEL_MASTER_SUSPEND_DELAY_MS);
1412                 pm_runtime_use_autosuspend(dev);
1413                 pm_runtime_mark_last_busy(dev);
1414
1415                 pm_runtime_set_active(dev);
1416                 pm_runtime_enable(dev);
1417         }
1418
1419         clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1420         if (clock_stop_quirks & SDW_INTEL_CLK_STOP_NOT_ALLOWED) {
1421                 /*
1422                  * To keep the clock running we need to prevent
1423                  * pm_runtime suspend from happening by increasing the
1424                  * reference count.
1425                  * This quirk is specified by the parent PCI device in
1426                  * case of specific latency requirements. It will have
1427                  * no effect if pm_runtime is disabled by the user via
1428                  * a module parameter for testing purposes.
1429                  */
1430                 pm_runtime_get_noresume(dev);
1431         }
1432
1433         /*
1434          * The runtime PM status of Slave devices is "Unsupported"
1435          * until they report as ATTACHED. If they don't, e.g. because
1436          * there are no Slave devices populated or if the power-on is
1437          * delayed or dependent on a power switch, the Master will
1438          * remain active and prevent its parent from suspending.
1439          *
1440          * Conditionally force the pm_runtime core to re-evaluate the
1441          * Master status in the absence of any Slave activity. A quirk
1442          * is provided to e.g. deal with Slaves that may be powered on
1443          * with a delay. A more complete solution would require the
1444          * definition of Master properties.
1445          */
1446         if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE))
1447                 pm_runtime_idle(dev);
1448
1449         sdw->startup_done = true;
1450         return 0;
1451
1452 err_interrupt:
1453         sdw_cdns_enable_interrupt(cdns, false);
1454 err_init:
1455         return ret;
1456 }
1457
1458 static void intel_link_remove(struct auxiliary_device *auxdev)
1459 {
1460         struct device *dev = &auxdev->dev;
1461         struct sdw_cdns *cdns = auxiliary_get_drvdata(auxdev);
1462         struct sdw_intel *sdw = cdns_to_intel(cdns);
1463         struct sdw_bus *bus = &cdns->bus;
1464
1465         /*
1466          * Since pm_runtime is already disabled, we don't decrease
1467          * the refcount when the clock_stop_quirk is
1468          * SDW_INTEL_CLK_STOP_NOT_ALLOWED
1469          */
1470         if (!bus->prop.hw_disabled) {
1471                 intel_debugfs_exit(sdw);
1472                 sdw_cdns_enable_interrupt(cdns, false);
1473                 snd_soc_unregister_component(dev);
1474         }
1475         sdw_bus_master_delete(bus);
1476 }
1477
1478 int intel_link_process_wakeen_event(struct auxiliary_device *auxdev)
1479 {
1480         struct device *dev = &auxdev->dev;
1481         struct sdw_intel *sdw;
1482         struct sdw_bus *bus;
1483         void __iomem *shim;
1484         u16 wake_sts;
1485
1486         sdw = auxiliary_get_drvdata(auxdev);
1487         bus = &sdw->cdns.bus;
1488
1489         if (bus->prop.hw_disabled || !sdw->startup_done) {
1490                 dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1491                         bus->link_id);
1492                 return 0;
1493         }
1494
1495         shim = sdw->link_res->shim;
1496         wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);
1497
1498         if (!(wake_sts & BIT(sdw->instance)))
1499                 return 0;
1500
1501         /* disable WAKEEN interrupt ASAP to prevent interrupt flood */
1502         intel_shim_wake(sdw, false);
1503
1504         /*
1505          * resume the Master, which will generate a bus reset and result in
1506          * Slaves re-attaching and be re-enumerated. The SoundWire physical
1507          * device which generated the wake will trigger an interrupt, which
1508          * will in turn cause the corresponding Linux Slave device to be
1509          * resumed and the Slave codec driver to check the status.
1510          */
1511         pm_request_resume(dev);
1512
1513         return 0;
1514 }
1515
1516 /*
1517  * PM calls
1518  */
1519
1520 static int intel_resume_child_device(struct device *dev, void *data)
1521 {
1522         int ret;
1523         struct sdw_slave *slave = dev_to_sdw_dev(dev);
1524
1525         if (!slave->probed) {
1526                 dev_dbg(dev, "%s: skipping device, no probed driver\n", __func__);
1527                 return 0;
1528         }
1529         if (!slave->dev_num_sticky) {
1530                 dev_dbg(dev, "%s: skipping device, never detected on bus\n", __func__);
1531                 return 0;
1532         }
1533
1534         ret = pm_request_resume(dev);
1535         if (ret < 0)
1536                 dev_err(dev, "%s: pm_request_resume failed: %d\n", __func__, ret);
1537
1538         return ret;
1539 }
1540
1541 static int __maybe_unused intel_pm_prepare(struct device *dev)
1542 {
1543         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1544         struct sdw_intel *sdw = cdns_to_intel(cdns);
1545         struct sdw_bus *bus = &cdns->bus;
1546         u32 clock_stop_quirks;
1547         int ret;
1548
1549         if (bus->prop.hw_disabled || !sdw->startup_done) {
1550                 dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1551                         bus->link_id);
1552                 return 0;
1553         }
1554
1555         clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1556
1557         if (pm_runtime_suspended(dev) &&
1558             pm_runtime_suspended(dev->parent) &&
1559             ((clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET) ||
1560              !clock_stop_quirks)) {
1561                 /*
1562                  * if we've enabled clock stop, and the parent is suspended, the SHIM registers
1563                  * are not accessible and the shim wake cannot be disabled.
1564                  * The only solution is to resume the entire bus to full power
1565                  */
1566
1567                 /*
1568                  * If any operation in this block fails, we keep going since we don't want
1569                  * to prevent system suspend from happening and errors should be recoverable
1570                  * on resume.
1571                  */
1572
1573                 /*
1574                  * first resume the device for this link. This will also by construction
1575                  * resume the PCI parent device.
1576                  */
1577                 ret = pm_request_resume(dev);
1578                 if (ret < 0) {
1579                         dev_err(dev, "%s: pm_request_resume failed: %d\n", __func__, ret);
1580                         return 0;
1581                 }
1582
1583                 /*
1584                  * Continue resuming the entire bus (parent + child devices) to exit
1585                  * the clock stop mode. If there are no devices connected on this link
1586                  * this is a no-op.
1587                  * The resume to full power could have been implemented with a .prepare
1588                  * step in SoundWire codec drivers. This would however require a lot
1589                  * of code to handle an Intel-specific corner case. It is simpler in
1590                  * practice to add a loop at the link level.
1591                  */
1592                 ret = device_for_each_child(bus->dev, NULL, intel_resume_child_device);
1593
1594                 if (ret < 0)
1595                         dev_err(dev, "%s: intel_resume_child_device failed: %d\n", __func__, ret);
1596         }
1597
1598         return 0;
1599 }
1600
1601 static int __maybe_unused intel_suspend(struct device *dev)
1602 {
1603         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1604         struct sdw_intel *sdw = cdns_to_intel(cdns);
1605         struct sdw_bus *bus = &cdns->bus;
1606         u32 clock_stop_quirks;
1607         int ret;
1608
1609         if (bus->prop.hw_disabled || !sdw->startup_done) {
1610                 dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1611                         bus->link_id);
1612                 return 0;
1613         }
1614
1615         if (pm_runtime_suspended(dev)) {
1616                 dev_dbg(dev, "%s: pm_runtime status: suspended\n", __func__);
1617
1618                 clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1619
1620                 if ((clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET) ||
1621                     !clock_stop_quirks) {
1622
1623                         if (pm_runtime_suspended(dev->parent)) {
1624                                 /*
1625                                  * paranoia check: this should not happen with the .prepare
1626                                  * resume to full power
1627                                  */
1628                                 dev_err(dev, "%s: invalid config: parent is suspended\n", __func__);
1629                         } else {
1630                                 intel_shim_wake(sdw, false);
1631                         }
1632                 }
1633
1634                 return 0;
1635         }
1636
1637         ret = sdw_cdns_enable_interrupt(cdns, false);
1638         if (ret < 0) {
1639                 dev_err(dev, "cannot disable interrupts on suspend\n");
1640                 return ret;
1641         }
1642
1643         ret = intel_link_power_down(sdw);
1644         if (ret) {
1645                 dev_err(dev, "Link power down failed: %d\n", ret);
1646                 return ret;
1647         }
1648
1649         intel_shim_wake(sdw, false);
1650
1651         return 0;
1652 }
1653
1654 static int __maybe_unused intel_suspend_runtime(struct device *dev)
1655 {
1656         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1657         struct sdw_intel *sdw = cdns_to_intel(cdns);
1658         struct sdw_bus *bus = &cdns->bus;
1659         u32 clock_stop_quirks;
1660         int ret;
1661
1662         if (bus->prop.hw_disabled || !sdw->startup_done) {
1663                 dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1664                         bus->link_id);
1665                 return 0;
1666         }
1667
1668         clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1669
1670         if (clock_stop_quirks & SDW_INTEL_CLK_STOP_TEARDOWN) {
1671
1672                 ret = sdw_cdns_enable_interrupt(cdns, false);
1673                 if (ret < 0) {
1674                         dev_err(dev, "cannot disable interrupts on suspend\n");
1675                         return ret;
1676                 }
1677
1678                 ret = intel_link_power_down(sdw);
1679                 if (ret) {
1680                         dev_err(dev, "Link power down failed: %d\n", ret);
1681                         return ret;
1682                 }
1683
1684                 intel_shim_wake(sdw, false);
1685
1686         } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET ||
1687                    !clock_stop_quirks) {
1688                 bool wake_enable = true;
1689
1690                 ret = sdw_cdns_clock_stop(cdns, true);
1691                 if (ret < 0) {
1692                         dev_err(dev, "cannot enable clock stop on suspend\n");
1693                         wake_enable = false;
1694                 }
1695
1696                 ret = sdw_cdns_enable_interrupt(cdns, false);
1697                 if (ret < 0) {
1698                         dev_err(dev, "cannot disable interrupts on suspend\n");
1699                         return ret;
1700                 }
1701
1702                 ret = intel_link_power_down(sdw);
1703                 if (ret) {
1704                         dev_err(dev, "Link power down failed: %d\n", ret);
1705                         return ret;
1706                 }
1707
1708                 intel_shim_wake(sdw, wake_enable);
1709         } else {
1710                 dev_err(dev, "%s clock_stop_quirks %x unsupported\n",
1711                         __func__, clock_stop_quirks);
1712                 ret = -EINVAL;
1713         }
1714
1715         return ret;
1716 }
1717
1718 static int __maybe_unused intel_resume(struct device *dev)
1719 {
1720         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1721         struct sdw_intel *sdw = cdns_to_intel(cdns);
1722         struct sdw_bus *bus = &cdns->bus;
1723         int link_flags;
1724         bool multi_link;
1725         int ret;
1726
1727         if (bus->prop.hw_disabled || !sdw->startup_done) {
1728                 dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1729                         bus->link_id);
1730                 return 0;
1731         }
1732
1733         link_flags = md_flags >> (bus->link_id * 8);
1734         multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK);
1735
1736         if (pm_runtime_suspended(dev)) {
1737                 dev_dbg(dev, "%s: pm_runtime status was suspended, forcing active\n", __func__);
1738
1739                 /* follow required sequence from runtime_pm.rst */
1740                 pm_runtime_disable(dev);
1741                 pm_runtime_set_active(dev);
1742                 pm_runtime_mark_last_busy(dev);
1743                 pm_runtime_enable(dev);
1744
1745                 link_flags = md_flags >> (bus->link_id * 8);
1746
1747                 if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE))
1748                         pm_runtime_idle(dev);
1749         }
1750
1751         ret = intel_init(sdw);
1752         if (ret) {
1753                 dev_err(dev, "%s failed: %d\n", __func__, ret);
1754                 return ret;
1755         }
1756
1757         /*
1758          * make sure all Slaves are tagged as UNATTACHED and provide
1759          * reason for reinitialization
1760          */
1761         sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET);
1762
1763         ret = sdw_cdns_enable_interrupt(cdns, true);
1764         if (ret < 0) {
1765                 dev_err(dev, "cannot enable interrupts during resume\n");
1766                 return ret;
1767         }
1768
1769         /*
1770          * follow recommended programming flows to avoid timeouts when
1771          * gsync is enabled
1772          */
1773         if (multi_link)
1774                 intel_shim_sync_arm(sdw);
1775
1776         ret = sdw_cdns_init(&sdw->cdns);
1777         if (ret < 0) {
1778                 dev_err(dev, "unable to initialize Cadence IP during resume\n");
1779                 return ret;
1780         }
1781
1782         ret = sdw_cdns_exit_reset(cdns);
1783         if (ret < 0) {
1784                 dev_err(dev, "unable to exit bus reset sequence during resume\n");
1785                 return ret;
1786         }
1787
1788         if (multi_link) {
1789                 ret = intel_shim_sync_go(sdw);
1790                 if (ret < 0) {
1791                         dev_err(dev, "sync go failed during resume\n");
1792                         return ret;
1793                 }
1794         }
1795         sdw_cdns_check_self_clearing_bits(cdns, __func__,
1796                                           true, INTEL_MASTER_RESET_ITERATIONS);
1797
1798         /*
1799          * after system resume, the pm_runtime suspend() may kick in
1800          * during the enumeration, before any children device force the
1801          * master device to remain active.  Using pm_runtime_get()
1802          * routines is not really possible, since it'd prevent the
1803          * master from suspending.
1804          * A reasonable compromise is to update the pm_runtime
1805          * counters and delay the pm_runtime suspend by several
1806          * seconds, by when all enumeration should be complete.
1807          */
1808         pm_runtime_mark_last_busy(dev);
1809
1810         return ret;
1811 }
1812
1813 static int __maybe_unused intel_resume_runtime(struct device *dev)
1814 {
1815         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1816         struct sdw_intel *sdw = cdns_to_intel(cdns);
1817         struct sdw_bus *bus = &cdns->bus;
1818         u32 clock_stop_quirks;
1819         bool clock_stop0;
1820         int link_flags;
1821         bool multi_link;
1822         int status;
1823         int ret;
1824
1825         if (bus->prop.hw_disabled || !sdw->startup_done) {
1826                 dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1827                         bus->link_id);
1828                 return 0;
1829         }
1830
1831         link_flags = md_flags >> (bus->link_id * 8);
1832         multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK);
1833
1834         clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1835
1836         if (clock_stop_quirks & SDW_INTEL_CLK_STOP_TEARDOWN) {
1837                 ret = intel_init(sdw);
1838                 if (ret) {
1839                         dev_err(dev, "%s failed: %d\n", __func__, ret);
1840                         return ret;
1841                 }
1842
1843                 /*
1844                  * make sure all Slaves are tagged as UNATTACHED and provide
1845                  * reason for reinitialization
1846                  */
1847                 sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET);
1848
1849                 ret = sdw_cdns_enable_interrupt(cdns, true);
1850                 if (ret < 0) {
1851                         dev_err(dev, "cannot enable interrupts during resume\n");
1852                         return ret;
1853                 }
1854
1855                 /*
1856                  * follow recommended programming flows to avoid
1857                  * timeouts when gsync is enabled
1858                  */
1859                 if (multi_link)
1860                         intel_shim_sync_arm(sdw);
1861
1862                 ret = sdw_cdns_init(&sdw->cdns);
1863                 if (ret < 0) {
1864                         dev_err(dev, "unable to initialize Cadence IP during resume\n");
1865                         return ret;
1866                 }
1867
1868                 ret = sdw_cdns_exit_reset(cdns);
1869                 if (ret < 0) {
1870                         dev_err(dev, "unable to exit bus reset sequence during resume\n");
1871                         return ret;
1872                 }
1873
1874                 if (multi_link) {
1875                         ret = intel_shim_sync_go(sdw);
1876                         if (ret < 0) {
1877                                 dev_err(dev, "sync go failed during resume\n");
1878                                 return ret;
1879                         }
1880                 }
1881                 sdw_cdns_check_self_clearing_bits(cdns, "intel_resume_runtime TEARDOWN",
1882                                                   true, INTEL_MASTER_RESET_ITERATIONS);
1883
1884         } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET) {
1885                 ret = intel_init(sdw);
1886                 if (ret) {
1887                         dev_err(dev, "%s failed: %d\n", __func__, ret);
1888                         return ret;
1889                 }
1890
1891                 /*
1892                  * An exception condition occurs for the CLK_STOP_BUS_RESET
1893                  * case if one or more masters remain active. In this condition,
1894                  * all the masters are powered on for they are in the same power
1895                  * domain. Master can preserve its context for clock stop0, so
1896                  * there is no need to clear slave status and reset bus.
1897                  */
1898                 clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns);
1899
1900                 if (!clock_stop0) {
1901
1902                         /*
1903                          * make sure all Slaves are tagged as UNATTACHED and
1904                          * provide reason for reinitialization
1905                          */
1906
1907                         status = SDW_UNATTACH_REQUEST_MASTER_RESET;
1908                         sdw_clear_slave_status(bus, status);
1909
1910                         ret = sdw_cdns_enable_interrupt(cdns, true);
1911                         if (ret < 0) {
1912                                 dev_err(dev, "cannot enable interrupts during resume\n");
1913                                 return ret;
1914                         }
1915
1916                         /*
1917                          * follow recommended programming flows to avoid
1918                          * timeouts when gsync is enabled
1919                          */
1920                         if (multi_link)
1921                                 intel_shim_sync_arm(sdw);
1922
1923                         /*
1924                          * Re-initialize the IP since it was powered-off
1925                          */
1926                         sdw_cdns_init(&sdw->cdns);
1927
1928                 } else {
1929                         ret = sdw_cdns_enable_interrupt(cdns, true);
1930                         if (ret < 0) {
1931                                 dev_err(dev, "cannot enable interrupts during resume\n");
1932                                 return ret;
1933                         }
1934                 }
1935
1936                 ret = sdw_cdns_clock_restart(cdns, !clock_stop0);
1937                 if (ret < 0) {
1938                         dev_err(dev, "unable to restart clock during resume\n");
1939                         return ret;
1940                 }
1941
1942                 if (!clock_stop0) {
1943                         ret = sdw_cdns_exit_reset(cdns);
1944                         if (ret < 0) {
1945                                 dev_err(dev, "unable to exit bus reset sequence during resume\n");
1946                                 return ret;
1947                         }
1948
1949                         if (multi_link) {
1950                                 ret = intel_shim_sync_go(sdw);
1951                                 if (ret < 0) {
1952                                         dev_err(sdw->cdns.dev, "sync go failed during resume\n");
1953                                         return ret;
1954                                 }
1955                         }
1956                 }
1957                 sdw_cdns_check_self_clearing_bits(cdns, "intel_resume_runtime BUS_RESET",
1958                                                   true, INTEL_MASTER_RESET_ITERATIONS);
1959
1960         } else if (!clock_stop_quirks) {
1961
1962                 clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns);
1963                 if (!clock_stop0)
1964                         dev_err(dev, "%s invalid configuration, clock was not stopped", __func__);
1965
1966                 ret = intel_init(sdw);
1967                 if (ret) {
1968                         dev_err(dev, "%s failed: %d\n", __func__, ret);
1969                         return ret;
1970                 }
1971
1972                 ret = sdw_cdns_enable_interrupt(cdns, true);
1973                 if (ret < 0) {
1974                         dev_err(dev, "cannot enable interrupts during resume\n");
1975                         return ret;
1976                 }
1977
1978                 ret = sdw_cdns_clock_restart(cdns, false);
1979                 if (ret < 0) {
1980                         dev_err(dev, "unable to resume master during resume\n");
1981                         return ret;
1982                 }
1983
1984                 sdw_cdns_check_self_clearing_bits(cdns, "intel_resume_runtime no_quirks",
1985                                                   true, INTEL_MASTER_RESET_ITERATIONS);
1986         } else {
1987                 dev_err(dev, "%s clock_stop_quirks %x unsupported\n",
1988                         __func__, clock_stop_quirks);
1989                 ret = -EINVAL;
1990         }
1991
1992         return ret;
1993 }
1994
1995 static const struct dev_pm_ops intel_pm = {
1996         .prepare = intel_pm_prepare,
1997         SET_SYSTEM_SLEEP_PM_OPS(intel_suspend, intel_resume)
1998         SET_RUNTIME_PM_OPS(intel_suspend_runtime, intel_resume_runtime, NULL)
1999 };
2000
2001 static const struct auxiliary_device_id intel_link_id_table[] = {
2002         { .name = "soundwire_intel.link" },
2003         {},
2004 };
2005 MODULE_DEVICE_TABLE(auxiliary, intel_link_id_table);
2006
2007 static struct auxiliary_driver sdw_intel_drv = {
2008         .probe = intel_link_probe,
2009         .remove = intel_link_remove,
2010         .driver = {
2011                 /* auxiliary_driver_register() sets .name to be the modname */
2012                 .pm = &intel_pm,
2013         },
2014         .id_table = intel_link_id_table
2015 };
2016 module_auxiliary_driver(sdw_intel_drv);
2017
2018 MODULE_LICENSE("Dual BSD/GPL");
2019 MODULE_DESCRIPTION("Intel Soundwire Link Driver");