1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2 // Copyright(c) 2015-17 Intel Corporation.
5 * Soundwire Intel Master Driver
8 #include <linux/acpi.h>
9 #include <linux/debugfs.h>
10 #include <linux/delay.h>
11 #include <linux/module.h>
12 #include <linux/interrupt.h>
14 #include <linux/auxiliary_bus.h>
15 #include <sound/pcm_params.h>
16 #include <linux/pm_runtime.h>
17 #include <sound/soc.h>
18 #include <linux/soundwire/sdw_registers.h>
19 #include <linux/soundwire/sdw.h>
20 #include <linux/soundwire/sdw_intel.h>
21 #include "cadence_master.h"
25 #define INTEL_MASTER_SUSPEND_DELAY_MS 3000
26 #define INTEL_MASTER_RESET_ITERATIONS 10
29 * debug/config flags for the Intel SoundWire Master.
31 * Since we may have multiple masters active, we can have up to 8
32 * flags reused in each byte, with master0 using the ls-byte, etc.
35 #define SDW_INTEL_MASTER_DISABLE_PM_RUNTIME BIT(0)
36 #define SDW_INTEL_MASTER_DISABLE_CLOCK_STOP BIT(1)
37 #define SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE BIT(2)
38 #define SDW_INTEL_MASTER_DISABLE_MULTI_LINK BIT(3)
41 module_param_named(sdw_md_flags, md_flags, int, 0444);
42 MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags (0x0 all off)");
50 #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns)
53 * Read, write helpers for HW registers
55 static inline int intel_readl(void __iomem *base, int offset)
57 return readl(base + offset);
60 static inline void intel_writel(void __iomem *base, int offset, int value)
62 writel(value, base + offset);
65 static inline u16 intel_readw(void __iomem *base, int offset)
67 return readw(base + offset);
70 static inline void intel_writew(void __iomem *base, int offset, u16 value)
72 writew(value, base + offset);
75 static int intel_wait_bit(void __iomem *base, int offset, u32 mask, u32 target)
81 reg_read = readl(base + offset);
82 if ((reg_read & mask) == target)
86 usleep_range(50, 100);
87 } while (timeout != 0);
92 static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask)
94 writel(value, base + offset);
95 return intel_wait_bit(base, offset, mask, 0);
98 static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask)
100 writel(value, base + offset);
101 return intel_wait_bit(base, offset, mask, mask);
107 #ifdef CONFIG_DEBUG_FS
109 #define RD_BUF (2 * PAGE_SIZE)
111 static ssize_t intel_sprintf(void __iomem *mem, bool l,
112 char *buf, size_t pos, unsigned int reg)
117 value = intel_readl(mem, reg);
119 value = intel_readw(mem, reg);
121 return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value);
124 static int intel_reg_show(struct seq_file *s_file, void *data)
126 struct sdw_intel *sdw = s_file->private;
127 void __iomem *s = sdw->link_res->shim;
128 void __iomem *a = sdw->link_res->alh;
132 unsigned int links, reg;
134 buf = kzalloc(RD_BUF, GFP_KERNEL);
138 links = intel_readl(s, SDW_SHIM_LCAP) & GENMASK(2, 0);
140 ret = scnprintf(buf, RD_BUF, "Register Value\n");
141 ret += scnprintf(buf + ret, RD_BUF - ret, "\nShim\n");
143 for (i = 0; i < links; i++) {
144 reg = SDW_SHIM_LCAP + i * 4;
145 ret += intel_sprintf(s, true, buf, ret, reg);
148 for (i = 0; i < links; i++) {
149 ret += scnprintf(buf + ret, RD_BUF - ret, "\nLink%d\n", i);
150 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLSCAP(i));
151 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS0CM(i));
152 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS1CM(i));
153 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS2CM(i));
154 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS3CM(i));
155 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PCMSCAP(i));
157 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PCMSyCH registers\n");
160 * the value 10 is the number of PDIs. We will need a
161 * cleanup to remove hard-coded Intel configurations
162 * from cadence_master.c
164 for (j = 0; j < 10; j++) {
165 ret += intel_sprintf(s, false, buf, ret,
166 SDW_SHIM_PCMSYCHM(i, j));
167 ret += intel_sprintf(s, false, buf, ret,
168 SDW_SHIM_PCMSYCHC(i, j));
170 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PDMSCAP, IOCTL, CTMCTL\n");
172 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PDMSCAP(i));
173 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_IOCTL(i));
174 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTMCTL(i));
177 ret += scnprintf(buf + ret, RD_BUF - ret, "\nWake registers\n");
178 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKEEN);
179 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKESTS);
181 ret += scnprintf(buf + ret, RD_BUF - ret, "\nALH STRMzCFG\n");
182 for (i = 0; i < SDW_ALH_NUM_STREAMS; i++)
183 ret += intel_sprintf(a, true, buf, ret, SDW_ALH_STRMZCFG(i));
185 seq_printf(s_file, "%s", buf);
190 DEFINE_SHOW_ATTRIBUTE(intel_reg);
192 static int intel_set_m_datamode(void *data, u64 value)
194 struct sdw_intel *sdw = data;
195 struct sdw_bus *bus = &sdw->cdns.bus;
197 if (value > SDW_PORT_DATA_MODE_STATIC_1)
200 /* Userspace changed the hardware state behind the kernel's back */
201 add_taint(TAINT_USER, LOCKDEP_STILL_OK);
203 bus->params.m_data_mode = value;
207 DEFINE_DEBUGFS_ATTRIBUTE(intel_set_m_datamode_fops, NULL,
208 intel_set_m_datamode, "%llu\n");
210 static int intel_set_s_datamode(void *data, u64 value)
212 struct sdw_intel *sdw = data;
213 struct sdw_bus *bus = &sdw->cdns.bus;
215 if (value > SDW_PORT_DATA_MODE_STATIC_1)
218 /* Userspace changed the hardware state behind the kernel's back */
219 add_taint(TAINT_USER, LOCKDEP_STILL_OK);
221 bus->params.s_data_mode = value;
225 DEFINE_DEBUGFS_ATTRIBUTE(intel_set_s_datamode_fops, NULL,
226 intel_set_s_datamode, "%llu\n");
228 static void intel_debugfs_init(struct sdw_intel *sdw)
230 struct dentry *root = sdw->cdns.bus.debugfs;
235 sdw->debugfs = debugfs_create_dir("intel-sdw", root);
237 debugfs_create_file("intel-registers", 0400, sdw->debugfs, sdw,
240 debugfs_create_file("intel-m-datamode", 0200, sdw->debugfs, sdw,
241 &intel_set_m_datamode_fops);
243 debugfs_create_file("intel-s-datamode", 0200, sdw->debugfs, sdw,
244 &intel_set_s_datamode_fops);
246 sdw_cdns_debugfs_init(&sdw->cdns, sdw->debugfs);
249 static void intel_debugfs_exit(struct sdw_intel *sdw)
251 debugfs_remove_recursive(sdw->debugfs);
254 static void intel_debugfs_init(struct sdw_intel *sdw) {}
255 static void intel_debugfs_exit(struct sdw_intel *sdw) {}
256 #endif /* CONFIG_DEBUG_FS */
262 static int intel_link_power_up(struct sdw_intel *sdw)
264 unsigned int link_id = sdw->instance;
265 void __iomem *shim = sdw->link_res->shim;
266 u32 *shim_mask = sdw->link_res->shim_mask;
267 struct sdw_bus *bus = &sdw->cdns.bus;
268 struct sdw_master_prop *prop = &bus->prop;
269 u32 spa_mask, cpa_mask;
275 mutex_lock(sdw->link_res->shim_lock);
278 * The hardware relies on an internal counter, typically 4kHz,
279 * to generate the SoundWire SSP - which defines a 'safe'
280 * synchronization point between commands and audio transport
281 * and allows for multi link synchronization. The SYNCPRD value
282 * is only dependent on the oscillator clock provided to
283 * the IP, so adjust based on _DSD properties reported in DSDT
284 * tables. The values reported are based on either 24MHz
285 * (CNL/CML) or 38.4 MHz (ICL/TGL+).
287 if (prop->mclk_freq % 6000000)
288 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;
290 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24;
293 dev_dbg(sdw->cdns.dev, "%s: powering up all links\n", __func__);
295 /* we first need to program the SyncPRD/CPU registers */
296 dev_dbg(sdw->cdns.dev,
297 "%s: first link up, programming SYNCPRD\n", __func__);
299 /* set SyncPRD period */
300 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
301 u32p_replace_bits(&sync_reg, syncprd, SDW_SHIM_SYNC_SYNCPRD);
303 /* Set SyncCPU bit */
304 sync_reg |= SDW_SHIM_SYNC_SYNCCPU;
305 intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
307 /* Link power up sequence */
308 link_control = intel_readl(shim, SDW_SHIM_LCTL);
310 /* only power-up enabled links */
311 spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, sdw->link_res->link_mask);
312 cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask);
314 link_control |= spa_mask;
316 ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
318 dev_err(sdw->cdns.dev, "Failed to power up link: %d\n", ret);
322 /* SyncCPU will change once link is active */
323 ret = intel_wait_bit(shim, SDW_SHIM_SYNC,
324 SDW_SHIM_SYNC_SYNCCPU, 0);
326 dev_err(sdw->cdns.dev,
327 "Failed to set SHIM_SYNC: %d\n", ret);
332 *shim_mask |= BIT(link_id);
334 sdw->cdns.link_up = true;
336 mutex_unlock(sdw->link_res->shim_lock);
341 /* this needs to be called with shim_lock */
342 static void intel_shim_glue_to_master_ip(struct sdw_intel *sdw)
344 void __iomem *shim = sdw->link_res->shim;
345 unsigned int link_id = sdw->instance;
348 /* Switch to MIP from Glue logic */
349 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
351 ioctl &= ~(SDW_SHIM_IOCTL_DOE);
352 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
353 usleep_range(10, 15);
355 ioctl &= ~(SDW_SHIM_IOCTL_DO);
356 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
357 usleep_range(10, 15);
359 ioctl |= (SDW_SHIM_IOCTL_MIF);
360 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
361 usleep_range(10, 15);
363 ioctl &= ~(SDW_SHIM_IOCTL_BKE);
364 ioctl &= ~(SDW_SHIM_IOCTL_COE);
365 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
366 usleep_range(10, 15);
368 /* at this point Master IP has full control of the I/Os */
371 /* this needs to be called with shim_lock */
372 static void intel_shim_master_ip_to_glue(struct sdw_intel *sdw)
374 unsigned int link_id = sdw->instance;
375 void __iomem *shim = sdw->link_res->shim;
379 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
380 ioctl |= SDW_SHIM_IOCTL_BKE;
381 ioctl |= SDW_SHIM_IOCTL_COE;
382 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
383 usleep_range(10, 15);
385 ioctl &= ~(SDW_SHIM_IOCTL_MIF);
386 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
387 usleep_range(10, 15);
389 /* at this point Integration Glue has full control of the I/Os */
392 static int intel_shim_init(struct sdw_intel *sdw, bool clock_stop)
394 void __iomem *shim = sdw->link_res->shim;
395 unsigned int link_id = sdw->instance;
397 u16 ioctl = 0, act = 0;
399 mutex_lock(sdw->link_res->shim_lock);
401 /* Initialize Shim */
402 ioctl |= SDW_SHIM_IOCTL_BKE;
403 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
404 usleep_range(10, 15);
406 ioctl |= SDW_SHIM_IOCTL_WPDD;
407 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
408 usleep_range(10, 15);
410 ioctl |= SDW_SHIM_IOCTL_DO;
411 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
412 usleep_range(10, 15);
414 ioctl |= SDW_SHIM_IOCTL_DOE;
415 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
416 usleep_range(10, 15);
418 intel_shim_glue_to_master_ip(sdw);
420 u16p_replace_bits(&act, 0x1, SDW_SHIM_CTMCTL_DOAIS);
421 act |= SDW_SHIM_CTMCTL_DACTQE;
422 act |= SDW_SHIM_CTMCTL_DODS;
423 intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act);
424 usleep_range(10, 15);
426 mutex_unlock(sdw->link_res->shim_lock);
431 static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable)
433 void __iomem *shim = sdw->link_res->shim;
434 unsigned int link_id = sdw->instance;
435 u16 wake_en, wake_sts;
437 mutex_lock(sdw->link_res->shim_lock);
438 wake_en = intel_readw(shim, SDW_SHIM_WAKEEN);
441 /* Enable the wakeup */
442 wake_en |= (SDW_SHIM_WAKEEN_ENABLE << link_id);
443 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
445 /* Disable the wake up interrupt */
446 wake_en &= ~(SDW_SHIM_WAKEEN_ENABLE << link_id);
447 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
449 /* Clear wake status */
450 wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);
451 wake_sts |= (SDW_SHIM_WAKEEN_ENABLE << link_id);
452 intel_writew(shim, SDW_SHIM_WAKESTS_STATUS, wake_sts);
454 mutex_unlock(sdw->link_res->shim_lock);
457 static int intel_link_power_down(struct sdw_intel *sdw)
459 u32 link_control, spa_mask, cpa_mask;
460 unsigned int link_id = sdw->instance;
461 void __iomem *shim = sdw->link_res->shim;
462 u32 *shim_mask = sdw->link_res->shim_mask;
465 mutex_lock(sdw->link_res->shim_lock);
467 if (!(*shim_mask & BIT(link_id)))
468 dev_err(sdw->cdns.dev,
469 "%s: Unbalanced power-up/down calls\n", __func__);
471 sdw->cdns.link_up = false;
473 intel_shim_master_ip_to_glue(sdw);
475 *shim_mask &= ~BIT(link_id);
479 dev_dbg(sdw->cdns.dev, "%s: powering down all links\n", __func__);
481 /* Link power down sequence */
482 link_control = intel_readl(shim, SDW_SHIM_LCTL);
484 /* only power-down enabled links */
485 spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, ~sdw->link_res->link_mask);
486 cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask);
488 link_control &= spa_mask;
490 ret = intel_clear_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
492 dev_err(sdw->cdns.dev, "%s: could not power down link\n", __func__);
495 * we leave the sdw->cdns.link_up flag as false since we've disabled
496 * the link at this point and cannot handle interrupts any longer.
501 mutex_unlock(sdw->link_res->shim_lock);
506 static void intel_shim_sync_arm(struct sdw_intel *sdw)
508 void __iomem *shim = sdw->link_res->shim;
511 mutex_lock(sdw->link_res->shim_lock);
513 /* update SYNC register */
514 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
515 sync_reg |= (SDW_SHIM_SYNC_CMDSYNC << sdw->instance);
516 intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
518 mutex_unlock(sdw->link_res->shim_lock);
521 static int intel_shim_sync_go_unlocked(struct sdw_intel *sdw)
523 void __iomem *shim = sdw->link_res->shim;
527 /* Read SYNC register */
528 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
531 * Set SyncGO bit to synchronously trigger a bank switch for
532 * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all
535 sync_reg |= SDW_SHIM_SYNC_SYNCGO;
537 ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
538 SDW_SHIM_SYNC_SYNCGO);
541 dev_err(sdw->cdns.dev, "SyncGO clear failed: %d\n", ret);
546 static int intel_shim_sync_go(struct sdw_intel *sdw)
550 mutex_lock(sdw->link_res->shim_lock);
552 ret = intel_shim_sync_go_unlocked(sdw);
554 mutex_unlock(sdw->link_res->shim_lock);
562 static void intel_pdi_init(struct sdw_intel *sdw,
563 struct sdw_cdns_stream_config *config)
565 void __iomem *shim = sdw->link_res->shim;
566 unsigned int link_id = sdw->instance;
569 /* PCM Stream Capability */
570 pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id));
572 config->pcm_bd = FIELD_GET(SDW_SHIM_PCMSCAP_BSS, pcm_cap);
573 config->pcm_in = FIELD_GET(SDW_SHIM_PCMSCAP_ISS, pcm_cap);
574 config->pcm_out = FIELD_GET(SDW_SHIM_PCMSCAP_OSS, pcm_cap);
576 dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n",
577 config->pcm_bd, config->pcm_in, config->pcm_out);
581 intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num)
583 void __iomem *shim = sdw->link_res->shim;
584 unsigned int link_id = sdw->instance;
587 count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num));
590 * WORKAROUND: on all existing Intel controllers, pdi
591 * number 2 reports channel count as 1 even though it
592 * supports 8 channels. Performing hardcoding for pdi
598 /* zero based values for channel count in register */
604 static int intel_pdi_get_ch_update(struct sdw_intel *sdw,
605 struct sdw_cdns_pdi *pdi,
606 unsigned int num_pdi,
607 unsigned int *num_ch)
611 for (i = 0; i < num_pdi; i++) {
612 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num);
613 ch_count += pdi->ch_count;
621 static int intel_pdi_stream_ch_update(struct sdw_intel *sdw,
622 struct sdw_cdns_streams *stream)
624 intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
627 intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
630 intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
631 &stream->num_ch_out);
636 static int intel_pdi_ch_update(struct sdw_intel *sdw)
638 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm);
644 intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
646 void __iomem *shim = sdw->link_res->shim;
647 unsigned int link_id = sdw->instance;
650 /* the Bulk and PCM streams are not contiguous */
651 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
653 pdi->intel_alh_id += 2;
656 * Program stream parameters to stream SHIM register
657 * This is applicable for PCM stream only.
659 if (pdi->type != SDW_STREAM_PCM)
662 if (pdi->dir == SDW_DATA_DIR_RX)
663 pdi_conf |= SDW_SHIM_PCMSYCM_DIR;
665 pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR);
667 u32p_replace_bits(&pdi_conf, pdi->intel_alh_id, SDW_SHIM_PCMSYCM_STREAM);
668 u32p_replace_bits(&pdi_conf, pdi->l_ch_num, SDW_SHIM_PCMSYCM_LCHN);
669 u32p_replace_bits(&pdi_conf, pdi->h_ch_num, SDW_SHIM_PCMSYCM_HCHN);
671 intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf);
675 intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
677 void __iomem *alh = sdw->link_res->alh;
678 unsigned int link_id = sdw->instance;
681 /* the Bulk and PCM streams are not contiguous */
682 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
684 pdi->intel_alh_id += 2;
686 /* Program Stream config ALH register */
687 conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id));
689 u32p_replace_bits(&conf, SDW_ALH_STRMZCFG_DMAT_VAL, SDW_ALH_STRMZCFG_DMAT);
690 u32p_replace_bits(&conf, pdi->ch_count - 1, SDW_ALH_STRMZCFG_CHN);
692 intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf);
695 static int intel_params_stream(struct sdw_intel *sdw,
697 struct snd_soc_dai *dai,
698 struct snd_pcm_hw_params *hw_params,
699 int link_id, int alh_stream_id)
701 struct sdw_intel_link_res *res = sdw->link_res;
702 struct sdw_intel_stream_params_data params_data;
704 params_data.stream = stream; /* direction */
705 params_data.dai = dai;
706 params_data.hw_params = hw_params;
707 params_data.link_id = link_id;
708 params_data.alh_stream_id = alh_stream_id;
710 if (res->ops && res->ops->params_stream && res->dev)
711 return res->ops->params_stream(res->dev,
716 static int intel_free_stream(struct sdw_intel *sdw,
718 struct snd_soc_dai *dai,
721 struct sdw_intel_link_res *res = sdw->link_res;
722 struct sdw_intel_stream_free_data free_data;
724 free_data.stream = stream; /* direction */
726 free_data.link_id = link_id;
728 if (res->ops && res->ops->free_stream && res->dev)
729 return res->ops->free_stream(res->dev,
736 * bank switch routines
739 static int intel_pre_bank_switch(struct sdw_bus *bus)
741 struct sdw_cdns *cdns = bus_to_cdns(bus);
742 struct sdw_intel *sdw = cdns_to_intel(cdns);
744 /* Write to register only for multi-link */
745 if (!bus->multi_link)
748 intel_shim_sync_arm(sdw);
753 static int intel_post_bank_switch(struct sdw_bus *bus)
755 struct sdw_cdns *cdns = bus_to_cdns(bus);
756 struct sdw_intel *sdw = cdns_to_intel(cdns);
757 void __iomem *shim = sdw->link_res->shim;
760 /* Write to register only for multi-link */
761 if (!bus->multi_link)
764 mutex_lock(sdw->link_res->shim_lock);
766 /* Read SYNC register */
767 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
770 * post_bank_switch() ops is called from the bus in loop for
771 * all the Masters in the steam with the expectation that
772 * we trigger the bankswitch for the only first Master in the list
773 * and do nothing for the other Masters
775 * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master.
777 if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK)) {
782 ret = intel_shim_sync_go_unlocked(sdw);
784 mutex_unlock(sdw->link_res->shim_lock);
787 dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret);
796 static int intel_startup(struct snd_pcm_substream *substream,
797 struct snd_soc_dai *dai)
799 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
802 ret = pm_runtime_get_sync(cdns->dev);
803 if (ret < 0 && ret != -EACCES) {
804 dev_err_ratelimited(cdns->dev,
805 "pm_runtime_get_sync failed in %s, ret %d\n",
807 pm_runtime_put_noidle(cdns->dev);
813 static int intel_hw_params(struct snd_pcm_substream *substream,
814 struct snd_pcm_hw_params *params,
815 struct snd_soc_dai *dai)
817 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
818 struct sdw_intel *sdw = cdns_to_intel(cdns);
819 struct sdw_cdns_dma_data *dma;
820 struct sdw_cdns_pdi *pdi;
821 struct sdw_stream_config sconfig;
822 struct sdw_port_config *pconfig;
826 dma = snd_soc_dai_get_dma_data(dai, substream);
830 ch = params_channels(params);
831 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
832 dir = SDW_DATA_DIR_RX;
834 dir = SDW_DATA_DIR_TX;
836 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id);
843 /* do run-time configurations for SHIM, ALH and PDI/PORT */
844 intel_pdi_shim_configure(sdw, pdi);
845 intel_pdi_alh_configure(sdw, pdi);
846 sdw_cdns_config_stream(cdns, ch, dir, pdi);
848 /* store pdi and hw_params, may be needed in prepare step */
850 dma->suspended = false;
852 dma->hw_params = params;
854 /* Inform DSP about PDI stream number */
855 ret = intel_params_stream(sdw, substream->stream, dai, params,
861 sconfig.direction = dir;
862 sconfig.ch_count = ch;
863 sconfig.frame_rate = params_rate(params);
864 sconfig.type = dma->stream_type;
866 sconfig.bps = snd_pcm_format_width(params_format(params));
868 /* Port configuration */
869 pconfig = kzalloc(sizeof(*pconfig), GFP_KERNEL);
875 pconfig->num = pdi->num;
876 pconfig->ch_mask = (1 << ch) - 1;
878 ret = sdw_stream_add_master(&cdns->bus, &sconfig,
879 pconfig, 1, dma->stream);
881 dev_err(cdns->dev, "add master to stream failed:%d\n", ret);
888 static int intel_prepare(struct snd_pcm_substream *substream,
889 struct snd_soc_dai *dai)
891 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
892 struct sdw_intel *sdw = cdns_to_intel(cdns);
893 struct sdw_cdns_dma_data *dma;
897 dma = snd_soc_dai_get_dma_data(dai, substream);
899 dev_err(dai->dev, "failed to get dma data in %s\n",
904 if (dma->suspended) {
905 dma->suspended = false;
908 * .prepare() is called after system resume, where we
909 * need to reinitialize the SHIM/ALH/Cadence IP.
910 * .prepare() is also called to deal with underflows,
911 * but in those cases we cannot touch ALH/SHIM
915 /* configure stream */
916 ch = params_channels(dma->hw_params);
917 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
918 dir = SDW_DATA_DIR_RX;
920 dir = SDW_DATA_DIR_TX;
922 intel_pdi_shim_configure(sdw, dma->pdi);
923 intel_pdi_alh_configure(sdw, dma->pdi);
924 sdw_cdns_config_stream(cdns, ch, dir, dma->pdi);
926 /* Inform DSP about PDI stream number */
927 ret = intel_params_stream(sdw, substream->stream, dai,
930 dma->pdi->intel_alh_id);
937 intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
939 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
940 struct sdw_intel *sdw = cdns_to_intel(cdns);
941 struct sdw_cdns_dma_data *dma;
944 dma = snd_soc_dai_get_dma_data(dai, substream);
949 * The sdw stream state will transition to RELEASED when stream->
950 * master_list is empty. So the stream state will transition to
951 * DEPREPARED for the first cpu-dai and to RELEASED for the last
954 ret = sdw_stream_remove_master(&cdns->bus, dma->stream);
956 dev_err(dai->dev, "remove master from stream %s failed: %d\n",
957 dma->stream->name, ret);
961 ret = intel_free_stream(sdw, substream->stream, dai, sdw->instance);
963 dev_err(dai->dev, "intel_free_stream: failed %d\n", ret);
967 dma->hw_params = NULL;
973 static void intel_shutdown(struct snd_pcm_substream *substream,
974 struct snd_soc_dai *dai)
976 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
978 pm_runtime_mark_last_busy(cdns->dev);
979 pm_runtime_put_autosuspend(cdns->dev);
982 static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai,
983 void *stream, int direction)
985 return cdns_set_sdw_stream(dai, stream, direction);
988 static void *intel_get_sdw_stream(struct snd_soc_dai *dai,
991 struct sdw_cdns_dma_data *dma;
993 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
994 dma = dai->playback_dma_data;
996 dma = dai->capture_dma_data;
999 return ERR_PTR(-EINVAL);
1004 static int intel_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
1006 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
1007 struct sdw_intel *sdw = cdns_to_intel(cdns);
1008 struct sdw_cdns_dma_data *dma;
1011 dma = snd_soc_dai_get_dma_data(dai, substream);
1013 dev_err(dai->dev, "failed to get dma data in %s\n",
1019 case SNDRV_PCM_TRIGGER_SUSPEND:
1022 * The .prepare callback is used to deal with xruns and resume operations.
1023 * In the case of xruns, the DMAs and SHIM registers cannot be touched,
1024 * but for resume operations the DMAs and SHIM registers need to be initialized.
1025 * the .trigger callback is used to track the suspend case only.
1028 dma->suspended = true;
1030 ret = intel_free_stream(sdw, substream->stream, dai, sdw->instance);
1033 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1036 case SNDRV_PCM_TRIGGER_STOP:
1037 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1038 dma->paused = false;
1047 static int intel_component_dais_suspend(struct snd_soc_component *component)
1049 struct snd_soc_dai *dai;
1052 * In the corner case where a SUSPEND happens during a PAUSE, the ALSA core
1053 * does not throw the TRIGGER_SUSPEND. This leaves the DAIs in an unbalanced state.
1054 * Since the component suspend is called last, we can trap this corner case
1055 * and force the DAIs to release their resources.
1057 for_each_component_dais(component, dai) {
1058 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
1059 struct sdw_intel *sdw = cdns_to_intel(cdns);
1060 struct sdw_cdns_dma_data *dma;
1064 dma = dai->playback_dma_data;
1065 stream = SNDRV_PCM_STREAM_PLAYBACK;
1067 dma = dai->capture_dma_data;
1068 stream = SNDRV_PCM_STREAM_CAPTURE;
1078 dma->suspended = true;
1080 ret = intel_free_stream(sdw, stream, dai, sdw->instance);
1089 static const struct snd_soc_dai_ops intel_pcm_dai_ops = {
1090 .startup = intel_startup,
1091 .hw_params = intel_hw_params,
1092 .prepare = intel_prepare,
1093 .hw_free = intel_hw_free,
1094 .trigger = intel_trigger,
1095 .shutdown = intel_shutdown,
1096 .set_stream = intel_pcm_set_sdw_stream,
1097 .get_stream = intel_get_sdw_stream,
1100 static const struct snd_soc_component_driver dai_component = {
1101 .name = "soundwire",
1102 .suspend = intel_component_dais_suspend
1105 static int intel_create_dai(struct sdw_cdns *cdns,
1106 struct snd_soc_dai_driver *dais,
1107 enum intel_pdi_type type,
1108 u32 num, u32 off, u32 max_ch)
1115 /* TODO: Read supported rates/formats from hardware */
1116 for (i = off; i < (off + num); i++) {
1117 dais[i].name = devm_kasprintf(cdns->dev, GFP_KERNEL,
1123 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) {
1124 dais[i].playback.channels_min = 1;
1125 dais[i].playback.channels_max = max_ch;
1126 dais[i].playback.rates = SNDRV_PCM_RATE_48000;
1127 dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
1130 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) {
1131 dais[i].capture.channels_min = 1;
1132 dais[i].capture.channels_max = max_ch;
1133 dais[i].capture.rates = SNDRV_PCM_RATE_48000;
1134 dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
1137 dais[i].ops = &intel_pcm_dai_ops;
1143 static int intel_register_dai(struct sdw_intel *sdw)
1145 struct sdw_cdns *cdns = &sdw->cdns;
1146 struct sdw_cdns_streams *stream;
1147 struct snd_soc_dai_driver *dais;
1148 int num_dai, ret, off = 0;
1150 /* DAIs are created based on total number of PDIs supported */
1151 num_dai = cdns->pcm.num_pdi;
1153 dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
1157 /* Create PCM DAIs */
1158 stream = &cdns->pcm;
1160 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in,
1161 off, stream->num_ch_in);
1165 off += cdns->pcm.num_in;
1166 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,
1167 off, stream->num_ch_out);
1171 off += cdns->pcm.num_out;
1172 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,
1173 off, stream->num_ch_bd);
1177 return snd_soc_register_component(cdns->dev, &dai_component,
1181 static int sdw_master_read_intel_prop(struct sdw_bus *bus)
1183 struct sdw_master_prop *prop = &bus->prop;
1184 struct fwnode_handle *link;
1188 /* Find master handle */
1189 snprintf(name, sizeof(name),
1190 "mipi-sdw-link-%d-subproperties", bus->link_id);
1192 link = device_get_named_child_node(bus->dev, name);
1194 dev_err(bus->dev, "Master node %s not found\n", name);
1198 fwnode_property_read_u32(link,
1199 "intel-sdw-ip-clock",
1202 /* the values reported by BIOS are the 2x clock, not the bus clock */
1203 prop->mclk_freq /= 2;
1205 fwnode_property_read_u32(link,
1209 if (quirk_mask & SDW_INTEL_QUIRK_MASK_BUS_DISABLE)
1210 prop->hw_disabled = true;
1212 prop->quirks = SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH |
1213 SDW_MASTER_QUIRKS_CLEAR_INITIAL_PARITY;
1218 static int intel_prop_read(struct sdw_bus *bus)
1220 /* Initialize with default handler to read all DisCo properties */
1221 sdw_master_read_prop(bus);
1223 /* read Intel-specific properties */
1224 sdw_master_read_intel_prop(bus);
1229 static struct sdw_master_ops sdw_intel_ops = {
1230 .read_prop = sdw_master_read_prop,
1231 .override_adr = sdw_dmi_override_adr,
1232 .xfer_msg = cdns_xfer_msg,
1233 .xfer_msg_defer = cdns_xfer_msg_defer,
1234 .reset_page_addr = cdns_reset_page_addr,
1235 .set_bus_conf = cdns_bus_conf,
1236 .pre_bank_switch = intel_pre_bank_switch,
1237 .post_bank_switch = intel_post_bank_switch,
1240 static int intel_init(struct sdw_intel *sdw)
1244 /* Initialize shim and controller */
1245 intel_link_power_up(sdw);
1247 clock_stop = sdw_cdns_is_clock_stop(&sdw->cdns);
1249 intel_shim_init(sdw, clock_stop);
1255 * probe and init (aux_dev_id argument is required by function prototype but not used)
1257 static int intel_link_probe(struct auxiliary_device *auxdev,
1258 const struct auxiliary_device_id *aux_dev_id)
1261 struct device *dev = &auxdev->dev;
1262 struct sdw_intel_link_dev *ldev = auxiliary_dev_to_sdw_intel_link_dev(auxdev);
1263 struct sdw_intel *sdw;
1264 struct sdw_cdns *cdns;
1265 struct sdw_bus *bus;
1268 sdw = devm_kzalloc(dev, sizeof(*sdw), GFP_KERNEL);
1275 sdw->instance = auxdev->id;
1276 sdw->link_res = &ldev->link_res;
1278 cdns->registers = sdw->link_res->registers;
1279 cdns->instance = sdw->instance;
1280 cdns->msg_count = 0;
1282 bus->link_id = auxdev->id;
1284 sdw_cdns_probe(cdns);
1286 /* Set property read ops */
1287 sdw_intel_ops.read_prop = intel_prop_read;
1288 bus->ops = &sdw_intel_ops;
1290 /* set driver data, accessed by snd_soc_dai_get_drvdata() */
1291 auxiliary_set_drvdata(auxdev, cdns);
1293 /* use generic bandwidth allocation algorithm */
1294 sdw->cdns.bus.compute_params = sdw_compute_params;
1296 ret = sdw_bus_master_add(bus, dev, dev->fwnode);
1298 dev_err(dev, "sdw_bus_master_add fail: %d\n", ret);
1302 if (bus->prop.hw_disabled)
1304 "SoundWire master %d is disabled, will be ignored\n",
1307 * Ignore BIOS err_threshold, it's a really bad idea when dealing
1308 * with multiple hardware synchronized links
1310 bus->prop.err_threshold = 0;
1315 int intel_link_startup(struct auxiliary_device *auxdev)
1317 struct sdw_cdns_stream_config config;
1318 struct device *dev = &auxdev->dev;
1319 struct sdw_cdns *cdns = auxiliary_get_drvdata(auxdev);
1320 struct sdw_intel *sdw = cdns_to_intel(cdns);
1321 struct sdw_bus *bus = &cdns->bus;
1324 u32 clock_stop_quirks;
1327 if (bus->prop.hw_disabled) {
1329 "SoundWire master %d is disabled, ignoring\n",
1334 link_flags = md_flags >> (bus->link_id * 8);
1335 multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK);
1337 dev_dbg(dev, "Multi-link is disabled\n");
1338 bus->multi_link = false;
1341 * hardware-based synchronization is required regardless
1342 * of the number of segments used by a stream: SSP-based
1343 * synchronization is gated by gsync when the multi-master
1346 bus->multi_link = true;
1347 bus->hw_sync_min_links = 1;
1350 /* Initialize shim, controller */
1351 ret = intel_init(sdw);
1355 /* Read the PDI config and initialize cadence PDI */
1356 intel_pdi_init(sdw, &config);
1357 ret = sdw_cdns_pdi_init(cdns, config);
1361 intel_pdi_ch_update(sdw);
1363 ret = sdw_cdns_enable_interrupt(cdns, true);
1365 dev_err(dev, "cannot enable interrupts\n");
1370 * follow recommended programming flows to avoid timeouts when
1374 intel_shim_sync_arm(sdw);
1376 ret = sdw_cdns_init(cdns);
1378 dev_err(dev, "unable to initialize Cadence IP\n");
1382 ret = sdw_cdns_exit_reset(cdns);
1384 dev_err(dev, "unable to exit bus reset sequence\n");
1389 ret = intel_shim_sync_go(sdw);
1391 dev_err(dev, "sync go failed: %d\n", ret);
1395 sdw_cdns_check_self_clearing_bits(cdns, __func__,
1396 true, INTEL_MASTER_RESET_ITERATIONS);
1399 ret = intel_register_dai(sdw);
1401 dev_err(dev, "DAI registration failed: %d\n", ret);
1402 snd_soc_unregister_component(dev);
1406 intel_debugfs_init(sdw);
1408 /* Enable runtime PM */
1409 if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME)) {
1410 pm_runtime_set_autosuspend_delay(dev,
1411 INTEL_MASTER_SUSPEND_DELAY_MS);
1412 pm_runtime_use_autosuspend(dev);
1413 pm_runtime_mark_last_busy(dev);
1415 pm_runtime_set_active(dev);
1416 pm_runtime_enable(dev);
1419 clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1420 if (clock_stop_quirks & SDW_INTEL_CLK_STOP_NOT_ALLOWED) {
1422 * To keep the clock running we need to prevent
1423 * pm_runtime suspend from happening by increasing the
1425 * This quirk is specified by the parent PCI device in
1426 * case of specific latency requirements. It will have
1427 * no effect if pm_runtime is disabled by the user via
1428 * a module parameter for testing purposes.
1430 pm_runtime_get_noresume(dev);
1434 * The runtime PM status of Slave devices is "Unsupported"
1435 * until they report as ATTACHED. If they don't, e.g. because
1436 * there are no Slave devices populated or if the power-on is
1437 * delayed or dependent on a power switch, the Master will
1438 * remain active and prevent its parent from suspending.
1440 * Conditionally force the pm_runtime core to re-evaluate the
1441 * Master status in the absence of any Slave activity. A quirk
1442 * is provided to e.g. deal with Slaves that may be powered on
1443 * with a delay. A more complete solution would require the
1444 * definition of Master properties.
1446 if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE))
1447 pm_runtime_idle(dev);
1449 sdw->startup_done = true;
1453 sdw_cdns_enable_interrupt(cdns, false);
1458 static void intel_link_remove(struct auxiliary_device *auxdev)
1460 struct device *dev = &auxdev->dev;
1461 struct sdw_cdns *cdns = auxiliary_get_drvdata(auxdev);
1462 struct sdw_intel *sdw = cdns_to_intel(cdns);
1463 struct sdw_bus *bus = &cdns->bus;
1466 * Since pm_runtime is already disabled, we don't decrease
1467 * the refcount when the clock_stop_quirk is
1468 * SDW_INTEL_CLK_STOP_NOT_ALLOWED
1470 if (!bus->prop.hw_disabled) {
1471 intel_debugfs_exit(sdw);
1472 sdw_cdns_enable_interrupt(cdns, false);
1473 snd_soc_unregister_component(dev);
1475 sdw_bus_master_delete(bus);
1478 int intel_link_process_wakeen_event(struct auxiliary_device *auxdev)
1480 struct device *dev = &auxdev->dev;
1481 struct sdw_intel *sdw;
1482 struct sdw_bus *bus;
1486 sdw = auxiliary_get_drvdata(auxdev);
1487 bus = &sdw->cdns.bus;
1489 if (bus->prop.hw_disabled || !sdw->startup_done) {
1490 dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1495 shim = sdw->link_res->shim;
1496 wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);
1498 if (!(wake_sts & BIT(sdw->instance)))
1501 /* disable WAKEEN interrupt ASAP to prevent interrupt flood */
1502 intel_shim_wake(sdw, false);
1505 * resume the Master, which will generate a bus reset and result in
1506 * Slaves re-attaching and be re-enumerated. The SoundWire physical
1507 * device which generated the wake will trigger an interrupt, which
1508 * will in turn cause the corresponding Linux Slave device to be
1509 * resumed and the Slave codec driver to check the status.
1511 pm_request_resume(dev);
1520 static int intel_resume_child_device(struct device *dev, void *data)
1523 struct sdw_slave *slave = dev_to_sdw_dev(dev);
1525 if (!slave->probed) {
1526 dev_dbg(dev, "%s: skipping device, no probed driver\n", __func__);
1529 if (!slave->dev_num_sticky) {
1530 dev_dbg(dev, "%s: skipping device, never detected on bus\n", __func__);
1534 ret = pm_request_resume(dev);
1536 dev_err(dev, "%s: pm_request_resume failed: %d\n", __func__, ret);
1541 static int __maybe_unused intel_pm_prepare(struct device *dev)
1543 struct sdw_cdns *cdns = dev_get_drvdata(dev);
1544 struct sdw_intel *sdw = cdns_to_intel(cdns);
1545 struct sdw_bus *bus = &cdns->bus;
1546 u32 clock_stop_quirks;
1549 if (bus->prop.hw_disabled || !sdw->startup_done) {
1550 dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1555 clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1557 if (pm_runtime_suspended(dev) &&
1558 pm_runtime_suspended(dev->parent) &&
1559 ((clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET) ||
1560 !clock_stop_quirks)) {
1562 * if we've enabled clock stop, and the parent is suspended, the SHIM registers
1563 * are not accessible and the shim wake cannot be disabled.
1564 * The only solution is to resume the entire bus to full power
1568 * If any operation in this block fails, we keep going since we don't want
1569 * to prevent system suspend from happening and errors should be recoverable
1574 * first resume the device for this link. This will also by construction
1575 * resume the PCI parent device.
1577 ret = pm_request_resume(dev);
1579 dev_err(dev, "%s: pm_request_resume failed: %d\n", __func__, ret);
1584 * Continue resuming the entire bus (parent + child devices) to exit
1585 * the clock stop mode. If there are no devices connected on this link
1587 * The resume to full power could have been implemented with a .prepare
1588 * step in SoundWire codec drivers. This would however require a lot
1589 * of code to handle an Intel-specific corner case. It is simpler in
1590 * practice to add a loop at the link level.
1592 ret = device_for_each_child(bus->dev, NULL, intel_resume_child_device);
1595 dev_err(dev, "%s: intel_resume_child_device failed: %d\n", __func__, ret);
1601 static int __maybe_unused intel_suspend(struct device *dev)
1603 struct sdw_cdns *cdns = dev_get_drvdata(dev);
1604 struct sdw_intel *sdw = cdns_to_intel(cdns);
1605 struct sdw_bus *bus = &cdns->bus;
1606 u32 clock_stop_quirks;
1609 if (bus->prop.hw_disabled || !sdw->startup_done) {
1610 dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1615 if (pm_runtime_suspended(dev)) {
1616 dev_dbg(dev, "%s: pm_runtime status: suspended\n", __func__);
1618 clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1620 if ((clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET) ||
1621 !clock_stop_quirks) {
1623 if (pm_runtime_suspended(dev->parent)) {
1625 * paranoia check: this should not happen with the .prepare
1626 * resume to full power
1628 dev_err(dev, "%s: invalid config: parent is suspended\n", __func__);
1630 intel_shim_wake(sdw, false);
1637 ret = sdw_cdns_enable_interrupt(cdns, false);
1639 dev_err(dev, "cannot disable interrupts on suspend\n");
1643 ret = intel_link_power_down(sdw);
1645 dev_err(dev, "Link power down failed: %d\n", ret);
1649 intel_shim_wake(sdw, false);
1654 static int __maybe_unused intel_suspend_runtime(struct device *dev)
1656 struct sdw_cdns *cdns = dev_get_drvdata(dev);
1657 struct sdw_intel *sdw = cdns_to_intel(cdns);
1658 struct sdw_bus *bus = &cdns->bus;
1659 u32 clock_stop_quirks;
1662 if (bus->prop.hw_disabled || !sdw->startup_done) {
1663 dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1668 clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1670 if (clock_stop_quirks & SDW_INTEL_CLK_STOP_TEARDOWN) {
1672 ret = sdw_cdns_enable_interrupt(cdns, false);
1674 dev_err(dev, "cannot disable interrupts on suspend\n");
1678 ret = intel_link_power_down(sdw);
1680 dev_err(dev, "Link power down failed: %d\n", ret);
1684 intel_shim_wake(sdw, false);
1686 } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET ||
1687 !clock_stop_quirks) {
1688 bool wake_enable = true;
1690 ret = sdw_cdns_clock_stop(cdns, true);
1692 dev_err(dev, "cannot enable clock stop on suspend\n");
1693 wake_enable = false;
1696 ret = sdw_cdns_enable_interrupt(cdns, false);
1698 dev_err(dev, "cannot disable interrupts on suspend\n");
1702 ret = intel_link_power_down(sdw);
1704 dev_err(dev, "Link power down failed: %d\n", ret);
1708 intel_shim_wake(sdw, wake_enable);
1710 dev_err(dev, "%s clock_stop_quirks %x unsupported\n",
1711 __func__, clock_stop_quirks);
1718 static int __maybe_unused intel_resume(struct device *dev)
1720 struct sdw_cdns *cdns = dev_get_drvdata(dev);
1721 struct sdw_intel *sdw = cdns_to_intel(cdns);
1722 struct sdw_bus *bus = &cdns->bus;
1727 if (bus->prop.hw_disabled || !sdw->startup_done) {
1728 dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1733 link_flags = md_flags >> (bus->link_id * 8);
1734 multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK);
1736 if (pm_runtime_suspended(dev)) {
1737 dev_dbg(dev, "%s: pm_runtime status was suspended, forcing active\n", __func__);
1739 /* follow required sequence from runtime_pm.rst */
1740 pm_runtime_disable(dev);
1741 pm_runtime_set_active(dev);
1742 pm_runtime_mark_last_busy(dev);
1743 pm_runtime_enable(dev);
1745 link_flags = md_flags >> (bus->link_id * 8);
1747 if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE))
1748 pm_runtime_idle(dev);
1751 ret = intel_init(sdw);
1753 dev_err(dev, "%s failed: %d\n", __func__, ret);
1758 * make sure all Slaves are tagged as UNATTACHED and provide
1759 * reason for reinitialization
1761 sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET);
1763 ret = sdw_cdns_enable_interrupt(cdns, true);
1765 dev_err(dev, "cannot enable interrupts during resume\n");
1770 * follow recommended programming flows to avoid timeouts when
1774 intel_shim_sync_arm(sdw);
1776 ret = sdw_cdns_init(&sdw->cdns);
1778 dev_err(dev, "unable to initialize Cadence IP during resume\n");
1782 ret = sdw_cdns_exit_reset(cdns);
1784 dev_err(dev, "unable to exit bus reset sequence during resume\n");
1789 ret = intel_shim_sync_go(sdw);
1791 dev_err(dev, "sync go failed during resume\n");
1795 sdw_cdns_check_self_clearing_bits(cdns, __func__,
1796 true, INTEL_MASTER_RESET_ITERATIONS);
1799 * after system resume, the pm_runtime suspend() may kick in
1800 * during the enumeration, before any children device force the
1801 * master device to remain active. Using pm_runtime_get()
1802 * routines is not really possible, since it'd prevent the
1803 * master from suspending.
1804 * A reasonable compromise is to update the pm_runtime
1805 * counters and delay the pm_runtime suspend by several
1806 * seconds, by when all enumeration should be complete.
1808 pm_runtime_mark_last_busy(dev);
1813 static int __maybe_unused intel_resume_runtime(struct device *dev)
1815 struct sdw_cdns *cdns = dev_get_drvdata(dev);
1816 struct sdw_intel *sdw = cdns_to_intel(cdns);
1817 struct sdw_bus *bus = &cdns->bus;
1818 u32 clock_stop_quirks;
1825 if (bus->prop.hw_disabled || !sdw->startup_done) {
1826 dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1831 link_flags = md_flags >> (bus->link_id * 8);
1832 multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK);
1834 clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1836 if (clock_stop_quirks & SDW_INTEL_CLK_STOP_TEARDOWN) {
1837 ret = intel_init(sdw);
1839 dev_err(dev, "%s failed: %d\n", __func__, ret);
1844 * make sure all Slaves are tagged as UNATTACHED and provide
1845 * reason for reinitialization
1847 sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET);
1849 ret = sdw_cdns_enable_interrupt(cdns, true);
1851 dev_err(dev, "cannot enable interrupts during resume\n");
1856 * follow recommended programming flows to avoid
1857 * timeouts when gsync is enabled
1860 intel_shim_sync_arm(sdw);
1862 ret = sdw_cdns_init(&sdw->cdns);
1864 dev_err(dev, "unable to initialize Cadence IP during resume\n");
1868 ret = sdw_cdns_exit_reset(cdns);
1870 dev_err(dev, "unable to exit bus reset sequence during resume\n");
1875 ret = intel_shim_sync_go(sdw);
1877 dev_err(dev, "sync go failed during resume\n");
1881 sdw_cdns_check_self_clearing_bits(cdns, "intel_resume_runtime TEARDOWN",
1882 true, INTEL_MASTER_RESET_ITERATIONS);
1884 } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET) {
1885 ret = intel_init(sdw);
1887 dev_err(dev, "%s failed: %d\n", __func__, ret);
1892 * An exception condition occurs for the CLK_STOP_BUS_RESET
1893 * case if one or more masters remain active. In this condition,
1894 * all the masters are powered on for they are in the same power
1895 * domain. Master can preserve its context for clock stop0, so
1896 * there is no need to clear slave status and reset bus.
1898 clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns);
1903 * make sure all Slaves are tagged as UNATTACHED and
1904 * provide reason for reinitialization
1907 status = SDW_UNATTACH_REQUEST_MASTER_RESET;
1908 sdw_clear_slave_status(bus, status);
1910 ret = sdw_cdns_enable_interrupt(cdns, true);
1912 dev_err(dev, "cannot enable interrupts during resume\n");
1917 * follow recommended programming flows to avoid
1918 * timeouts when gsync is enabled
1921 intel_shim_sync_arm(sdw);
1924 * Re-initialize the IP since it was powered-off
1926 sdw_cdns_init(&sdw->cdns);
1929 ret = sdw_cdns_enable_interrupt(cdns, true);
1931 dev_err(dev, "cannot enable interrupts during resume\n");
1936 ret = sdw_cdns_clock_restart(cdns, !clock_stop0);
1938 dev_err(dev, "unable to restart clock during resume\n");
1943 ret = sdw_cdns_exit_reset(cdns);
1945 dev_err(dev, "unable to exit bus reset sequence during resume\n");
1950 ret = intel_shim_sync_go(sdw);
1952 dev_err(sdw->cdns.dev, "sync go failed during resume\n");
1957 sdw_cdns_check_self_clearing_bits(cdns, "intel_resume_runtime BUS_RESET",
1958 true, INTEL_MASTER_RESET_ITERATIONS);
1960 } else if (!clock_stop_quirks) {
1962 clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns);
1964 dev_err(dev, "%s invalid configuration, clock was not stopped", __func__);
1966 ret = intel_init(sdw);
1968 dev_err(dev, "%s failed: %d\n", __func__, ret);
1972 ret = sdw_cdns_enable_interrupt(cdns, true);
1974 dev_err(dev, "cannot enable interrupts during resume\n");
1978 ret = sdw_cdns_clock_restart(cdns, false);
1980 dev_err(dev, "unable to resume master during resume\n");
1984 sdw_cdns_check_self_clearing_bits(cdns, "intel_resume_runtime no_quirks",
1985 true, INTEL_MASTER_RESET_ITERATIONS);
1987 dev_err(dev, "%s clock_stop_quirks %x unsupported\n",
1988 __func__, clock_stop_quirks);
1995 static const struct dev_pm_ops intel_pm = {
1996 .prepare = intel_pm_prepare,
1997 SET_SYSTEM_SLEEP_PM_OPS(intel_suspend, intel_resume)
1998 SET_RUNTIME_PM_OPS(intel_suspend_runtime, intel_resume_runtime, NULL)
2001 static const struct auxiliary_device_id intel_link_id_table[] = {
2002 { .name = "soundwire_intel.link" },
2005 MODULE_DEVICE_TABLE(auxiliary, intel_link_id_table);
2007 static struct auxiliary_driver sdw_intel_drv = {
2008 .probe = intel_link_probe,
2009 .remove = intel_link_remove,
2011 /* auxiliary_driver_register() sets .name to be the modname */
2014 .id_table = intel_link_id_table
2016 module_auxiliary_driver(sdw_intel_drv);
2018 MODULE_LICENSE("Dual BSD/GPL");
2019 MODULE_DESCRIPTION("Intel Soundwire Link Driver");