drivers/soundwire/intel.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
   2 // Copyright(c) 2015-17 Intel Corporation.
   3
   4 /*
   5  * Soundwire Intel Master Driver
   6  */
   7
   8 #include <linux/acpi.h>
   9 #include <linux/debugfs.h>
  10 #include <linux/delay.h>
  11 #include <linux/module.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/platform_device.h>
  15 #include <sound/pcm_params.h>
  16 #include <linux/pm_runtime.h>
  17 #include <sound/soc.h>
  18 #include <linux/soundwire/sdw_registers.h>
  19 #include <linux/soundwire/sdw.h>
  20 #include <linux/soundwire/sdw_intel.h>
  21 #include "cadence_master.h"
  22 #include "bus.h"
  23 #include "intel.h"
  24
  25 #define INTEL_MASTER_SUSPEND_DELAY_MS   3000
  26
  27 /*
  28  * debug/config flags for the Intel SoundWire Master.
  29  *
  30  * Since we may have multiple masters active, we can have up to 8
  31  * flags reused in each byte, with master0 using the ls-byte, etc.
  32  */
  33
  34 #define SDW_INTEL_MASTER_DISABLE_PM_RUNTIME             BIT(0)
  35 #define SDW_INTEL_MASTER_DISABLE_CLOCK_STOP             BIT(1)
  36 #define SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE        BIT(2)
  37 #define SDW_INTEL_MASTER_DISABLE_MULTI_LINK             BIT(3)
  38
  39 static int md_flags;
  40 module_param_named(sdw_md_flags, md_flags, int, 0444);
  41 MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags (0x0 all off)");
  42
  43 /* Intel SHIM Registers Definition */
  44 #define SDW_SHIM_LCAP                   0x0
  45 #define SDW_SHIM_LCTL                   0x4
  46 #define SDW_SHIM_IPPTR                  0x8
  47 #define SDW_SHIM_SYNC                   0xC
  48
  49 #define SDW_SHIM_CTLSCAP(x)             (0x010 + 0x60 * (x))
  50 #define SDW_SHIM_CTLS0CM(x)             (0x012 + 0x60 * (x))
  51 #define SDW_SHIM_CTLS1CM(x)             (0x014 + 0x60 * (x))
  52 #define SDW_SHIM_CTLS2CM(x)             (0x016 + 0x60 * (x))
  53 #define SDW_SHIM_CTLS3CM(x)             (0x018 + 0x60 * (x))
  54 #define SDW_SHIM_PCMSCAP(x)             (0x020 + 0x60 * (x))
  55
  56 #define SDW_SHIM_PCMSYCHM(x, y)         (0x022 + (0x60 * (x)) + (0x2 * (y)))
  57 #define SDW_SHIM_PCMSYCHC(x, y)         (0x042 + (0x60 * (x)) + (0x2 * (y)))
  58 #define SDW_SHIM_PDMSCAP(x)             (0x062 + 0x60 * (x))
  59 #define SDW_SHIM_IOCTL(x)               (0x06C + 0x60 * (x))
  60 #define SDW_SHIM_CTMCTL(x)              (0x06E + 0x60 * (x))
  61
  62 #define SDW_SHIM_WAKEEN                 0x190
  63 #define SDW_SHIM_WAKESTS                0x192
  64
  65 #define SDW_SHIM_LCTL_SPA               BIT(0)
  66 #define SDW_SHIM_LCTL_SPA_MASK          GENMASK(3, 0)
  67 #define SDW_SHIM_LCTL_CPA               BIT(8)
  68 #define SDW_SHIM_LCTL_CPA_MASK          GENMASK(11, 8)
  69
  70 #define SDW_SHIM_SYNC_SYNCPRD_VAL_24    (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
  71 #define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4  (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
  72 #define SDW_SHIM_SYNC_SYNCPRD           GENMASK(14, 0)
  73 #define SDW_SHIM_SYNC_SYNCCPU           BIT(15)
  74 #define SDW_SHIM_SYNC_CMDSYNC_MASK      GENMASK(19, 16)
  75 #define SDW_SHIM_SYNC_CMDSYNC           BIT(16)
  76 #define SDW_SHIM_SYNC_SYNCGO            BIT(24)
  77
  78 #define SDW_SHIM_PCMSCAP_ISS            GENMASK(3, 0)
  79 #define SDW_SHIM_PCMSCAP_OSS            GENMASK(7, 4)
  80 #define SDW_SHIM_PCMSCAP_BSS            GENMASK(12, 8)
  81
  82 #define SDW_SHIM_PCMSYCM_LCHN           GENMASK(3, 0)
  83 #define SDW_SHIM_PCMSYCM_HCHN           GENMASK(7, 4)
  84 #define SDW_SHIM_PCMSYCM_STREAM         GENMASK(13, 8)
  85 #define SDW_SHIM_PCMSYCM_DIR            BIT(15)
  86
  87 #define SDW_SHIM_PDMSCAP_ISS            GENMASK(3, 0)
  88 #define SDW_SHIM_PDMSCAP_OSS            GENMASK(7, 4)
  89 #define SDW_SHIM_PDMSCAP_BSS            GENMASK(12, 8)
  90 #define SDW_SHIM_PDMSCAP_CPSS           GENMASK(15, 13)
  91
  92 #define SDW_SHIM_IOCTL_MIF              BIT(0)
  93 #define SDW_SHIM_IOCTL_CO               BIT(1)
  94 #define SDW_SHIM_IOCTL_COE              BIT(2)
  95 #define SDW_SHIM_IOCTL_DO               BIT(3)
  96 #define SDW_SHIM_IOCTL_DOE              BIT(4)
  97 #define SDW_SHIM_IOCTL_BKE              BIT(5)
  98 #define SDW_SHIM_IOCTL_WPDD             BIT(6)
  99 #define SDW_SHIM_IOCTL_CIBD             BIT(8)
 100 #define SDW_SHIM_IOCTL_DIBD             BIT(9)
 101
 102 #define SDW_SHIM_CTMCTL_DACTQE          BIT(0)
 103 #define SDW_SHIM_CTMCTL_DODS            BIT(1)
 104 #define SDW_SHIM_CTMCTL_DOAIS           GENMASK(4, 3)
 105
 106 #define SDW_SHIM_WAKEEN_ENABLE          BIT(0)
 107 #define SDW_SHIM_WAKESTS_STATUS         BIT(0)
 108
 109 /* Intel ALH Register definitions */
 110 #define SDW_ALH_STRMZCFG(x)             (0x000 + (0x4 * (x)))
 111 #define SDW_ALH_NUM_STREAMS             64
 112
 113 #define SDW_ALH_STRMZCFG_DMAT_VAL       0x3
 114 #define SDW_ALH_STRMZCFG_DMAT           GENMASK(7, 0)
 115 #define SDW_ALH_STRMZCFG_CHN            GENMASK(19, 16)
 116
 117 enum intel_pdi_type {
 118         INTEL_PDI_IN = 0,
 119         INTEL_PDI_OUT = 1,
 120         INTEL_PDI_BD = 2,
 121 };
 122
 123 #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns)
 124
 125 /*
 126  * Read, write helpers for HW registers
 127  */
 128 static inline int intel_readl(void __iomem *base, int offset)
 129 {
 130         return readl(base + offset);
 131 }
 132
 133 static inline void intel_writel(void __iomem *base, int offset, int value)
 134 {
 135         writel(value, base + offset);
 136 }
 137
 138 static inline u16 intel_readw(void __iomem *base, int offset)
 139 {
 140         return readw(base + offset);
 141 }
 142
 143 static inline void intel_writew(void __iomem *base, int offset, u16 value)
 144 {
 145         writew(value, base + offset);
 146 }
 147
 148 static int intel_wait_bit(void __iomem *base, int offset, u32 mask, u32 target)
 149 {
 150         int timeout = 10;
 151         u32 reg_read;
 152
 153         do {
 154                 reg_read = readl(base + offset);
 155                 if ((reg_read & mask) == target)
 156                         return 0;
 157
 158                 timeout--;
 159                 usleep_range(50, 100);
 160         } while (timeout != 0);
 161
 162         return -EAGAIN;
 163 }
 164
 165 static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask)
 166 {
 167         writel(value, base + offset);
 168         return intel_wait_bit(base, offset, mask, 0);
 169 }
 170
 171 static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask)
 172 {
 173         writel(value, base + offset);
 174         return intel_wait_bit(base, offset, mask, mask);
 175 }
 176
 177 /*
 178  * debugfs
 179  */
 180 #ifdef CONFIG_DEBUG_FS
 181
 182 #define RD_BUF (2 * PAGE_SIZE)
 183
 184 static ssize_t intel_sprintf(void __iomem *mem, bool l,
 185                              char *buf, size_t pos, unsigned int reg)
 186 {
 187         int value;
 188
 189         if (l)
 190                 value = intel_readl(mem, reg);
 191         else
 192                 value = intel_readw(mem, reg);
 193
 194         return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value);
 195 }
 196
 197 static int intel_reg_show(struct seq_file *s_file, void *data)
 198 {
 199         struct sdw_intel *sdw = s_file->private;
 200         void __iomem *s = sdw->link_res->shim;
 201         void __iomem *a = sdw->link_res->alh;
 202         char *buf;
 203         ssize_t ret;
 204         int i, j;
 205         unsigned int links, reg;
 206
 207         buf = kzalloc(RD_BUF, GFP_KERNEL);
 208         if (!buf)
 209                 return -ENOMEM;
 210
 211         links = intel_readl(s, SDW_SHIM_LCAP) & GENMASK(2, 0);
 212
 213         ret = scnprintf(buf, RD_BUF, "Register  Value\n");
 214         ret += scnprintf(buf + ret, RD_BUF - ret, "\nShim\n");
 215
 216         for (i = 0; i < links; i++) {
 217                 reg = SDW_SHIM_LCAP + i * 4;
 218                 ret += intel_sprintf(s, true, buf, ret, reg);
 219         }
 220
 221         for (i = 0; i < links; i++) {
 222                 ret += scnprintf(buf + ret, RD_BUF - ret, "\nLink%d\n", i);
 223                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLSCAP(i));
 224                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS0CM(i));
 225                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS1CM(i));
 226                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS2CM(i));
 227                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS3CM(i));
 228                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PCMSCAP(i));
 229
 230                 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PCMSyCH registers\n");
 231
 232                 /*
 233                  * the value 10 is the number of PDIs. We will need a
 234                  * cleanup to remove hard-coded Intel configurations
 235                  * from cadence_master.c
 236                  */
 237                 for (j = 0; j < 10; j++) {
 238                         ret += intel_sprintf(s, false, buf, ret,
 239                                         SDW_SHIM_PCMSYCHM(i, j));
 240                         ret += intel_sprintf(s, false, buf, ret,
 241                                         SDW_SHIM_PCMSYCHC(i, j));
 242                 }
 243                 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PDMSCAP, IOCTL, CTMCTL\n");
 244
 245                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PDMSCAP(i));
 246                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_IOCTL(i));
 247                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTMCTL(i));
 248         }
 249
 250         ret += scnprintf(buf + ret, RD_BUF - ret, "\nWake registers\n");
 251         ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKEEN);
 252         ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKESTS);
 253
 254         ret += scnprintf(buf + ret, RD_BUF - ret, "\nALH STRMzCFG\n");
 255         for (i = 0; i < SDW_ALH_NUM_STREAMS; i++)
 256                 ret += intel_sprintf(a, true, buf, ret, SDW_ALH_STRMZCFG(i));
 257
 258         seq_printf(s_file, "%s", buf);
 259         kfree(buf);
 260
 261         return 0;
 262 }
 263 DEFINE_SHOW_ATTRIBUTE(intel_reg);
 264
 265 static int intel_set_m_datamode(void *data, u64 value)
 266 {
 267         struct sdw_intel *sdw = data;
 268         struct sdw_bus *bus = &sdw->cdns.bus;
 269
 270         if (value > SDW_PORT_DATA_MODE_STATIC_1)
 271                 return -EINVAL;
 272
 273         /* Userspace changed the hardware state behind the kernel's back */
 274         add_taint(TAINT_USER, LOCKDEP_STILL_OK);
 275
 276         bus->params.m_data_mode = value;
 277
 278         return 0;
 279 }
 280 DEFINE_DEBUGFS_ATTRIBUTE(intel_set_m_datamode_fops, NULL,
 281                          intel_set_m_datamode, "%llu\n");
 282
 283 static int intel_set_s_datamode(void *data, u64 value)
 284 {
 285         struct sdw_intel *sdw = data;
 286         struct sdw_bus *bus = &sdw->cdns.bus;
 287
 288         if (value > SDW_PORT_DATA_MODE_STATIC_1)
 289                 return -EINVAL;
 290
 291         /* Userspace changed the hardware state behind the kernel's back */
 292         add_taint(TAINT_USER, LOCKDEP_STILL_OK);
 293
 294         bus->params.s_data_mode = value;
 295
 296         return 0;
 297 }
 298 DEFINE_DEBUGFS_ATTRIBUTE(intel_set_s_datamode_fops, NULL,
 299                          intel_set_s_datamode, "%llu\n");
 300
 301 static void intel_debugfs_init(struct sdw_intel *sdw)
 302 {
 303         struct dentry *root = sdw->cdns.bus.debugfs;
 304
 305         if (!root)
 306                 return;
 307
 308         sdw->debugfs = debugfs_create_dir("intel-sdw", root);
 309
 310         debugfs_create_file("intel-registers", 0400, sdw->debugfs, sdw,
 311                             &intel_reg_fops);
 312
 313         debugfs_create_file("intel-m-datamode", 0200, sdw->debugfs, sdw,
 314                             &intel_set_m_datamode_fops);
 315
 316         debugfs_create_file("intel-s-datamode", 0200, sdw->debugfs, sdw,
 317                             &intel_set_s_datamode_fops);
 318
 319         sdw_cdns_debugfs_init(&sdw->cdns, sdw->debugfs);
 320 }
 321
 322 static void intel_debugfs_exit(struct sdw_intel *sdw)
 323 {
 324         debugfs_remove_recursive(sdw->debugfs);
 325 }
 326 #else
 327 static void intel_debugfs_init(struct sdw_intel *sdw) {}
 328 static void intel_debugfs_exit(struct sdw_intel *sdw) {}
 329 #endif /* CONFIG_DEBUG_FS */
 330
 331 /*
 332  * shim ops
 333  */
 334
 335 static int intel_link_power_up(struct sdw_intel *sdw)
 336 {
 337         unsigned int link_id = sdw->instance;
 338         void __iomem *shim = sdw->link_res->shim;
 339         u32 *shim_mask = sdw->link_res->shim_mask;
 340         struct sdw_bus *bus = &sdw->cdns.bus;
 341         struct sdw_master_prop *prop = &bus->prop;
 342         u32 spa_mask, cpa_mask;
 343         u32 link_control;
 344         int ret = 0;
 345         u32 syncprd;
 346         u32 sync_reg;
 347
 348         mutex_lock(sdw->link_res->shim_lock);
 349
 350         /*
 351          * The hardware relies on an internal counter, typically 4kHz,
 352          * to generate the SoundWire SSP - which defines a 'safe'
 353          * synchronization point between commands and audio transport
 354          * and allows for multi link synchronization. The SYNCPRD value
 355          * is only dependent on the oscillator clock provided to
 356          * the IP, so adjust based on _DSD properties reported in DSDT
 357          * tables. The values reported are based on either 24MHz
 358          * (CNL/CML) or 38.4 MHz (ICL/TGL+).
 359          */
 360         if (prop->mclk_freq % 6000000)
 361                 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;
 362         else
 363                 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24;
 364
 365         if (!*shim_mask) {
 366                 dev_dbg(sdw->cdns.dev, "%s: powering up all links\n", __func__);
 367
 368                 /* we first need to program the SyncPRD/CPU registers */
 369                 dev_dbg(sdw->cdns.dev,
 370                         "%s: first link up, programming SYNCPRD\n", __func__);
 371
 372                 /* set SyncPRD period */
 373                 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
 374                 u32p_replace_bits(&sync_reg, syncprd, SDW_SHIM_SYNC_SYNCPRD);
 375
 376                 /* Set SyncCPU bit */
 377                 sync_reg |= SDW_SHIM_SYNC_SYNCCPU;
 378                 intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
 379
 380                 /* Link power up sequence */
 381                 link_control = intel_readl(shim, SDW_SHIM_LCTL);
 382
 383                 /* only power-up enabled links */
 384                 spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, sdw->link_res->link_mask);
 385                 cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask);
 386
 387                 link_control |=  spa_mask;
 388
 389                 ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
 390                 if (ret < 0) {
 391                         dev_err(sdw->cdns.dev, "Failed to power up link: %d\n", ret);
 392                         goto out;
 393                 }
 394
 395                 /* SyncCPU will change once link is active */
 396                 ret = intel_wait_bit(shim, SDW_SHIM_SYNC,
 397                                      SDW_SHIM_SYNC_SYNCCPU, 0);
 398                 if (ret < 0) {
 399                         dev_err(sdw->cdns.dev,
 400                                 "Failed to set SHIM_SYNC: %d\n", ret);
 401                         goto out;
 402                 }
 403         }
 404
 405         *shim_mask |= BIT(link_id);
 406
 407         sdw->cdns.link_up = true;
 408 out:
 409         mutex_unlock(sdw->link_res->shim_lock);
 410
 411         return ret;
 412 }
 413
 414 /* this needs to be called with shim_lock */
 415 static void intel_shim_glue_to_master_ip(struct sdw_intel *sdw)
 416 {
 417         void __iomem *shim = sdw->link_res->shim;
 418         unsigned int link_id = sdw->instance;
 419         u16 ioctl;
 420
 421         /* Switch to MIP from Glue logic */
 422         ioctl = intel_readw(shim,  SDW_SHIM_IOCTL(link_id));
 423
 424         ioctl &= ~(SDW_SHIM_IOCTL_DOE);
 425         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 426         usleep_range(10, 15);
 427
 428         ioctl &= ~(SDW_SHIM_IOCTL_DO);
 429         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 430         usleep_range(10, 15);
 431
 432         ioctl |= (SDW_SHIM_IOCTL_MIF);
 433         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 434         usleep_range(10, 15);
 435
 436         ioctl &= ~(SDW_SHIM_IOCTL_BKE);
 437         ioctl &= ~(SDW_SHIM_IOCTL_COE);
 438         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 439         usleep_range(10, 15);
 440
 441         /* at this point Master IP has full control of the I/Os */
 442 }
 443
 444 /* this needs to be called with shim_lock */
 445 static void intel_shim_master_ip_to_glue(struct sdw_intel *sdw)
 446 {
 447         unsigned int link_id = sdw->instance;
 448         void __iomem *shim = sdw->link_res->shim;
 449         u16 ioctl;
 450
 451         /* Glue logic */
 452         ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
 453         ioctl |= SDW_SHIM_IOCTL_BKE;
 454         ioctl |= SDW_SHIM_IOCTL_COE;
 455         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 456         usleep_range(10, 15);
 457
 458         ioctl &= ~(SDW_SHIM_IOCTL_MIF);
 459         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 460         usleep_range(10, 15);
 461
 462         /* at this point Integration Glue has full control of the I/Os */
 463 }
 464
 465 static int intel_shim_init(struct sdw_intel *sdw, bool clock_stop)
 466 {
 467         void __iomem *shim = sdw->link_res->shim;
 468         unsigned int link_id = sdw->instance;
 469         int ret = 0;
 470         u16 ioctl = 0, act = 0;
 471
 472         mutex_lock(sdw->link_res->shim_lock);
 473
 474         /* Initialize Shim */
 475         ioctl |= SDW_SHIM_IOCTL_BKE;
 476         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 477         usleep_range(10, 15);
 478
 479         ioctl |= SDW_SHIM_IOCTL_WPDD;
 480         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 481         usleep_range(10, 15);
 482
 483         ioctl |= SDW_SHIM_IOCTL_DO;
 484         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 485         usleep_range(10, 15);
 486
 487         ioctl |= SDW_SHIM_IOCTL_DOE;
 488         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 489         usleep_range(10, 15);
 490
 491         intel_shim_glue_to_master_ip(sdw);
 492
 493         u16p_replace_bits(&act, 0x1, SDW_SHIM_CTMCTL_DOAIS);
 494         act |= SDW_SHIM_CTMCTL_DACTQE;
 495         act |= SDW_SHIM_CTMCTL_DODS;
 496         intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act);
 497         usleep_range(10, 15);
 498
 499         mutex_unlock(sdw->link_res->shim_lock);
 500
 501         return ret;
 502 }
 503
 504 static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable)
 505 {
 506         void __iomem *shim = sdw->link_res->shim;
 507         unsigned int link_id = sdw->instance;
 508         u16 wake_en, wake_sts;
 509
 510         mutex_lock(sdw->link_res->shim_lock);
 511         wake_en = intel_readw(shim, SDW_SHIM_WAKEEN);
 512
 513         if (wake_enable) {
 514                 /* Enable the wakeup */
 515                 wake_en |= (SDW_SHIM_WAKEEN_ENABLE << link_id);
 516                 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
 517         } else {
 518                 /* Disable the wake up interrupt */
 519                 wake_en &= ~(SDW_SHIM_WAKEEN_ENABLE << link_id);
 520                 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
 521
 522                 /* Clear wake status */
 523                 wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);
 524                 wake_sts |= (SDW_SHIM_WAKEEN_ENABLE << link_id);
 525                 intel_writew(shim, SDW_SHIM_WAKESTS_STATUS, wake_sts);
 526         }
 527         mutex_unlock(sdw->link_res->shim_lock);
 528 }
 529
 530 static int intel_link_power_down(struct sdw_intel *sdw)
 531 {
 532         u32 link_control, spa_mask, cpa_mask;
 533         unsigned int link_id = sdw->instance;
 534         void __iomem *shim = sdw->link_res->shim;
 535         u32 *shim_mask = sdw->link_res->shim_mask;
 536         int ret = 0;
 537
 538         mutex_lock(sdw->link_res->shim_lock);
 539
 540         intel_shim_master_ip_to_glue(sdw);
 541
 542         if (!(*shim_mask & BIT(link_id)))
 543                 dev_err(sdw->cdns.dev,
 544                         "%s: Unbalanced power-up/down calls\n", __func__);
 545
 546         *shim_mask &= ~BIT(link_id);
 547
 548         if (!*shim_mask) {
 549
 550                 dev_dbg(sdw->cdns.dev, "%s: powering down all links\n", __func__);
 551
 552                 /* Link power down sequence */
 553                 link_control = intel_readl(shim, SDW_SHIM_LCTL);
 554
 555                 /* only power-down enabled links */
 556                 spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, ~sdw->link_res->link_mask);
 557                 cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask);
 558
 559                 link_control &=  spa_mask;
 560
 561                 ret = intel_clear_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
 562         }
 563
 564         link_control = intel_readl(shim, SDW_SHIM_LCTL);
 565
 566         mutex_unlock(sdw->link_res->shim_lock);
 567
 568         if (ret < 0) {
 569                 dev_err(sdw->cdns.dev, "%s: could not power down link\n", __func__);
 570
 571                 return ret;
 572         }
 573
 574         sdw->cdns.link_up = false;
 575         return 0;
 576 }
 577
 578 static void intel_shim_sync_arm(struct sdw_intel *sdw)
 579 {
 580         void __iomem *shim = sdw->link_res->shim;
 581         u32 sync_reg;
 582
 583         mutex_lock(sdw->link_res->shim_lock);
 584
 585         /* update SYNC register */
 586         sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
 587         sync_reg |= (SDW_SHIM_SYNC_CMDSYNC << sdw->instance);
 588         intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
 589
 590         mutex_unlock(sdw->link_res->shim_lock);
 591 }
 592
 593 static int intel_shim_sync_go_unlocked(struct sdw_intel *sdw)
 594 {
 595         void __iomem *shim = sdw->link_res->shim;
 596         u32 sync_reg;
 597         int ret;
 598
 599         /* Read SYNC register */
 600         sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
 601
 602         /*
 603          * Set SyncGO bit to synchronously trigger a bank switch for
 604          * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all
 605          * the Masters.
 606          */
 607         sync_reg |= SDW_SHIM_SYNC_SYNCGO;
 608
 609         ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
 610                               SDW_SHIM_SYNC_SYNCGO);
 611
 612         if (ret < 0)
 613                 dev_err(sdw->cdns.dev, "SyncGO clear failed: %d\n", ret);
 614
 615         return ret;
 616 }
 617
 618 static int intel_shim_sync_go(struct sdw_intel *sdw)
 619 {
 620         int ret;
 621
 622         mutex_lock(sdw->link_res->shim_lock);
 623
 624         ret = intel_shim_sync_go_unlocked(sdw);
 625
 626         mutex_unlock(sdw->link_res->shim_lock);
 627
 628         return ret;
 629 }
 630
 631 /*
 632  * PDI routines
 633  */
 634 static void intel_pdi_init(struct sdw_intel *sdw,
 635                            struct sdw_cdns_stream_config *config)
 636 {
 637         void __iomem *shim = sdw->link_res->shim;
 638         unsigned int link_id = sdw->instance;
 639         int pcm_cap, pdm_cap;
 640
 641         /* PCM Stream Capability */
 642         pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id));
 643
 644         config->pcm_bd = FIELD_GET(SDW_SHIM_PCMSCAP_BSS, pcm_cap);
 645         config->pcm_in = FIELD_GET(SDW_SHIM_PCMSCAP_ISS, pcm_cap);
 646         config->pcm_out = FIELD_GET(SDW_SHIM_PCMSCAP_OSS, pcm_cap);
 647
 648         dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n",
 649                 config->pcm_bd, config->pcm_in, config->pcm_out);
 650
 651         /* PDM Stream Capability */
 652         pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
 653
 654         config->pdm_bd = FIELD_GET(SDW_SHIM_PDMSCAP_BSS, pdm_cap);
 655         config->pdm_in = FIELD_GET(SDW_SHIM_PDMSCAP_ISS, pdm_cap);
 656         config->pdm_out = FIELD_GET(SDW_SHIM_PDMSCAP_OSS, pdm_cap);
 657
 658         dev_dbg(sdw->cdns.dev, "PDM cap bd:%d in:%d out:%d\n",
 659                 config->pdm_bd, config->pdm_in, config->pdm_out);
 660 }
 661
 662 static int
 663 intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm)
 664 {
 665         void __iomem *shim = sdw->link_res->shim;
 666         unsigned int link_id = sdw->instance;
 667         int count;
 668
 669         if (pcm) {
 670                 count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num));
 671
 672                 /*
 673                  * WORKAROUND: on all existing Intel controllers, pdi
 674                  * number 2 reports channel count as 1 even though it
 675                  * supports 8 channels. Performing hardcoding for pdi
 676                  * number 2.
 677                  */
 678                 if (pdi_num == 2)
 679                         count = 7;
 680
 681         } else {
 682                 count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
 683                 count = FIELD_GET(SDW_SHIM_PDMSCAP_CPSS, count);
 684         }
 685
 686         /* zero based values for channel count in register */
 687         count++;
 688
 689         return count;
 690 }
 691
 692 static int intel_pdi_get_ch_update(struct sdw_intel *sdw,
 693                                    struct sdw_cdns_pdi *pdi,
 694                                    unsigned int num_pdi,
 695                                    unsigned int *num_ch, bool pcm)
 696 {
 697         int i, ch_count = 0;
 698
 699         for (i = 0; i < num_pdi; i++) {
 700                 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm);
 701                 ch_count += pdi->ch_count;
 702                 pdi++;
 703         }
 704
 705         *num_ch = ch_count;
 706         return 0;
 707 }
 708
 709 static int intel_pdi_stream_ch_update(struct sdw_intel *sdw,
 710                                       struct sdw_cdns_streams *stream, bool pcm)
 711 {
 712         intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
 713                                 &stream->num_ch_bd, pcm);
 714
 715         intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
 716                                 &stream->num_ch_in, pcm);
 717
 718         intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
 719                                 &stream->num_ch_out, pcm);
 720
 721         return 0;
 722 }
 723
 724 static int intel_pdi_ch_update(struct sdw_intel *sdw)
 725 {
 726         /* First update PCM streams followed by PDM streams */
 727         intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true);
 728         intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false);
 729
 730         return 0;
 731 }
 732
 733 static void
 734 intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
 735 {
 736         void __iomem *shim = sdw->link_res->shim;
 737         unsigned int link_id = sdw->instance;
 738         int pdi_conf = 0;
 739
 740         /* the Bulk and PCM streams are not contiguous */
 741         pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
 742         if (pdi->num >= 2)
 743                 pdi->intel_alh_id += 2;
 744
 745         /*
 746          * Program stream parameters to stream SHIM register
 747          * This is applicable for PCM stream only.
 748          */
 749         if (pdi->type != SDW_STREAM_PCM)
 750                 return;
 751
 752         if (pdi->dir == SDW_DATA_DIR_RX)
 753                 pdi_conf |= SDW_SHIM_PCMSYCM_DIR;
 754         else
 755                 pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR);
 756
 757         u32p_replace_bits(&pdi_conf, pdi->intel_alh_id, SDW_SHIM_PCMSYCM_STREAM);
 758         u32p_replace_bits(&pdi_conf, pdi->l_ch_num, SDW_SHIM_PCMSYCM_LCHN);
 759         u32p_replace_bits(&pdi_conf, pdi->h_ch_num, SDW_SHIM_PCMSYCM_HCHN);
 760
 761         intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf);
 762 }
 763
 764 static void
 765 intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
 766 {
 767         void __iomem *alh = sdw->link_res->alh;
 768         unsigned int link_id = sdw->instance;
 769         unsigned int conf;
 770
 771         /* the Bulk and PCM streams are not contiguous */
 772         pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
 773         if (pdi->num >= 2)
 774                 pdi->intel_alh_id += 2;
 775
 776         /* Program Stream config ALH register */
 777         conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id));
 778
 779         u32p_replace_bits(&conf, SDW_ALH_STRMZCFG_DMAT_VAL, SDW_ALH_STRMZCFG_DMAT);
 780         u32p_replace_bits(&conf, pdi->ch_count - 1, SDW_ALH_STRMZCFG_CHN);
 781
 782         intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf);
 783 }
 784
 785 static int intel_params_stream(struct sdw_intel *sdw,
 786                                struct snd_pcm_substream *substream,
 787                                struct snd_soc_dai *dai,
 788                                struct snd_pcm_hw_params *hw_params,
 789                                int link_id, int alh_stream_id)
 790 {
 791         struct sdw_intel_link_res *res = sdw->link_res;
 792         struct sdw_intel_stream_params_data params_data;
 793
 794         params_data.substream = substream;
 795         params_data.dai = dai;
 796         params_data.hw_params = hw_params;
 797         params_data.link_id = link_id;
 798         params_data.alh_stream_id = alh_stream_id;
 799
 800         if (res->ops && res->ops->params_stream && res->dev)
 801                 return res->ops->params_stream(res->dev,
 802                                                &params_data);
 803         return -EIO;
 804 }
 805
 806 static int intel_free_stream(struct sdw_intel *sdw,
 807                              struct snd_pcm_substream *substream,
 808                              struct snd_soc_dai *dai,
 809                              int link_id)
 810 {
 811         struct sdw_intel_link_res *res = sdw->link_res;
 812         struct sdw_intel_stream_free_data free_data;
 813
 814         free_data.substream = substream;
 815         free_data.dai = dai;
 816         free_data.link_id = link_id;
 817
 818         if (res->ops && res->ops->free_stream && res->dev)
 819                 return res->ops->free_stream(res->dev,
 820                                              &free_data);
 821
 822         return 0;
 823 }
 824
 825 /*
 826  * bank switch routines
 827  */
 828
 829 static int intel_pre_bank_switch(struct sdw_bus *bus)
 830 {
 831         struct sdw_cdns *cdns = bus_to_cdns(bus);
 832         struct sdw_intel *sdw = cdns_to_intel(cdns);
 833
 834         /* Write to register only for multi-link */
 835         if (!bus->multi_link)
 836                 return 0;
 837
 838         intel_shim_sync_arm(sdw);
 839
 840         return 0;
 841 }
 842
 843 static int intel_post_bank_switch(struct sdw_bus *bus)
 844 {
 845         struct sdw_cdns *cdns = bus_to_cdns(bus);
 846         struct sdw_intel *sdw = cdns_to_intel(cdns);
 847         void __iomem *shim = sdw->link_res->shim;
 848         int sync_reg, ret;
 849
 850         /* Write to register only for multi-link */
 851         if (!bus->multi_link)
 852                 return 0;
 853
 854         mutex_lock(sdw->link_res->shim_lock);
 855
 856         /* Read SYNC register */
 857         sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
 858
 859         /*
 860          * post_bank_switch() ops is called from the bus in loop for
 861          * all the Masters in the steam with the expectation that
 862          * we trigger the bankswitch for the only first Master in the list
 863          * and do nothing for the other Masters
 864          *
 865          * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master.
 866          */
 867         if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK)) {
 868                 ret = 0;
 869                 goto unlock;
 870         }
 871
 872         ret = intel_shim_sync_go_unlocked(sdw);
 873 unlock:
 874         mutex_unlock(sdw->link_res->shim_lock);
 875
 876         if (ret < 0)
 877                 dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret);
 878
 879         return ret;
 880 }
 881
 882 /*
 883  * DAI routines
 884  */
 885
 886 static int intel_startup(struct snd_pcm_substream *substream,
 887                          struct snd_soc_dai *dai)
 888 {
 889         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
 890         int ret;
 891
 892         ret = pm_runtime_get_sync(cdns->dev);
 893         if (ret < 0 && ret != -EACCES) {
 894                 dev_err_ratelimited(cdns->dev,
 895                                     "pm_runtime_get_sync failed in %s, ret %d\n",
 896                                     __func__, ret);
 897                 pm_runtime_put_noidle(cdns->dev);
 898                 return ret;
 899         }
 900         return 0;
 901 }
 902
 903 static int intel_hw_params(struct snd_pcm_substream *substream,
 904                            struct snd_pcm_hw_params *params,
 905                            struct snd_soc_dai *dai)
 906 {
 907         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
 908         struct sdw_intel *sdw = cdns_to_intel(cdns);
 909         struct sdw_cdns_dma_data *dma;
 910         struct sdw_cdns_pdi *pdi;
 911         struct sdw_stream_config sconfig;
 912         struct sdw_port_config *pconfig;
 913         int ch, dir;
 914         int ret;
 915         bool pcm = true;
 916
 917         dma = snd_soc_dai_get_dma_data(dai, substream);
 918         if (!dma)
 919                 return -EIO;
 920
 921         ch = params_channels(params);
 922         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 923                 dir = SDW_DATA_DIR_RX;
 924         else
 925                 dir = SDW_DATA_DIR_TX;
 926
 927         if (dma->stream_type == SDW_STREAM_PDM)
 928                 pcm = false;
 929
 930         if (pcm)
 931                 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id);
 932         else
 933                 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pdm, ch, dir, dai->id);
 934
 935         if (!pdi) {
 936                 ret = -EINVAL;
 937                 goto error;
 938         }
 939
 940         /* do run-time configurations for SHIM, ALH and PDI/PORT */
 941         intel_pdi_shim_configure(sdw, pdi);
 942         intel_pdi_alh_configure(sdw, pdi);
 943         sdw_cdns_config_stream(cdns, ch, dir, pdi);
 944
 945         /* store pdi and hw_params, may be needed in prepare step */
 946         dma->suspended = false;
 947         dma->pdi = pdi;
 948         dma->hw_params = params;
 949
 950         /* Inform DSP about PDI stream number */
 951         ret = intel_params_stream(sdw, substream, dai, params,
 952                                   sdw->instance,
 953                                   pdi->intel_alh_id);
 954         if (ret)
 955                 goto error;
 956
 957         sconfig.direction = dir;
 958         sconfig.ch_count = ch;
 959         sconfig.frame_rate = params_rate(params);
 960         sconfig.type = dma->stream_type;
 961
 962         if (dma->stream_type == SDW_STREAM_PDM) {
 963                 sconfig.frame_rate *= 50;
 964                 sconfig.bps = 1;
 965         } else {
 966                 sconfig.bps = snd_pcm_format_width(params_format(params));
 967         }
 968
 969         /* Port configuration */
 970         pconfig = kcalloc(1, sizeof(*pconfig), GFP_KERNEL);
 971         if (!pconfig) {
 972                 ret =  -ENOMEM;
 973                 goto error;
 974         }
 975
 976         pconfig->num = pdi->num;
 977         pconfig->ch_mask = (1 << ch) - 1;
 978
 979         ret = sdw_stream_add_master(&cdns->bus, &sconfig,
 980                                     pconfig, 1, dma->stream);
 981         if (ret)
 982                 dev_err(cdns->dev, "add master to stream failed:%d\n", ret);
 983
 984         kfree(pconfig);
 985 error:
 986         return ret;
 987 }
 988
 989 static int intel_prepare(struct snd_pcm_substream *substream,
 990                          struct snd_soc_dai *dai)
 991 {
 992         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
 993         struct sdw_intel *sdw = cdns_to_intel(cdns);
 994         struct sdw_cdns_dma_data *dma;
 995         int ch, dir;
 996         int ret = 0;
 997
 998         dma = snd_soc_dai_get_dma_data(dai, substream);
 999         if (!dma) {
1000                 dev_err(dai->dev, "failed to get dma data in %s",
1001                         __func__);
1002                 return -EIO;
1003         }
1004
1005         if (dma->suspended) {
1006                 dma->suspended = false;
1007
1008                 /*
1009                  * .prepare() is called after system resume, where we
1010                  * need to reinitialize the SHIM/ALH/Cadence IP.
1011                  * .prepare() is also called to deal with underflows,
1012                  * but in those cases we cannot touch ALH/SHIM
1013                  * registers
1014                  */
1015
1016                 /* configure stream */
1017                 ch = params_channels(dma->hw_params);
1018                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1019                         dir = SDW_DATA_DIR_RX;
1020                 else
1021                         dir = SDW_DATA_DIR_TX;
1022
1023                 intel_pdi_shim_configure(sdw, dma->pdi);
1024                 intel_pdi_alh_configure(sdw, dma->pdi);
1025                 sdw_cdns_config_stream(cdns, ch, dir, dma->pdi);
1026
1027                 /* Inform DSP about PDI stream number */
1028                 ret = intel_params_stream(sdw, substream, dai,
1029                                           dma->hw_params,
1030                                           sdw->instance,
1031                                           dma->pdi->intel_alh_id);
1032         }
1033
1034         return ret;
1035 }
1036
1037 static int
1038 intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
1039 {
1040         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
1041         struct sdw_intel *sdw = cdns_to_intel(cdns);
1042         struct sdw_cdns_dma_data *dma;
1043         int ret;
1044
1045         dma = snd_soc_dai_get_dma_data(dai, substream);
1046         if (!dma)
1047                 return -EIO;
1048
1049         /*
1050          * The sdw stream state will transition to RELEASED when stream->
1051          * master_list is empty. So the stream state will transition to
1052          * DEPREPARED for the first cpu-dai and to RELEASED for the last
1053          * cpu-dai.
1054          */
1055         ret = sdw_stream_remove_master(&cdns->bus, dma->stream);
1056         if (ret < 0) {
1057                 dev_err(dai->dev, "remove master from stream %s failed: %d\n",
1058                         dma->stream->name, ret);
1059                 return ret;
1060         }
1061
1062         ret = intel_free_stream(sdw, substream, dai, sdw->instance);
1063         if (ret < 0) {
1064                 dev_err(dai->dev, "intel_free_stream: failed %d", ret);
1065                 return ret;
1066         }
1067
1068         dma->hw_params = NULL;
1069         dma->pdi = NULL;
1070
1071         return 0;
1072 }
1073
1074 static void intel_shutdown(struct snd_pcm_substream *substream,
1075                            struct snd_soc_dai *dai)
1076 {
1077         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
1078
1079         pm_runtime_mark_last_busy(cdns->dev);
1080         pm_runtime_put_autosuspend(cdns->dev);
1081 }
1082
1083 static int intel_component_dais_suspend(struct snd_soc_component *component)
1084 {
1085         struct sdw_cdns_dma_data *dma;
1086         struct snd_soc_dai *dai;
1087
1088         for_each_component_dais(component, dai) {
1089                 /*
1090                  * we don't have a .suspend dai_ops, and we don't have access
1091                  * to the substream, so let's mark both capture and playback
1092                  * DMA contexts as suspended
1093                  */
1094                 dma = dai->playback_dma_data;
1095                 if (dma)
1096                         dma->suspended = true;
1097
1098                 dma = dai->capture_dma_data;
1099                 if (dma)
1100                         dma->suspended = true;
1101         }
1102
1103         return 0;
1104 }
1105
1106 static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai,
1107                                     void *stream, int direction)
1108 {
1109         return cdns_set_sdw_stream(dai, stream, true, direction);
1110 }
1111
1112 static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai,
1113                                     void *stream, int direction)
1114 {
1115         return cdns_set_sdw_stream(dai, stream, false, direction);
1116 }
1117
1118 static void *intel_get_sdw_stream(struct snd_soc_dai *dai,
1119                                   int direction)
1120 {
1121         struct sdw_cdns_dma_data *dma;
1122
1123         if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1124                 dma = dai->playback_dma_data;
1125         else
1126                 dma = dai->capture_dma_data;
1127
1128         if (!dma)
1129                 return ERR_PTR(-EINVAL);
1130
1131         return dma->stream;
1132 }
1133
1134 static const struct snd_soc_dai_ops intel_pcm_dai_ops = {
1135         .startup = intel_startup,
1136         .hw_params = intel_hw_params,
1137         .prepare = intel_prepare,
1138         .hw_free = intel_hw_free,
1139         .shutdown = intel_shutdown,
1140         .set_sdw_stream = intel_pcm_set_sdw_stream,
1141         .get_sdw_stream = intel_get_sdw_stream,
1142 };
1143
1144 static const struct snd_soc_dai_ops intel_pdm_dai_ops = {
1145         .startup = intel_startup,
1146         .hw_params = intel_hw_params,
1147         .prepare = intel_prepare,
1148         .hw_free = intel_hw_free,
1149         .shutdown = intel_shutdown,
1150         .set_sdw_stream = intel_pdm_set_sdw_stream,
1151         .get_sdw_stream = intel_get_sdw_stream,
1152 };
1153
1154 static const struct snd_soc_component_driver dai_component = {
1155         .name           = "soundwire",
1156         .suspend        = intel_component_dais_suspend
1157 };
1158
1159 static int intel_create_dai(struct sdw_cdns *cdns,
1160                             struct snd_soc_dai_driver *dais,
1161                             enum intel_pdi_type type,
1162                             u32 num, u32 off, u32 max_ch, bool pcm)
1163 {
1164         int i;
1165
1166         if (num == 0)
1167                 return 0;
1168
1169          /* TODO: Read supported rates/formats from hardware */
1170         for (i = off; i < (off + num); i++) {
1171                 dais[i].name = devm_kasprintf(cdns->dev, GFP_KERNEL,
1172                                               "SDW%d Pin%d",
1173                                               cdns->instance, i);
1174                 if (!dais[i].name)
1175                         return -ENOMEM;
1176
1177                 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) {
1178                         dais[i].playback.channels_min = 1;
1179                         dais[i].playback.channels_max = max_ch;
1180                         dais[i].playback.rates = SNDRV_PCM_RATE_48000;
1181                         dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
1182                 }
1183
1184                 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) {
1185                         dais[i].capture.channels_min = 1;
1186                         dais[i].capture.channels_max = max_ch;
1187                         dais[i].capture.rates = SNDRV_PCM_RATE_48000;
1188                         dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
1189                 }
1190
1191                 if (pcm)
1192                         dais[i].ops = &intel_pcm_dai_ops;
1193                 else
1194                         dais[i].ops = &intel_pdm_dai_ops;
1195         }
1196
1197         return 0;
1198 }
1199
1200 static int intel_register_dai(struct sdw_intel *sdw)
1201 {
1202         struct sdw_cdns *cdns = &sdw->cdns;
1203         struct sdw_cdns_streams *stream;
1204         struct snd_soc_dai_driver *dais;
1205         int num_dai, ret, off = 0;
1206
1207         /* DAIs are created based on total number of PDIs supported */
1208         num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi;
1209
1210         dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
1211         if (!dais)
1212                 return -ENOMEM;
1213
1214         /* Create PCM DAIs */
1215         stream = &cdns->pcm;
1216
1217         ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in,
1218                                off, stream->num_ch_in, true);
1219         if (ret)
1220                 return ret;
1221
1222         off += cdns->pcm.num_in;
1223         ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,
1224                                off, stream->num_ch_out, true);
1225         if (ret)
1226                 return ret;
1227
1228         off += cdns->pcm.num_out;
1229         ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,
1230                                off, stream->num_ch_bd, true);
1231         if (ret)
1232                 return ret;
1233
1234         /* Create PDM DAIs */
1235         stream = &cdns->pdm;
1236         off += cdns->pcm.num_bd;
1237         ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pdm.num_in,
1238                                off, stream->num_ch_in, false);
1239         if (ret)
1240                 return ret;
1241
1242         off += cdns->pdm.num_in;
1243         ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pdm.num_out,
1244                                off, stream->num_ch_out, false);
1245         if (ret)
1246                 return ret;
1247
1248         off += cdns->pdm.num_out;
1249         ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pdm.num_bd,
1250                                off, stream->num_ch_bd, false);
1251         if (ret)
1252                 return ret;
1253
1254         return snd_soc_register_component(cdns->dev, &dai_component,
1255                                           dais, num_dai);
1256 }
1257
1258 static int sdw_master_read_intel_prop(struct sdw_bus *bus)
1259 {
1260         struct sdw_master_prop *prop = &bus->prop;
1261         struct fwnode_handle *link;
1262         char name[32];
1263         u32 quirk_mask;
1264
1265         /* Find master handle */
1266         snprintf(name, sizeof(name),
1267                  "mipi-sdw-link-%d-subproperties", bus->link_id);
1268
1269         link = device_get_named_child_node(bus->dev, name);
1270         if (!link) {
1271                 dev_err(bus->dev, "Master node %s not found\n", name);
1272                 return -EIO;
1273         }
1274
1275         fwnode_property_read_u32(link,
1276                                  "intel-sdw-ip-clock",
1277                                  &prop->mclk_freq);
1278
1279         /* the values reported by BIOS are the 2x clock, not the bus clock */
1280         prop->mclk_freq /= 2;
1281
1282         fwnode_property_read_u32(link,
1283                                  "intel-quirk-mask",
1284                                  &quirk_mask);
1285
1286         if (quirk_mask & SDW_INTEL_QUIRK_MASK_BUS_DISABLE)
1287                 prop->hw_disabled = true;
1288
1289         return 0;
1290 }
1291
1292 static int intel_prop_read(struct sdw_bus *bus)
1293 {
1294         /* Initialize with default handler to read all DisCo properties */
1295         sdw_master_read_prop(bus);
1296
1297         /* read Intel-specific properties */
1298         sdw_master_read_intel_prop(bus);
1299
1300         return 0;
1301 }
1302
1303 static struct sdw_master_ops sdw_intel_ops = {
1304         .read_prop = sdw_master_read_prop,
1305         .xfer_msg = cdns_xfer_msg,
1306         .xfer_msg_defer = cdns_xfer_msg_defer,
1307         .reset_page_addr = cdns_reset_page_addr,
1308         .set_bus_conf = cdns_bus_conf,
1309         .pre_bank_switch = intel_pre_bank_switch,
1310         .post_bank_switch = intel_post_bank_switch,
1311 };
1312
1313 static int intel_init(struct sdw_intel *sdw)
1314 {
1315         bool clock_stop;
1316
1317         /* Initialize shim and controller */
1318         intel_link_power_up(sdw);
1319
1320         clock_stop = sdw_cdns_is_clock_stop(&sdw->cdns);
1321
1322         intel_shim_init(sdw, clock_stop);
1323
1324         return 0;
1325 }
1326
1327 /*
1328  * probe and init
1329  */
1330 static int intel_master_probe(struct platform_device *pdev)
1331 {
1332         struct device *dev = &pdev->dev;
1333         struct sdw_intel *sdw;
1334         struct sdw_cdns *cdns;
1335         struct sdw_bus *bus;
1336         int ret;
1337
1338         sdw = devm_kzalloc(dev, sizeof(*sdw), GFP_KERNEL);
1339         if (!sdw)
1340                 return -ENOMEM;
1341
1342         cdns = &sdw->cdns;
1343         bus = &cdns->bus;
1344
1345         sdw->instance = pdev->id;
1346         sdw->link_res = dev_get_platdata(dev);
1347         cdns->dev = dev;
1348         cdns->registers = sdw->link_res->registers;
1349         cdns->instance = sdw->instance;
1350         cdns->msg_count = 0;
1351
1352         bus->link_id = pdev->id;
1353
1354         sdw_cdns_probe(cdns);
1355
1356         /* Set property read ops */
1357         sdw_intel_ops.read_prop = intel_prop_read;
1358         bus->ops = &sdw_intel_ops;
1359
1360         /* set driver data, accessed by snd_soc_dai_get_drvdata() */
1361         dev_set_drvdata(dev, cdns);
1362
1363         /* use generic bandwidth allocation algorithm */
1364         sdw->cdns.bus.compute_params = sdw_compute_params;
1365
1366         ret = sdw_bus_master_add(bus, dev, dev->fwnode);
1367         if (ret) {
1368                 dev_err(dev, "sdw_bus_master_add fail: %d\n", ret);
1369                 return ret;
1370         }
1371
1372         if (bus->prop.hw_disabled)
1373                 dev_info(dev,
1374                          "SoundWire master %d is disabled, will be ignored\n",
1375                          bus->link_id);
1376         /*
1377          * Ignore BIOS err_threshold, it's a really bad idea when dealing
1378          * with multiple hardware synchronized links
1379          */
1380         bus->prop.err_threshold = 0;
1381
1382         return 0;
1383 }
1384
1385 int intel_master_startup(struct platform_device *pdev)
1386 {
1387         struct sdw_cdns_stream_config config;
1388         struct device *dev = &pdev->dev;
1389         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1390         struct sdw_intel *sdw = cdns_to_intel(cdns);
1391         struct sdw_bus *bus = &cdns->bus;
1392         int link_flags;
1393         bool multi_link;
1394         u32 clock_stop_quirks;
1395         int ret;
1396
1397         if (bus->prop.hw_disabled) {
1398                 dev_info(dev,
1399                          "SoundWire master %d is disabled, ignoring\n",
1400                          sdw->instance);
1401                 return 0;
1402         }
1403
1404         link_flags = md_flags >> (bus->link_id * 8);
1405         multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK);
1406         if (!multi_link) {
1407                 dev_dbg(dev, "Multi-link is disabled\n");
1408                 bus->multi_link = false;
1409         } else {
1410                 /*
1411                  * hardware-based synchronization is required regardless
1412                  * of the number of segments used by a stream: SSP-based
1413                  * synchronization is gated by gsync when the multi-master
1414                  * mode is set.
1415                  */
1416                 bus->multi_link = true;
1417                 bus->hw_sync_min_links = 1;
1418         }
1419
1420         /* Initialize shim, controller */
1421         ret = intel_init(sdw);
1422         if (ret)
1423                 goto err_init;
1424
1425         /* Read the PDI config and initialize cadence PDI */
1426         intel_pdi_init(sdw, &config);
1427         ret = sdw_cdns_pdi_init(cdns, config);
1428         if (ret)
1429                 goto err_init;
1430
1431         intel_pdi_ch_update(sdw);
1432
1433         ret = sdw_cdns_enable_interrupt(cdns, true);
1434         if (ret < 0) {
1435                 dev_err(dev, "cannot enable interrupts\n");
1436                 goto err_init;
1437         }
1438
1439         /*
1440          * follow recommended programming flows to avoid timeouts when
1441          * gsync is enabled
1442          */
1443         if (multi_link)
1444                 intel_shim_sync_arm(sdw);
1445
1446         ret = sdw_cdns_init(cdns);
1447         if (ret < 0) {
1448                 dev_err(dev, "unable to initialize Cadence IP\n");
1449                 goto err_interrupt;
1450         }
1451
1452         ret = sdw_cdns_exit_reset(cdns);
1453         if (ret < 0) {
1454                 dev_err(dev, "unable to exit bus reset sequence\n");
1455                 goto err_interrupt;
1456         }
1457
1458         if (multi_link) {
1459                 ret = intel_shim_sync_go(sdw);
1460                 if (ret < 0) {
1461                         dev_err(dev, "sync go failed: %d\n", ret);
1462                         goto err_interrupt;
1463                 }
1464         }
1465
1466         /* Register DAIs */
1467         ret = intel_register_dai(sdw);
1468         if (ret) {
1469                 dev_err(dev, "DAI registration failed: %d\n", ret);
1470                 snd_soc_unregister_component(dev);
1471                 goto err_interrupt;
1472         }
1473
1474         intel_debugfs_init(sdw);
1475
1476         /* Enable runtime PM */
1477         if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME)) {
1478                 pm_runtime_set_autosuspend_delay(dev,
1479                                                  INTEL_MASTER_SUSPEND_DELAY_MS);
1480                 pm_runtime_use_autosuspend(dev);
1481                 pm_runtime_mark_last_busy(dev);
1482
1483                 pm_runtime_set_active(dev);
1484                 pm_runtime_enable(dev);
1485         }
1486
1487         clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1488         if (clock_stop_quirks & SDW_INTEL_CLK_STOP_NOT_ALLOWED) {
1489                 /*
1490                  * To keep the clock running we need to prevent
1491                  * pm_runtime suspend from happening by increasing the
1492                  * reference count.
1493                  * This quirk is specified by the parent PCI device in
1494                  * case of specific latency requirements. It will have
1495                  * no effect if pm_runtime is disabled by the user via
1496                  * a module parameter for testing purposes.
1497                  */
1498                 pm_runtime_get_noresume(dev);
1499         }
1500
1501         /*
1502          * The runtime PM status of Slave devices is "Unsupported"
1503          * until they report as ATTACHED. If they don't, e.g. because
1504          * there are no Slave devices populated or if the power-on is
1505          * delayed or dependent on a power switch, the Master will
1506          * remain active and prevent its parent from suspending.
1507          *
1508          * Conditionally force the pm_runtime core to re-evaluate the
1509          * Master status in the absence of any Slave activity. A quirk
1510          * is provided to e.g. deal with Slaves that may be powered on
1511          * with a delay. A more complete solution would require the
1512          * definition of Master properties.
1513          */
1514         if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE))
1515                 pm_runtime_idle(dev);
1516
1517         return 0;
1518
1519 err_interrupt:
1520         sdw_cdns_enable_interrupt(cdns, false);
1521 err_init:
1522         return ret;
1523 }
1524
1525 static int intel_master_remove(struct platform_device *pdev)
1526 {
1527         struct device *dev = &pdev->dev;
1528         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1529         struct sdw_intel *sdw = cdns_to_intel(cdns);
1530         struct sdw_bus *bus = &cdns->bus;
1531
1532         /*
1533          * Since pm_runtime is already disabled, we don't decrease
1534          * the refcount when the clock_stop_quirk is
1535          * SDW_INTEL_CLK_STOP_NOT_ALLOWED
1536          */
1537         if (!bus->prop.hw_disabled) {
1538                 intel_debugfs_exit(sdw);
1539                 sdw_cdns_enable_interrupt(cdns, false);
1540                 snd_soc_unregister_component(dev);
1541         }
1542         sdw_bus_master_delete(bus);
1543
1544         return 0;
1545 }
1546
1547 int intel_master_process_wakeen_event(struct platform_device *pdev)
1548 {
1549         struct device *dev = &pdev->dev;
1550         struct sdw_intel *sdw;
1551         struct sdw_bus *bus;
1552         void __iomem *shim;
1553         u16 wake_sts;
1554
1555         sdw = platform_get_drvdata(pdev);
1556         bus = &sdw->cdns.bus;
1557
1558         if (bus->prop.hw_disabled) {
1559                 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n", bus->link_id);
1560                 return 0;
1561         }
1562
1563         shim = sdw->link_res->shim;
1564         wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);
1565
1566         if (!(wake_sts & BIT(sdw->instance)))
1567                 return 0;
1568
1569         /* disable WAKEEN interrupt ASAP to prevent interrupt flood */
1570         intel_shim_wake(sdw, false);
1571
1572         /*
1573          * resume the Master, which will generate a bus reset and result in
1574          * Slaves re-attaching and be re-enumerated. The SoundWire physical
1575          * device which generated the wake will trigger an interrupt, which
1576          * will in turn cause the corresponding Linux Slave device to be
1577          * resumed and the Slave codec driver to check the status.
1578          */
1579         pm_request_resume(dev);
1580
1581         return 0;
1582 }
1583
1584 /*
1585  * PM calls
1586  */
1587
1588 #ifdef CONFIG_PM
1589
1590 static int __maybe_unused intel_suspend(struct device *dev)
1591 {
1592         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1593         struct sdw_intel *sdw = cdns_to_intel(cdns);
1594         struct sdw_bus *bus = &cdns->bus;
1595         u32 clock_stop_quirks;
1596         int ret;
1597
1598         if (bus->prop.hw_disabled) {
1599                 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n",
1600                         bus->link_id);
1601                 return 0;
1602         }
1603
1604         if (pm_runtime_suspended(dev)) {
1605                 dev_dbg(dev, "%s: pm_runtime status: suspended\n", __func__);
1606
1607                 clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1608
1609                 if ((clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET ||
1610                      !clock_stop_quirks) &&
1611                     !pm_runtime_suspended(dev->parent)) {
1612
1613                         /*
1614                          * if we've enabled clock stop, and the parent
1615                          * is still active, disable shim wake. The
1616                          * SHIM registers are not accessible if the
1617                          * parent is already pm_runtime suspended so
1618                          * it's too late to change that configuration
1619                          */
1620
1621                         intel_shim_wake(sdw, false);
1622                 }
1623
1624                 return 0;
1625         }
1626
1627         ret = sdw_cdns_enable_interrupt(cdns, false);
1628         if (ret < 0) {
1629                 dev_err(dev, "cannot disable interrupts on suspend\n");
1630                 return ret;
1631         }
1632
1633         ret = intel_link_power_down(sdw);
1634         if (ret) {
1635                 dev_err(dev, "Link power down failed: %d", ret);
1636                 return ret;
1637         }
1638
1639         intel_shim_wake(sdw, false);
1640
1641         return 0;
1642 }
1643
1644 static int intel_suspend_runtime(struct device *dev)
1645 {
1646         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1647         struct sdw_intel *sdw = cdns_to_intel(cdns);
1648         struct sdw_bus *bus = &cdns->bus;
1649         u32 clock_stop_quirks;
1650         int ret;
1651
1652         if (bus->prop.hw_disabled) {
1653                 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n",
1654                         bus->link_id);
1655                 return 0;
1656         }
1657
1658         clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1659
1660         if (clock_stop_quirks & SDW_INTEL_CLK_STOP_TEARDOWN) {
1661
1662                 ret = sdw_cdns_enable_interrupt(cdns, false);
1663                 if (ret < 0) {
1664                         dev_err(dev, "cannot disable interrupts on suspend\n");
1665                         return ret;
1666                 }
1667
1668                 ret = intel_link_power_down(sdw);
1669                 if (ret) {
1670                         dev_err(dev, "Link power down failed: %d", ret);
1671                         return ret;
1672                 }
1673
1674                 intel_shim_wake(sdw, false);
1675
1676         } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET ||
1677                    !clock_stop_quirks) {
1678                 ret = sdw_cdns_clock_stop(cdns, true);
1679                 if (ret < 0) {
1680                         dev_err(dev, "cannot enable clock stop on suspend\n");
1681                         return ret;
1682                 }
1683
1684                 ret = sdw_cdns_enable_interrupt(cdns, false);
1685                 if (ret < 0) {
1686                         dev_err(dev, "cannot disable interrupts on suspend\n");
1687                         return ret;
1688                 }
1689
1690                 ret = intel_link_power_down(sdw);
1691                 if (ret) {
1692                         dev_err(dev, "Link power down failed: %d", ret);
1693                         return ret;
1694                 }
1695
1696                 intel_shim_wake(sdw, true);
1697         } else {
1698                 dev_err(dev, "%s clock_stop_quirks %x unsupported\n",
1699                         __func__, clock_stop_quirks);
1700                 ret = -EINVAL;
1701         }
1702
1703         return ret;
1704 }
1705
1706 static int __maybe_unused intel_resume(struct device *dev)
1707 {
1708         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1709         struct sdw_intel *sdw = cdns_to_intel(cdns);
1710         struct sdw_bus *bus = &cdns->bus;
1711         int link_flags;
1712         bool multi_link;
1713         int ret;
1714
1715         if (bus->prop.hw_disabled) {
1716                 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n",
1717                         bus->link_id);
1718                 return 0;
1719         }
1720
1721         link_flags = md_flags >> (bus->link_id * 8);
1722         multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK);
1723
1724         if (pm_runtime_suspended(dev)) {
1725                 dev_dbg(dev, "%s: pm_runtime status was suspended, forcing active\n", __func__);
1726
1727                 /* follow required sequence from runtime_pm.rst */
1728                 pm_runtime_disable(dev);
1729                 pm_runtime_set_active(dev);
1730                 pm_runtime_mark_last_busy(dev);
1731                 pm_runtime_enable(dev);
1732
1733                 link_flags = md_flags >> (bus->link_id * 8);
1734
1735                 if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE))
1736                         pm_runtime_idle(dev);
1737         }
1738
1739         ret = intel_init(sdw);
1740         if (ret) {
1741                 dev_err(dev, "%s failed: %d", __func__, ret);
1742                 return ret;
1743         }
1744
1745         /*
1746          * make sure all Slaves are tagged as UNATTACHED and provide
1747          * reason for reinitialization
1748          */
1749         sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET);
1750
1751         ret = sdw_cdns_enable_interrupt(cdns, true);
1752         if (ret < 0) {
1753                 dev_err(dev, "cannot enable interrupts during resume\n");
1754                 return ret;
1755         }
1756
1757         /*
1758          * follow recommended programming flows to avoid timeouts when
1759          * gsync is enabled
1760          */
1761         if (multi_link)
1762                 intel_shim_sync_arm(sdw);
1763
1764         ret = sdw_cdns_init(&sdw->cdns);
1765         if (ret < 0) {
1766                 dev_err(dev, "unable to initialize Cadence IP during resume\n");
1767                 return ret;
1768         }
1769
1770         ret = sdw_cdns_exit_reset(cdns);
1771         if (ret < 0) {
1772                 dev_err(dev, "unable to exit bus reset sequence during resume\n");
1773                 return ret;
1774         }
1775
1776         if (multi_link) {
1777                 ret = intel_shim_sync_go(sdw);
1778                 if (ret < 0) {
1779                         dev_err(dev, "sync go failed during resume\n");
1780                         return ret;
1781                 }
1782         }
1783
1784         /*
1785          * after system resume, the pm_runtime suspend() may kick in
1786          * during the enumeration, before any children device force the
1787          * master device to remain active.  Using pm_runtime_get()
1788          * routines is not really possible, since it'd prevent the
1789          * master from suspending.
1790          * A reasonable compromise is to update the pm_runtime
1791          * counters and delay the pm_runtime suspend by several
1792          * seconds, by when all enumeration should be complete.
1793          */
1794         pm_runtime_mark_last_busy(dev);
1795
1796         return ret;
1797 }
1798
1799 static int intel_resume_runtime(struct device *dev)
1800 {
1801         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1802         struct sdw_intel *sdw = cdns_to_intel(cdns);
1803         struct sdw_bus *bus = &cdns->bus;
1804         u32 clock_stop_quirks;
1805         bool clock_stop0;
1806         int link_flags;
1807         bool multi_link;
1808         int status;
1809         int ret;
1810
1811         if (bus->prop.hw_disabled) {
1812                 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n",
1813                         bus->link_id);
1814                 return 0;
1815         }
1816
1817         link_flags = md_flags >> (bus->link_id * 8);
1818         multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK);
1819
1820         clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1821
1822         if (clock_stop_quirks & SDW_INTEL_CLK_STOP_TEARDOWN) {
1823                 ret = intel_init(sdw);
1824                 if (ret) {
1825                         dev_err(dev, "%s failed: %d", __func__, ret);
1826                         return ret;
1827                 }
1828
1829                 /*
1830                  * make sure all Slaves are tagged as UNATTACHED and provide
1831                  * reason for reinitialization
1832                  */
1833                 sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET);
1834
1835                 ret = sdw_cdns_enable_interrupt(cdns, true);
1836                 if (ret < 0) {
1837                         dev_err(dev, "cannot enable interrupts during resume\n");
1838                         return ret;
1839                 }
1840
1841                 /*
1842                  * follow recommended programming flows to avoid
1843                  * timeouts when gsync is enabled
1844                  */
1845                 if (multi_link)
1846                         intel_shim_sync_arm(sdw);
1847
1848                 ret = sdw_cdns_init(&sdw->cdns);
1849                 if (ret < 0) {
1850                         dev_err(dev, "unable to initialize Cadence IP during resume\n");
1851                         return ret;
1852                 }
1853
1854                 ret = sdw_cdns_exit_reset(cdns);
1855                 if (ret < 0) {
1856                         dev_err(dev, "unable to exit bus reset sequence during resume\n");
1857                         return ret;
1858                 }
1859
1860                 if (multi_link) {
1861                         ret = intel_shim_sync_go(sdw);
1862                         if (ret < 0) {
1863                                 dev_err(dev, "sync go failed during resume\n");
1864                                 return ret;
1865                         }
1866                 }
1867         } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET) {
1868                 ret = intel_init(sdw);
1869                 if (ret) {
1870                         dev_err(dev, "%s failed: %d", __func__, ret);
1871                         return ret;
1872                 }
1873
1874                 /*
1875                  * An exception condition occurs for the CLK_STOP_BUS_RESET
1876                  * case if one or more masters remain active. In this condition,
1877                  * all the masters are powered on for they are in the same power
1878                  * domain. Master can preserve its context for clock stop0, so
1879                  * there is no need to clear slave status and reset bus.
1880                  */
1881                 clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns);
1882
1883                 if (!clock_stop0) {
1884
1885                         /*
1886                          * make sure all Slaves are tagged as UNATTACHED and
1887                          * provide reason for reinitialization
1888                          */
1889
1890                         status = SDW_UNATTACH_REQUEST_MASTER_RESET;
1891                         sdw_clear_slave_status(bus, status);
1892
1893                         ret = sdw_cdns_enable_interrupt(cdns, true);
1894                         if (ret < 0) {
1895                                 dev_err(dev, "cannot enable interrupts during resume\n");
1896                                 return ret;
1897                         }
1898
1899                         /*
1900                          * follow recommended programming flows to avoid
1901                          * timeouts when gsync is enabled
1902                          */
1903                         if (multi_link)
1904                                 intel_shim_sync_arm(sdw);
1905
1906                         /*
1907                          * Re-initialize the IP since it was powered-off
1908                          */
1909                         sdw_cdns_init(&sdw->cdns);
1910
1911                 } else {
1912                         ret = sdw_cdns_enable_interrupt(cdns, true);
1913                         if (ret < 0) {
1914                                 dev_err(dev, "cannot enable interrupts during resume\n");
1915                                 return ret;
1916                         }
1917                 }
1918
1919                 ret = sdw_cdns_clock_restart(cdns, !clock_stop0);
1920                 if (ret < 0) {
1921                         dev_err(dev, "unable to restart clock during resume\n");
1922                         return ret;
1923                 }
1924
1925                 if (!clock_stop0) {
1926                         ret = sdw_cdns_exit_reset(cdns);
1927                         if (ret < 0) {
1928                                 dev_err(dev, "unable to exit bus reset sequence during resume\n");
1929                                 return ret;
1930                         }
1931
1932                         if (multi_link) {
1933                                 ret = intel_shim_sync_go(sdw);
1934                                 if (ret < 0) {
1935                                         dev_err(sdw->cdns.dev, "sync go failed during resume\n");
1936                                         return ret;
1937                                 }
1938                         }
1939                 }
1940         } else if (!clock_stop_quirks) {
1941
1942                 clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns);
1943                 if (!clock_stop0)
1944                         dev_err(dev, "%s invalid configuration, clock was not stopped", __func__);
1945
1946                 ret = intel_init(sdw);
1947                 if (ret) {
1948                         dev_err(dev, "%s failed: %d", __func__, ret);
1949                         return ret;
1950                 }
1951
1952                 ret = sdw_cdns_enable_interrupt(cdns, true);
1953                 if (ret < 0) {
1954                         dev_err(dev, "cannot enable interrupts during resume\n");
1955                         return ret;
1956                 }
1957
1958                 ret = sdw_cdns_clock_restart(cdns, false);
1959                 if (ret < 0) {
1960                         dev_err(dev, "unable to resume master during resume\n");
1961                         return ret;
1962                 }
1963         } else {
1964                 dev_err(dev, "%s clock_stop_quirks %x unsupported\n",
1965                         __func__, clock_stop_quirks);
1966                 ret = -EINVAL;
1967         }
1968
1969         return ret;
1970 }
1971
1972 #endif
1973
1974 static const struct dev_pm_ops intel_pm = {
1975         SET_SYSTEM_SLEEP_PM_OPS(intel_suspend, intel_resume)
1976         SET_RUNTIME_PM_OPS(intel_suspend_runtime, intel_resume_runtime, NULL)
1977 };
1978
1979 static struct platform_driver sdw_intel_drv = {
1980         .probe = intel_master_probe,
1981         .remove = intel_master_remove,
1982         .driver = {
1983                 .name = "intel-sdw",
1984                 .pm = &intel_pm,
1985         }
1986 };
1987
1988 module_platform_driver(sdw_intel_drv);
1989
1990 MODULE_LICENSE("Dual BSD/GPL");
1991 MODULE_ALIAS("platform:intel-sdw");
1992 MODULE_DESCRIPTION("Intel Soundwire Master Driver");