drivers/soundwire/intel.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
   2 // Copyright(c) 2015-17 Intel Corporation.
   3
   4 /*
   5  * Soundwire Intel Master Driver
   6  */
   7
   8 #include <linux/acpi.h>
   9 #include <linux/debugfs.h>
  10 #include <linux/delay.h>
  11 #include <linux/module.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/auxiliary_bus.h>
  15 #include <sound/pcm_params.h>
  16 #include <linux/pm_runtime.h>
  17 #include <sound/soc.h>
  18 #include <linux/soundwire/sdw_registers.h>
  19 #include <linux/soundwire/sdw.h>
  20 #include <linux/soundwire/sdw_intel.h>
  21 #include "cadence_master.h"
  22 #include "bus.h"
  23 #include "intel.h"
  24
  25 #define INTEL_MASTER_SUSPEND_DELAY_MS   3000
  26
  27 /*
  28  * debug/config flags for the Intel SoundWire Master.
  29  *
  30  * Since we may have multiple masters active, we can have up to 8
  31  * flags reused in each byte, with master0 using the ls-byte, etc.
  32  */
  33
  34 #define SDW_INTEL_MASTER_DISABLE_PM_RUNTIME             BIT(0)
  35 #define SDW_INTEL_MASTER_DISABLE_CLOCK_STOP             BIT(1)
  36 #define SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE        BIT(2)
  37 #define SDW_INTEL_MASTER_DISABLE_MULTI_LINK             BIT(3)
  38
  39 static int md_flags;
  40 module_param_named(sdw_md_flags, md_flags, int, 0444);
  41 MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags (0x0 all off)");
  42
  43 enum intel_pdi_type {
  44         INTEL_PDI_IN = 0,
  45         INTEL_PDI_OUT = 1,
  46         INTEL_PDI_BD = 2,
  47 };
  48
  49 #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns)
  50
  51 /*
  52  * Read, write helpers for HW registers
  53  */
  54 static inline int intel_readl(void __iomem *base, int offset)
  55 {
  56         return readl(base + offset);
  57 }
  58
  59 static inline void intel_writel(void __iomem *base, int offset, int value)
  60 {
  61         writel(value, base + offset);
  62 }
  63
  64 static inline u16 intel_readw(void __iomem *base, int offset)
  65 {
  66         return readw(base + offset);
  67 }
  68
  69 static inline void intel_writew(void __iomem *base, int offset, u16 value)
  70 {
  71         writew(value, base + offset);
  72 }
  73
  74 static int intel_wait_bit(void __iomem *base, int offset, u32 mask, u32 target)
  75 {
  76         int timeout = 10;
  77         u32 reg_read;
  78
  79         do {
  80                 reg_read = readl(base + offset);
  81                 if ((reg_read & mask) == target)
  82                         return 0;
  83
  84                 timeout--;
  85                 usleep_range(50, 100);
  86         } while (timeout != 0);
  87
  88         return -EAGAIN;
  89 }
  90
  91 static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask)
  92 {
  93         writel(value, base + offset);
  94         return intel_wait_bit(base, offset, mask, 0);
  95 }
  96
  97 static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask)
  98 {
  99         writel(value, base + offset);
 100         return intel_wait_bit(base, offset, mask, mask);
 101 }
 102
 103 /*
 104  * debugfs
 105  */
 106 #ifdef CONFIG_DEBUG_FS
 107
 108 #define RD_BUF (2 * PAGE_SIZE)
 109
 110 static ssize_t intel_sprintf(void __iomem *mem, bool l,
 111                              char *buf, size_t pos, unsigned int reg)
 112 {
 113         int value;
 114
 115         if (l)
 116                 value = intel_readl(mem, reg);
 117         else
 118                 value = intel_readw(mem, reg);
 119
 120         return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value);
 121 }
 122
 123 static int intel_reg_show(struct seq_file *s_file, void *data)
 124 {
 125         struct sdw_intel *sdw = s_file->private;
 126         void __iomem *s = sdw->link_res->shim;
 127         void __iomem *a = sdw->link_res->alh;
 128         char *buf;
 129         ssize_t ret;
 130         int i, j;
 131         unsigned int links, reg;
 132
 133         buf = kzalloc(RD_BUF, GFP_KERNEL);
 134         if (!buf)
 135                 return -ENOMEM;
 136
 137         links = intel_readl(s, SDW_SHIM_LCAP) & GENMASK(2, 0);
 138
 139         ret = scnprintf(buf, RD_BUF, "Register  Value\n");
 140         ret += scnprintf(buf + ret, RD_BUF - ret, "\nShim\n");
 141
 142         for (i = 0; i < links; i++) {
 143                 reg = SDW_SHIM_LCAP + i * 4;
 144                 ret += intel_sprintf(s, true, buf, ret, reg);
 145         }
 146
 147         for (i = 0; i < links; i++) {
 148                 ret += scnprintf(buf + ret, RD_BUF - ret, "\nLink%d\n", i);
 149                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLSCAP(i));
 150                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS0CM(i));
 151                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS1CM(i));
 152                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS2CM(i));
 153                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS3CM(i));
 154                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PCMSCAP(i));
 155
 156                 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PCMSyCH registers\n");
 157
 158                 /*
 159                  * the value 10 is the number of PDIs. We will need a
 160                  * cleanup to remove hard-coded Intel configurations
 161                  * from cadence_master.c
 162                  */
 163                 for (j = 0; j < 10; j++) {
 164                         ret += intel_sprintf(s, false, buf, ret,
 165                                         SDW_SHIM_PCMSYCHM(i, j));
 166                         ret += intel_sprintf(s, false, buf, ret,
 167                                         SDW_SHIM_PCMSYCHC(i, j));
 168                 }
 169                 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PDMSCAP, IOCTL, CTMCTL\n");
 170
 171                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PDMSCAP(i));
 172                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_IOCTL(i));
 173                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTMCTL(i));
 174         }
 175
 176         ret += scnprintf(buf + ret, RD_BUF - ret, "\nWake registers\n");
 177         ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKEEN);
 178         ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKESTS);
 179
 180         ret += scnprintf(buf + ret, RD_BUF - ret, "\nALH STRMzCFG\n");
 181         for (i = 0; i < SDW_ALH_NUM_STREAMS; i++)
 182                 ret += intel_sprintf(a, true, buf, ret, SDW_ALH_STRMZCFG(i));
 183
 184         seq_printf(s_file, "%s", buf);
 185         kfree(buf);
 186
 187         return 0;
 188 }
 189 DEFINE_SHOW_ATTRIBUTE(intel_reg);
 190
 191 static int intel_set_m_datamode(void *data, u64 value)
 192 {
 193         struct sdw_intel *sdw = data;
 194         struct sdw_bus *bus = &sdw->cdns.bus;
 195
 196         if (value > SDW_PORT_DATA_MODE_STATIC_1)
 197                 return -EINVAL;
 198
 199         /* Userspace changed the hardware state behind the kernel's back */
 200         add_taint(TAINT_USER, LOCKDEP_STILL_OK);
 201
 202         bus->params.m_data_mode = value;
 203
 204         return 0;
 205 }
 206 DEFINE_DEBUGFS_ATTRIBUTE(intel_set_m_datamode_fops, NULL,
 207                          intel_set_m_datamode, "%llu\n");
 208
 209 static int intel_set_s_datamode(void *data, u64 value)
 210 {
 211         struct sdw_intel *sdw = data;
 212         struct sdw_bus *bus = &sdw->cdns.bus;
 213
 214         if (value > SDW_PORT_DATA_MODE_STATIC_1)
 215                 return -EINVAL;
 216
 217         /* Userspace changed the hardware state behind the kernel's back */
 218         add_taint(TAINT_USER, LOCKDEP_STILL_OK);
 219
 220         bus->params.s_data_mode = value;
 221
 222         return 0;
 223 }
 224 DEFINE_DEBUGFS_ATTRIBUTE(intel_set_s_datamode_fops, NULL,
 225                          intel_set_s_datamode, "%llu\n");
 226
 227 static void intel_debugfs_init(struct sdw_intel *sdw)
 228 {
 229         struct dentry *root = sdw->cdns.bus.debugfs;
 230
 231         if (!root)
 232                 return;
 233
 234         sdw->debugfs = debugfs_create_dir("intel-sdw", root);
 235
 236         debugfs_create_file("intel-registers", 0400, sdw->debugfs, sdw,
 237                             &intel_reg_fops);
 238
 239         debugfs_create_file("intel-m-datamode", 0200, sdw->debugfs, sdw,
 240                             &intel_set_m_datamode_fops);
 241
 242         debugfs_create_file("intel-s-datamode", 0200, sdw->debugfs, sdw,
 243                             &intel_set_s_datamode_fops);
 244
 245         sdw_cdns_debugfs_init(&sdw->cdns, sdw->debugfs);
 246 }
 247
 248 static void intel_debugfs_exit(struct sdw_intel *sdw)
 249 {
 250         debugfs_remove_recursive(sdw->debugfs);
 251 }
 252 #else
 253 static void intel_debugfs_init(struct sdw_intel *sdw) {}
 254 static void intel_debugfs_exit(struct sdw_intel *sdw) {}
 255 #endif /* CONFIG_DEBUG_FS */
 256
 257 /*
 258  * shim ops
 259  */
 260
 261 static int intel_link_power_up(struct sdw_intel *sdw)
 262 {
 263         unsigned int link_id = sdw->instance;
 264         void __iomem *shim = sdw->link_res->shim;
 265         u32 *shim_mask = sdw->link_res->shim_mask;
 266         struct sdw_bus *bus = &sdw->cdns.bus;
 267         struct sdw_master_prop *prop = &bus->prop;
 268         u32 spa_mask, cpa_mask;
 269         u32 link_control;
 270         int ret = 0;
 271         u32 syncprd;
 272         u32 sync_reg;
 273
 274         mutex_lock(sdw->link_res->shim_lock);
 275
 276         /*
 277          * The hardware relies on an internal counter, typically 4kHz,
 278          * to generate the SoundWire SSP - which defines a 'safe'
 279          * synchronization point between commands and audio transport
 280          * and allows for multi link synchronization. The SYNCPRD value
 281          * is only dependent on the oscillator clock provided to
 282          * the IP, so adjust based on _DSD properties reported in DSDT
 283          * tables. The values reported are based on either 24MHz
 284          * (CNL/CML) or 38.4 MHz (ICL/TGL+).
 285          */
 286         if (prop->mclk_freq % 6000000)
 287                 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;
 288         else
 289                 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24;
 290
 291         if (!*shim_mask) {
 292                 dev_dbg(sdw->cdns.dev, "%s: powering up all links\n", __func__);
 293
 294                 /* we first need to program the SyncPRD/CPU registers */
 295                 dev_dbg(sdw->cdns.dev,
 296                         "%s: first link up, programming SYNCPRD\n", __func__);
 297
 298                 /* set SyncPRD period */
 299                 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
 300                 u32p_replace_bits(&sync_reg, syncprd, SDW_SHIM_SYNC_SYNCPRD);
 301
 302                 /* Set SyncCPU bit */
 303                 sync_reg |= SDW_SHIM_SYNC_SYNCCPU;
 304                 intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
 305
 306                 /* Link power up sequence */
 307                 link_control = intel_readl(shim, SDW_SHIM_LCTL);
 308
 309                 /* only power-up enabled links */
 310                 spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, sdw->link_res->link_mask);
 311                 cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask);
 312
 313                 link_control |=  spa_mask;
 314
 315                 ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
 316                 if (ret < 0) {
 317                         dev_err(sdw->cdns.dev, "Failed to power up link: %d\n", ret);
 318                         goto out;
 319                 }
 320
 321                 /* SyncCPU will change once link is active */
 322                 ret = intel_wait_bit(shim, SDW_SHIM_SYNC,
 323                                      SDW_SHIM_SYNC_SYNCCPU, 0);
 324                 if (ret < 0) {
 325                         dev_err(sdw->cdns.dev,
 326                                 "Failed to set SHIM_SYNC: %d\n", ret);
 327                         goto out;
 328                 }
 329         }
 330
 331         *shim_mask |= BIT(link_id);
 332
 333         sdw->cdns.link_up = true;
 334 out:
 335         mutex_unlock(sdw->link_res->shim_lock);
 336
 337         return ret;
 338 }
 339
 340 /* this needs to be called with shim_lock */
 341 static void intel_shim_glue_to_master_ip(struct sdw_intel *sdw)
 342 {
 343         void __iomem *shim = sdw->link_res->shim;
 344         unsigned int link_id = sdw->instance;
 345         u16 ioctl;
 346
 347         /* Switch to MIP from Glue logic */
 348         ioctl = intel_readw(shim,  SDW_SHIM_IOCTL(link_id));
 349
 350         ioctl &= ~(SDW_SHIM_IOCTL_DOE);
 351         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 352         usleep_range(10, 15);
 353
 354         ioctl &= ~(SDW_SHIM_IOCTL_DO);
 355         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 356         usleep_range(10, 15);
 357
 358         ioctl |= (SDW_SHIM_IOCTL_MIF);
 359         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 360         usleep_range(10, 15);
 361
 362         ioctl &= ~(SDW_SHIM_IOCTL_BKE);
 363         ioctl &= ~(SDW_SHIM_IOCTL_COE);
 364         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 365         usleep_range(10, 15);
 366
 367         /* at this point Master IP has full control of the I/Os */
 368 }
 369
 370 /* this needs to be called with shim_lock */
 371 static void intel_shim_master_ip_to_glue(struct sdw_intel *sdw)
 372 {
 373         unsigned int link_id = sdw->instance;
 374         void __iomem *shim = sdw->link_res->shim;
 375         u16 ioctl;
 376
 377         /* Glue logic */
 378         ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
 379         ioctl |= SDW_SHIM_IOCTL_BKE;
 380         ioctl |= SDW_SHIM_IOCTL_COE;
 381         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 382         usleep_range(10, 15);
 383
 384         ioctl &= ~(SDW_SHIM_IOCTL_MIF);
 385         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 386         usleep_range(10, 15);
 387
 388         /* at this point Integration Glue has full control of the I/Os */
 389 }
 390
 391 static int intel_shim_init(struct sdw_intel *sdw, bool clock_stop)
 392 {
 393         void __iomem *shim = sdw->link_res->shim;
 394         unsigned int link_id = sdw->instance;
 395         int ret = 0;
 396         u16 ioctl = 0, act = 0;
 397
 398         mutex_lock(sdw->link_res->shim_lock);
 399
 400         /* Initialize Shim */
 401         ioctl |= SDW_SHIM_IOCTL_BKE;
 402         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 403         usleep_range(10, 15);
 404
 405         ioctl |= SDW_SHIM_IOCTL_WPDD;
 406         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 407         usleep_range(10, 15);
 408
 409         ioctl |= SDW_SHIM_IOCTL_DO;
 410         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 411         usleep_range(10, 15);
 412
 413         ioctl |= SDW_SHIM_IOCTL_DOE;
 414         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 415         usleep_range(10, 15);
 416
 417         intel_shim_glue_to_master_ip(sdw);
 418
 419         u16p_replace_bits(&act, 0x1, SDW_SHIM_CTMCTL_DOAIS);
 420         act |= SDW_SHIM_CTMCTL_DACTQE;
 421         act |= SDW_SHIM_CTMCTL_DODS;
 422         intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act);
 423         usleep_range(10, 15);
 424
 425         mutex_unlock(sdw->link_res->shim_lock);
 426
 427         return ret;
 428 }
 429
 430 static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable)
 431 {
 432         void __iomem *shim = sdw->link_res->shim;
 433         unsigned int link_id = sdw->instance;
 434         u16 wake_en, wake_sts;
 435
 436         mutex_lock(sdw->link_res->shim_lock);
 437         wake_en = intel_readw(shim, SDW_SHIM_WAKEEN);
 438
 439         if (wake_enable) {
 440                 /* Enable the wakeup */
 441                 wake_en |= (SDW_SHIM_WAKEEN_ENABLE << link_id);
 442                 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
 443         } else {
 444                 /* Disable the wake up interrupt */
 445                 wake_en &= ~(SDW_SHIM_WAKEEN_ENABLE << link_id);
 446                 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
 447
 448                 /* Clear wake status */
 449                 wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);
 450                 wake_sts |= (SDW_SHIM_WAKEEN_ENABLE << link_id);
 451                 intel_writew(shim, SDW_SHIM_WAKESTS_STATUS, wake_sts);
 452         }
 453         mutex_unlock(sdw->link_res->shim_lock);
 454 }
 455
 456 static int intel_link_power_down(struct sdw_intel *sdw)
 457 {
 458         u32 link_control, spa_mask, cpa_mask;
 459         unsigned int link_id = sdw->instance;
 460         void __iomem *shim = sdw->link_res->shim;
 461         u32 *shim_mask = sdw->link_res->shim_mask;
 462         int ret = 0;
 463
 464         mutex_lock(sdw->link_res->shim_lock);
 465
 466         intel_shim_master_ip_to_glue(sdw);
 467
 468         if (!(*shim_mask & BIT(link_id)))
 469                 dev_err(sdw->cdns.dev,
 470                         "%s: Unbalanced power-up/down calls\n", __func__);
 471
 472         *shim_mask &= ~BIT(link_id);
 473
 474         if (!*shim_mask) {
 475
 476                 dev_dbg(sdw->cdns.dev, "%s: powering down all links\n", __func__);
 477
 478                 /* Link power down sequence */
 479                 link_control = intel_readl(shim, SDW_SHIM_LCTL);
 480
 481                 /* only power-down enabled links */
 482                 spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, ~sdw->link_res->link_mask);
 483                 cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask);
 484
 485                 link_control &=  spa_mask;
 486
 487                 ret = intel_clear_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
 488         }
 489
 490         mutex_unlock(sdw->link_res->shim_lock);
 491
 492         if (ret < 0) {
 493                 dev_err(sdw->cdns.dev, "%s: could not power down link\n", __func__);
 494
 495                 return ret;
 496         }
 497
 498         sdw->cdns.link_up = false;
 499         return 0;
 500 }
 501
 502 static void intel_shim_sync_arm(struct sdw_intel *sdw)
 503 {
 504         void __iomem *shim = sdw->link_res->shim;
 505         u32 sync_reg;
 506
 507         mutex_lock(sdw->link_res->shim_lock);
 508
 509         /* update SYNC register */
 510         sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
 511         sync_reg |= (SDW_SHIM_SYNC_CMDSYNC << sdw->instance);
 512         intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
 513
 514         mutex_unlock(sdw->link_res->shim_lock);
 515 }
 516
 517 static int intel_shim_sync_go_unlocked(struct sdw_intel *sdw)
 518 {
 519         void __iomem *shim = sdw->link_res->shim;
 520         u32 sync_reg;
 521         int ret;
 522
 523         /* Read SYNC register */
 524         sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
 525
 526         /*
 527          * Set SyncGO bit to synchronously trigger a bank switch for
 528          * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all
 529          * the Masters.
 530          */
 531         sync_reg |= SDW_SHIM_SYNC_SYNCGO;
 532
 533         ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
 534                               SDW_SHIM_SYNC_SYNCGO);
 535
 536         if (ret < 0)
 537                 dev_err(sdw->cdns.dev, "SyncGO clear failed: %d\n", ret);
 538
 539         return ret;
 540 }
 541
 542 static int intel_shim_sync_go(struct sdw_intel *sdw)
 543 {
 544         int ret;
 545
 546         mutex_lock(sdw->link_res->shim_lock);
 547
 548         ret = intel_shim_sync_go_unlocked(sdw);
 549
 550         mutex_unlock(sdw->link_res->shim_lock);
 551
 552         return ret;
 553 }
 554
 555 /*
 556  * PDI routines
 557  */
 558 static void intel_pdi_init(struct sdw_intel *sdw,
 559                            struct sdw_cdns_stream_config *config)
 560 {
 561         void __iomem *shim = sdw->link_res->shim;
 562         unsigned int link_id = sdw->instance;
 563         int pcm_cap, pdm_cap;
 564
 565         /* PCM Stream Capability */
 566         pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id));
 567
 568         config->pcm_bd = FIELD_GET(SDW_SHIM_PCMSCAP_BSS, pcm_cap);
 569         config->pcm_in = FIELD_GET(SDW_SHIM_PCMSCAP_ISS, pcm_cap);
 570         config->pcm_out = FIELD_GET(SDW_SHIM_PCMSCAP_OSS, pcm_cap);
 571
 572         dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n",
 573                 config->pcm_bd, config->pcm_in, config->pcm_out);
 574
 575         /* PDM Stream Capability */
 576         pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
 577
 578         config->pdm_bd = FIELD_GET(SDW_SHIM_PDMSCAP_BSS, pdm_cap);
 579         config->pdm_in = FIELD_GET(SDW_SHIM_PDMSCAP_ISS, pdm_cap);
 580         config->pdm_out = FIELD_GET(SDW_SHIM_PDMSCAP_OSS, pdm_cap);
 581
 582         dev_dbg(sdw->cdns.dev, "PDM cap bd:%d in:%d out:%d\n",
 583                 config->pdm_bd, config->pdm_in, config->pdm_out);
 584 }
 585
 586 static int
 587 intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm)
 588 {
 589         void __iomem *shim = sdw->link_res->shim;
 590         unsigned int link_id = sdw->instance;
 591         int count;
 592
 593         if (pcm) {
 594                 count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num));
 595
 596                 /*
 597                  * WORKAROUND: on all existing Intel controllers, pdi
 598                  * number 2 reports channel count as 1 even though it
 599                  * supports 8 channels. Performing hardcoding for pdi
 600                  * number 2.
 601                  */
 602                 if (pdi_num == 2)
 603                         count = 7;
 604
 605         } else {
 606                 count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
 607                 count = FIELD_GET(SDW_SHIM_PDMSCAP_CPSS, count);
 608         }
 609
 610         /* zero based values for channel count in register */
 611         count++;
 612
 613         return count;
 614 }
 615
 616 static int intel_pdi_get_ch_update(struct sdw_intel *sdw,
 617                                    struct sdw_cdns_pdi *pdi,
 618                                    unsigned int num_pdi,
 619                                    unsigned int *num_ch, bool pcm)
 620 {
 621         int i, ch_count = 0;
 622
 623         for (i = 0; i < num_pdi; i++) {
 624                 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm);
 625                 ch_count += pdi->ch_count;
 626                 pdi++;
 627         }
 628
 629         *num_ch = ch_count;
 630         return 0;
 631 }
 632
 633 static int intel_pdi_stream_ch_update(struct sdw_intel *sdw,
 634                                       struct sdw_cdns_streams *stream, bool pcm)
 635 {
 636         intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
 637                                 &stream->num_ch_bd, pcm);
 638
 639         intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
 640                                 &stream->num_ch_in, pcm);
 641
 642         intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
 643                                 &stream->num_ch_out, pcm);
 644
 645         return 0;
 646 }
 647
 648 static int intel_pdi_ch_update(struct sdw_intel *sdw)
 649 {
 650         /* First update PCM streams followed by PDM streams */
 651         intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true);
 652         intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false);
 653
 654         return 0;
 655 }
 656
 657 static void
 658 intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
 659 {
 660         void __iomem *shim = sdw->link_res->shim;
 661         unsigned int link_id = sdw->instance;
 662         int pdi_conf = 0;
 663
 664         /* the Bulk and PCM streams are not contiguous */
 665         pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
 666         if (pdi->num >= 2)
 667                 pdi->intel_alh_id += 2;
 668
 669         /*
 670          * Program stream parameters to stream SHIM register
 671          * This is applicable for PCM stream only.
 672          */
 673         if (pdi->type != SDW_STREAM_PCM)
 674                 return;
 675
 676         if (pdi->dir == SDW_DATA_DIR_RX)
 677                 pdi_conf |= SDW_SHIM_PCMSYCM_DIR;
 678         else
 679                 pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR);
 680
 681         u32p_replace_bits(&pdi_conf, pdi->intel_alh_id, SDW_SHIM_PCMSYCM_STREAM);
 682         u32p_replace_bits(&pdi_conf, pdi->l_ch_num, SDW_SHIM_PCMSYCM_LCHN);
 683         u32p_replace_bits(&pdi_conf, pdi->h_ch_num, SDW_SHIM_PCMSYCM_HCHN);
 684
 685         intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf);
 686 }
 687
 688 static void
 689 intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
 690 {
 691         void __iomem *alh = sdw->link_res->alh;
 692         unsigned int link_id = sdw->instance;
 693         unsigned int conf;
 694
 695         /* the Bulk and PCM streams are not contiguous */
 696         pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
 697         if (pdi->num >= 2)
 698                 pdi->intel_alh_id += 2;
 699
 700         /* Program Stream config ALH register */
 701         conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id));
 702
 703         u32p_replace_bits(&conf, SDW_ALH_STRMZCFG_DMAT_VAL, SDW_ALH_STRMZCFG_DMAT);
 704         u32p_replace_bits(&conf, pdi->ch_count - 1, SDW_ALH_STRMZCFG_CHN);
 705
 706         intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf);
 707 }
 708
 709 static int intel_params_stream(struct sdw_intel *sdw,
 710                                struct snd_pcm_substream *substream,
 711                                struct snd_soc_dai *dai,
 712                                struct snd_pcm_hw_params *hw_params,
 713                                int link_id, int alh_stream_id)
 714 {
 715         struct sdw_intel_link_res *res = sdw->link_res;
 716         struct sdw_intel_stream_params_data params_data;
 717
 718         params_data.substream = substream;
 719         params_data.dai = dai;
 720         params_data.hw_params = hw_params;
 721         params_data.link_id = link_id;
 722         params_data.alh_stream_id = alh_stream_id;
 723
 724         if (res->ops && res->ops->params_stream && res->dev)
 725                 return res->ops->params_stream(res->dev,
 726                                                &params_data);
 727         return -EIO;
 728 }
 729
 730 static int intel_free_stream(struct sdw_intel *sdw,
 731                              struct snd_pcm_substream *substream,
 732                              struct snd_soc_dai *dai,
 733                              int link_id)
 734 {
 735         struct sdw_intel_link_res *res = sdw->link_res;
 736         struct sdw_intel_stream_free_data free_data;
 737
 738         free_data.substream = substream;
 739         free_data.dai = dai;
 740         free_data.link_id = link_id;
 741
 742         if (res->ops && res->ops->free_stream && res->dev)
 743                 return res->ops->free_stream(res->dev,
 744                                              &free_data);
 745
 746         return 0;
 747 }
 748
 749 /*
 750  * bank switch routines
 751  */
 752
 753 static int intel_pre_bank_switch(struct sdw_bus *bus)
 754 {
 755         struct sdw_cdns *cdns = bus_to_cdns(bus);
 756         struct sdw_intel *sdw = cdns_to_intel(cdns);
 757
 758         /* Write to register only for multi-link */
 759         if (!bus->multi_link)
 760                 return 0;
 761
 762         intel_shim_sync_arm(sdw);
 763
 764         return 0;
 765 }
 766
 767 static int intel_post_bank_switch(struct sdw_bus *bus)
 768 {
 769         struct sdw_cdns *cdns = bus_to_cdns(bus);
 770         struct sdw_intel *sdw = cdns_to_intel(cdns);
 771         void __iomem *shim = sdw->link_res->shim;
 772         int sync_reg, ret;
 773
 774         /* Write to register only for multi-link */
 775         if (!bus->multi_link)
 776                 return 0;
 777
 778         mutex_lock(sdw->link_res->shim_lock);
 779
 780         /* Read SYNC register */
 781         sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
 782
 783         /*
 784          * post_bank_switch() ops is called from the bus in loop for
 785          * all the Masters in the steam with the expectation that
 786          * we trigger the bankswitch for the only first Master in the list
 787          * and do nothing for the other Masters
 788          *
 789          * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master.
 790          */
 791         if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK)) {
 792                 ret = 0;
 793                 goto unlock;
 794         }
 795
 796         ret = intel_shim_sync_go_unlocked(sdw);
 797 unlock:
 798         mutex_unlock(sdw->link_res->shim_lock);
 799
 800         if (ret < 0)
 801                 dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret);
 802
 803         return ret;
 804 }
 805
 806 /*
 807  * DAI routines
 808  */
 809
 810 static int intel_startup(struct snd_pcm_substream *substream,
 811                          struct snd_soc_dai *dai)
 812 {
 813         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
 814         int ret;
 815
 816         ret = pm_runtime_get_sync(cdns->dev);
 817         if (ret < 0 && ret != -EACCES) {
 818                 dev_err_ratelimited(cdns->dev,
 819                                     "pm_runtime_get_sync failed in %s, ret %d\n",
 820                                     __func__, ret);
 821                 pm_runtime_put_noidle(cdns->dev);
 822                 return ret;
 823         }
 824         return 0;
 825 }
 826
 827 static int intel_hw_params(struct snd_pcm_substream *substream,
 828                            struct snd_pcm_hw_params *params,
 829                            struct snd_soc_dai *dai)
 830 {
 831         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
 832         struct sdw_intel *sdw = cdns_to_intel(cdns);
 833         struct sdw_cdns_dma_data *dma;
 834         struct sdw_cdns_pdi *pdi;
 835         struct sdw_stream_config sconfig;
 836         struct sdw_port_config *pconfig;
 837         int ch, dir;
 838         int ret;
 839         bool pcm = true;
 840
 841         dma = snd_soc_dai_get_dma_data(dai, substream);
 842         if (!dma)
 843                 return -EIO;
 844
 845         ch = params_channels(params);
 846         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 847                 dir = SDW_DATA_DIR_RX;
 848         else
 849                 dir = SDW_DATA_DIR_TX;
 850
 851         if (dma->stream_type == SDW_STREAM_PDM)
 852                 pcm = false;
 853
 854         if (pcm)
 855                 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id);
 856         else
 857                 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pdm, ch, dir, dai->id);
 858
 859         if (!pdi) {
 860                 ret = -EINVAL;
 861                 goto error;
 862         }
 863
 864         /* do run-time configurations for SHIM, ALH and PDI/PORT */
 865         intel_pdi_shim_configure(sdw, pdi);
 866         intel_pdi_alh_configure(sdw, pdi);
 867         sdw_cdns_config_stream(cdns, ch, dir, pdi);
 868
 869         /* store pdi and hw_params, may be needed in prepare step */
 870         dma->suspended = false;
 871         dma->pdi = pdi;
 872         dma->hw_params = params;
 873
 874         /* Inform DSP about PDI stream number */
 875         ret = intel_params_stream(sdw, substream, dai, params,
 876                                   sdw->instance,
 877                                   pdi->intel_alh_id);
 878         if (ret)
 879                 goto error;
 880
 881         sconfig.direction = dir;
 882         sconfig.ch_count = ch;
 883         sconfig.frame_rate = params_rate(params);
 884         sconfig.type = dma->stream_type;
 885
 886         if (dma->stream_type == SDW_STREAM_PDM) {
 887                 sconfig.frame_rate *= 50;
 888                 sconfig.bps = 1;
 889         } else {
 890                 sconfig.bps = snd_pcm_format_width(params_format(params));
 891         }
 892
 893         /* Port configuration */
 894         pconfig = kzalloc(sizeof(*pconfig), GFP_KERNEL);
 895         if (!pconfig) {
 896                 ret =  -ENOMEM;
 897                 goto error;
 898         }
 899
 900         pconfig->num = pdi->num;
 901         pconfig->ch_mask = (1 << ch) - 1;
 902
 903         ret = sdw_stream_add_master(&cdns->bus, &sconfig,
 904                                     pconfig, 1, dma->stream);
 905         if (ret)
 906                 dev_err(cdns->dev, "add master to stream failed:%d\n", ret);
 907
 908         kfree(pconfig);
 909 error:
 910         return ret;
 911 }
 912
 913 static int intel_prepare(struct snd_pcm_substream *substream,
 914                          struct snd_soc_dai *dai)
 915 {
 916         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
 917         struct sdw_intel *sdw = cdns_to_intel(cdns);
 918         struct sdw_cdns_dma_data *dma;
 919         int ch, dir;
 920         int ret = 0;
 921
 922         dma = snd_soc_dai_get_dma_data(dai, substream);
 923         if (!dma) {
 924                 dev_err(dai->dev, "failed to get dma data in %s\n",
 925                         __func__);
 926                 return -EIO;
 927         }
 928
 929         if (dma->suspended) {
 930                 dma->suspended = false;
 931
 932                 /*
 933                  * .prepare() is called after system resume, where we
 934                  * need to reinitialize the SHIM/ALH/Cadence IP.
 935                  * .prepare() is also called to deal with underflows,
 936                  * but in those cases we cannot touch ALH/SHIM
 937                  * registers
 938                  */
 939
 940                 /* configure stream */
 941                 ch = params_channels(dma->hw_params);
 942                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 943                         dir = SDW_DATA_DIR_RX;
 944                 else
 945                         dir = SDW_DATA_DIR_TX;
 946
 947                 intel_pdi_shim_configure(sdw, dma->pdi);
 948                 intel_pdi_alh_configure(sdw, dma->pdi);
 949                 sdw_cdns_config_stream(cdns, ch, dir, dma->pdi);
 950
 951                 /* Inform DSP about PDI stream number */
 952                 ret = intel_params_stream(sdw, substream, dai,
 953                                           dma->hw_params,
 954                                           sdw->instance,
 955                                           dma->pdi->intel_alh_id);
 956         }
 957
 958         return ret;
 959 }
 960
 961 static int
 962 intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
 963 {
 964         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
 965         struct sdw_intel *sdw = cdns_to_intel(cdns);
 966         struct sdw_cdns_dma_data *dma;
 967         int ret;
 968
 969         dma = snd_soc_dai_get_dma_data(dai, substream);
 970         if (!dma)
 971                 return -EIO;
 972
 973         /*
 974          * The sdw stream state will transition to RELEASED when stream->
 975          * master_list is empty. So the stream state will transition to
 976          * DEPREPARED for the first cpu-dai and to RELEASED for the last
 977          * cpu-dai.
 978          */
 979         ret = sdw_stream_remove_master(&cdns->bus, dma->stream);
 980         if (ret < 0) {
 981                 dev_err(dai->dev, "remove master from stream %s failed: %d\n",
 982                         dma->stream->name, ret);
 983                 return ret;
 984         }
 985
 986         ret = intel_free_stream(sdw, substream, dai, sdw->instance);
 987         if (ret < 0) {
 988                 dev_err(dai->dev, "intel_free_stream: failed %d\n", ret);
 989                 return ret;
 990         }
 991
 992         dma->hw_params = NULL;
 993         dma->pdi = NULL;
 994
 995         return 0;
 996 }
 997
 998 static void intel_shutdown(struct snd_pcm_substream *substream,
 999                            struct snd_soc_dai *dai)
1000 {
1001         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
1002
1003         pm_runtime_mark_last_busy(cdns->dev);
1004         pm_runtime_put_autosuspend(cdns->dev);
1005 }
1006
1007 static int intel_component_dais_suspend(struct snd_soc_component *component)
1008 {
1009         struct sdw_cdns_dma_data *dma;
1010         struct snd_soc_dai *dai;
1011
1012         for_each_component_dais(component, dai) {
1013                 /*
1014                  * we don't have a .suspend dai_ops, and we don't have access
1015                  * to the substream, so let's mark both capture and playback
1016                  * DMA contexts as suspended
1017                  */
1018                 dma = dai->playback_dma_data;
1019                 if (dma)
1020                         dma->suspended = true;
1021
1022                 dma = dai->capture_dma_data;
1023                 if (dma)
1024                         dma->suspended = true;
1025         }
1026
1027         return 0;
1028 }
1029
1030 static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai,
1031                                     void *stream, int direction)
1032 {
1033         return cdns_set_sdw_stream(dai, stream, true, direction);
1034 }
1035
1036 static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai,
1037                                     void *stream, int direction)
1038 {
1039         return cdns_set_sdw_stream(dai, stream, false, direction);
1040 }
1041
1042 static void *intel_get_sdw_stream(struct snd_soc_dai *dai,
1043                                   int direction)
1044 {
1045         struct sdw_cdns_dma_data *dma;
1046
1047         if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1048                 dma = dai->playback_dma_data;
1049         else
1050                 dma = dai->capture_dma_data;
1051
1052         if (!dma)
1053                 return ERR_PTR(-EINVAL);
1054
1055         return dma->stream;
1056 }
1057
1058 static const struct snd_soc_dai_ops intel_pcm_dai_ops = {
1059         .startup = intel_startup,
1060         .hw_params = intel_hw_params,
1061         .prepare = intel_prepare,
1062         .hw_free = intel_hw_free,
1063         .shutdown = intel_shutdown,
1064         .set_sdw_stream = intel_pcm_set_sdw_stream,
1065         .get_sdw_stream = intel_get_sdw_stream,
1066 };
1067
1068 static const struct snd_soc_dai_ops intel_pdm_dai_ops = {
1069         .startup = intel_startup,
1070         .hw_params = intel_hw_params,
1071         .prepare = intel_prepare,
1072         .hw_free = intel_hw_free,
1073         .shutdown = intel_shutdown,
1074         .set_sdw_stream = intel_pdm_set_sdw_stream,
1075         .get_sdw_stream = intel_get_sdw_stream,
1076 };
1077
1078 static const struct snd_soc_component_driver dai_component = {
1079         .name           = "soundwire",
1080         .suspend        = intel_component_dais_suspend
1081 };
1082
1083 static int intel_create_dai(struct sdw_cdns *cdns,
1084                             struct snd_soc_dai_driver *dais,
1085                             enum intel_pdi_type type,
1086                             u32 num, u32 off, u32 max_ch, bool pcm)
1087 {
1088         int i;
1089
1090         if (num == 0)
1091                 return 0;
1092
1093          /* TODO: Read supported rates/formats from hardware */
1094         for (i = off; i < (off + num); i++) {
1095                 dais[i].name = devm_kasprintf(cdns->dev, GFP_KERNEL,
1096                                               "SDW%d Pin%d",
1097                                               cdns->instance, i);
1098                 if (!dais[i].name)
1099                         return -ENOMEM;
1100
1101                 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) {
1102                         dais[i].playback.channels_min = 1;
1103                         dais[i].playback.channels_max = max_ch;
1104                         dais[i].playback.rates = SNDRV_PCM_RATE_48000;
1105                         dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
1106                 }
1107
1108                 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) {
1109                         dais[i].capture.channels_min = 1;
1110                         dais[i].capture.channels_max = max_ch;
1111                         dais[i].capture.rates = SNDRV_PCM_RATE_48000;
1112                         dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
1113                 }
1114
1115                 if (pcm)
1116                         dais[i].ops = &intel_pcm_dai_ops;
1117                 else
1118                         dais[i].ops = &intel_pdm_dai_ops;
1119         }
1120
1121         return 0;
1122 }
1123
1124 static int intel_register_dai(struct sdw_intel *sdw)
1125 {
1126         struct sdw_cdns *cdns = &sdw->cdns;
1127         struct sdw_cdns_streams *stream;
1128         struct snd_soc_dai_driver *dais;
1129         int num_dai, ret, off = 0;
1130
1131         /* DAIs are created based on total number of PDIs supported */
1132         num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi;
1133
1134         dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
1135         if (!dais)
1136                 return -ENOMEM;
1137
1138         /* Create PCM DAIs */
1139         stream = &cdns->pcm;
1140
1141         ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in,
1142                                off, stream->num_ch_in, true);
1143         if (ret)
1144                 return ret;
1145
1146         off += cdns->pcm.num_in;
1147         ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,
1148                                off, stream->num_ch_out, true);
1149         if (ret)
1150                 return ret;
1151
1152         off += cdns->pcm.num_out;
1153         ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,
1154                                off, stream->num_ch_bd, true);
1155         if (ret)
1156                 return ret;
1157
1158         /* Create PDM DAIs */
1159         stream = &cdns->pdm;
1160         off += cdns->pcm.num_bd;
1161         ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pdm.num_in,
1162                                off, stream->num_ch_in, false);
1163         if (ret)
1164                 return ret;
1165
1166         off += cdns->pdm.num_in;
1167         ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pdm.num_out,
1168                                off, stream->num_ch_out, false);
1169         if (ret)
1170                 return ret;
1171
1172         off += cdns->pdm.num_out;
1173         ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pdm.num_bd,
1174                                off, stream->num_ch_bd, false);
1175         if (ret)
1176                 return ret;
1177
1178         return snd_soc_register_component(cdns->dev, &dai_component,
1179                                           dais, num_dai);
1180 }
1181
1182 static int sdw_master_read_intel_prop(struct sdw_bus *bus)
1183 {
1184         struct sdw_master_prop *prop = &bus->prop;
1185         struct fwnode_handle *link;
1186         char name[32];
1187         u32 quirk_mask;
1188
1189         /* Find master handle */
1190         snprintf(name, sizeof(name),
1191                  "mipi-sdw-link-%d-subproperties", bus->link_id);
1192
1193         link = device_get_named_child_node(bus->dev, name);
1194         if (!link) {
1195                 dev_err(bus->dev, "Master node %s not found\n", name);
1196                 return -EIO;
1197         }
1198
1199         fwnode_property_read_u32(link,
1200                                  "intel-sdw-ip-clock",
1201                                  &prop->mclk_freq);
1202
1203         /* the values reported by BIOS are the 2x clock, not the bus clock */
1204         prop->mclk_freq /= 2;
1205
1206         fwnode_property_read_u32(link,
1207                                  "intel-quirk-mask",
1208                                  &quirk_mask);
1209
1210         if (quirk_mask & SDW_INTEL_QUIRK_MASK_BUS_DISABLE)
1211                 prop->hw_disabled = true;
1212
1213         prop->quirks = SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH |
1214                 SDW_MASTER_QUIRKS_CLEAR_INITIAL_PARITY;
1215
1216         return 0;
1217 }
1218
1219 static int intel_prop_read(struct sdw_bus *bus)
1220 {
1221         /* Initialize with default handler to read all DisCo properties */
1222         sdw_master_read_prop(bus);
1223
1224         /* read Intel-specific properties */
1225         sdw_master_read_intel_prop(bus);
1226
1227         return 0;
1228 }
1229
1230 static struct sdw_master_ops sdw_intel_ops = {
1231         .read_prop = sdw_master_read_prop,
1232         .override_adr = sdw_dmi_override_adr,
1233         .xfer_msg = cdns_xfer_msg,
1234         .xfer_msg_defer = cdns_xfer_msg_defer,
1235         .reset_page_addr = cdns_reset_page_addr,
1236         .set_bus_conf = cdns_bus_conf,
1237         .pre_bank_switch = intel_pre_bank_switch,
1238         .post_bank_switch = intel_post_bank_switch,
1239 };
1240
1241 static int intel_init(struct sdw_intel *sdw)
1242 {
1243         bool clock_stop;
1244
1245         /* Initialize shim and controller */
1246         intel_link_power_up(sdw);
1247
1248         clock_stop = sdw_cdns_is_clock_stop(&sdw->cdns);
1249
1250         intel_shim_init(sdw, clock_stop);
1251
1252         return 0;
1253 }
1254
1255 /*
1256  * probe and init (aux_dev_id argument is required by function prototype but not used)
1257  */
1258 static int intel_link_probe(struct auxiliary_device *auxdev,
1259                             const struct auxiliary_device_id *aux_dev_id)
1260
1261 {
1262         struct device *dev = &auxdev->dev;
1263         struct sdw_intel_link_dev *ldev = auxiliary_dev_to_sdw_intel_link_dev(auxdev);
1264         struct sdw_intel *sdw;
1265         struct sdw_cdns *cdns;
1266         struct sdw_bus *bus;
1267         int ret;
1268
1269         sdw = devm_kzalloc(dev, sizeof(*sdw), GFP_KERNEL);
1270         if (!sdw)
1271                 return -ENOMEM;
1272
1273         cdns = &sdw->cdns;
1274         bus = &cdns->bus;
1275
1276         sdw->instance = auxdev->id;
1277         sdw->link_res = &ldev->link_res;
1278         cdns->dev = dev;
1279         cdns->registers = sdw->link_res->registers;
1280         cdns->instance = sdw->instance;
1281         cdns->msg_count = 0;
1282
1283         bus->link_id = auxdev->id;
1284
1285         sdw_cdns_probe(cdns);
1286
1287         /* Set property read ops */
1288         sdw_intel_ops.read_prop = intel_prop_read;
1289         bus->ops = &sdw_intel_ops;
1290
1291         /* set driver data, accessed by snd_soc_dai_get_drvdata() */
1292         dev_set_drvdata(dev, cdns);
1293
1294         /* use generic bandwidth allocation algorithm */
1295         sdw->cdns.bus.compute_params = sdw_compute_params;
1296
1297         ret = sdw_bus_master_add(bus, dev, dev->fwnode);
1298         if (ret) {
1299                 dev_err(dev, "sdw_bus_master_add fail: %d\n", ret);
1300                 return ret;
1301         }
1302
1303         if (bus->prop.hw_disabled)
1304                 dev_info(dev,
1305                          "SoundWire master %d is disabled, will be ignored\n",
1306                          bus->link_id);
1307         /*
1308          * Ignore BIOS err_threshold, it's a really bad idea when dealing
1309          * with multiple hardware synchronized links
1310          */
1311         bus->prop.err_threshold = 0;
1312
1313         return 0;
1314 }
1315
1316 int intel_link_startup(struct auxiliary_device *auxdev)
1317 {
1318         struct sdw_cdns_stream_config config;
1319         struct device *dev = &auxdev->dev;
1320         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1321         struct sdw_intel *sdw = cdns_to_intel(cdns);
1322         struct sdw_bus *bus = &cdns->bus;
1323         int link_flags;
1324         bool multi_link;
1325         u32 clock_stop_quirks;
1326         int ret;
1327
1328         if (bus->prop.hw_disabled) {
1329                 dev_info(dev,
1330                          "SoundWire master %d is disabled, ignoring\n",
1331                          sdw->instance);
1332                 return 0;
1333         }
1334
1335         link_flags = md_flags >> (bus->link_id * 8);
1336         multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK);
1337         if (!multi_link) {
1338                 dev_dbg(dev, "Multi-link is disabled\n");
1339                 bus->multi_link = false;
1340         } else {
1341                 /*
1342                  * hardware-based synchronization is required regardless
1343                  * of the number of segments used by a stream: SSP-based
1344                  * synchronization is gated by gsync when the multi-master
1345                  * mode is set.
1346                  */
1347                 bus->multi_link = true;
1348                 bus->hw_sync_min_links = 1;
1349         }
1350
1351         /* Initialize shim, controller */
1352         ret = intel_init(sdw);
1353         if (ret)
1354                 goto err_init;
1355
1356         /* Read the PDI config and initialize cadence PDI */
1357         intel_pdi_init(sdw, &config);
1358         ret = sdw_cdns_pdi_init(cdns, config);
1359         if (ret)
1360                 goto err_init;
1361
1362         intel_pdi_ch_update(sdw);
1363
1364         ret = sdw_cdns_enable_interrupt(cdns, true);
1365         if (ret < 0) {
1366                 dev_err(dev, "cannot enable interrupts\n");
1367                 goto err_init;
1368         }
1369
1370         /*
1371          * follow recommended programming flows to avoid timeouts when
1372          * gsync is enabled
1373          */
1374         if (multi_link)
1375                 intel_shim_sync_arm(sdw);
1376
1377         ret = sdw_cdns_init(cdns);
1378         if (ret < 0) {
1379                 dev_err(dev, "unable to initialize Cadence IP\n");
1380                 goto err_interrupt;
1381         }
1382
1383         ret = sdw_cdns_exit_reset(cdns);
1384         if (ret < 0) {
1385                 dev_err(dev, "unable to exit bus reset sequence\n");
1386                 goto err_interrupt;
1387         }
1388
1389         if (multi_link) {
1390                 ret = intel_shim_sync_go(sdw);
1391                 if (ret < 0) {
1392                         dev_err(dev, "sync go failed: %d\n", ret);
1393                         goto err_interrupt;
1394                 }
1395         }
1396
1397         /* Register DAIs */
1398         ret = intel_register_dai(sdw);
1399         if (ret) {
1400                 dev_err(dev, "DAI registration failed: %d\n", ret);
1401                 snd_soc_unregister_component(dev);
1402                 goto err_interrupt;
1403         }
1404
1405         intel_debugfs_init(sdw);
1406
1407         /* Enable runtime PM */
1408         if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME)) {
1409                 pm_runtime_set_autosuspend_delay(dev,
1410                                                  INTEL_MASTER_SUSPEND_DELAY_MS);
1411                 pm_runtime_use_autosuspend(dev);
1412                 pm_runtime_mark_last_busy(dev);
1413
1414                 pm_runtime_set_active(dev);
1415                 pm_runtime_enable(dev);
1416         }
1417
1418         clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1419         if (clock_stop_quirks & SDW_INTEL_CLK_STOP_NOT_ALLOWED) {
1420                 /*
1421                  * To keep the clock running we need to prevent
1422                  * pm_runtime suspend from happening by increasing the
1423                  * reference count.
1424                  * This quirk is specified by the parent PCI device in
1425                  * case of specific latency requirements. It will have
1426                  * no effect if pm_runtime is disabled by the user via
1427                  * a module parameter for testing purposes.
1428                  */
1429                 pm_runtime_get_noresume(dev);
1430         }
1431
1432         /*
1433          * The runtime PM status of Slave devices is "Unsupported"
1434          * until they report as ATTACHED. If they don't, e.g. because
1435          * there are no Slave devices populated or if the power-on is
1436          * delayed or dependent on a power switch, the Master will
1437          * remain active and prevent its parent from suspending.
1438          *
1439          * Conditionally force the pm_runtime core to re-evaluate the
1440          * Master status in the absence of any Slave activity. A quirk
1441          * is provided to e.g. deal with Slaves that may be powered on
1442          * with a delay. A more complete solution would require the
1443          * definition of Master properties.
1444          */
1445         if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE))
1446                 pm_runtime_idle(dev);
1447
1448         return 0;
1449
1450 err_interrupt:
1451         sdw_cdns_enable_interrupt(cdns, false);
1452 err_init:
1453         return ret;
1454 }
1455
1456 static void intel_link_remove(struct auxiliary_device *auxdev)
1457 {
1458         struct device *dev = &auxdev->dev;
1459         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1460         struct sdw_intel *sdw = cdns_to_intel(cdns);
1461         struct sdw_bus *bus = &cdns->bus;
1462
1463         /*
1464          * Since pm_runtime is already disabled, we don't decrease
1465          * the refcount when the clock_stop_quirk is
1466          * SDW_INTEL_CLK_STOP_NOT_ALLOWED
1467          */
1468         if (!bus->prop.hw_disabled) {
1469                 intel_debugfs_exit(sdw);
1470                 sdw_cdns_enable_interrupt(cdns, false);
1471                 snd_soc_unregister_component(dev);
1472         }
1473         sdw_bus_master_delete(bus);
1474 }
1475
1476 int intel_link_process_wakeen_event(struct auxiliary_device *auxdev)
1477 {
1478         struct device *dev = &auxdev->dev;
1479         struct sdw_intel *sdw;
1480         struct sdw_bus *bus;
1481         void __iomem *shim;
1482         u16 wake_sts;
1483
1484         sdw = dev_get_drvdata(dev);
1485         bus = &sdw->cdns.bus;
1486
1487         if (bus->prop.hw_disabled) {
1488                 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n", bus->link_id);
1489                 return 0;
1490         }
1491
1492         shim = sdw->link_res->shim;
1493         wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);
1494
1495         if (!(wake_sts & BIT(sdw->instance)))
1496                 return 0;
1497
1498         /* disable WAKEEN interrupt ASAP to prevent interrupt flood */
1499         intel_shim_wake(sdw, false);
1500
1501         /*
1502          * resume the Master, which will generate a bus reset and result in
1503          * Slaves re-attaching and be re-enumerated. The SoundWire physical
1504          * device which generated the wake will trigger an interrupt, which
1505          * will in turn cause the corresponding Linux Slave device to be
1506          * resumed and the Slave codec driver to check the status.
1507          */
1508         pm_request_resume(dev);
1509
1510         return 0;
1511 }
1512
1513 /*
1514  * PM calls
1515  */
1516
1517 static int __maybe_unused intel_suspend(struct device *dev)
1518 {
1519         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1520         struct sdw_intel *sdw = cdns_to_intel(cdns);
1521         struct sdw_bus *bus = &cdns->bus;
1522         u32 clock_stop_quirks;
1523         int ret;
1524
1525         if (bus->prop.hw_disabled) {
1526                 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n",
1527                         bus->link_id);
1528                 return 0;
1529         }
1530
1531         if (pm_runtime_suspended(dev)) {
1532                 dev_dbg(dev, "%s: pm_runtime status: suspended\n", __func__);
1533
1534                 clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1535
1536                 if ((clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET ||
1537                      !clock_stop_quirks) &&
1538                     !pm_runtime_suspended(dev->parent)) {
1539
1540                         /*
1541                          * if we've enabled clock stop, and the parent
1542                          * is still active, disable shim wake. The
1543                          * SHIM registers are not accessible if the
1544                          * parent is already pm_runtime suspended so
1545                          * it's too late to change that configuration
1546                          */
1547
1548                         intel_shim_wake(sdw, false);
1549                 }
1550
1551                 return 0;
1552         }
1553
1554         ret = sdw_cdns_enable_interrupt(cdns, false);
1555         if (ret < 0) {
1556                 dev_err(dev, "cannot disable interrupts on suspend\n");
1557                 return ret;
1558         }
1559
1560         ret = intel_link_power_down(sdw);
1561         if (ret) {
1562                 dev_err(dev, "Link power down failed: %d\n", ret);
1563                 return ret;
1564         }
1565
1566         intel_shim_wake(sdw, false);
1567
1568         return 0;
1569 }
1570
1571 static int __maybe_unused intel_suspend_runtime(struct device *dev)
1572 {
1573         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1574         struct sdw_intel *sdw = cdns_to_intel(cdns);
1575         struct sdw_bus *bus = &cdns->bus;
1576         u32 clock_stop_quirks;
1577         int ret;
1578
1579         if (bus->prop.hw_disabled) {
1580                 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n",
1581                         bus->link_id);
1582                 return 0;
1583         }
1584
1585         clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1586
1587         if (clock_stop_quirks & SDW_INTEL_CLK_STOP_TEARDOWN) {
1588
1589                 ret = sdw_cdns_enable_interrupt(cdns, false);
1590                 if (ret < 0) {
1591                         dev_err(dev, "cannot disable interrupts on suspend\n");
1592                         return ret;
1593                 }
1594
1595                 ret = intel_link_power_down(sdw);
1596                 if (ret) {
1597                         dev_err(dev, "Link power down failed: %d\n", ret);
1598                         return ret;
1599                 }
1600
1601                 intel_shim_wake(sdw, false);
1602
1603         } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET ||
1604                    !clock_stop_quirks) {
1605                 bool wake_enable = true;
1606
1607                 ret = sdw_cdns_clock_stop(cdns, true);
1608                 if (ret < 0) {
1609                         dev_err(dev, "cannot enable clock stop on suspend\n");
1610                         wake_enable = false;
1611                 }
1612
1613                 ret = sdw_cdns_enable_interrupt(cdns, false);
1614                 if (ret < 0) {
1615                         dev_err(dev, "cannot disable interrupts on suspend\n");
1616                         return ret;
1617                 }
1618
1619                 ret = intel_link_power_down(sdw);
1620                 if (ret) {
1621                         dev_err(dev, "Link power down failed: %d\n", ret);
1622                         return ret;
1623                 }
1624
1625                 intel_shim_wake(sdw, wake_enable);
1626         } else {
1627                 dev_err(dev, "%s clock_stop_quirks %x unsupported\n",
1628                         __func__, clock_stop_quirks);
1629                 ret = -EINVAL;
1630         }
1631
1632         return ret;
1633 }
1634
1635 static int __maybe_unused intel_resume(struct device *dev)
1636 {
1637         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1638         struct sdw_intel *sdw = cdns_to_intel(cdns);
1639         struct sdw_bus *bus = &cdns->bus;
1640         int link_flags;
1641         bool multi_link;
1642         int ret;
1643
1644         if (bus->prop.hw_disabled) {
1645                 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n",
1646                         bus->link_id);
1647                 return 0;
1648         }
1649
1650         link_flags = md_flags >> (bus->link_id * 8);
1651         multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK);
1652
1653         if (pm_runtime_suspended(dev)) {
1654                 dev_dbg(dev, "%s: pm_runtime status was suspended, forcing active\n", __func__);
1655
1656                 /* follow required sequence from runtime_pm.rst */
1657                 pm_runtime_disable(dev);
1658                 pm_runtime_set_active(dev);
1659                 pm_runtime_mark_last_busy(dev);
1660                 pm_runtime_enable(dev);
1661
1662                 link_flags = md_flags >> (bus->link_id * 8);
1663
1664                 if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE))
1665                         pm_runtime_idle(dev);
1666         }
1667
1668         ret = intel_init(sdw);
1669         if (ret) {
1670                 dev_err(dev, "%s failed: %d\n", __func__, ret);
1671                 return ret;
1672         }
1673
1674         /*
1675          * make sure all Slaves are tagged as UNATTACHED and provide
1676          * reason for reinitialization
1677          */
1678         sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET);
1679
1680         ret = sdw_cdns_enable_interrupt(cdns, true);
1681         if (ret < 0) {
1682                 dev_err(dev, "cannot enable interrupts during resume\n");
1683                 return ret;
1684         }
1685
1686         /*
1687          * follow recommended programming flows to avoid timeouts when
1688          * gsync is enabled
1689          */
1690         if (multi_link)
1691                 intel_shim_sync_arm(sdw);
1692
1693         ret = sdw_cdns_init(&sdw->cdns);
1694         if (ret < 0) {
1695                 dev_err(dev, "unable to initialize Cadence IP during resume\n");
1696                 return ret;
1697         }
1698
1699         ret = sdw_cdns_exit_reset(cdns);
1700         if (ret < 0) {
1701                 dev_err(dev, "unable to exit bus reset sequence during resume\n");
1702                 return ret;
1703         }
1704
1705         if (multi_link) {
1706                 ret = intel_shim_sync_go(sdw);
1707                 if (ret < 0) {
1708                         dev_err(dev, "sync go failed during resume\n");
1709                         return ret;
1710                 }
1711         }
1712
1713         /*
1714          * after system resume, the pm_runtime suspend() may kick in
1715          * during the enumeration, before any children device force the
1716          * master device to remain active.  Using pm_runtime_get()
1717          * routines is not really possible, since it'd prevent the
1718          * master from suspending.
1719          * A reasonable compromise is to update the pm_runtime
1720          * counters and delay the pm_runtime suspend by several
1721          * seconds, by when all enumeration should be complete.
1722          */
1723         pm_runtime_mark_last_busy(dev);
1724
1725         return ret;
1726 }
1727
1728 static int __maybe_unused intel_resume_runtime(struct device *dev)
1729 {
1730         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1731         struct sdw_intel *sdw = cdns_to_intel(cdns);
1732         struct sdw_bus *bus = &cdns->bus;
1733         u32 clock_stop_quirks;
1734         bool clock_stop0;
1735         int link_flags;
1736         bool multi_link;
1737         int status;
1738         int ret;
1739
1740         if (bus->prop.hw_disabled) {
1741                 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n",
1742                         bus->link_id);
1743                 return 0;
1744         }
1745
1746         link_flags = md_flags >> (bus->link_id * 8);
1747         multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK);
1748
1749         clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1750
1751         if (clock_stop_quirks & SDW_INTEL_CLK_STOP_TEARDOWN) {
1752                 ret = intel_init(sdw);
1753                 if (ret) {
1754                         dev_err(dev, "%s failed: %d\n", __func__, ret);
1755                         return ret;
1756                 }
1757
1758                 /*
1759                  * make sure all Slaves are tagged as UNATTACHED and provide
1760                  * reason for reinitialization
1761                  */
1762                 sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET);
1763
1764                 ret = sdw_cdns_enable_interrupt(cdns, true);
1765                 if (ret < 0) {
1766                         dev_err(dev, "cannot enable interrupts during resume\n");
1767                         return ret;
1768                 }
1769
1770                 /*
1771                  * follow recommended programming flows to avoid
1772                  * timeouts when gsync is enabled
1773                  */
1774                 if (multi_link)
1775                         intel_shim_sync_arm(sdw);
1776
1777                 ret = sdw_cdns_init(&sdw->cdns);
1778                 if (ret < 0) {
1779                         dev_err(dev, "unable to initialize Cadence IP during resume\n");
1780                         return ret;
1781                 }
1782
1783                 ret = sdw_cdns_exit_reset(cdns);
1784                 if (ret < 0) {
1785                         dev_err(dev, "unable to exit bus reset sequence during resume\n");
1786                         return ret;
1787                 }
1788
1789                 if (multi_link) {
1790                         ret = intel_shim_sync_go(sdw);
1791                         if (ret < 0) {
1792                                 dev_err(dev, "sync go failed during resume\n");
1793                                 return ret;
1794                         }
1795                 }
1796         } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET) {
1797                 ret = intel_init(sdw);
1798                 if (ret) {
1799                         dev_err(dev, "%s failed: %d\n", __func__, ret);
1800                         return ret;
1801                 }
1802
1803                 /*
1804                  * An exception condition occurs for the CLK_STOP_BUS_RESET
1805                  * case if one or more masters remain active. In this condition,
1806                  * all the masters are powered on for they are in the same power
1807                  * domain. Master can preserve its context for clock stop0, so
1808                  * there is no need to clear slave status and reset bus.
1809                  */
1810                 clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns);
1811
1812                 if (!clock_stop0) {
1813
1814                         /*
1815                          * make sure all Slaves are tagged as UNATTACHED and
1816                          * provide reason for reinitialization
1817                          */
1818
1819                         status = SDW_UNATTACH_REQUEST_MASTER_RESET;
1820                         sdw_clear_slave_status(bus, status);
1821
1822                         ret = sdw_cdns_enable_interrupt(cdns, true);
1823                         if (ret < 0) {
1824                                 dev_err(dev, "cannot enable interrupts during resume\n");
1825                                 return ret;
1826                         }
1827
1828                         /*
1829                          * follow recommended programming flows to avoid
1830                          * timeouts when gsync is enabled
1831                          */
1832                         if (multi_link)
1833                                 intel_shim_sync_arm(sdw);
1834
1835                         /*
1836                          * Re-initialize the IP since it was powered-off
1837                          */
1838                         sdw_cdns_init(&sdw->cdns);
1839
1840                 } else {
1841                         ret = sdw_cdns_enable_interrupt(cdns, true);
1842                         if (ret < 0) {
1843                                 dev_err(dev, "cannot enable interrupts during resume\n");
1844                                 return ret;
1845                         }
1846                 }
1847
1848                 ret = sdw_cdns_clock_restart(cdns, !clock_stop0);
1849                 if (ret < 0) {
1850                         dev_err(dev, "unable to restart clock during resume\n");
1851                         return ret;
1852                 }
1853
1854                 if (!clock_stop0) {
1855                         ret = sdw_cdns_exit_reset(cdns);
1856                         if (ret < 0) {
1857                                 dev_err(dev, "unable to exit bus reset sequence during resume\n");
1858                                 return ret;
1859                         }
1860
1861                         if (multi_link) {
1862                                 ret = intel_shim_sync_go(sdw);
1863                                 if (ret < 0) {
1864                                         dev_err(sdw->cdns.dev, "sync go failed during resume\n");
1865                                         return ret;
1866                                 }
1867                         }
1868                 }
1869         } else if (!clock_stop_quirks) {
1870
1871                 clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns);
1872                 if (!clock_stop0)
1873                         dev_err(dev, "%s invalid configuration, clock was not stopped", __func__);
1874
1875                 ret = intel_init(sdw);
1876                 if (ret) {
1877                         dev_err(dev, "%s failed: %d\n", __func__, ret);
1878                         return ret;
1879                 }
1880
1881                 ret = sdw_cdns_enable_interrupt(cdns, true);
1882                 if (ret < 0) {
1883                         dev_err(dev, "cannot enable interrupts during resume\n");
1884                         return ret;
1885                 }
1886
1887                 ret = sdw_cdns_clock_restart(cdns, false);
1888                 if (ret < 0) {
1889                         dev_err(dev, "unable to resume master during resume\n");
1890                         return ret;
1891                 }
1892         } else {
1893                 dev_err(dev, "%s clock_stop_quirks %x unsupported\n",
1894                         __func__, clock_stop_quirks);
1895                 ret = -EINVAL;
1896         }
1897
1898         return ret;
1899 }
1900
1901 static const struct dev_pm_ops intel_pm = {
1902         SET_SYSTEM_SLEEP_PM_OPS(intel_suspend, intel_resume)
1903         SET_RUNTIME_PM_OPS(intel_suspend_runtime, intel_resume_runtime, NULL)
1904 };
1905
1906 static const struct auxiliary_device_id intel_link_id_table[] = {
1907         { .name = "soundwire_intel.link" },
1908         {},
1909 };
1910 MODULE_DEVICE_TABLE(auxiliary, intel_link_id_table);
1911
1912 static struct auxiliary_driver sdw_intel_drv = {
1913         .probe = intel_link_probe,
1914         .remove = intel_link_remove,
1915         .driver = {
1916                 /* auxiliary_driver_register() sets .name to be the modname */
1917                 .pm = &intel_pm,
1918         },
1919         .id_table = intel_link_id_table
1920 };
1921 module_auxiliary_driver(sdw_intel_drv);
1922
1923 MODULE_LICENSE("Dual BSD/GPL");
1924 MODULE_DESCRIPTION("Intel Soundwire Link Driver");