1 // SPDX-License-Identifier: GPL-2.0
3 * AM33XX Power Management Routines
5 * Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
6 * Vaibhav Bedia, Dave Gerlach
10 #include <linux/cpu.h>
11 #include <linux/err.h>
12 #include <linux/genalloc.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/nvmem-consumer.h>
19 #include <linux/of_address.h>
20 #include <linux/platform_data/pm33xx.h>
21 #include <linux/platform_device.h>
22 #include <linux/rtc.h>
23 #include <linux/rtc/rtc-omap.h>
24 #include <linux/sizes.h>
25 #include <linux/sram.h>
26 #include <linux/suspend.h>
27 #include <linux/ti-emif-sram.h>
28 #include <linux/wkup_m3_ipc.h>
30 #include <asm/proc-fns.h>
31 #include <asm/suspend.h>
32 #include <asm/system_misc.h>
34 #define AMX3_PM_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
35 (unsigned long)pm_sram->do_wfi)
37 #define RTC_SCRATCH_RESUME_REG 0
38 #define RTC_SCRATCH_MAGIC_REG 1
39 #define RTC_REG_BOOT_MAGIC 0x8cd0 /* RTC */
40 #define GIC_INT_SET_PENDING_BASE 0x200
41 #define AM43XX_GIC_DIST_BASE 0x48241000
43 static void __iomem *rtc_base_virt;
44 static struct clk *rtc_fck;
45 static u32 rtc_magic_val;
47 static int (*am33xx_do_wfi_sram)(unsigned long unused);
48 static phys_addr_t am33xx_do_wfi_sram_phys;
50 static struct gen_pool *sram_pool, *sram_pool_data;
51 static unsigned long ocmcram_location, ocmcram_location_data;
53 static struct rtc_device *omap_rtc;
54 static void __iomem *gic_dist_base;
56 static struct am33xx_pm_platform_data *pm_ops;
57 static struct am33xx_pm_sram_addr *pm_sram;
59 static struct device *pm33xx_dev;
60 static struct wkup_m3_ipc *m3_ipc;
63 static int rtc_only_idle;
64 static int retrigger_irq;
65 static unsigned long suspend_wfi_flags;
67 static struct wkup_m3_wakeup_src wakeup_src = {.irq_nr = 0,
71 static struct wkup_m3_wakeup_src rtc_alarm_wakeup = {
72 .irq_nr = 108, .src = "RTC Alarm",
75 static struct wkup_m3_wakeup_src rtc_ext_wakeup = {
76 .irq_nr = 0, .src = "Ext wakeup",
80 static u32 sram_suspend_address(unsigned long addr)
82 return ((unsigned long)am33xx_do_wfi_sram +
83 AMX3_PM_SRAM_SYMBOL_OFFSET(addr));
86 static int am33xx_push_sram_idle(void)
88 struct am33xx_pm_ro_sram_data ro_sram_data;
90 u32 table_addr, ro_data_addr;
93 ro_sram_data.amx3_pm_sram_data_virt = ocmcram_location_data;
94 ro_sram_data.amx3_pm_sram_data_phys =
95 gen_pool_virt_to_phys(sram_pool_data, ocmcram_location_data);
96 ro_sram_data.rtc_base_virt = rtc_base_virt;
98 /* Save physical address to calculate resume offset during pm init */
99 am33xx_do_wfi_sram_phys = gen_pool_virt_to_phys(sram_pool,
102 am33xx_do_wfi_sram = sram_exec_copy(sram_pool, (void *)ocmcram_location,
104 *pm_sram->do_wfi_sz);
105 if (!am33xx_do_wfi_sram) {
107 "PM: %s: am33xx_do_wfi copy to sram failed\n",
113 sram_suspend_address((unsigned long)pm_sram->emif_sram_table);
114 ret = ti_emif_copy_pm_function_table(sram_pool, (void *)table_addr);
117 "PM: %s: EMIF function copy failed\n", __func__);
118 return -EPROBE_DEFER;
122 sram_suspend_address((unsigned long)pm_sram->ro_sram_data);
123 copy_addr = sram_exec_copy(sram_pool, (void *)ro_data_addr,
125 sizeof(ro_sram_data));
128 "PM: %s: ro_sram_data copy to sram failed\n",
136 static int am33xx_do_sram_idle(u32 wfi_flags)
140 if (!m3_ipc || !pm_ops)
143 if (wfi_flags & WFI_FLAG_WAKE_M3)
144 ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_IDLE);
146 return pm_ops->cpu_suspend(am33xx_do_wfi_sram, wfi_flags);
149 static int __init am43xx_map_gic(void)
151 gic_dist_base = ioremap(AM43XX_GIC_DIST_BASE, SZ_4K);
159 #ifdef CONFIG_SUSPEND
160 static struct wkup_m3_wakeup_src rtc_wake_src(void)
164 i = __raw_readl(rtc_base_virt + 0x44) & 0x40;
167 retrigger_irq = rtc_alarm_wakeup.irq_nr;
168 return rtc_alarm_wakeup;
171 retrigger_irq = rtc_ext_wakeup.irq_nr;
173 return rtc_ext_wakeup;
176 static int am33xx_rtc_only_idle(unsigned long wfi_flags)
178 omap_rtc_power_off_program(&omap_rtc->dev);
179 am33xx_do_wfi_sram(wfi_flags);
184 * Note that the RTC module clock must be re-enabled only for rtc+ddr suspend.
185 * And looks like the module can stay in SYSC_IDLE_SMART_WKUP mode configured
186 * by the interconnect code just fine for both rtc+ddr suspend and retention
189 static int am33xx_pm_suspend(suspend_state_t suspend_state)
193 if (suspend_state == PM_SUSPEND_MEM &&
194 pm_ops->check_off_mode_enable()) {
195 ret = clk_prepare_enable(rtc_fck);
197 dev_err(pm33xx_dev, "Failed to enable clock: %i\n", ret);
201 pm_ops->save_context();
202 suspend_wfi_flags |= WFI_FLAG_RTC_ONLY;
204 ret = pm_ops->soc_suspend(suspend_state, am33xx_rtc_only_idle,
207 suspend_wfi_flags &= ~WFI_FLAG_RTC_ONLY;
208 dev_info(pm33xx_dev, "Entering RTC Only mode with DDR in self-refresh\n");
211 clk_restore_context();
212 pm_ops->restore_context();
213 m3_ipc->ops->set_rtc_only(m3_ipc);
214 am33xx_push_sram_idle();
217 ret = pm_ops->soc_suspend(suspend_state, am33xx_do_wfi_sram,
222 dev_err(pm33xx_dev, "PM: Kernel suspend failure\n");
224 i = m3_ipc->ops->request_pm_status(m3_ipc);
229 "PM: Successfully put all powerdomains to target state\n");
233 "PM: Could not transition all powerdomains to target state\n");
238 "PM: CM3 returned unknown result = %d\n", i);
242 /* print the wakeup reason */
244 wakeup_src = rtc_wake_src();
245 pr_info("PM: Wakeup source %s\n", wakeup_src.src);
247 pr_info("PM: Wakeup source %s\n",
248 m3_ipc->ops->request_wake_src(m3_ipc));
252 if (suspend_state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable())
253 clk_disable_unprepare(rtc_fck);
258 static int am33xx_pm_enter(suspend_state_t suspend_state)
262 switch (suspend_state) {
264 case PM_SUSPEND_STANDBY:
265 ret = am33xx_pm_suspend(suspend_state);
274 static int am33xx_pm_begin(suspend_state_t state)
277 struct nvmem_device *nvmem;
279 if (state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable()) {
280 nvmem = devm_nvmem_device_get(&omap_rtc->dev,
281 "omap_rtc_scratch0");
283 nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 4,
284 (void *)&rtc_magic_val);
290 pm_ops->begin_suspend();
294 ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_DEEPSLEEP);
296 case PM_SUSPEND_STANDBY:
297 ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_STANDBY);
304 static void am33xx_pm_end(void)
307 struct nvmem_device *nvmem;
309 nvmem = devm_nvmem_device_get(&omap_rtc->dev, "omap_rtc_scratch0");
313 m3_ipc->ops->finish_low_power(m3_ipc);
317 * 32 bits of Interrupt Set-Pending correspond to 32
318 * 32 interrupts. Compute the bit offset of the
319 * Interrupt and set that particular bit
320 * Compute the register offset by dividing interrupt
321 * number by 32 and mutiplying by 4
323 writel_relaxed(1 << (retrigger_irq & 31),
324 gic_dist_base + GIC_INT_SET_PENDING_BASE
325 + retrigger_irq / 32 * 4);
328 nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 4,
334 pm_ops->finish_suspend();
337 static int am33xx_pm_valid(suspend_state_t state)
340 case PM_SUSPEND_STANDBY:
348 static const struct platform_suspend_ops am33xx_pm_ops = {
349 .begin = am33xx_pm_begin,
350 .end = am33xx_pm_end,
351 .enter = am33xx_pm_enter,
352 .valid = am33xx_pm_valid,
354 #endif /* CONFIG_SUSPEND */
356 static void am33xx_pm_set_ipc_ops(void)
361 temp = ti_emif_get_mem_type();
363 dev_err(pm33xx_dev, "PM: Cannot determine memory type, no PM available\n");
366 m3_ipc->ops->set_mem_type(m3_ipc, temp);
368 /* Physical resume address to be used by ROM code */
369 resume_address = am33xx_do_wfi_sram_phys +
370 *pm_sram->resume_offset + 0x4;
372 m3_ipc->ops->set_resume_address(m3_ipc, (void *)resume_address);
375 static void am33xx_pm_free_sram(void)
377 gen_pool_free(sram_pool, ocmcram_location, *pm_sram->do_wfi_sz);
378 gen_pool_free(sram_pool_data, ocmcram_location_data,
379 sizeof(struct am33xx_pm_ro_sram_data));
383 * Push the minimal suspend-resume code to SRAM
385 static int am33xx_pm_alloc_sram(void)
387 struct device_node *np;
390 np = of_find_compatible_node(NULL, NULL, "ti,omap3-mpu");
392 np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
394 dev_err(pm33xx_dev, "PM: %s: Unable to find device node for mpu\n",
400 sram_pool = of_gen_pool_get(np, "pm-sram", 0);
402 dev_err(pm33xx_dev, "PM: %s: Unable to get sram pool for ocmcram\n",
408 sram_pool_data = of_gen_pool_get(np, "pm-sram", 1);
409 if (!sram_pool_data) {
410 dev_err(pm33xx_dev, "PM: %s: Unable to get sram data pool for ocmcram\n",
416 ocmcram_location = gen_pool_alloc(sram_pool, *pm_sram->do_wfi_sz);
417 if (!ocmcram_location) {
418 dev_err(pm33xx_dev, "PM: %s: Unable to allocate memory from ocmcram\n",
424 ocmcram_location_data = gen_pool_alloc(sram_pool_data,
425 sizeof(struct emif_regs_amx3));
426 if (!ocmcram_location_data) {
427 dev_err(pm33xx_dev, "PM: Unable to allocate memory from ocmcram\n");
428 gen_pool_free(sram_pool, ocmcram_location, *pm_sram->do_wfi_sz);
437 static int am33xx_pm_rtc_setup(void)
439 struct device_node *np;
440 unsigned long val = 0;
441 struct nvmem_device *nvmem;
444 np = of_find_node_by_name(NULL, "rtc");
446 if (of_device_is_available(np)) {
447 /* RTC interconnect target module clock */
448 rtc_fck = of_clk_get_by_name(np->parent, "fck");
450 return PTR_ERR(rtc_fck);
452 rtc_base_virt = of_iomap(np, 0);
453 if (!rtc_base_virt) {
454 pr_warn("PM: could not iomap rtc");
459 omap_rtc = rtc_class_open("rtc0");
461 pr_warn("PM: rtc0 not available");
462 error = -EPROBE_DEFER;
466 nvmem = devm_nvmem_device_get(&omap_rtc->dev,
467 "omap_rtc_scratch0");
468 if (!IS_ERR(nvmem)) {
469 nvmem_device_read(nvmem, RTC_SCRATCH_MAGIC_REG * 4,
470 4, (void *)&rtc_magic_val);
471 if ((rtc_magic_val & 0xffff) != RTC_REG_BOOT_MAGIC)
472 pr_warn("PM: bootloader does not support rtc-only!\n");
474 nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4,
476 val = pm_sram->resume_address;
477 nvmem_device_write(nvmem, RTC_SCRATCH_RESUME_REG * 4,
481 pr_warn("PM: no-rtc available, rtc-only mode disabled.\n");
487 iounmap(rtc_base_virt);
494 static int am33xx_pm_probe(struct platform_device *pdev)
496 struct device *dev = &pdev->dev;
499 if (!of_machine_is_compatible("ti,am33xx") &&
500 !of_machine_is_compatible("ti,am43"))
503 pm_ops = dev->platform_data;
505 dev_err(dev, "PM: Cannot get core PM ops!\n");
509 ret = am43xx_map_gic();
511 pr_err("PM: Could not ioremap GIC base\n");
515 pm_sram = pm_ops->get_sram_addrs();
517 dev_err(dev, "PM: Cannot get PM asm function addresses!!\n");
521 m3_ipc = wkup_m3_ipc_get();
523 pr_err("PM: Cannot get wkup_m3_ipc handle\n");
524 return -EPROBE_DEFER;
529 ret = am33xx_pm_alloc_sram();
533 ret = am33xx_pm_rtc_setup();
537 ret = am33xx_push_sram_idle();
541 am33xx_pm_set_ipc_ops();
543 #ifdef CONFIG_SUSPEND
544 suspend_set_ops(&am33xx_pm_ops);
547 * For a system suspend we must flush the caches, we want
548 * the DDR in self-refresh, we want to save the context
549 * of the EMIF, and we want the wkup_m3 to handle low-power
552 suspend_wfi_flags |= WFI_FLAG_FLUSH_CACHE;
553 suspend_wfi_flags |= WFI_FLAG_SELF_REFRESH;
554 suspend_wfi_flags |= WFI_FLAG_SAVE_EMIF;
555 suspend_wfi_flags |= WFI_FLAG_WAKE_M3;
556 #endif /* CONFIG_SUSPEND */
558 ret = pm_ops->init(am33xx_do_sram_idle);
560 dev_err(dev, "Unable to call core pm init!\n");
562 goto err_put_wkup_m3_ipc;
568 wkup_m3_ipc_put(m3_ipc);
570 am33xx_pm_free_sram();
575 static int am33xx_pm_remove(struct platform_device *pdev)
579 suspend_set_ops(NULL);
580 wkup_m3_ipc_put(m3_ipc);
581 am33xx_pm_free_sram();
582 iounmap(rtc_base_virt);
587 static struct platform_driver am33xx_pm_driver = {
591 .probe = am33xx_pm_probe,
592 .remove = am33xx_pm_remove,
594 module_platform_driver(am33xx_pm_driver);
596 MODULE_ALIAS("platform:pm33xx");
597 MODULE_LICENSE("GPL v2");
598 MODULE_DESCRIPTION("am33xx power management driver");