1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/soc/tegra/pmc.c
5 * Copyright (c) 2010 Google, Inc
6 * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
9 * Colin Cross <ccross@google.com>
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/clkdev.h>
18 #include <linux/clk/clk-conf.h>
19 #include <linux/clk/tegra.h>
20 #include <linux/debugfs.h>
21 #include <linux/delay.h>
22 #include <linux/device.h>
23 #include <linux/err.h>
24 #include <linux/export.h>
25 #include <linux/init.h>
27 #include <linux/iopoll.h>
28 #include <linux/irqdomain.h>
29 #include <linux/irq.h>
30 #include <linux/kernel.h>
31 #include <linux/of_address.h>
32 #include <linux/of_clk.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_platform.h>
36 #include <linux/pinctrl/pinconf-generic.h>
37 #include <linux/pinctrl/pinconf.h>
38 #include <linux/pinctrl/pinctrl.h>
39 #include <linux/platform_device.h>
40 #include <linux/pm_domain.h>
41 #include <linux/reboot.h>
42 #include <linux/reset.h>
43 #include <linux/seq_file.h>
44 #include <linux/slab.h>
45 #include <linux/spinlock.h>
47 #include <soc/tegra/common.h>
48 #include <soc/tegra/fuse.h>
49 #include <soc/tegra/pmc.h>
51 #include <dt-bindings/interrupt-controller/arm-gic.h>
52 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
53 #include <dt-bindings/gpio/tegra186-gpio.h>
54 #include <dt-bindings/gpio/tegra194-gpio.h>
55 #include <dt-bindings/soc/tegra-pmc.h>
58 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
59 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
60 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
61 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
62 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
63 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
64 #define PMC_CNTRL_PWRREQ_POLARITY BIT(8)
65 #define PMC_CNTRL_BLINK_EN 7
66 #define PMC_CNTRL_MAIN_RST BIT(4)
68 #define PMC_WAKE_MASK 0x0c
69 #define PMC_WAKE_LEVEL 0x10
70 #define PMC_WAKE_STATUS 0x14
71 #define PMC_SW_WAKE_STATUS 0x18
72 #define PMC_DPD_PADS_ORIDE 0x1c
73 #define PMC_DPD_PADS_ORIDE_BLINK 20
75 #define DPD_SAMPLE 0x020
76 #define DPD_SAMPLE_ENABLE BIT(0)
77 #define DPD_SAMPLE_DISABLE (0 << 0)
79 #define PWRGATE_TOGGLE 0x30
80 #define PWRGATE_TOGGLE_START BIT(8)
82 #define REMOVE_CLAMPING 0x34
84 #define PWRGATE_STATUS 0x38
86 #define PMC_BLINK_TIMER 0x40
87 #define PMC_IMPL_E_33V_PWR 0x40
89 #define PMC_PWR_DET 0x48
91 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
92 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
93 #define PMC_SCRATCH0_MODE_RCM BIT(1)
94 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
95 PMC_SCRATCH0_MODE_BOOTLOADER | \
96 PMC_SCRATCH0_MODE_RCM)
98 #define PMC_CPUPWRGOOD_TIMER 0xc8
99 #define PMC_CPUPWROFF_TIMER 0xcc
100 #define PMC_COREPWRGOOD_TIMER 0x3c
101 #define PMC_COREPWROFF_TIMER 0xe0
103 #define PMC_PWR_DET_VALUE 0xe4
105 #define PMC_SCRATCH41 0x140
107 #define PMC_WAKE2_MASK 0x160
108 #define PMC_WAKE2_LEVEL 0x164
109 #define PMC_WAKE2_STATUS 0x168
110 #define PMC_SW_WAKE2_STATUS 0x16c
112 #define PMC_CLK_OUT_CNTRL 0x1a8
113 #define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0)
114 #define PMC_SENSOR_CTRL 0x1b0
115 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
116 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
118 #define PMC_RST_STATUS_POR 0
119 #define PMC_RST_STATUS_WATCHDOG 1
120 #define PMC_RST_STATUS_SENSOR 2
121 #define PMC_RST_STATUS_SW_MAIN 3
122 #define PMC_RST_STATUS_LP0 4
123 #define PMC_RST_STATUS_AOTAG 5
125 #define IO_DPD_REQ 0x1b8
126 #define IO_DPD_REQ_CODE_IDLE (0U << 30)
127 #define IO_DPD_REQ_CODE_OFF (1U << 30)
128 #define IO_DPD_REQ_CODE_ON (2U << 30)
129 #define IO_DPD_REQ_CODE_MASK (3U << 30)
131 #define IO_DPD_STATUS 0x1bc
132 #define IO_DPD2_REQ 0x1c0
133 #define IO_DPD2_STATUS 0x1c4
134 #define SEL_DPD_TIM 0x1c8
136 #define PMC_SCRATCH54 0x258
137 #define PMC_SCRATCH54_DATA_SHIFT 8
138 #define PMC_SCRATCH54_ADDR_SHIFT 0
140 #define PMC_SCRATCH55 0x25c
141 #define PMC_SCRATCH55_RESET_TEGRA BIT(31)
142 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
143 #define PMC_SCRATCH55_PINMUX_SHIFT 24
144 #define PMC_SCRATCH55_16BITOP BIT(15)
145 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
146 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
148 #define GPU_RG_CNTRL 0x2d4
150 /* Tegra186 and later */
151 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
152 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)
153 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))
154 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))
155 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))
156 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))
157 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
158 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
159 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
161 #define WAKE_AOWAKE_CTRL 0x4f4
162 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
165 #define TEGRA_SMC_PMC 0xc2fffe00
166 #define TEGRA_SMC_PMC_READ 0xaa
167 #define TEGRA_SMC_PMC_WRITE 0xbb
176 #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
178 struct pmc_clk_gate {
184 #define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
186 struct pmc_clk_init_data {
188 const char *const *parents;
195 static const char * const clk_out1_parents[] = { "osc", "osc_div2",
196 "osc_div4", "extern1",
199 static const char * const clk_out2_parents[] = { "osc", "osc_div2",
200 "osc_div4", "extern2",
203 static const char * const clk_out3_parents[] = { "osc", "osc_div2",
204 "osc_div4", "extern3",
207 static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
209 .name = "pmc_clk_out_1",
210 .parents = clk_out1_parents,
211 .num_parents = ARRAY_SIZE(clk_out1_parents),
212 .clk_id = TEGRA_PMC_CLK_OUT_1,
217 .name = "pmc_clk_out_2",
218 .parents = clk_out2_parents,
219 .num_parents = ARRAY_SIZE(clk_out2_parents),
220 .clk_id = TEGRA_PMC_CLK_OUT_2,
222 .force_en_shift = 10,
225 .name = "pmc_clk_out_3",
226 .parents = clk_out3_parents,
227 .num_parents = ARRAY_SIZE(clk_out3_parents),
228 .clk_id = TEGRA_PMC_CLK_OUT_3,
230 .force_en_shift = 18,
234 struct tegra_powergate {
235 struct generic_pm_domain genpd;
236 struct tegra_pmc *pmc;
239 unsigned int num_clks;
240 struct reset_control *reset;
243 struct tegra_io_pad_soc {
244 enum tegra_io_pad id;
246 unsigned int voltage;
250 struct tegra_pmc_regs {
251 unsigned int scratch0;
252 unsigned int dpd_req;
253 unsigned int dpd_status;
254 unsigned int dpd2_req;
255 unsigned int dpd2_status;
256 unsigned int rst_status;
257 unsigned int rst_source_shift;
258 unsigned int rst_source_mask;
259 unsigned int rst_level_shift;
260 unsigned int rst_level_mask;
263 struct tegra_wake_event {
268 unsigned int instance;
273 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \
279 .instance = UINT_MAX, \
284 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \
290 .instance = _instance, \
295 struct tegra_pmc_soc {
296 unsigned int num_powergates;
297 const char *const *powergates;
298 unsigned int num_cpu_powergates;
299 const u8 *cpu_powergates;
301 bool has_tsense_reset;
303 bool needs_mbist_war;
304 bool has_impl_33v_pwr;
307 const struct tegra_io_pad_soc *io_pads;
308 unsigned int num_io_pads;
310 const struct pinctrl_pin_desc *pin_descs;
311 unsigned int num_pin_descs;
313 const struct tegra_pmc_regs *regs;
314 void (*init)(struct tegra_pmc *pmc);
315 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
316 struct device_node *np,
318 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
319 int (*irq_set_type)(struct irq_data *data, unsigned int type);
321 const char * const *reset_sources;
322 unsigned int num_reset_sources;
323 const char * const *reset_levels;
324 unsigned int num_reset_levels;
327 * These describe events that can wake the system from sleep (i.e.
328 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2)
329 * are dealt with in the LIC.
331 const struct tegra_wake_event *wake_events;
332 unsigned int num_wake_events;
334 const struct pmc_clk_init_data *pmc_clks_data;
335 unsigned int num_pmc_clks;
336 bool has_blink_output;
339 static const char * const tegra186_reset_sources[] = {
357 static const char * const tegra186_reset_levels[] = {
358 "L0", "L1", "L2", "WARM"
361 static const char * const tegra30_reset_sources[] = {
369 static const char * const tegra210_reset_sources[] = {
379 * struct tegra_pmc - NVIDIA Tegra PMC
380 * @dev: pointer to PMC device structure
381 * @base: pointer to I/O remapped register region
382 * @wake: pointer to I/O remapped region for WAKE registers
383 * @aotag: pointer to I/O remapped region for AOTAG registers
384 * @scratch: pointer to I/O remapped region for scratch registers
385 * @clk: pointer to pclk clock
386 * @soc: pointer to SoC data structure
387 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone
388 * @debugfs: pointer to debugfs entry
389 * @rate: currently configured rate of pclk
390 * @suspend_mode: lowest suspend mode available
391 * @cpu_good_time: CPU power good time (in microseconds)
392 * @cpu_off_time: CPU power off time (in microsecends)
393 * @core_osc_time: core power good OSC time (in microseconds)
394 * @core_pmu_time: core power good PMU time (in microseconds)
395 * @core_off_time: core power off time (in microseconds)
396 * @corereq_high: core power request is active-high
397 * @sysclkreq_high: system clock request is active-high
398 * @combined_req: combined power request for CPU & core
399 * @cpu_pwr_good_en: CPU power good signal is enabled
400 * @lp0_vec_phys: physical base address of the LP0 warm boot code
401 * @lp0_vec_size: size of the LP0 warm boot code
402 * @powergates_available: Bitmap of available power gates
403 * @powergates_lock: mutex for power gate register access
404 * @pctl_dev: pin controller exposed by the PMC
405 * @domain: IRQ domain provided by the PMC
406 * @irq: chip implementation for the IRQ domain
407 * @clk_nb: pclk clock changes handler
414 void __iomem *scratch;
416 struct dentry *debugfs;
418 const struct tegra_pmc_soc *soc;
423 enum tegra_suspend_mode suspend_mode;
432 bool cpu_pwr_good_en;
435 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
437 struct mutex powergates_lock;
439 struct pinctrl_dev *pctl_dev;
441 struct irq_domain *domain;
444 struct notifier_block clk_nb;
447 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
449 .suspend_mode = TEGRA_SUSPEND_NONE,
452 static inline struct tegra_powergate *
453 to_powergate(struct generic_pm_domain *domain)
455 return container_of(domain, struct tegra_powergate, genpd);
458 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
460 struct arm_smccc_res res;
463 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
467 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
470 pr_warn("%s(): SMC failed: %lu\n", __func__,
477 return readl(pmc->base + offset);
480 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
481 unsigned long offset)
483 struct arm_smccc_res res;
486 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
487 value, 0, 0, 0, 0, &res);
490 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
493 pr_warn("%s(): SMC failed: %lu\n", __func__,
497 writel(value, pmc->base + offset);
501 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)
504 return tegra_pmc_readl(pmc, offset);
506 return readl(pmc->scratch + offset);
509 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
510 unsigned long offset)
513 tegra_pmc_writel(pmc, value, offset);
515 writel(value, pmc->scratch + offset);
519 * TODO Figure out a way to call this with the struct tegra_pmc * passed in.
520 * This currently doesn't work because readx_poll_timeout() can only operate
521 * on functions that take a single argument.
523 static inline bool tegra_powergate_state(int id)
525 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
526 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;
528 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;
531 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id)
533 return (pmc->soc && pmc->soc->powergates[id]);
536 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id)
538 return test_bit(id, pmc->powergates_available);
541 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
545 if (!pmc || !pmc->soc || !name)
548 for (i = 0; i < pmc->soc->num_powergates; i++) {
549 if (!tegra_powergate_is_valid(pmc, i))
552 if (!strcmp(name, pmc->soc->powergates[i]))
560 * tegra_powergate_set() - set the state of a partition
561 * @pmc: power management controller
563 * @new_state: new state of the partition
565 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id,
571 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
574 mutex_lock(&pmc->powergates_lock);
576 if (tegra_powergate_state(id) == new_state) {
577 mutex_unlock(&pmc->powergates_lock);
581 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
583 err = readx_poll_timeout(tegra_powergate_state, id, status,
584 status == new_state, 10, 100000);
586 mutex_unlock(&pmc->powergates_lock);
591 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
596 mutex_lock(&pmc->powergates_lock);
599 * On Tegra124 and later, the clamps for the GPU are controlled by a
600 * separate register (with different semantics).
602 if (id == TEGRA_POWERGATE_3D) {
603 if (pmc->soc->has_gpu_clamps) {
604 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);
610 * Tegra 2 has a bug where PCIE and VDE clamping masks are
611 * swapped relatively to the partition ids
613 if (id == TEGRA_POWERGATE_VDEC)
614 mask = (1 << TEGRA_POWERGATE_PCIE);
615 else if (id == TEGRA_POWERGATE_PCIE)
616 mask = (1 << TEGRA_POWERGATE_VDEC);
620 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);
623 mutex_unlock(&pmc->powergates_lock);
628 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
632 for (i = 0; i < pg->num_clks; i++)
633 clk_disable_unprepare(pg->clks[i]);
636 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
641 for (i = 0; i < pg->num_clks; i++) {
642 err = clk_prepare_enable(pg->clks[i]);
651 clk_disable_unprepare(pg->clks[i]);
656 int __weak tegra210_clk_handle_mbist_war(unsigned int id)
661 static int tegra_powergate_power_up(struct tegra_powergate *pg,
666 err = reset_control_assert(pg->reset);
670 usleep_range(10, 20);
672 err = tegra_powergate_set(pg->pmc, pg->id, true);
676 usleep_range(10, 20);
678 err = tegra_powergate_enable_clocks(pg);
682 usleep_range(10, 20);
684 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
688 usleep_range(10, 20);
690 err = reset_control_deassert(pg->reset);
694 usleep_range(10, 20);
696 if (pg->pmc->soc->needs_mbist_war)
697 err = tegra210_clk_handle_mbist_war(pg->id);
702 tegra_powergate_disable_clocks(pg);
707 tegra_powergate_disable_clocks(pg);
708 usleep_range(10, 20);
711 tegra_powergate_set(pg->pmc, pg->id, false);
716 static int tegra_powergate_power_down(struct tegra_powergate *pg)
720 err = tegra_powergate_enable_clocks(pg);
724 usleep_range(10, 20);
726 err = reset_control_assert(pg->reset);
730 usleep_range(10, 20);
732 tegra_powergate_disable_clocks(pg);
734 usleep_range(10, 20);
736 err = tegra_powergate_set(pg->pmc, pg->id, false);
743 tegra_powergate_enable_clocks(pg);
744 usleep_range(10, 20);
745 reset_control_deassert(pg->reset);
746 usleep_range(10, 20);
749 tegra_powergate_disable_clocks(pg);
754 static int tegra_genpd_power_on(struct generic_pm_domain *domain)
756 struct tegra_powergate *pg = to_powergate(domain);
757 struct device *dev = pg->pmc->dev;
760 err = tegra_powergate_power_up(pg, true);
762 dev_err(dev, "failed to turn on PM domain %s: %d\n",
763 pg->genpd.name, err);
767 reset_control_release(pg->reset);
773 static int tegra_genpd_power_off(struct generic_pm_domain *domain)
775 struct tegra_powergate *pg = to_powergate(domain);
776 struct device *dev = pg->pmc->dev;
779 err = reset_control_acquire(pg->reset);
781 pr_err("failed to acquire resets: %d\n", err);
785 err = tegra_powergate_power_down(pg);
787 dev_err(dev, "failed to turn off PM domain %s: %d\n",
788 pg->genpd.name, err);
789 reset_control_release(pg->reset);
796 * tegra_powergate_power_on() - power on partition
799 int tegra_powergate_power_on(unsigned int id)
801 if (!tegra_powergate_is_available(pmc, id))
804 return tegra_powergate_set(pmc, id, true);
806 EXPORT_SYMBOL(tegra_powergate_power_on);
809 * tegra_powergate_power_off() - power off partition
812 int tegra_powergate_power_off(unsigned int id)
814 if (!tegra_powergate_is_available(pmc, id))
817 return tegra_powergate_set(pmc, id, false);
819 EXPORT_SYMBOL(tegra_powergate_power_off);
822 * tegra_powergate_is_powered() - check if partition is powered
823 * @pmc: power management controller
826 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id)
828 if (!tegra_powergate_is_valid(pmc, id))
831 return tegra_powergate_state(id);
835 * tegra_powergate_remove_clamping() - remove power clamps for partition
838 int tegra_powergate_remove_clamping(unsigned int id)
840 if (!tegra_powergate_is_available(pmc, id))
843 return __tegra_powergate_remove_clamping(pmc, id);
845 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
848 * tegra_powergate_sequence_power_up() - power up partition
850 * @clk: clock for partition
851 * @rst: reset for partition
853 * Must be called with clk disabled, and returns with clk enabled.
855 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
856 struct reset_control *rst)
858 struct tegra_powergate *pg;
861 if (!tegra_powergate_is_available(pmc, id))
864 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
874 err = tegra_powergate_power_up(pg, false);
876 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
883 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
886 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
887 * @pmc: power management controller
888 * @cpuid: CPU partition ID
890 * Returns the partition ID corresponding to the CPU partition ID or a
891 * negative error code on failure.
893 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc,
896 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
897 return pmc->soc->cpu_powergates[cpuid];
903 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
904 * @cpuid: CPU partition ID
906 bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
910 id = tegra_get_cpu_powergate_id(pmc, cpuid);
914 return tegra_powergate_is_powered(pmc, id);
918 * tegra_pmc_cpu_power_on() - power on CPU partition
919 * @cpuid: CPU partition ID
921 int tegra_pmc_cpu_power_on(unsigned int cpuid)
925 id = tegra_get_cpu_powergate_id(pmc, cpuid);
929 return tegra_powergate_set(pmc, id, true);
933 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
934 * @cpuid: CPU partition ID
936 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
940 id = tegra_get_cpu_powergate_id(pmc, cpuid);
944 return tegra_powergate_remove_clamping(id);
947 static int tegra_pmc_restart_notify(struct notifier_block *this,
948 unsigned long action, void *data)
950 const char *cmd = data;
953 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
954 value &= ~PMC_SCRATCH0_MODE_MASK;
957 if (strcmp(cmd, "recovery") == 0)
958 value |= PMC_SCRATCH0_MODE_RECOVERY;
960 if (strcmp(cmd, "bootloader") == 0)
961 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
963 if (strcmp(cmd, "forced-recovery") == 0)
964 value |= PMC_SCRATCH0_MODE_RCM;
967 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
969 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
970 value = tegra_pmc_readl(pmc, PMC_CNTRL);
971 value |= PMC_CNTRL_MAIN_RST;
972 tegra_pmc_writel(pmc, value, PMC_CNTRL);
977 static struct notifier_block tegra_pmc_restart_handler = {
978 .notifier_call = tegra_pmc_restart_notify,
982 static int powergate_show(struct seq_file *s, void *data)
987 seq_printf(s, " powergate powered\n");
988 seq_printf(s, "------------------\n");
990 for (i = 0; i < pmc->soc->num_powergates; i++) {
991 status = tegra_powergate_is_powered(pmc, i);
995 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
996 status ? "yes" : "no");
1002 DEFINE_SHOW_ATTRIBUTE(powergate);
1004 static int tegra_powergate_debugfs_init(void)
1006 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
1014 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
1015 struct device_node *np)
1018 unsigned int i, count;
1021 count = of_clk_get_parent_count(np);
1025 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
1029 for (i = 0; i < count; i++) {
1030 pg->clks[i] = of_clk_get(np, i);
1031 if (IS_ERR(pg->clks[i])) {
1032 err = PTR_ERR(pg->clks[i]);
1037 pg->num_clks = count;
1043 clk_put(pg->clks[i]);
1050 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
1051 struct device_node *np, bool off)
1053 struct device *dev = pg->pmc->dev;
1056 pg->reset = of_reset_control_array_get_exclusive_released(np);
1057 if (IS_ERR(pg->reset)) {
1058 err = PTR_ERR(pg->reset);
1059 dev_err(dev, "failed to get device resets: %d\n", err);
1063 err = reset_control_acquire(pg->reset);
1065 pr_err("failed to acquire resets: %d\n", err);
1070 err = reset_control_assert(pg->reset);
1072 err = reset_control_deassert(pg->reset);
1076 reset_control_release(pg->reset);
1081 reset_control_release(pg->reset);
1082 reset_control_put(pg->reset);
1088 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
1090 struct device *dev = pmc->dev;
1091 struct tegra_powergate *pg;
1095 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
1099 id = tegra_powergate_lookup(pmc, np->name);
1101 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id);
1107 * Clear the bit for this powergate so it cannot be managed
1108 * directly via the legacy APIs for controlling powergates.
1110 clear_bit(id, pmc->powergates_available);
1113 pg->genpd.name = np->name;
1114 pg->genpd.power_off = tegra_genpd_power_off;
1115 pg->genpd.power_on = tegra_genpd_power_on;
1118 off = !tegra_powergate_is_powered(pmc, pg->id);
1120 err = tegra_powergate_of_get_clks(pg, np);
1122 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err);
1126 err = tegra_powergate_of_get_resets(pg, np, off);
1128 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err);
1132 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
1134 WARN_ON(tegra_powergate_power_up(pg, true));
1139 err = pm_genpd_init(&pg->genpd, NULL, off);
1141 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np,
1146 err = of_genpd_add_provider_simple(np, &pg->genpd);
1148 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n",
1153 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name);
1158 pm_genpd_remove(&pg->genpd);
1161 reset_control_put(pg->reset);
1164 while (pg->num_clks--)
1165 clk_put(pg->clks[pg->num_clks]);
1170 set_bit(id, pmc->powergates_available);
1178 static int tegra_powergate_init(struct tegra_pmc *pmc,
1179 struct device_node *parent)
1181 struct device_node *np, *child;
1184 np = of_get_child_by_name(parent, "powergates");
1188 for_each_child_of_node(np, child) {
1189 err = tegra_powergate_add(pmc, child);
1201 static void tegra_powergate_remove(struct generic_pm_domain *genpd)
1203 struct tegra_powergate *pg = to_powergate(genpd);
1205 reset_control_put(pg->reset);
1207 while (pg->num_clks--)
1208 clk_put(pg->clks[pg->num_clks]);
1212 set_bit(pg->id, pmc->powergates_available);
1217 static void tegra_powergate_remove_all(struct device_node *parent)
1219 struct generic_pm_domain *genpd;
1220 struct device_node *np, *child;
1222 np = of_get_child_by_name(parent, "powergates");
1226 for_each_child_of_node(np, child) {
1227 of_genpd_del_provider(child);
1229 genpd = of_genpd_remove_last(child);
1233 tegra_powergate_remove(genpd);
1239 static const struct tegra_io_pad_soc *
1240 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
1244 for (i = 0; i < pmc->soc->num_io_pads; i++)
1245 if (pmc->soc->io_pads[i].id == id)
1246 return &pmc->soc->io_pads[i];
1251 static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc,
1252 enum tegra_io_pad id,
1253 unsigned long *request,
1254 unsigned long *status,
1257 const struct tegra_io_pad_soc *pad;
1259 pad = tegra_io_pad_find(pmc, id);
1261 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1265 if (pad->dpd == UINT_MAX)
1268 *mask = BIT(pad->dpd % 32);
1270 if (pad->dpd < 32) {
1271 *status = pmc->soc->regs->dpd_status;
1272 *request = pmc->soc->regs->dpd_req;
1274 *status = pmc->soc->regs->dpd2_status;
1275 *request = pmc->soc->regs->dpd2_req;
1281 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id,
1282 unsigned long *request, unsigned long *status,
1285 unsigned long rate, value;
1288 err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask);
1295 dev_err(pmc->dev, "failed to get clock rate\n");
1299 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);
1301 /* must be at least 200 ns, in APB (PCLK) clock cycles */
1302 value = DIV_ROUND_UP(1000000000, rate);
1303 value = DIV_ROUND_UP(200, value);
1304 tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
1310 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset,
1311 u32 mask, u32 val, unsigned long timeout)
1315 timeout = jiffies + msecs_to_jiffies(timeout);
1317 while (time_after(timeout, jiffies)) {
1318 value = tegra_pmc_readl(pmc, offset);
1319 if ((value & mask) == val)
1322 usleep_range(250, 1000);
1328 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)
1331 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);
1335 * tegra_io_pad_power_enable() - enable power to I/O pad
1336 * @id: Tegra I/O pad ID for which to enable power
1338 * Returns: 0 on success or a negative error code on failure.
1340 int tegra_io_pad_power_enable(enum tegra_io_pad id)
1342 unsigned long request, status;
1346 mutex_lock(&pmc->powergates_lock);
1348 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1350 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1354 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);
1356 err = tegra_io_pad_poll(pmc, status, mask, 0, 250);
1358 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err);
1362 tegra_io_pad_unprepare(pmc);
1365 mutex_unlock(&pmc->powergates_lock);
1368 EXPORT_SYMBOL(tegra_io_pad_power_enable);
1371 * tegra_io_pad_power_disable() - disable power to I/O pad
1372 * @id: Tegra I/O pad ID for which to disable power
1374 * Returns: 0 on success or a negative error code on failure.
1376 int tegra_io_pad_power_disable(enum tegra_io_pad id)
1378 unsigned long request, status;
1382 mutex_lock(&pmc->powergates_lock);
1384 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1386 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1390 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);
1392 err = tegra_io_pad_poll(pmc, status, mask, mask, 250);
1394 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err);
1398 tegra_io_pad_unprepare(pmc);
1401 mutex_unlock(&pmc->powergates_lock);
1404 EXPORT_SYMBOL(tegra_io_pad_power_disable);
1406 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)
1408 unsigned long request, status;
1412 err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status,
1417 value = tegra_pmc_readl(pmc, status);
1419 return !(value & mask);
1422 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,
1425 const struct tegra_io_pad_soc *pad;
1428 pad = tegra_io_pad_find(pmc, id);
1432 if (pad->voltage == UINT_MAX)
1435 mutex_lock(&pmc->powergates_lock);
1437 if (pmc->soc->has_impl_33v_pwr) {
1438 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1440 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1441 value &= ~BIT(pad->voltage);
1443 value |= BIT(pad->voltage);
1445 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
1447 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1448 value = tegra_pmc_readl(pmc, PMC_PWR_DET);
1449 value |= BIT(pad->voltage);
1450 tegra_pmc_writel(pmc, value, PMC_PWR_DET);
1452 /* update I/O voltage */
1453 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1455 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1456 value &= ~BIT(pad->voltage);
1458 value |= BIT(pad->voltage);
1460 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
1463 mutex_unlock(&pmc->powergates_lock);
1465 usleep_range(100, 250);
1470 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)
1472 const struct tegra_io_pad_soc *pad;
1475 pad = tegra_io_pad_find(pmc, id);
1479 if (pad->voltage == UINT_MAX)
1482 if (pmc->soc->has_impl_33v_pwr)
1483 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1485 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1487 if ((value & BIT(pad->voltage)) == 0)
1488 return TEGRA_IO_PAD_VOLTAGE_1V8;
1490 return TEGRA_IO_PAD_VOLTAGE_3V3;
1494 * tegra_io_rail_power_on() - enable power to I/O rail
1495 * @id: Tegra I/O pad ID for which to enable power
1497 * See also: tegra_io_pad_power_enable()
1499 int tegra_io_rail_power_on(unsigned int id)
1501 return tegra_io_pad_power_enable(id);
1503 EXPORT_SYMBOL(tegra_io_rail_power_on);
1506 * tegra_io_rail_power_off() - disable power to I/O rail
1507 * @id: Tegra I/O pad ID for which to disable power
1509 * See also: tegra_io_pad_power_disable()
1511 int tegra_io_rail_power_off(unsigned int id)
1513 return tegra_io_pad_power_disable(id);
1515 EXPORT_SYMBOL(tegra_io_rail_power_off);
1517 #ifdef CONFIG_PM_SLEEP
1518 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1520 return pmc->suspend_mode;
1523 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1525 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1528 pmc->suspend_mode = mode;
1531 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1533 unsigned long long rate = 0;
1538 case TEGRA_SUSPEND_LP1:
1542 case TEGRA_SUSPEND_LP2:
1550 if (WARN_ON_ONCE(rate == 0))
1553 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1554 do_div(ticks, USEC_PER_SEC);
1555 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
1557 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1558 do_div(ticks, USEC_PER_SEC);
1559 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
1561 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1562 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1563 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1564 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1568 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1570 u32 value, values[2];
1572 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1576 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1580 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1584 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1588 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1593 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1595 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1596 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1598 pmc->cpu_good_time = value;
1600 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1601 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1603 pmc->cpu_off_time = value;
1605 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1606 values, ARRAY_SIZE(values)))
1607 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1609 pmc->core_osc_time = values[0];
1610 pmc->core_pmu_time = values[1];
1612 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1613 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1615 pmc->core_off_time = value;
1617 pmc->corereq_high = of_property_read_bool(np,
1618 "nvidia,core-power-req-active-high");
1620 pmc->sysclkreq_high = of_property_read_bool(np,
1621 "nvidia,sys-clock-req-active-high");
1623 pmc->combined_req = of_property_read_bool(np,
1624 "nvidia,combined-power-req");
1626 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1627 "nvidia,cpu-pwr-good-en");
1629 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1630 ARRAY_SIZE(values)))
1631 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1632 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1634 pmc->lp0_vec_phys = values[0];
1635 pmc->lp0_vec_size = values[1];
1640 static void tegra_pmc_init(struct tegra_pmc *pmc)
1643 pmc->soc->init(pmc);
1646 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1648 static const char disabled[] = "emergency thermal reset disabled";
1649 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1650 struct device *dev = pmc->dev;
1651 struct device_node *np;
1652 u32 value, checksum;
1654 if (!pmc->soc->has_tsense_reset)
1657 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
1659 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1663 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1664 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1668 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1669 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1673 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) {
1674 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1678 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) {
1679 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1683 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1686 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1687 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1688 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1690 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1691 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1692 tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
1694 value = PMC_SCRATCH55_RESET_TEGRA;
1695 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1696 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1697 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1700 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
1701 * contain the checksum and are currently zero, so they are not added.
1703 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1704 + ((value >> 24) & 0xff);
1706 checksum = 0x100 - checksum;
1708 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1710 tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
1712 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1713 value |= PMC_SENSOR_CTRL_ENABLE_RST;
1714 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1716 dev_info(pmc->dev, "emergency thermal reset enabled\n");
1722 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev)
1724 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1726 return pmc->soc->num_io_pads;
1729 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl,
1732 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl);
1734 return pmc->soc->io_pads[group].name;
1737 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev,
1739 const unsigned int **pins,
1740 unsigned int *num_pins)
1742 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1744 *pins = &pmc->soc->io_pads[group].id;
1750 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = {
1751 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count,
1752 .get_group_name = tegra_io_pad_pinctrl_get_group_name,
1753 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins,
1754 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1755 .dt_free_map = pinconf_generic_dt_free_map,
1758 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev,
1759 unsigned int pin, unsigned long *config)
1761 enum pin_config_param param = pinconf_to_config_param(*config);
1762 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1763 const struct tegra_io_pad_soc *pad;
1767 pad = tegra_io_pad_find(pmc, pin);
1772 case PIN_CONFIG_POWER_SOURCE:
1773 ret = tegra_io_pad_get_voltage(pmc, pad->id);
1780 case PIN_CONFIG_LOW_POWER_MODE:
1781 ret = tegra_io_pad_is_powered(pmc, pad->id);
1792 *config = pinconf_to_config_packed(param, arg);
1797 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev,
1798 unsigned int pin, unsigned long *configs,
1799 unsigned int num_configs)
1801 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1802 const struct tegra_io_pad_soc *pad;
1803 enum pin_config_param param;
1808 pad = tegra_io_pad_find(pmc, pin);
1812 for (i = 0; i < num_configs; ++i) {
1813 param = pinconf_to_config_param(configs[i]);
1814 arg = pinconf_to_config_argument(configs[i]);
1817 case PIN_CONFIG_LOW_POWER_MODE:
1819 err = tegra_io_pad_power_disable(pad->id);
1821 err = tegra_io_pad_power_enable(pad->id);
1825 case PIN_CONFIG_POWER_SOURCE:
1826 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 &&
1827 arg != TEGRA_IO_PAD_VOLTAGE_3V3)
1829 err = tegra_io_pad_set_voltage(pmc, pad->id, arg);
1841 static const struct pinconf_ops tegra_io_pad_pinconf_ops = {
1842 .pin_config_get = tegra_io_pad_pinconf_get,
1843 .pin_config_set = tegra_io_pad_pinconf_set,
1847 static struct pinctrl_desc tegra_pmc_pctl_desc = {
1848 .pctlops = &tegra_io_pad_pinctrl_ops,
1849 .confops = &tegra_io_pad_pinconf_ops,
1852 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
1856 if (!pmc->soc->num_pin_descs)
1859 tegra_pmc_pctl_desc.name = dev_name(pmc->dev);
1860 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs;
1861 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs;
1863 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc,
1865 if (IS_ERR(pmc->pctl_dev)) {
1866 err = PTR_ERR(pmc->pctl_dev);
1867 dev_err(pmc->dev, "failed to register pin controller: %d\n",
1875 static ssize_t reset_reason_show(struct device *dev,
1876 struct device_attribute *attr, char *buf)
1880 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
1881 value &= pmc->soc->regs->rst_source_mask;
1882 value >>= pmc->soc->regs->rst_source_shift;
1884 if (WARN_ON(value >= pmc->soc->num_reset_sources))
1885 return sprintf(buf, "%s\n", "UNKNOWN");
1887 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
1890 static DEVICE_ATTR_RO(reset_reason);
1892 static ssize_t reset_level_show(struct device *dev,
1893 struct device_attribute *attr, char *buf)
1897 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
1898 value &= pmc->soc->regs->rst_level_mask;
1899 value >>= pmc->soc->regs->rst_level_shift;
1901 if (WARN_ON(value >= pmc->soc->num_reset_levels))
1902 return sprintf(buf, "%s\n", "UNKNOWN");
1904 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
1907 static DEVICE_ATTR_RO(reset_level);
1909 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
1911 struct device *dev = pmc->dev;
1914 if (pmc->soc->reset_sources) {
1915 err = device_create_file(dev, &dev_attr_reset_reason);
1918 "failed to create attr \"reset_reason\": %d\n",
1922 if (pmc->soc->reset_levels) {
1923 err = device_create_file(dev, &dev_attr_reset_level);
1926 "failed to create attr \"reset_level\": %d\n",
1931 static int tegra_pmc_irq_translate(struct irq_domain *domain,
1932 struct irq_fwspec *fwspec,
1933 unsigned long *hwirq,
1936 if (WARN_ON(fwspec->param_count < 2))
1939 *hwirq = fwspec->param[0];
1940 *type = fwspec->param[1];
1945 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq,
1946 unsigned int num_irqs, void *data)
1948 struct tegra_pmc *pmc = domain->host_data;
1949 const struct tegra_pmc_soc *soc = pmc->soc;
1950 struct irq_fwspec *fwspec = data;
1954 if (WARN_ON(num_irqs > 1))
1957 for (i = 0; i < soc->num_wake_events; i++) {
1958 const struct tegra_wake_event *event = &soc->wake_events[i];
1960 if (fwspec->param_count == 2) {
1961 struct irq_fwspec spec;
1963 if (event->id != fwspec->param[0])
1966 err = irq_domain_set_hwirq_and_chip(domain, virq,
1972 spec.fwnode = &pmc->dev->of_node->fwnode;
1973 spec.param_count = 3;
1974 spec.param[0] = GIC_SPI;
1975 spec.param[1] = event->irq;
1976 spec.param[2] = fwspec->param[1];
1978 err = irq_domain_alloc_irqs_parent(domain, virq,
1984 if (fwspec->param_count == 3) {
1985 if (event->gpio.instance != fwspec->param[0] ||
1986 event->gpio.pin != fwspec->param[1])
1989 err = irq_domain_set_hwirq_and_chip(domain, virq,
1994 * GPIOs don't have an equivalent interrupt in the
1995 * parent controller (GIC). However some code, such
1996 * as the one in irq_get_irqchip_state(), require a
1997 * valid IRQ chip to be set. Make sure that's the
1998 * case by passing NULL here, which will install a
1999 * dummy IRQ chip for the interrupt in the parent
2003 irq_domain_set_hwirq_and_chip(domain->parent,
2012 * For interrupts that don't have associated wake events, assign a
2013 * dummy hardware IRQ number. This is used in the ->irq_set_type()
2014 * and ->irq_set_wake() callbacks to return early for these IRQs.
2016 if (i == soc->num_wake_events) {
2017 err = irq_domain_set_hwirq_and_chip(domain, virq, ULONG_MAX,
2021 * Interrupts without a wake event don't have a corresponding
2022 * interrupt in the parent controller (GIC). Pass NULL for the
2023 * chip here, which causes a dummy IRQ chip to be installed
2024 * for the interrupt in the parent domain, to make this
2028 irq_domain_set_hwirq_and_chip(domain->parent, virq, 0,
2035 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {
2036 .translate = tegra_pmc_irq_translate,
2037 .alloc = tegra_pmc_irq_alloc,
2040 static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2042 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2043 unsigned int offset, bit;
2046 if (data->hwirq == ULONG_MAX)
2049 offset = data->hwirq / 32;
2050 bit = data->hwirq % 32;
2052 /* clear wake status */
2053 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);
2054 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);
2056 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);
2057 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);
2059 /* enable PMC wake */
2060 if (data->hwirq >= 32)
2061 offset = PMC_WAKE2_MASK;
2063 offset = PMC_WAKE_MASK;
2065 value = tegra_pmc_readl(pmc, offset);
2072 tegra_pmc_writel(pmc, value, offset);
2077 static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2079 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2080 unsigned int offset, bit;
2083 if (data->hwirq == ULONG_MAX)
2086 offset = data->hwirq / 32;
2087 bit = data->hwirq % 32;
2089 if (data->hwirq >= 32)
2090 offset = PMC_WAKE2_LEVEL;
2092 offset = PMC_WAKE_LEVEL;
2094 value = tegra_pmc_readl(pmc, offset);
2097 case IRQ_TYPE_EDGE_RISING:
2098 case IRQ_TYPE_LEVEL_HIGH:
2102 case IRQ_TYPE_EDGE_FALLING:
2103 case IRQ_TYPE_LEVEL_LOW:
2107 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2115 tegra_pmc_writel(pmc, value, offset);
2120 static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2122 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2123 unsigned int offset, bit;
2126 /* nothing to do if there's no associated wake event */
2127 if (WARN_ON(data->hwirq == ULONG_MAX))
2130 offset = data->hwirq / 32;
2131 bit = data->hwirq % 32;
2133 /* clear wake status */
2134 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
2136 /* route wake to tier 2 */
2137 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2140 value &= ~(1 << bit);
2144 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2146 /* enable wakeup event */
2147 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
2152 static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2154 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2157 /* nothing to do if there's no associated wake event */
2158 if (data->hwirq == ULONG_MAX)
2161 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2164 case IRQ_TYPE_EDGE_RISING:
2165 case IRQ_TYPE_LEVEL_HIGH:
2166 value |= WAKE_AOWAKE_CNTRL_LEVEL;
2169 case IRQ_TYPE_EDGE_FALLING:
2170 case IRQ_TYPE_LEVEL_LOW:
2171 value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
2174 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2175 value ^= WAKE_AOWAKE_CNTRL_LEVEL;
2182 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2187 static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
2189 struct irq_domain *parent = NULL;
2190 struct device_node *np;
2192 np = of_irq_find_parent(pmc->dev->of_node);
2194 parent = irq_find_host(np);
2201 pmc->irq.name = dev_name(pmc->dev);
2202 pmc->irq.irq_mask = irq_chip_mask_parent;
2203 pmc->irq.irq_unmask = irq_chip_unmask_parent;
2204 pmc->irq.irq_eoi = irq_chip_eoi_parent;
2205 pmc->irq.irq_set_affinity = irq_chip_set_affinity_parent;
2206 pmc->irq.irq_set_type = pmc->soc->irq_set_type;
2207 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake;
2209 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,
2210 &tegra_pmc_irq_domain_ops, pmc);
2212 dev_err(pmc->dev, "failed to allocate domain\n");
2219 static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
2220 unsigned long action, void *ptr)
2222 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb);
2223 struct clk_notifier_data *data = ptr;
2226 case PRE_RATE_CHANGE:
2227 mutex_lock(&pmc->powergates_lock);
2230 case POST_RATE_CHANGE:
2231 pmc->rate = data->new_rate;
2234 case ABORT_RATE_CHANGE:
2235 mutex_unlock(&pmc->powergates_lock);
2240 return notifier_from_errno(-EINVAL);
2246 static void pmc_clk_fence_udelay(u32 offset)
2248 tegra_pmc_readl(pmc, offset);
2249 /* pmc clk propagation delay 2 us */
2253 static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
2255 struct pmc_clk *clk = to_pmc_clk(hw);
2258 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
2259 val &= PMC_CLK_OUT_MUX_MASK;
2264 static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
2266 struct pmc_clk *clk = to_pmc_clk(hw);
2269 val = tegra_pmc_readl(pmc, clk->offs);
2270 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift);
2271 val |= index << clk->mux_shift;
2272 tegra_pmc_writel(pmc, val, clk->offs);
2273 pmc_clk_fence_udelay(clk->offs);
2278 static int pmc_clk_is_enabled(struct clk_hw *hw)
2280 struct pmc_clk *clk = to_pmc_clk(hw);
2283 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift);
2288 static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
2292 val = tegra_pmc_readl(pmc, offs);
2293 val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
2294 tegra_pmc_writel(pmc, val, offs);
2295 pmc_clk_fence_udelay(offs);
2298 static int pmc_clk_enable(struct clk_hw *hw)
2300 struct pmc_clk *clk = to_pmc_clk(hw);
2302 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1);
2307 static void pmc_clk_disable(struct clk_hw *hw)
2309 struct pmc_clk *clk = to_pmc_clk(hw);
2311 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0);
2314 static const struct clk_ops pmc_clk_ops = {
2315 .get_parent = pmc_clk_mux_get_parent,
2316 .set_parent = pmc_clk_mux_set_parent,
2317 .determine_rate = __clk_mux_determine_rate,
2318 .is_enabled = pmc_clk_is_enabled,
2319 .enable = pmc_clk_enable,
2320 .disable = pmc_clk_disable,
2324 tegra_pmc_clk_out_register(struct tegra_pmc *pmc,
2325 const struct pmc_clk_init_data *data,
2326 unsigned long offset)
2328 struct clk_init_data init;
2329 struct pmc_clk *pmc_clk;
2331 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL);
2333 return ERR_PTR(-ENOMEM);
2335 init.name = data->name;
2336 init.ops = &pmc_clk_ops;
2337 init.parent_names = data->parents;
2338 init.num_parents = data->num_parents;
2339 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
2340 CLK_SET_PARENT_GATE;
2342 pmc_clk->hw.init = &init;
2343 pmc_clk->offs = offset;
2344 pmc_clk->mux_shift = data->mux_shift;
2345 pmc_clk->force_en_shift = data->force_en_shift;
2347 return clk_register(NULL, &pmc_clk->hw);
2350 static int pmc_clk_gate_is_enabled(struct clk_hw *hw)
2352 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2354 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
2357 static int pmc_clk_gate_enable(struct clk_hw *hw)
2359 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2361 pmc_clk_set_state(gate->offs, gate->shift, 1);
2366 static void pmc_clk_gate_disable(struct clk_hw *hw)
2368 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2370 pmc_clk_set_state(gate->offs, gate->shift, 0);
2373 static const struct clk_ops pmc_clk_gate_ops = {
2374 .is_enabled = pmc_clk_gate_is_enabled,
2375 .enable = pmc_clk_gate_enable,
2376 .disable = pmc_clk_gate_disable,
2380 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name,
2381 const char *parent_name, unsigned long offset,
2384 struct clk_init_data init;
2385 struct pmc_clk_gate *gate;
2387 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL);
2389 return ERR_PTR(-ENOMEM);
2392 init.ops = &pmc_clk_gate_ops;
2393 init.parent_names = &parent_name;
2394 init.num_parents = 1;
2397 gate->hw.init = &init;
2398 gate->offs = offset;
2399 gate->shift = shift;
2401 return clk_register(NULL, &gate->hw);
2404 static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
2405 struct device_node *np)
2408 struct clk_onecell_data *clk_data;
2409 unsigned int num_clks;
2412 num_clks = pmc->soc->num_pmc_clks;
2413 if (pmc->soc->has_blink_output)
2419 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL);
2423 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX,
2424 sizeof(*clk_data->clks), GFP_KERNEL);
2425 if (!clk_data->clks)
2428 clk_data->clk_num = TEGRA_PMC_CLK_MAX;
2430 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
2431 clk_data->clks[i] = ERR_PTR(-ENOENT);
2433 for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
2434 const struct pmc_clk_init_data *data;
2436 data = pmc->soc->pmc_clks_data + i;
2438 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL);
2440 dev_warn(pmc->dev, "unable to register clock %s: %d\n",
2441 data->name, PTR_ERR_OR_ZERO(clk));
2445 err = clk_register_clkdev(clk, data->name, NULL);
2448 "unable to register %s clock lookup: %d\n",
2453 clk_data->clks[data->clk_id] = clk;
2456 if (pmc->soc->has_blink_output) {
2457 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER);
2458 clk = tegra_pmc_clk_gate_register(pmc,
2459 "pmc_blink_override",
2462 PMC_DPD_PADS_ORIDE_BLINK);
2465 "unable to register pmc_blink_override: %d\n",
2466 PTR_ERR_OR_ZERO(clk));
2470 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink",
2471 "pmc_blink_override",
2473 PMC_CNTRL_BLINK_EN);
2476 "unable to register pmc_blink: %d\n",
2477 PTR_ERR_OR_ZERO(clk));
2481 err = clk_register_clkdev(clk, "pmc_blink", NULL);
2484 "unable to register pmc_blink lookup: %d\n",
2489 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk;
2492 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
2494 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n",
2498 static int tegra_pmc_probe(struct platform_device *pdev)
2501 struct resource *res;
2505 * Early initialisation should have configured an initial
2506 * register mapping and setup the soc data pointer. If these
2507 * are not valid then something went badly wrong!
2509 if (WARN_ON(!pmc->base || !pmc->soc))
2512 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
2516 /* take over the memory region from the early initialization */
2517 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2518 base = devm_ioremap_resource(&pdev->dev, res);
2520 return PTR_ERR(base);
2522 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
2524 pmc->wake = devm_ioremap_resource(&pdev->dev, res);
2525 if (IS_ERR(pmc->wake))
2526 return PTR_ERR(pmc->wake);
2531 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
2533 pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
2534 if (IS_ERR(pmc->aotag))
2535 return PTR_ERR(pmc->aotag);
2540 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
2542 pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
2543 if (IS_ERR(pmc->scratch))
2544 return PTR_ERR(pmc->scratch);
2546 pmc->scratch = base;
2549 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
2550 if (IS_ERR(pmc->clk)) {
2551 err = PTR_ERR(pmc->clk);
2553 if (err != -ENOENT) {
2554 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
2562 * PCLK clock rate can't be retrieved using CLK API because it
2563 * causes lockup if CPU enters LP2 idle state from some other
2564 * CLK notifier, hence we're caching the rate's value locally.
2567 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb;
2568 err = clk_notifier_register(pmc->clk, &pmc->clk_nb);
2571 "failed to register clk notifier\n");
2575 pmc->rate = clk_get_rate(pmc->clk);
2578 pmc->dev = &pdev->dev;
2580 tegra_pmc_init(pmc);
2582 tegra_pmc_init_tsense_reset(pmc);
2584 tegra_pmc_reset_sysfs_init(pmc);
2586 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2587 err = tegra_powergate_debugfs_init();
2592 err = register_restart_handler(&tegra_pmc_restart_handler);
2594 dev_err(&pdev->dev, "unable to register restart handler, %d\n",
2596 goto cleanup_debugfs;
2599 err = tegra_pmc_pinctrl_init(pmc);
2601 goto cleanup_restart_handler;
2603 err = tegra_powergate_init(pmc, pdev->dev.of_node);
2605 goto cleanup_powergates;
2607 err = tegra_pmc_irq_init(pmc);
2609 goto cleanup_powergates;
2611 mutex_lock(&pmc->powergates_lock);
2614 mutex_unlock(&pmc->powergates_lock);
2616 tegra_pmc_clock_register(pmc, pdev->dev.of_node);
2617 platform_set_drvdata(pdev, pmc);
2622 tegra_powergate_remove_all(pdev->dev.of_node);
2623 cleanup_restart_handler:
2624 unregister_restart_handler(&tegra_pmc_restart_handler);
2626 debugfs_remove(pmc->debugfs);
2628 device_remove_file(&pdev->dev, &dev_attr_reset_reason);
2629 device_remove_file(&pdev->dev, &dev_attr_reset_level);
2630 clk_notifier_unregister(pmc->clk, &pmc->clk_nb);
2635 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
2636 static int tegra_pmc_suspend(struct device *dev)
2638 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2640 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);
2645 static int tegra_pmc_resume(struct device *dev)
2647 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2649 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);
2654 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
2658 static const char * const tegra20_powergates[] = {
2659 [TEGRA_POWERGATE_CPU] = "cpu",
2660 [TEGRA_POWERGATE_3D] = "3d",
2661 [TEGRA_POWERGATE_VENC] = "venc",
2662 [TEGRA_POWERGATE_VDEC] = "vdec",
2663 [TEGRA_POWERGATE_PCIE] = "pcie",
2664 [TEGRA_POWERGATE_L2] = "l2",
2665 [TEGRA_POWERGATE_MPE] = "mpe",
2668 static const struct tegra_pmc_regs tegra20_pmc_regs = {
2671 .dpd_status = 0x1bc,
2673 .dpd2_status = 0x1c4,
2674 .rst_status = 0x1b4,
2675 .rst_source_shift = 0x0,
2676 .rst_source_mask = 0x7,
2677 .rst_level_shift = 0x0,
2678 .rst_level_mask = 0x0,
2681 static void tegra20_pmc_init(struct tegra_pmc *pmc)
2683 u32 value, osc, pmu, off;
2685 /* Always enable CPU power request */
2686 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2687 value |= PMC_CNTRL_CPU_PWRREQ_OE;
2688 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2690 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2692 if (pmc->sysclkreq_high)
2693 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
2695 value |= PMC_CNTRL_SYSCLK_POLARITY;
2697 if (pmc->corereq_high)
2698 value &= ~PMC_CNTRL_PWRREQ_POLARITY;
2700 value |= PMC_CNTRL_PWRREQ_POLARITY;
2702 /* configure the output polarity while the request is tristated */
2703 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2705 /* now enable the request */
2706 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2707 value |= PMC_CNTRL_SYSCLK_OE;
2708 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2710 /* program core timings which are applicable only for suspend state */
2711 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) {
2712 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000);
2713 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000);
2714 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000);
2715 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),
2716 PMC_COREPWRGOOD_TIMER);
2717 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);
2721 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
2722 struct device_node *np,
2727 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2730 value |= PMC_CNTRL_INTR_POLARITY;
2732 value &= ~PMC_CNTRL_INTR_POLARITY;
2734 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2737 static const struct tegra_pmc_soc tegra20_pmc_soc = {
2738 .num_powergates = ARRAY_SIZE(tegra20_powergates),
2739 .powergates = tegra20_powergates,
2740 .num_cpu_powergates = 0,
2741 .cpu_powergates = NULL,
2742 .has_tsense_reset = false,
2743 .has_gpu_clamps = false,
2744 .needs_mbist_war = false,
2745 .has_impl_33v_pwr = false,
2746 .maybe_tz_only = false,
2751 .regs = &tegra20_pmc_regs,
2752 .init = tegra20_pmc_init,
2753 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2754 .reset_sources = NULL,
2755 .num_reset_sources = 0,
2756 .reset_levels = NULL,
2757 .num_reset_levels = 0,
2758 .pmc_clks_data = NULL,
2760 .has_blink_output = true,
2763 static const char * const tegra30_powergates[] = {
2764 [TEGRA_POWERGATE_CPU] = "cpu0",
2765 [TEGRA_POWERGATE_3D] = "3d0",
2766 [TEGRA_POWERGATE_VENC] = "venc",
2767 [TEGRA_POWERGATE_VDEC] = "vdec",
2768 [TEGRA_POWERGATE_PCIE] = "pcie",
2769 [TEGRA_POWERGATE_L2] = "l2",
2770 [TEGRA_POWERGATE_MPE] = "mpe",
2771 [TEGRA_POWERGATE_HEG] = "heg",
2772 [TEGRA_POWERGATE_SATA] = "sata",
2773 [TEGRA_POWERGATE_CPU1] = "cpu1",
2774 [TEGRA_POWERGATE_CPU2] = "cpu2",
2775 [TEGRA_POWERGATE_CPU3] = "cpu3",
2776 [TEGRA_POWERGATE_CELP] = "celp",
2777 [TEGRA_POWERGATE_3D1] = "3d1",
2780 static const u8 tegra30_cpu_powergates[] = {
2781 TEGRA_POWERGATE_CPU,
2782 TEGRA_POWERGATE_CPU1,
2783 TEGRA_POWERGATE_CPU2,
2784 TEGRA_POWERGATE_CPU3,
2787 static const struct tegra_pmc_soc tegra30_pmc_soc = {
2788 .num_powergates = ARRAY_SIZE(tegra30_powergates),
2789 .powergates = tegra30_powergates,
2790 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
2791 .cpu_powergates = tegra30_cpu_powergates,
2792 .has_tsense_reset = true,
2793 .has_gpu_clamps = false,
2794 .needs_mbist_war = false,
2795 .has_impl_33v_pwr = false,
2796 .maybe_tz_only = false,
2801 .regs = &tegra20_pmc_regs,
2802 .init = tegra20_pmc_init,
2803 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2804 .reset_sources = tegra30_reset_sources,
2805 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2806 .reset_levels = NULL,
2807 .num_reset_levels = 0,
2808 .pmc_clks_data = tegra_pmc_clks_data,
2809 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
2810 .has_blink_output = true,
2813 static const char * const tegra114_powergates[] = {
2814 [TEGRA_POWERGATE_CPU] = "crail",
2815 [TEGRA_POWERGATE_3D] = "3d",
2816 [TEGRA_POWERGATE_VENC] = "venc",
2817 [TEGRA_POWERGATE_VDEC] = "vdec",
2818 [TEGRA_POWERGATE_MPE] = "mpe",
2819 [TEGRA_POWERGATE_HEG] = "heg",
2820 [TEGRA_POWERGATE_CPU1] = "cpu1",
2821 [TEGRA_POWERGATE_CPU2] = "cpu2",
2822 [TEGRA_POWERGATE_CPU3] = "cpu3",
2823 [TEGRA_POWERGATE_CELP] = "celp",
2824 [TEGRA_POWERGATE_CPU0] = "cpu0",
2825 [TEGRA_POWERGATE_C0NC] = "c0nc",
2826 [TEGRA_POWERGATE_C1NC] = "c1nc",
2827 [TEGRA_POWERGATE_DIS] = "dis",
2828 [TEGRA_POWERGATE_DISB] = "disb",
2829 [TEGRA_POWERGATE_XUSBA] = "xusba",
2830 [TEGRA_POWERGATE_XUSBB] = "xusbb",
2831 [TEGRA_POWERGATE_XUSBC] = "xusbc",
2834 static const u8 tegra114_cpu_powergates[] = {
2835 TEGRA_POWERGATE_CPU0,
2836 TEGRA_POWERGATE_CPU1,
2837 TEGRA_POWERGATE_CPU2,
2838 TEGRA_POWERGATE_CPU3,
2841 static const struct tegra_pmc_soc tegra114_pmc_soc = {
2842 .num_powergates = ARRAY_SIZE(tegra114_powergates),
2843 .powergates = tegra114_powergates,
2844 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
2845 .cpu_powergates = tegra114_cpu_powergates,
2846 .has_tsense_reset = true,
2847 .has_gpu_clamps = false,
2848 .needs_mbist_war = false,
2849 .has_impl_33v_pwr = false,
2850 .maybe_tz_only = false,
2855 .regs = &tegra20_pmc_regs,
2856 .init = tegra20_pmc_init,
2857 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2858 .reset_sources = tegra30_reset_sources,
2859 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2860 .reset_levels = NULL,
2861 .num_reset_levels = 0,
2862 .pmc_clks_data = tegra_pmc_clks_data,
2863 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
2864 .has_blink_output = true,
2867 static const char * const tegra124_powergates[] = {
2868 [TEGRA_POWERGATE_CPU] = "crail",
2869 [TEGRA_POWERGATE_3D] = "3d",
2870 [TEGRA_POWERGATE_VENC] = "venc",
2871 [TEGRA_POWERGATE_PCIE] = "pcie",
2872 [TEGRA_POWERGATE_VDEC] = "vdec",
2873 [TEGRA_POWERGATE_MPE] = "mpe",
2874 [TEGRA_POWERGATE_HEG] = "heg",
2875 [TEGRA_POWERGATE_SATA] = "sata",
2876 [TEGRA_POWERGATE_CPU1] = "cpu1",
2877 [TEGRA_POWERGATE_CPU2] = "cpu2",
2878 [TEGRA_POWERGATE_CPU3] = "cpu3",
2879 [TEGRA_POWERGATE_CELP] = "celp",
2880 [TEGRA_POWERGATE_CPU0] = "cpu0",
2881 [TEGRA_POWERGATE_C0NC] = "c0nc",
2882 [TEGRA_POWERGATE_C1NC] = "c1nc",
2883 [TEGRA_POWERGATE_SOR] = "sor",
2884 [TEGRA_POWERGATE_DIS] = "dis",
2885 [TEGRA_POWERGATE_DISB] = "disb",
2886 [TEGRA_POWERGATE_XUSBA] = "xusba",
2887 [TEGRA_POWERGATE_XUSBB] = "xusbb",
2888 [TEGRA_POWERGATE_XUSBC] = "xusbc",
2889 [TEGRA_POWERGATE_VIC] = "vic",
2890 [TEGRA_POWERGATE_IRAM] = "iram",
2893 static const u8 tegra124_cpu_powergates[] = {
2894 TEGRA_POWERGATE_CPU0,
2895 TEGRA_POWERGATE_CPU1,
2896 TEGRA_POWERGATE_CPU2,
2897 TEGRA_POWERGATE_CPU3,
2900 #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \
2901 ((struct tegra_io_pad_soc) { \
2904 .voltage = (_voltage), \
2908 #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \
2909 ((struct pinctrl_pin_desc) { \
2914 #define TEGRA124_IO_PAD_TABLE(_pad) \
2915 /* .id .dpd .voltage .name */ \
2916 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
2917 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \
2918 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \
2919 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \
2920 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
2921 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \
2922 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \
2923 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
2924 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
2925 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
2926 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
2927 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
2928 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
2929 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \
2930 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
2931 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
2932 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \
2933 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
2934 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
2935 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
2936 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
2937 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \
2938 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \
2939 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \
2940 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \
2941 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
2942 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
2943 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
2944 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
2945 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias")
2947 static const struct tegra_io_pad_soc tegra124_io_pads[] = {
2948 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD)
2951 static const struct pinctrl_pin_desc tegra124_pin_descs[] = {
2952 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
2955 static const struct tegra_pmc_soc tegra124_pmc_soc = {
2956 .num_powergates = ARRAY_SIZE(tegra124_powergates),
2957 .powergates = tegra124_powergates,
2958 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
2959 .cpu_powergates = tegra124_cpu_powergates,
2960 .has_tsense_reset = true,
2961 .has_gpu_clamps = true,
2962 .needs_mbist_war = false,
2963 .has_impl_33v_pwr = false,
2964 .maybe_tz_only = false,
2965 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
2966 .io_pads = tegra124_io_pads,
2967 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs),
2968 .pin_descs = tegra124_pin_descs,
2969 .regs = &tegra20_pmc_regs,
2970 .init = tegra20_pmc_init,
2971 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2972 .reset_sources = tegra30_reset_sources,
2973 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2974 .reset_levels = NULL,
2975 .num_reset_levels = 0,
2976 .pmc_clks_data = tegra_pmc_clks_data,
2977 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
2978 .has_blink_output = true,
2981 static const char * const tegra210_powergates[] = {
2982 [TEGRA_POWERGATE_CPU] = "crail",
2983 [TEGRA_POWERGATE_3D] = "3d",
2984 [TEGRA_POWERGATE_VENC] = "venc",
2985 [TEGRA_POWERGATE_PCIE] = "pcie",
2986 [TEGRA_POWERGATE_MPE] = "mpe",
2987 [TEGRA_POWERGATE_SATA] = "sata",
2988 [TEGRA_POWERGATE_CPU1] = "cpu1",
2989 [TEGRA_POWERGATE_CPU2] = "cpu2",
2990 [TEGRA_POWERGATE_CPU3] = "cpu3",
2991 [TEGRA_POWERGATE_CPU0] = "cpu0",
2992 [TEGRA_POWERGATE_C0NC] = "c0nc",
2993 [TEGRA_POWERGATE_SOR] = "sor",
2994 [TEGRA_POWERGATE_DIS] = "dis",
2995 [TEGRA_POWERGATE_DISB] = "disb",
2996 [TEGRA_POWERGATE_XUSBA] = "xusba",
2997 [TEGRA_POWERGATE_XUSBB] = "xusbb",
2998 [TEGRA_POWERGATE_XUSBC] = "xusbc",
2999 [TEGRA_POWERGATE_VIC] = "vic",
3000 [TEGRA_POWERGATE_IRAM] = "iram",
3001 [TEGRA_POWERGATE_NVDEC] = "nvdec",
3002 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
3003 [TEGRA_POWERGATE_AUD] = "aud",
3004 [TEGRA_POWERGATE_DFD] = "dfd",
3005 [TEGRA_POWERGATE_VE2] = "ve2",
3008 static const u8 tegra210_cpu_powergates[] = {
3009 TEGRA_POWERGATE_CPU0,
3010 TEGRA_POWERGATE_CPU1,
3011 TEGRA_POWERGATE_CPU2,
3012 TEGRA_POWERGATE_CPU3,
3015 #define TEGRA210_IO_PAD_TABLE(_pad) \
3016 /* .id .dpd .voltage .name */ \
3017 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \
3018 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \
3019 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \
3020 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3021 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3022 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \
3023 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \
3024 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \
3025 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \
3026 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \
3027 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \
3028 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \
3029 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \
3030 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3031 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
3032 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
3033 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
3034 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \
3035 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \
3036 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \
3037 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
3038 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3039 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
3040 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3041 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
3042 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
3043 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3044 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \
3045 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \
3046 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \
3047 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \
3048 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \
3049 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \
3050 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3051 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3052 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3053 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \
3054 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias")
3056 static const struct tegra_io_pad_soc tegra210_io_pads[] = {
3057 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD)
3060 static const struct pinctrl_pin_desc tegra210_pin_descs[] = {
3061 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3064 static const struct tegra_wake_event tegra210_wake_events[] = {
3065 TEGRA_WAKE_IRQ("rtc", 16, 2),
3066 TEGRA_WAKE_IRQ("pmu", 51, 86),
3069 static const struct tegra_pmc_soc tegra210_pmc_soc = {
3070 .num_powergates = ARRAY_SIZE(tegra210_powergates),
3071 .powergates = tegra210_powergates,
3072 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
3073 .cpu_powergates = tegra210_cpu_powergates,
3074 .has_tsense_reset = true,
3075 .has_gpu_clamps = true,
3076 .needs_mbist_war = true,
3077 .has_impl_33v_pwr = false,
3078 .maybe_tz_only = true,
3079 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
3080 .io_pads = tegra210_io_pads,
3081 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
3082 .pin_descs = tegra210_pin_descs,
3083 .regs = &tegra20_pmc_regs,
3084 .init = tegra20_pmc_init,
3085 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3086 .irq_set_wake = tegra210_pmc_irq_set_wake,
3087 .irq_set_type = tegra210_pmc_irq_set_type,
3088 .reset_sources = tegra210_reset_sources,
3089 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
3090 .reset_levels = NULL,
3091 .num_reset_levels = 0,
3092 .num_wake_events = ARRAY_SIZE(tegra210_wake_events),
3093 .wake_events = tegra210_wake_events,
3094 .pmc_clks_data = tegra_pmc_clks_data,
3095 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3096 .has_blink_output = true,
3099 #define TEGRA186_IO_PAD_TABLE(_pad) \
3100 /* .id .dpd .voltage .name */ \
3101 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3102 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3103 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3104 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3105 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3106 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3107 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3108 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3109 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3110 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3111 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3112 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \
3113 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3114 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3115 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3116 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
3117 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3118 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3119 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3120 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \
3121 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
3122 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
3123 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \
3124 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \
3125 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \
3126 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
3127 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
3128 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
3129 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
3130 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
3131 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
3132 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \
3133 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
3134 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3135 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3136 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
3137 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3138 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3140 static const struct tegra_io_pad_soc tegra186_io_pads[] = {
3141 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD)
3144 static const struct pinctrl_pin_desc tegra186_pin_descs[] = {
3145 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3148 static const struct tegra_pmc_regs tegra186_pmc_regs = {
3153 .dpd2_status = 0x80,
3155 .rst_source_shift = 0x2,
3156 .rst_source_mask = 0x3c,
3157 .rst_level_shift = 0x0,
3158 .rst_level_mask = 0x3,
3161 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3162 struct device_node *np,
3165 struct resource regs;
3170 index = of_property_match_string(np, "reg-names", "wake");
3172 dev_err(pmc->dev, "failed to find PMC wake registers\n");
3176 of_address_to_resource(np, index, ®s);
3178 wake = ioremap(regs.start, resource_size(®s));
3180 dev_err(pmc->dev, "failed to map PMC wake registers\n");
3184 value = readl(wake + WAKE_AOWAKE_CTRL);
3187 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
3189 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
3191 writel(value, wake + WAKE_AOWAKE_CTRL);
3196 static const struct tegra_wake_event tegra186_wake_events[] = {
3197 TEGRA_WAKE_IRQ("pmu", 24, 209),
3198 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
3199 TEGRA_WAKE_IRQ("rtc", 73, 10),
3202 static const struct tegra_pmc_soc tegra186_pmc_soc = {
3203 .num_powergates = 0,
3205 .num_cpu_powergates = 0,
3206 .cpu_powergates = NULL,
3207 .has_tsense_reset = false,
3208 .has_gpu_clamps = false,
3209 .needs_mbist_war = false,
3210 .has_impl_33v_pwr = true,
3211 .maybe_tz_only = false,
3212 .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
3213 .io_pads = tegra186_io_pads,
3214 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
3215 .pin_descs = tegra186_pin_descs,
3216 .regs = &tegra186_pmc_regs,
3218 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3219 .irq_set_wake = tegra186_pmc_irq_set_wake,
3220 .irq_set_type = tegra186_pmc_irq_set_type,
3221 .reset_sources = tegra186_reset_sources,
3222 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),
3223 .reset_levels = tegra186_reset_levels,
3224 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3225 .num_wake_events = ARRAY_SIZE(tegra186_wake_events),
3226 .wake_events = tegra186_wake_events,
3227 .pmc_clks_data = NULL,
3229 .has_blink_output = false,
3232 #define TEGRA194_IO_PAD_TABLE(_pad) \
3233 /* .id .dpd .voltage .name */ \
3234 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3235 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3236 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3237 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3238 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3239 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3240 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3241 _pad(TEGRA_IO_PAD_EQOS, 8, UINT_MAX, "eqos"), \
3242 _pad(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, UINT_MAX, "pex-clk-2-bias"), \
3243 _pad(TEGRA_IO_PAD_PEX_CLK_2, 10, UINT_MAX, "pex-clk-2"), \
3244 _pad(TEGRA_IO_PAD_DAP3, 11, UINT_MAX, "dap3"), \
3245 _pad(TEGRA_IO_PAD_DAP5, 12, UINT_MAX, "dap5"), \
3246 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3247 _pad(TEGRA_IO_PAD_PWR_CTL, 15, UINT_MAX, "pwr-ctl"), \
3248 _pad(TEGRA_IO_PAD_SOC_GPIO53, 16, UINT_MAX, "soc-gpio53"), \
3249 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3250 _pad(TEGRA_IO_PAD_GP_PWM2, 18, UINT_MAX, "gp-pwm2"), \
3251 _pad(TEGRA_IO_PAD_GP_PWM3, 19, UINT_MAX, "gp-pwm3"), \
3252 _pad(TEGRA_IO_PAD_SOC_GPIO12, 20, UINT_MAX, "soc-gpio12"), \
3253 _pad(TEGRA_IO_PAD_SOC_GPIO13, 21, UINT_MAX, "soc-gpio13"), \
3254 _pad(TEGRA_IO_PAD_SOC_GPIO10, 22, UINT_MAX, "soc-gpio10"), \
3255 _pad(TEGRA_IO_PAD_UART4, 23, UINT_MAX, "uart4"), \
3256 _pad(TEGRA_IO_PAD_UART5, 24, UINT_MAX, "uart5"), \
3257 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
3258 _pad(TEGRA_IO_PAD_HDMI_DP3, 26, UINT_MAX, "hdmi-dp3"), \
3259 _pad(TEGRA_IO_PAD_HDMI_DP2, 27, UINT_MAX, "hdmi-dp2"), \
3260 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3261 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3262 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3263 _pad(TEGRA_IO_PAD_PEX_CTL2, 33, UINT_MAX, "pex-ctl2"), \
3264 _pad(TEGRA_IO_PAD_PEX_L0_RST_N, 34, UINT_MAX, "pex-l0-rst"), \
3265 _pad(TEGRA_IO_PAD_PEX_L1_RST_N, 35, UINT_MAX, "pex-l1-rst"), \
3266 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
3267 _pad(TEGRA_IO_PAD_PEX_L5_RST_N, 37, UINT_MAX, "pex-l5-rst"), \
3268 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
3269 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
3270 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
3271 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
3272 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
3273 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
3274 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
3275 _pad(TEGRA_IO_PAD_CSIG, 50, UINT_MAX, "csig"), \
3276 _pad(TEGRA_IO_PAD_CSIH, 51, UINT_MAX, "csih"), \
3277 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
3278 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3279 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3280 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
3281 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3282 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3284 static const struct tegra_io_pad_soc tegra194_io_pads[] = {
3285 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PAD)
3288 static const struct pinctrl_pin_desc tegra194_pin_descs[] = {
3289 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3292 static const struct tegra_pmc_regs tegra194_pmc_regs = {
3297 .dpd2_status = 0x80,
3299 .rst_source_shift = 0x2,
3300 .rst_source_mask = 0x7c,
3301 .rst_level_shift = 0x0,
3302 .rst_level_mask = 0x3,
3305 static const char * const tegra194_reset_sources[] = {
3329 static const struct tegra_wake_event tegra194_wake_events[] = {
3330 TEGRA_WAKE_IRQ("pmu", 24, 209),
3331 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)),
3332 TEGRA_WAKE_IRQ("rtc", 73, 10),
3335 static const struct tegra_pmc_soc tegra194_pmc_soc = {
3336 .num_powergates = 0,
3338 .num_cpu_powergates = 0,
3339 .cpu_powergates = NULL,
3340 .has_tsense_reset = false,
3341 .has_gpu_clamps = false,
3342 .needs_mbist_war = false,
3343 .has_impl_33v_pwr = true,
3344 .maybe_tz_only = false,
3345 .num_io_pads = ARRAY_SIZE(tegra194_io_pads),
3346 .io_pads = tegra194_io_pads,
3347 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs),
3348 .pin_descs = tegra194_pin_descs,
3349 .regs = &tegra194_pmc_regs,
3351 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3352 .irq_set_wake = tegra186_pmc_irq_set_wake,
3353 .irq_set_type = tegra186_pmc_irq_set_type,
3354 .reset_sources = tegra194_reset_sources,
3355 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources),
3356 .reset_levels = tegra186_reset_levels,
3357 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3358 .num_wake_events = ARRAY_SIZE(tegra194_wake_events),
3359 .wake_events = tegra194_wake_events,
3360 .pmc_clks_data = NULL,
3362 .has_blink_output = false,
3365 static const struct of_device_id tegra_pmc_match[] = {
3366 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
3367 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
3368 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
3369 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
3370 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
3371 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
3372 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
3373 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
3377 static struct platform_driver tegra_pmc_driver = {
3379 .name = "tegra-pmc",
3380 .suppress_bind_attrs = true,
3381 .of_match_table = tegra_pmc_match,
3382 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
3383 .pm = &tegra_pmc_pm_ops,
3386 .probe = tegra_pmc_probe,
3388 builtin_platform_driver(tegra_pmc_driver);
3390 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)
3394 saved = readl(pmc->base + pmc->soc->regs->scratch0);
3395 value = saved ^ 0xffffffff;
3397 if (value == 0xffffffff)
3400 /* write pattern and read it back */
3401 writel(value, pmc->base + pmc->soc->regs->scratch0);
3402 value = readl(pmc->base + pmc->soc->regs->scratch0);
3404 /* if we read all-zeroes, access is restricted to TZ only */
3406 pr_info("access to PMC is restricted to TZ\n");
3410 /* restore original value */
3411 writel(saved, pmc->base + pmc->soc->regs->scratch0);
3417 * Early initialization to allow access to registers in the very early boot
3420 static int __init tegra_pmc_early_init(void)
3422 const struct of_device_id *match;
3423 struct device_node *np;
3424 struct resource regs;
3428 mutex_init(&pmc->powergates_lock);
3430 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
3433 * Fall back to legacy initialization for 32-bit ARM only. All
3434 * 64-bit ARM device tree files for Tegra are required to have
3437 * This is for backwards-compatibility with old device trees
3438 * that didn't contain a PMC node. Note that in this case the
3439 * SoC data can't be matched and therefore powergating is
3442 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
3443 pr_warn("DT node not found, powergating disabled\n");
3445 regs.start = 0x7000e400;
3446 regs.end = 0x7000e7ff;
3447 regs.flags = IORESOURCE_MEM;
3449 pr_warn("Using memory region %pR\n", ®s);
3452 * At this point we're not running on Tegra, so play
3453 * nice with multi-platform kernels.
3459 * Extract information from the device tree if we've found a
3462 if (of_address_to_resource(np, 0, ®s) < 0) {
3463 pr_err("failed to get PMC registers\n");
3469 pmc->base = ioremap(regs.start, resource_size(®s));
3471 pr_err("failed to map PMC registers\n");
3477 pmc->soc = match->data;
3479 if (pmc->soc->maybe_tz_only)
3480 pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
3482 /* Create a bitmap of the available and valid partitions */
3483 for (i = 0; i < pmc->soc->num_powergates; i++)
3484 if (pmc->soc->powergates[i])
3485 set_bit(i, pmc->powergates_available);
3488 * Invert the interrupt polarity if a PMC device tree node
3489 * exists and contains the nvidia,invert-interrupt property.
3491 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
3493 pmc->soc->setup_irq_polarity(pmc, np, invert);
3500 early_initcall(tegra_pmc_early_init);