1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/soc/tegra/pmc.c
5 * Copyright (c) 2010 Google, Inc
6 * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
9 * Colin Cross <ccross@google.com>
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/clkdev.h>
18 #include <linux/clk/clk-conf.h>
19 #include <linux/clk/tegra.h>
20 #include <linux/debugfs.h>
21 #include <linux/delay.h>
22 #include <linux/device.h>
23 #include <linux/err.h>
24 #include <linux/export.h>
25 #include <linux/init.h>
27 #include <linux/iopoll.h>
28 #include <linux/irqdomain.h>
29 #include <linux/irq.h>
30 #include <linux/kernel.h>
31 #include <linux/of_address.h>
32 #include <linux/of_clk.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_platform.h>
36 #include <linux/pinctrl/pinconf-generic.h>
37 #include <linux/pinctrl/pinconf.h>
38 #include <linux/pinctrl/pinctrl.h>
39 #include <linux/platform_device.h>
40 #include <linux/pm_domain.h>
41 #include <linux/reboot.h>
42 #include <linux/regmap.h>
43 #include <linux/reset.h>
44 #include <linux/seq_file.h>
45 #include <linux/slab.h>
46 #include <linux/spinlock.h>
48 #include <soc/tegra/common.h>
49 #include <soc/tegra/fuse.h>
50 #include <soc/tegra/pmc.h>
52 #include <dt-bindings/interrupt-controller/arm-gic.h>
53 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
54 #include <dt-bindings/gpio/tegra186-gpio.h>
55 #include <dt-bindings/gpio/tegra194-gpio.h>
56 #include <dt-bindings/soc/tegra-pmc.h>
59 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
60 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
61 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
62 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
63 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
64 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
65 #define PMC_CNTRL_PWRREQ_POLARITY BIT(8)
66 #define PMC_CNTRL_BLINK_EN 7
67 #define PMC_CNTRL_MAIN_RST BIT(4)
69 #define PMC_WAKE_MASK 0x0c
70 #define PMC_WAKE_LEVEL 0x10
71 #define PMC_WAKE_STATUS 0x14
72 #define PMC_SW_WAKE_STATUS 0x18
73 #define PMC_DPD_PADS_ORIDE 0x1c
74 #define PMC_DPD_PADS_ORIDE_BLINK 20
76 #define DPD_SAMPLE 0x020
77 #define DPD_SAMPLE_ENABLE BIT(0)
78 #define DPD_SAMPLE_DISABLE (0 << 0)
80 #define PWRGATE_TOGGLE 0x30
81 #define PWRGATE_TOGGLE_START BIT(8)
83 #define REMOVE_CLAMPING 0x34
85 #define PWRGATE_STATUS 0x38
87 #define PMC_BLINK_TIMER 0x40
88 #define PMC_IMPL_E_33V_PWR 0x40
90 #define PMC_PWR_DET 0x48
92 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
93 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
94 #define PMC_SCRATCH0_MODE_RCM BIT(1)
95 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
96 PMC_SCRATCH0_MODE_BOOTLOADER | \
97 PMC_SCRATCH0_MODE_RCM)
99 #define PMC_CPUPWRGOOD_TIMER 0xc8
100 #define PMC_CPUPWROFF_TIMER 0xcc
101 #define PMC_COREPWRGOOD_TIMER 0x3c
102 #define PMC_COREPWROFF_TIMER 0xe0
104 #define PMC_PWR_DET_VALUE 0xe4
106 #define PMC_USB_DEBOUNCE_DEL 0xec
107 #define PMC_USB_AO 0xf0
109 #define PMC_SCRATCH41 0x140
111 #define PMC_WAKE2_MASK 0x160
112 #define PMC_WAKE2_LEVEL 0x164
113 #define PMC_WAKE2_STATUS 0x168
114 #define PMC_SW_WAKE2_STATUS 0x16c
116 #define PMC_CLK_OUT_CNTRL 0x1a8
117 #define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0)
118 #define PMC_SENSOR_CTRL 0x1b0
119 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
120 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
122 #define PMC_RST_STATUS_POR 0
123 #define PMC_RST_STATUS_WATCHDOG 1
124 #define PMC_RST_STATUS_SENSOR 2
125 #define PMC_RST_STATUS_SW_MAIN 3
126 #define PMC_RST_STATUS_LP0 4
127 #define PMC_RST_STATUS_AOTAG 5
129 #define IO_DPD_REQ 0x1b8
130 #define IO_DPD_REQ_CODE_IDLE (0U << 30)
131 #define IO_DPD_REQ_CODE_OFF (1U << 30)
132 #define IO_DPD_REQ_CODE_ON (2U << 30)
133 #define IO_DPD_REQ_CODE_MASK (3U << 30)
135 #define IO_DPD_STATUS 0x1bc
136 #define IO_DPD2_REQ 0x1c0
137 #define IO_DPD2_STATUS 0x1c4
138 #define SEL_DPD_TIM 0x1c8
140 #define PMC_UTMIP_UHSIC_TRIGGERS 0x1ec
141 #define PMC_UTMIP_UHSIC_SAVED_STATE 0x1f0
143 #define PMC_UTMIP_TERM_PAD_CFG 0x1f8
144 #define PMC_UTMIP_UHSIC_SLEEP_CFG 0x1fc
145 #define PMC_UTMIP_UHSIC_FAKE 0x218
147 #define PMC_SCRATCH54 0x258
148 #define PMC_SCRATCH54_DATA_SHIFT 8
149 #define PMC_SCRATCH54_ADDR_SHIFT 0
151 #define PMC_SCRATCH55 0x25c
152 #define PMC_SCRATCH55_RESET_TEGRA BIT(31)
153 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
154 #define PMC_SCRATCH55_PINMUX_SHIFT 24
155 #define PMC_SCRATCH55_16BITOP BIT(15)
156 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
157 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
159 #define PMC_UTMIP_UHSIC_LINE_WAKEUP 0x26c
161 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270
162 #define PMC_UTMIP_MASTER_CONFIG 0x274
163 #define PMC_UTMIP_UHSIC2_TRIGGERS 0x27c
164 #define PMC_UTMIP_MASTER2_CONFIG 0x29c
166 #define GPU_RG_CNTRL 0x2d4
168 #define PMC_UTMIP_PAD_CFG0 0x4c0
169 #define PMC_UTMIP_UHSIC_SLEEP_CFG1 0x4d0
170 #define PMC_UTMIP_SLEEPWALK_P3 0x4e0
171 /* Tegra186 and later */
172 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
173 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)
174 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))
175 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))
176 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))
177 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))
178 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
179 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
180 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
182 #define WAKE_AOWAKE_CTRL 0x4f4
183 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
186 #define TEGRA_SMC_PMC 0xc2fffe00
187 #define TEGRA_SMC_PMC_READ 0xaa
188 #define TEGRA_SMC_PMC_WRITE 0xbb
197 #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
199 struct pmc_clk_gate {
205 #define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
207 struct pmc_clk_init_data {
209 const char *const *parents;
216 static const char * const clk_out1_parents[] = { "osc", "osc_div2",
217 "osc_div4", "extern1",
220 static const char * const clk_out2_parents[] = { "osc", "osc_div2",
221 "osc_div4", "extern2",
224 static const char * const clk_out3_parents[] = { "osc", "osc_div2",
225 "osc_div4", "extern3",
228 static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
230 .name = "pmc_clk_out_1",
231 .parents = clk_out1_parents,
232 .num_parents = ARRAY_SIZE(clk_out1_parents),
233 .clk_id = TEGRA_PMC_CLK_OUT_1,
238 .name = "pmc_clk_out_2",
239 .parents = clk_out2_parents,
240 .num_parents = ARRAY_SIZE(clk_out2_parents),
241 .clk_id = TEGRA_PMC_CLK_OUT_2,
243 .force_en_shift = 10,
246 .name = "pmc_clk_out_3",
247 .parents = clk_out3_parents,
248 .num_parents = ARRAY_SIZE(clk_out3_parents),
249 .clk_id = TEGRA_PMC_CLK_OUT_3,
251 .force_en_shift = 18,
255 struct tegra_powergate {
256 struct generic_pm_domain genpd;
257 struct tegra_pmc *pmc;
260 unsigned int num_clks;
261 unsigned long *clk_rates;
262 struct reset_control *reset;
265 struct tegra_io_pad_soc {
266 enum tegra_io_pad id;
268 unsigned int voltage;
272 struct tegra_pmc_regs {
273 unsigned int scratch0;
274 unsigned int dpd_req;
275 unsigned int dpd_status;
276 unsigned int dpd2_req;
277 unsigned int dpd2_status;
278 unsigned int rst_status;
279 unsigned int rst_source_shift;
280 unsigned int rst_source_mask;
281 unsigned int rst_level_shift;
282 unsigned int rst_level_mask;
285 struct tegra_wake_event {
290 unsigned int instance;
295 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \
301 .instance = UINT_MAX, \
306 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \
312 .instance = _instance, \
317 struct tegra_pmc_soc {
318 unsigned int num_powergates;
319 const char *const *powergates;
320 unsigned int num_cpu_powergates;
321 const u8 *cpu_powergates;
323 bool has_tsense_reset;
325 bool needs_mbist_war;
326 bool has_impl_33v_pwr;
329 const struct tegra_io_pad_soc *io_pads;
330 unsigned int num_io_pads;
332 const struct pinctrl_pin_desc *pin_descs;
333 unsigned int num_pin_descs;
335 const struct tegra_pmc_regs *regs;
336 void (*init)(struct tegra_pmc *pmc);
337 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
338 struct device_node *np,
340 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
341 int (*irq_set_type)(struct irq_data *data, unsigned int type);
342 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id,
345 const char * const *reset_sources;
346 unsigned int num_reset_sources;
347 const char * const *reset_levels;
348 unsigned int num_reset_levels;
351 * These describe events that can wake the system from sleep (i.e.
352 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2)
353 * are dealt with in the LIC.
355 const struct tegra_wake_event *wake_events;
356 unsigned int num_wake_events;
358 const struct pmc_clk_init_data *pmc_clks_data;
359 unsigned int num_pmc_clks;
360 bool has_blink_output;
361 bool has_usb_sleepwalk;
365 * struct tegra_pmc - NVIDIA Tegra PMC
366 * @dev: pointer to PMC device structure
367 * @base: pointer to I/O remapped register region
368 * @wake: pointer to I/O remapped region for WAKE registers
369 * @aotag: pointer to I/O remapped region for AOTAG registers
370 * @scratch: pointer to I/O remapped region for scratch registers
371 * @clk: pointer to pclk clock
372 * @soc: pointer to SoC data structure
373 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone
374 * @debugfs: pointer to debugfs entry
375 * @rate: currently configured rate of pclk
376 * @suspend_mode: lowest suspend mode available
377 * @cpu_good_time: CPU power good time (in microseconds)
378 * @cpu_off_time: CPU power off time (in microsecends)
379 * @core_osc_time: core power good OSC time (in microseconds)
380 * @core_pmu_time: core power good PMU time (in microseconds)
381 * @core_off_time: core power off time (in microseconds)
382 * @corereq_high: core power request is active-high
383 * @sysclkreq_high: system clock request is active-high
384 * @combined_req: combined power request for CPU & core
385 * @cpu_pwr_good_en: CPU power good signal is enabled
386 * @lp0_vec_phys: physical base address of the LP0 warm boot code
387 * @lp0_vec_size: size of the LP0 warm boot code
388 * @powergates_available: Bitmap of available power gates
389 * @powergates_lock: mutex for power gate register access
390 * @pctl_dev: pin controller exposed by the PMC
391 * @domain: IRQ domain provided by the PMC
392 * @irq: chip implementation for the IRQ domain
393 * @clk_nb: pclk clock changes handler
400 void __iomem *scratch;
402 struct dentry *debugfs;
404 const struct tegra_pmc_soc *soc;
409 enum tegra_suspend_mode suspend_mode;
418 bool cpu_pwr_good_en;
421 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
423 struct mutex powergates_lock;
425 struct pinctrl_dev *pctl_dev;
427 struct irq_domain *domain;
430 struct notifier_block clk_nb;
433 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
435 .suspend_mode = TEGRA_SUSPEND_NONE,
438 static inline struct tegra_powergate *
439 to_powergate(struct generic_pm_domain *domain)
441 return container_of(domain, struct tegra_powergate, genpd);
444 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
446 struct arm_smccc_res res;
449 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
453 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
456 pr_warn("%s(): SMC failed: %lu\n", __func__,
463 return readl(pmc->base + offset);
466 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
467 unsigned long offset)
469 struct arm_smccc_res res;
472 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
473 value, 0, 0, 0, 0, &res);
476 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
479 pr_warn("%s(): SMC failed: %lu\n", __func__,
483 writel(value, pmc->base + offset);
487 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)
490 return tegra_pmc_readl(pmc, offset);
492 return readl(pmc->scratch + offset);
495 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
496 unsigned long offset)
499 tegra_pmc_writel(pmc, value, offset);
501 writel(value, pmc->scratch + offset);
505 * TODO Figure out a way to call this with the struct tegra_pmc * passed in.
506 * This currently doesn't work because readx_poll_timeout() can only operate
507 * on functions that take a single argument.
509 static inline bool tegra_powergate_state(int id)
511 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
512 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;
514 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;
517 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id)
519 return (pmc->soc && pmc->soc->powergates[id]);
522 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id)
524 return test_bit(id, pmc->powergates_available);
527 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
531 if (!pmc || !pmc->soc || !name)
534 for (i = 0; i < pmc->soc->num_powergates; i++) {
535 if (!tegra_powergate_is_valid(pmc, i))
538 if (!strcmp(name, pmc->soc->powergates[i]))
545 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id,
548 unsigned int retries = 100;
553 * As per TRM documentation, the toggle command will be dropped by PMC
554 * if there is contention with a HW-initiated toggling (i.e. CPU core
555 * power-gated), the command should be retried in that case.
558 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
560 /* wait for PMC to execute the command */
561 ret = readx_poll_timeout(tegra_powergate_state, id, status,
562 status == new_state, 1, 10);
563 } while (ret == -ETIMEDOUT && retries--);
568 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc)
570 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START);
573 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id,
579 /* wait while PMC power gating is contended */
580 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
581 status == true, 1, 100);
585 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
587 /* wait for PMC to accept the command */
588 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
589 status == true, 1, 100);
593 /* wait for PMC to execute the command */
594 err = readx_poll_timeout(tegra_powergate_state, id, status,
595 status == new_state, 10, 100000);
603 * tegra_powergate_set() - set the state of a partition
604 * @pmc: power management controller
606 * @new_state: new state of the partition
608 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id,
613 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
616 mutex_lock(&pmc->powergates_lock);
618 if (tegra_powergate_state(id) == new_state) {
619 mutex_unlock(&pmc->powergates_lock);
623 err = pmc->soc->powergate_set(pmc, id, new_state);
625 mutex_unlock(&pmc->powergates_lock);
630 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
635 mutex_lock(&pmc->powergates_lock);
638 * On Tegra124 and later, the clamps for the GPU are controlled by a
639 * separate register (with different semantics).
641 if (id == TEGRA_POWERGATE_3D) {
642 if (pmc->soc->has_gpu_clamps) {
643 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);
649 * Tegra 2 has a bug where PCIE and VDE clamping masks are
650 * swapped relatively to the partition ids
652 if (id == TEGRA_POWERGATE_VDEC)
653 mask = (1 << TEGRA_POWERGATE_PCIE);
654 else if (id == TEGRA_POWERGATE_PCIE)
655 mask = (1 << TEGRA_POWERGATE_VDEC);
659 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);
662 mutex_unlock(&pmc->powergates_lock);
667 static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg)
669 unsigned long safe_rate = 100 * 1000 * 1000;
673 for (i = 0; i < pg->num_clks; i++) {
674 pg->clk_rates[i] = clk_get_rate(pg->clks[i]);
676 if (!pg->clk_rates[i]) {
681 if (pg->clk_rates[i] <= safe_rate)
685 * We don't know whether voltage state is okay for the
686 * current clock rate, hence it's better to temporally
687 * switch clock to a safe rate which is suitable for
688 * all voltages, before enabling the clock.
690 err = clk_set_rate(pg->clks[i], safe_rate);
699 clk_set_rate(pg->clks[i], pg->clk_rates[i]);
704 static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg)
709 for (i = 0; i < pg->num_clks; i++) {
710 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]);
718 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
722 for (i = 0; i < pg->num_clks; i++)
723 clk_disable_unprepare(pg->clks[i]);
726 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
731 for (i = 0; i < pg->num_clks; i++) {
732 err = clk_prepare_enable(pg->clks[i]);
741 clk_disable_unprepare(pg->clks[i]);
746 static int tegra_powergate_power_up(struct tegra_powergate *pg,
751 err = reset_control_assert(pg->reset);
755 usleep_range(10, 20);
757 err = tegra_powergate_set(pg->pmc, pg->id, true);
761 usleep_range(10, 20);
763 err = tegra_powergate_prepare_clocks(pg);
767 err = tegra_powergate_enable_clocks(pg);
771 usleep_range(10, 20);
773 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
777 usleep_range(10, 20);
779 err = reset_control_deassert(pg->reset);
783 usleep_range(10, 20);
785 if (pg->pmc->soc->needs_mbist_war)
786 err = tegra210_clk_handle_mbist_war(pg->id);
791 tegra_powergate_disable_clocks(pg);
793 err = tegra_powergate_unprepare_clocks(pg);
800 tegra_powergate_disable_clocks(pg);
801 usleep_range(10, 20);
804 tegra_powergate_unprepare_clocks(pg);
807 tegra_powergate_set(pg->pmc, pg->id, false);
812 static int tegra_powergate_power_down(struct tegra_powergate *pg)
816 err = tegra_powergate_prepare_clocks(pg);
820 err = tegra_powergate_enable_clocks(pg);
824 usleep_range(10, 20);
826 err = reset_control_assert(pg->reset);
830 usleep_range(10, 20);
832 tegra_powergate_disable_clocks(pg);
834 usleep_range(10, 20);
836 err = tegra_powergate_set(pg->pmc, pg->id, false);
840 err = tegra_powergate_unprepare_clocks(pg);
847 tegra_powergate_enable_clocks(pg);
848 usleep_range(10, 20);
849 reset_control_deassert(pg->reset);
850 usleep_range(10, 20);
853 tegra_powergate_disable_clocks(pg);
856 tegra_powergate_unprepare_clocks(pg);
861 static int tegra_genpd_power_on(struct generic_pm_domain *domain)
863 struct tegra_powergate *pg = to_powergate(domain);
864 struct device *dev = pg->pmc->dev;
867 err = tegra_powergate_power_up(pg, true);
869 dev_err(dev, "failed to turn on PM domain %s: %d\n",
870 pg->genpd.name, err);
874 reset_control_release(pg->reset);
880 static int tegra_genpd_power_off(struct generic_pm_domain *domain)
882 struct tegra_powergate *pg = to_powergate(domain);
883 struct device *dev = pg->pmc->dev;
886 err = reset_control_acquire(pg->reset);
888 dev_err(dev, "failed to acquire resets for PM domain %s: %d\n",
889 pg->genpd.name, err);
893 err = tegra_powergate_power_down(pg);
895 dev_err(dev, "failed to turn off PM domain %s: %d\n",
896 pg->genpd.name, err);
897 reset_control_release(pg->reset);
904 * tegra_powergate_power_on() - power on partition
907 int tegra_powergate_power_on(unsigned int id)
909 if (!tegra_powergate_is_available(pmc, id))
912 return tegra_powergate_set(pmc, id, true);
914 EXPORT_SYMBOL(tegra_powergate_power_on);
917 * tegra_powergate_power_off() - power off partition
920 int tegra_powergate_power_off(unsigned int id)
922 if (!tegra_powergate_is_available(pmc, id))
925 return tegra_powergate_set(pmc, id, false);
927 EXPORT_SYMBOL(tegra_powergate_power_off);
930 * tegra_powergate_is_powered() - check if partition is powered
931 * @pmc: power management controller
934 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id)
936 if (!tegra_powergate_is_valid(pmc, id))
939 return tegra_powergate_state(id);
943 * tegra_powergate_remove_clamping() - remove power clamps for partition
946 int tegra_powergate_remove_clamping(unsigned int id)
948 if (!tegra_powergate_is_available(pmc, id))
951 return __tegra_powergate_remove_clamping(pmc, id);
953 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
956 * tegra_powergate_sequence_power_up() - power up partition
958 * @clk: clock for partition
959 * @rst: reset for partition
961 * Must be called with clk disabled, and returns with clk enabled.
963 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
964 struct reset_control *rst)
966 struct tegra_powergate *pg;
969 if (!tegra_powergate_is_available(pmc, id))
972 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
976 pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL);
977 if (!pg->clk_rates) {
988 err = tegra_powergate_power_up(pg, false);
990 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
993 kfree(pg->clk_rates);
998 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
1001 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
1002 * @pmc: power management controller
1003 * @cpuid: CPU partition ID
1005 * Returns the partition ID corresponding to the CPU partition ID or a
1006 * negative error code on failure.
1008 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc,
1011 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
1012 return pmc->soc->cpu_powergates[cpuid];
1018 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
1019 * @cpuid: CPU partition ID
1021 bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
1025 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1029 return tegra_powergate_is_powered(pmc, id);
1033 * tegra_pmc_cpu_power_on() - power on CPU partition
1034 * @cpuid: CPU partition ID
1036 int tegra_pmc_cpu_power_on(unsigned int cpuid)
1040 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1044 return tegra_powergate_set(pmc, id, true);
1048 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
1049 * @cpuid: CPU partition ID
1051 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
1055 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1059 return tegra_powergate_remove_clamping(id);
1062 static int tegra_pmc_restart_notify(struct notifier_block *this,
1063 unsigned long action, void *data)
1065 const char *cmd = data;
1068 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
1069 value &= ~PMC_SCRATCH0_MODE_MASK;
1072 if (strcmp(cmd, "recovery") == 0)
1073 value |= PMC_SCRATCH0_MODE_RECOVERY;
1075 if (strcmp(cmd, "bootloader") == 0)
1076 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
1078 if (strcmp(cmd, "forced-recovery") == 0)
1079 value |= PMC_SCRATCH0_MODE_RCM;
1082 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
1084 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
1085 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1086 value |= PMC_CNTRL_MAIN_RST;
1087 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1092 static struct notifier_block tegra_pmc_restart_handler = {
1093 .notifier_call = tegra_pmc_restart_notify,
1097 static int powergate_show(struct seq_file *s, void *data)
1102 seq_printf(s, " powergate powered\n");
1103 seq_printf(s, "------------------\n");
1105 for (i = 0; i < pmc->soc->num_powergates; i++) {
1106 status = tegra_powergate_is_powered(pmc, i);
1110 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
1111 status ? "yes" : "no");
1117 DEFINE_SHOW_ATTRIBUTE(powergate);
1119 static int tegra_powergate_debugfs_init(void)
1121 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
1129 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
1130 struct device_node *np)
1133 unsigned int i, count;
1136 count = of_clk_get_parent_count(np);
1140 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
1144 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL);
1145 if (!pg->clk_rates) {
1150 for (i = 0; i < count; i++) {
1151 pg->clks[i] = of_clk_get(np, i);
1152 if (IS_ERR(pg->clks[i])) {
1153 err = PTR_ERR(pg->clks[i]);
1158 pg->num_clks = count;
1164 clk_put(pg->clks[i]);
1166 kfree(pg->clk_rates);
1172 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
1173 struct device_node *np, bool off)
1175 struct device *dev = pg->pmc->dev;
1178 pg->reset = of_reset_control_array_get_exclusive_released(np);
1179 if (IS_ERR(pg->reset)) {
1180 err = PTR_ERR(pg->reset);
1181 dev_err(dev, "failed to get device resets: %d\n", err);
1185 err = reset_control_acquire(pg->reset);
1187 pr_err("failed to acquire resets: %d\n", err);
1192 err = reset_control_assert(pg->reset);
1194 err = reset_control_deassert(pg->reset);
1198 reset_control_release(pg->reset);
1203 reset_control_release(pg->reset);
1204 reset_control_put(pg->reset);
1210 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
1212 struct device *dev = pmc->dev;
1213 struct tegra_powergate *pg;
1217 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
1221 id = tegra_powergate_lookup(pmc, np->name);
1223 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id);
1229 * Clear the bit for this powergate so it cannot be managed
1230 * directly via the legacy APIs for controlling powergates.
1232 clear_bit(id, pmc->powergates_available);
1235 pg->genpd.name = np->name;
1236 pg->genpd.power_off = tegra_genpd_power_off;
1237 pg->genpd.power_on = tegra_genpd_power_on;
1240 off = !tegra_powergate_is_powered(pmc, pg->id);
1242 err = tegra_powergate_of_get_clks(pg, np);
1244 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err);
1248 err = tegra_powergate_of_get_resets(pg, np, off);
1250 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err);
1254 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
1256 WARN_ON(tegra_powergate_power_up(pg, true));
1261 err = pm_genpd_init(&pg->genpd, NULL, off);
1263 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np,
1268 err = of_genpd_add_provider_simple(np, &pg->genpd);
1270 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n",
1275 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name);
1280 pm_genpd_remove(&pg->genpd);
1283 reset_control_put(pg->reset);
1286 while (pg->num_clks--)
1287 clk_put(pg->clks[pg->num_clks]);
1292 set_bit(id, pmc->powergates_available);
1300 static int tegra_powergate_init(struct tegra_pmc *pmc,
1301 struct device_node *parent)
1303 struct device_node *np, *child;
1306 np = of_get_child_by_name(parent, "powergates");
1310 for_each_child_of_node(np, child) {
1311 err = tegra_powergate_add(pmc, child);
1323 static void tegra_powergate_remove(struct generic_pm_domain *genpd)
1325 struct tegra_powergate *pg = to_powergate(genpd);
1327 reset_control_put(pg->reset);
1329 while (pg->num_clks--)
1330 clk_put(pg->clks[pg->num_clks]);
1334 set_bit(pg->id, pmc->powergates_available);
1339 static void tegra_powergate_remove_all(struct device_node *parent)
1341 struct generic_pm_domain *genpd;
1342 struct device_node *np, *child;
1344 np = of_get_child_by_name(parent, "powergates");
1348 for_each_child_of_node(np, child) {
1349 of_genpd_del_provider(child);
1351 genpd = of_genpd_remove_last(child);
1355 tegra_powergate_remove(genpd);
1361 static const struct tegra_io_pad_soc *
1362 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
1366 for (i = 0; i < pmc->soc->num_io_pads; i++)
1367 if (pmc->soc->io_pads[i].id == id)
1368 return &pmc->soc->io_pads[i];
1373 static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc,
1374 enum tegra_io_pad id,
1375 unsigned long *request,
1376 unsigned long *status,
1379 const struct tegra_io_pad_soc *pad;
1381 pad = tegra_io_pad_find(pmc, id);
1383 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1387 if (pad->dpd == UINT_MAX)
1390 *mask = BIT(pad->dpd % 32);
1392 if (pad->dpd < 32) {
1393 *status = pmc->soc->regs->dpd_status;
1394 *request = pmc->soc->regs->dpd_req;
1396 *status = pmc->soc->regs->dpd2_status;
1397 *request = pmc->soc->regs->dpd2_req;
1403 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id,
1404 unsigned long *request, unsigned long *status,
1407 unsigned long rate, value;
1410 err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask);
1417 dev_err(pmc->dev, "failed to get clock rate\n");
1421 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);
1423 /* must be at least 200 ns, in APB (PCLK) clock cycles */
1424 value = DIV_ROUND_UP(1000000000, rate);
1425 value = DIV_ROUND_UP(200, value);
1426 tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
1432 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset,
1433 u32 mask, u32 val, unsigned long timeout)
1437 timeout = jiffies + msecs_to_jiffies(timeout);
1439 while (time_after(timeout, jiffies)) {
1440 value = tegra_pmc_readl(pmc, offset);
1441 if ((value & mask) == val)
1444 usleep_range(250, 1000);
1450 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)
1453 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);
1457 * tegra_io_pad_power_enable() - enable power to I/O pad
1458 * @id: Tegra I/O pad ID for which to enable power
1460 * Returns: 0 on success or a negative error code on failure.
1462 int tegra_io_pad_power_enable(enum tegra_io_pad id)
1464 unsigned long request, status;
1468 mutex_lock(&pmc->powergates_lock);
1470 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1472 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1476 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);
1478 err = tegra_io_pad_poll(pmc, status, mask, 0, 250);
1480 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err);
1484 tegra_io_pad_unprepare(pmc);
1487 mutex_unlock(&pmc->powergates_lock);
1490 EXPORT_SYMBOL(tegra_io_pad_power_enable);
1493 * tegra_io_pad_power_disable() - disable power to I/O pad
1494 * @id: Tegra I/O pad ID for which to disable power
1496 * Returns: 0 on success or a negative error code on failure.
1498 int tegra_io_pad_power_disable(enum tegra_io_pad id)
1500 unsigned long request, status;
1504 mutex_lock(&pmc->powergates_lock);
1506 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1508 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1512 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);
1514 err = tegra_io_pad_poll(pmc, status, mask, mask, 250);
1516 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err);
1520 tegra_io_pad_unprepare(pmc);
1523 mutex_unlock(&pmc->powergates_lock);
1526 EXPORT_SYMBOL(tegra_io_pad_power_disable);
1528 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)
1530 unsigned long request, status;
1534 err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status,
1539 value = tegra_pmc_readl(pmc, status);
1541 return !(value & mask);
1544 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,
1547 const struct tegra_io_pad_soc *pad;
1550 pad = tegra_io_pad_find(pmc, id);
1554 if (pad->voltage == UINT_MAX)
1557 mutex_lock(&pmc->powergates_lock);
1559 if (pmc->soc->has_impl_33v_pwr) {
1560 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1562 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1563 value &= ~BIT(pad->voltage);
1565 value |= BIT(pad->voltage);
1567 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
1569 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1570 value = tegra_pmc_readl(pmc, PMC_PWR_DET);
1571 value |= BIT(pad->voltage);
1572 tegra_pmc_writel(pmc, value, PMC_PWR_DET);
1574 /* update I/O voltage */
1575 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1577 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1578 value &= ~BIT(pad->voltage);
1580 value |= BIT(pad->voltage);
1582 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
1585 mutex_unlock(&pmc->powergates_lock);
1587 usleep_range(100, 250);
1592 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)
1594 const struct tegra_io_pad_soc *pad;
1597 pad = tegra_io_pad_find(pmc, id);
1601 if (pad->voltage == UINT_MAX)
1604 if (pmc->soc->has_impl_33v_pwr)
1605 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1607 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1609 if ((value & BIT(pad->voltage)) == 0)
1610 return TEGRA_IO_PAD_VOLTAGE_1V8;
1612 return TEGRA_IO_PAD_VOLTAGE_3V3;
1616 * tegra_io_rail_power_on() - enable power to I/O rail
1617 * @id: Tegra I/O pad ID for which to enable power
1619 * See also: tegra_io_pad_power_enable()
1621 int tegra_io_rail_power_on(unsigned int id)
1623 return tegra_io_pad_power_enable(id);
1625 EXPORT_SYMBOL(tegra_io_rail_power_on);
1628 * tegra_io_rail_power_off() - disable power to I/O rail
1629 * @id: Tegra I/O pad ID for which to disable power
1631 * See also: tegra_io_pad_power_disable()
1633 int tegra_io_rail_power_off(unsigned int id)
1635 return tegra_io_pad_power_disable(id);
1637 EXPORT_SYMBOL(tegra_io_rail_power_off);
1639 #ifdef CONFIG_PM_SLEEP
1640 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1642 return pmc->suspend_mode;
1645 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1647 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1650 pmc->suspend_mode = mode;
1653 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1655 unsigned long long rate = 0;
1660 case TEGRA_SUSPEND_LP1:
1664 case TEGRA_SUSPEND_LP2:
1672 if (WARN_ON_ONCE(rate == 0))
1675 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1676 do_div(ticks, USEC_PER_SEC);
1677 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
1679 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1680 do_div(ticks, USEC_PER_SEC);
1681 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
1683 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1684 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1685 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1686 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1690 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1692 u32 value, values[2];
1694 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1698 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1702 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1706 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1710 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1715 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1717 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1718 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1720 pmc->cpu_good_time = value;
1722 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1723 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1725 pmc->cpu_off_time = value;
1727 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1728 values, ARRAY_SIZE(values)))
1729 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1731 pmc->core_osc_time = values[0];
1732 pmc->core_pmu_time = values[1];
1734 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1735 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1737 pmc->core_off_time = value;
1739 pmc->corereq_high = of_property_read_bool(np,
1740 "nvidia,core-power-req-active-high");
1742 pmc->sysclkreq_high = of_property_read_bool(np,
1743 "nvidia,sys-clock-req-active-high");
1745 pmc->combined_req = of_property_read_bool(np,
1746 "nvidia,combined-power-req");
1748 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1749 "nvidia,cpu-pwr-good-en");
1751 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1752 ARRAY_SIZE(values)))
1753 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1754 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1756 pmc->lp0_vec_phys = values[0];
1757 pmc->lp0_vec_size = values[1];
1762 static void tegra_pmc_init(struct tegra_pmc *pmc)
1765 pmc->soc->init(pmc);
1768 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1770 static const char disabled[] = "emergency thermal reset disabled";
1771 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1772 struct device *dev = pmc->dev;
1773 struct device_node *np;
1774 u32 value, checksum;
1776 if (!pmc->soc->has_tsense_reset)
1779 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
1781 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1785 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1786 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1790 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1791 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1795 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) {
1796 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1800 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) {
1801 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1805 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1808 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1809 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1810 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1812 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1813 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1814 tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
1816 value = PMC_SCRATCH55_RESET_TEGRA;
1817 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1818 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1819 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1822 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
1823 * contain the checksum and are currently zero, so they are not added.
1825 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1826 + ((value >> 24) & 0xff);
1828 checksum = 0x100 - checksum;
1830 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1832 tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
1834 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1835 value |= PMC_SENSOR_CTRL_ENABLE_RST;
1836 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1838 dev_info(pmc->dev, "emergency thermal reset enabled\n");
1844 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev)
1846 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1848 return pmc->soc->num_io_pads;
1851 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl,
1854 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl);
1856 return pmc->soc->io_pads[group].name;
1859 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev,
1861 const unsigned int **pins,
1862 unsigned int *num_pins)
1864 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1866 *pins = &pmc->soc->io_pads[group].id;
1872 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = {
1873 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count,
1874 .get_group_name = tegra_io_pad_pinctrl_get_group_name,
1875 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins,
1876 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1877 .dt_free_map = pinconf_generic_dt_free_map,
1880 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev,
1881 unsigned int pin, unsigned long *config)
1883 enum pin_config_param param = pinconf_to_config_param(*config);
1884 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1885 const struct tegra_io_pad_soc *pad;
1889 pad = tegra_io_pad_find(pmc, pin);
1894 case PIN_CONFIG_POWER_SOURCE:
1895 ret = tegra_io_pad_get_voltage(pmc, pad->id);
1902 case PIN_CONFIG_MODE_LOW_POWER:
1903 ret = tegra_io_pad_is_powered(pmc, pad->id);
1914 *config = pinconf_to_config_packed(param, arg);
1919 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev,
1920 unsigned int pin, unsigned long *configs,
1921 unsigned int num_configs)
1923 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1924 const struct tegra_io_pad_soc *pad;
1925 enum pin_config_param param;
1930 pad = tegra_io_pad_find(pmc, pin);
1934 for (i = 0; i < num_configs; ++i) {
1935 param = pinconf_to_config_param(configs[i]);
1936 arg = pinconf_to_config_argument(configs[i]);
1939 case PIN_CONFIG_MODE_LOW_POWER:
1941 err = tegra_io_pad_power_disable(pad->id);
1943 err = tegra_io_pad_power_enable(pad->id);
1947 case PIN_CONFIG_POWER_SOURCE:
1948 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 &&
1949 arg != TEGRA_IO_PAD_VOLTAGE_3V3)
1951 err = tegra_io_pad_set_voltage(pmc, pad->id, arg);
1963 static const struct pinconf_ops tegra_io_pad_pinconf_ops = {
1964 .pin_config_get = tegra_io_pad_pinconf_get,
1965 .pin_config_set = tegra_io_pad_pinconf_set,
1969 static struct pinctrl_desc tegra_pmc_pctl_desc = {
1970 .pctlops = &tegra_io_pad_pinctrl_ops,
1971 .confops = &tegra_io_pad_pinconf_ops,
1974 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
1978 if (!pmc->soc->num_pin_descs)
1981 tegra_pmc_pctl_desc.name = dev_name(pmc->dev);
1982 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs;
1983 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs;
1985 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc,
1987 if (IS_ERR(pmc->pctl_dev)) {
1988 err = PTR_ERR(pmc->pctl_dev);
1989 dev_err(pmc->dev, "failed to register pin controller: %d\n",
1997 static ssize_t reset_reason_show(struct device *dev,
1998 struct device_attribute *attr, char *buf)
2002 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2003 value &= pmc->soc->regs->rst_source_mask;
2004 value >>= pmc->soc->regs->rst_source_shift;
2006 if (WARN_ON(value >= pmc->soc->num_reset_sources))
2007 return sprintf(buf, "%s\n", "UNKNOWN");
2009 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
2012 static DEVICE_ATTR_RO(reset_reason);
2014 static ssize_t reset_level_show(struct device *dev,
2015 struct device_attribute *attr, char *buf)
2019 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2020 value &= pmc->soc->regs->rst_level_mask;
2021 value >>= pmc->soc->regs->rst_level_shift;
2023 if (WARN_ON(value >= pmc->soc->num_reset_levels))
2024 return sprintf(buf, "%s\n", "UNKNOWN");
2026 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
2029 static DEVICE_ATTR_RO(reset_level);
2031 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
2033 struct device *dev = pmc->dev;
2036 if (pmc->soc->reset_sources) {
2037 err = device_create_file(dev, &dev_attr_reset_reason);
2040 "failed to create attr \"reset_reason\": %d\n",
2044 if (pmc->soc->reset_levels) {
2045 err = device_create_file(dev, &dev_attr_reset_level);
2048 "failed to create attr \"reset_level\": %d\n",
2053 static int tegra_pmc_irq_translate(struct irq_domain *domain,
2054 struct irq_fwspec *fwspec,
2055 unsigned long *hwirq,
2058 if (WARN_ON(fwspec->param_count < 2))
2061 *hwirq = fwspec->param[0];
2062 *type = fwspec->param[1];
2067 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq,
2068 unsigned int num_irqs, void *data)
2070 struct tegra_pmc *pmc = domain->host_data;
2071 const struct tegra_pmc_soc *soc = pmc->soc;
2072 struct irq_fwspec *fwspec = data;
2076 if (WARN_ON(num_irqs > 1))
2079 for (i = 0; i < soc->num_wake_events; i++) {
2080 const struct tegra_wake_event *event = &soc->wake_events[i];
2082 if (fwspec->param_count == 2) {
2083 struct irq_fwspec spec;
2085 if (event->id != fwspec->param[0])
2088 err = irq_domain_set_hwirq_and_chip(domain, virq,
2094 spec.fwnode = &pmc->dev->of_node->fwnode;
2095 spec.param_count = 3;
2096 spec.param[0] = GIC_SPI;
2097 spec.param[1] = event->irq;
2098 spec.param[2] = fwspec->param[1];
2100 err = irq_domain_alloc_irqs_parent(domain, virq,
2106 if (fwspec->param_count == 3) {
2107 if (event->gpio.instance != fwspec->param[0] ||
2108 event->gpio.pin != fwspec->param[1])
2111 err = irq_domain_set_hwirq_and_chip(domain, virq,
2115 /* GPIO hierarchies stop at the PMC level */
2116 if (!err && domain->parent)
2117 err = irq_domain_disconnect_hierarchy(domain->parent,
2123 /* If there is no wake-up event, there is no PMC mapping */
2124 if (i == soc->num_wake_events)
2125 err = irq_domain_disconnect_hierarchy(domain, virq);
2130 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {
2131 .translate = tegra_pmc_irq_translate,
2132 .alloc = tegra_pmc_irq_alloc,
2135 static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2137 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2138 unsigned int offset, bit;
2141 offset = data->hwirq / 32;
2142 bit = data->hwirq % 32;
2144 /* clear wake status */
2145 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);
2146 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);
2148 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);
2149 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);
2151 /* enable PMC wake */
2152 if (data->hwirq >= 32)
2153 offset = PMC_WAKE2_MASK;
2155 offset = PMC_WAKE_MASK;
2157 value = tegra_pmc_readl(pmc, offset);
2164 tegra_pmc_writel(pmc, value, offset);
2169 static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2171 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2172 unsigned int offset, bit;
2175 offset = data->hwirq / 32;
2176 bit = data->hwirq % 32;
2178 if (data->hwirq >= 32)
2179 offset = PMC_WAKE2_LEVEL;
2181 offset = PMC_WAKE_LEVEL;
2183 value = tegra_pmc_readl(pmc, offset);
2186 case IRQ_TYPE_EDGE_RISING:
2187 case IRQ_TYPE_LEVEL_HIGH:
2191 case IRQ_TYPE_EDGE_FALLING:
2192 case IRQ_TYPE_LEVEL_LOW:
2196 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2204 tegra_pmc_writel(pmc, value, offset);
2209 static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2211 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2212 unsigned int offset, bit;
2215 offset = data->hwirq / 32;
2216 bit = data->hwirq % 32;
2218 /* clear wake status */
2219 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
2221 /* route wake to tier 2 */
2222 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2225 value &= ~(1 << bit);
2229 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2231 /* enable wakeup event */
2232 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
2237 static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2239 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2242 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2245 case IRQ_TYPE_EDGE_RISING:
2246 case IRQ_TYPE_LEVEL_HIGH:
2247 value |= WAKE_AOWAKE_CNTRL_LEVEL;
2250 case IRQ_TYPE_EDGE_FALLING:
2251 case IRQ_TYPE_LEVEL_LOW:
2252 value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
2255 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2256 value ^= WAKE_AOWAKE_CNTRL_LEVEL;
2263 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2268 static void tegra_irq_mask_parent(struct irq_data *data)
2270 if (data->parent_data)
2271 irq_chip_mask_parent(data);
2274 static void tegra_irq_unmask_parent(struct irq_data *data)
2276 if (data->parent_data)
2277 irq_chip_unmask_parent(data);
2280 static void tegra_irq_eoi_parent(struct irq_data *data)
2282 if (data->parent_data)
2283 irq_chip_eoi_parent(data);
2286 static int tegra_irq_set_affinity_parent(struct irq_data *data,
2287 const struct cpumask *dest,
2290 if (data->parent_data)
2291 return irq_chip_set_affinity_parent(data, dest, force);
2296 static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
2298 struct irq_domain *parent = NULL;
2299 struct device_node *np;
2301 np = of_irq_find_parent(pmc->dev->of_node);
2303 parent = irq_find_host(np);
2310 pmc->irq.name = dev_name(pmc->dev);
2311 pmc->irq.irq_mask = tegra_irq_mask_parent;
2312 pmc->irq.irq_unmask = tegra_irq_unmask_parent;
2313 pmc->irq.irq_eoi = tegra_irq_eoi_parent;
2314 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent;
2315 pmc->irq.irq_set_type = pmc->soc->irq_set_type;
2316 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake;
2318 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,
2319 &tegra_pmc_irq_domain_ops, pmc);
2321 dev_err(pmc->dev, "failed to allocate domain\n");
2328 static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
2329 unsigned long action, void *ptr)
2331 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb);
2332 struct clk_notifier_data *data = ptr;
2335 case PRE_RATE_CHANGE:
2336 mutex_lock(&pmc->powergates_lock);
2339 case POST_RATE_CHANGE:
2340 pmc->rate = data->new_rate;
2343 case ABORT_RATE_CHANGE:
2344 mutex_unlock(&pmc->powergates_lock);
2349 return notifier_from_errno(-EINVAL);
2355 static void pmc_clk_fence_udelay(u32 offset)
2357 tegra_pmc_readl(pmc, offset);
2358 /* pmc clk propagation delay 2 us */
2362 static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
2364 struct pmc_clk *clk = to_pmc_clk(hw);
2367 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
2368 val &= PMC_CLK_OUT_MUX_MASK;
2373 static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
2375 struct pmc_clk *clk = to_pmc_clk(hw);
2378 val = tegra_pmc_readl(pmc, clk->offs);
2379 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift);
2380 val |= index << clk->mux_shift;
2381 tegra_pmc_writel(pmc, val, clk->offs);
2382 pmc_clk_fence_udelay(clk->offs);
2387 static int pmc_clk_is_enabled(struct clk_hw *hw)
2389 struct pmc_clk *clk = to_pmc_clk(hw);
2392 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift);
2397 static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
2401 val = tegra_pmc_readl(pmc, offs);
2402 val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
2403 tegra_pmc_writel(pmc, val, offs);
2404 pmc_clk_fence_udelay(offs);
2407 static int pmc_clk_enable(struct clk_hw *hw)
2409 struct pmc_clk *clk = to_pmc_clk(hw);
2411 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1);
2416 static void pmc_clk_disable(struct clk_hw *hw)
2418 struct pmc_clk *clk = to_pmc_clk(hw);
2420 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0);
2423 static const struct clk_ops pmc_clk_ops = {
2424 .get_parent = pmc_clk_mux_get_parent,
2425 .set_parent = pmc_clk_mux_set_parent,
2426 .determine_rate = __clk_mux_determine_rate,
2427 .is_enabled = pmc_clk_is_enabled,
2428 .enable = pmc_clk_enable,
2429 .disable = pmc_clk_disable,
2433 tegra_pmc_clk_out_register(struct tegra_pmc *pmc,
2434 const struct pmc_clk_init_data *data,
2435 unsigned long offset)
2437 struct clk_init_data init;
2438 struct pmc_clk *pmc_clk;
2440 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL);
2442 return ERR_PTR(-ENOMEM);
2444 init.name = data->name;
2445 init.ops = &pmc_clk_ops;
2446 init.parent_names = data->parents;
2447 init.num_parents = data->num_parents;
2448 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
2449 CLK_SET_PARENT_GATE;
2451 pmc_clk->hw.init = &init;
2452 pmc_clk->offs = offset;
2453 pmc_clk->mux_shift = data->mux_shift;
2454 pmc_clk->force_en_shift = data->force_en_shift;
2456 return clk_register(NULL, &pmc_clk->hw);
2459 static int pmc_clk_gate_is_enabled(struct clk_hw *hw)
2461 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2463 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
2466 static int pmc_clk_gate_enable(struct clk_hw *hw)
2468 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2470 pmc_clk_set_state(gate->offs, gate->shift, 1);
2475 static void pmc_clk_gate_disable(struct clk_hw *hw)
2477 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2479 pmc_clk_set_state(gate->offs, gate->shift, 0);
2482 static const struct clk_ops pmc_clk_gate_ops = {
2483 .is_enabled = pmc_clk_gate_is_enabled,
2484 .enable = pmc_clk_gate_enable,
2485 .disable = pmc_clk_gate_disable,
2489 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name,
2490 const char *parent_name, unsigned long offset,
2493 struct clk_init_data init;
2494 struct pmc_clk_gate *gate;
2496 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL);
2498 return ERR_PTR(-ENOMEM);
2501 init.ops = &pmc_clk_gate_ops;
2502 init.parent_names = &parent_name;
2503 init.num_parents = 1;
2506 gate->hw.init = &init;
2507 gate->offs = offset;
2508 gate->shift = shift;
2510 return clk_register(NULL, &gate->hw);
2513 static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
2514 struct device_node *np)
2517 struct clk_onecell_data *clk_data;
2518 unsigned int num_clks;
2521 num_clks = pmc->soc->num_pmc_clks;
2522 if (pmc->soc->has_blink_output)
2528 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL);
2532 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX,
2533 sizeof(*clk_data->clks), GFP_KERNEL);
2534 if (!clk_data->clks)
2537 clk_data->clk_num = TEGRA_PMC_CLK_MAX;
2539 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
2540 clk_data->clks[i] = ERR_PTR(-ENOENT);
2542 for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
2543 const struct pmc_clk_init_data *data;
2545 data = pmc->soc->pmc_clks_data + i;
2547 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL);
2549 dev_warn(pmc->dev, "unable to register clock %s: %d\n",
2550 data->name, PTR_ERR_OR_ZERO(clk));
2554 err = clk_register_clkdev(clk, data->name, NULL);
2557 "unable to register %s clock lookup: %d\n",
2562 clk_data->clks[data->clk_id] = clk;
2565 if (pmc->soc->has_blink_output) {
2566 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER);
2567 clk = tegra_pmc_clk_gate_register(pmc,
2568 "pmc_blink_override",
2571 PMC_DPD_PADS_ORIDE_BLINK);
2574 "unable to register pmc_blink_override: %d\n",
2575 PTR_ERR_OR_ZERO(clk));
2579 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink",
2580 "pmc_blink_override",
2582 PMC_CNTRL_BLINK_EN);
2585 "unable to register pmc_blink: %d\n",
2586 PTR_ERR_OR_ZERO(clk));
2590 err = clk_register_clkdev(clk, "pmc_blink", NULL);
2593 "unable to register pmc_blink lookup: %d\n",
2598 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk;
2601 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
2603 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n",
2607 static const struct regmap_range pmc_usb_sleepwalk_ranges[] = {
2608 regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO),
2609 regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE),
2610 regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE),
2611 regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP, PMC_UTMIP_UHSIC_LINE_WAKEUP),
2612 regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG),
2613 regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG),
2614 regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1),
2615 regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3),
2618 static const struct regmap_access_table pmc_usb_sleepwalk_table = {
2619 .yes_ranges = pmc_usb_sleepwalk_ranges,
2620 .n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges),
2623 static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value)
2625 struct tegra_pmc *pmc = context;
2627 *value = tegra_pmc_readl(pmc, offset);
2631 static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value)
2633 struct tegra_pmc *pmc = context;
2635 tegra_pmc_writel(pmc, value, offset);
2639 static const struct regmap_config usb_sleepwalk_regmap_config = {
2640 .name = "usb_sleepwalk",
2645 .rd_table = &pmc_usb_sleepwalk_table,
2646 .wr_table = &pmc_usb_sleepwalk_table,
2647 .reg_read = tegra_pmc_regmap_readl,
2648 .reg_write = tegra_pmc_regmap_writel,
2651 static int tegra_pmc_regmap_init(struct tegra_pmc *pmc)
2653 struct regmap *regmap;
2656 if (pmc->soc->has_usb_sleepwalk) {
2657 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config);
2658 if (IS_ERR(regmap)) {
2659 err = PTR_ERR(regmap);
2660 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err);
2668 static int tegra_pmc_probe(struct platform_device *pdev)
2671 struct resource *res;
2675 * Early initialisation should have configured an initial
2676 * register mapping and setup the soc data pointer. If these
2677 * are not valid then something went badly wrong!
2679 if (WARN_ON(!pmc->base || !pmc->soc))
2682 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
2686 /* take over the memory region from the early initialization */
2687 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2688 base = devm_ioremap_resource(&pdev->dev, res);
2690 return PTR_ERR(base);
2692 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
2694 pmc->wake = devm_ioremap_resource(&pdev->dev, res);
2695 if (IS_ERR(pmc->wake))
2696 return PTR_ERR(pmc->wake);
2701 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
2703 pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
2704 if (IS_ERR(pmc->aotag))
2705 return PTR_ERR(pmc->aotag);
2710 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
2712 pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
2713 if (IS_ERR(pmc->scratch))
2714 return PTR_ERR(pmc->scratch);
2716 pmc->scratch = base;
2719 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
2720 if (IS_ERR(pmc->clk)) {
2721 err = PTR_ERR(pmc->clk);
2723 if (err != -ENOENT) {
2724 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
2732 * PCLK clock rate can't be retrieved using CLK API because it
2733 * causes lockup if CPU enters LP2 idle state from some other
2734 * CLK notifier, hence we're caching the rate's value locally.
2737 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb;
2738 err = clk_notifier_register(pmc->clk, &pmc->clk_nb);
2741 "failed to register clk notifier\n");
2745 pmc->rate = clk_get_rate(pmc->clk);
2748 pmc->dev = &pdev->dev;
2750 tegra_pmc_init(pmc);
2752 tegra_pmc_init_tsense_reset(pmc);
2754 tegra_pmc_reset_sysfs_init(pmc);
2756 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2757 err = tegra_powergate_debugfs_init();
2762 err = register_restart_handler(&tegra_pmc_restart_handler);
2764 dev_err(&pdev->dev, "unable to register restart handler, %d\n",
2766 goto cleanup_debugfs;
2769 err = tegra_pmc_pinctrl_init(pmc);
2771 goto cleanup_restart_handler;
2773 err = tegra_pmc_regmap_init(pmc);
2775 goto cleanup_restart_handler;
2777 err = tegra_powergate_init(pmc, pdev->dev.of_node);
2779 goto cleanup_powergates;
2781 err = tegra_pmc_irq_init(pmc);
2783 goto cleanup_powergates;
2785 mutex_lock(&pmc->powergates_lock);
2788 mutex_unlock(&pmc->powergates_lock);
2790 tegra_pmc_clock_register(pmc, pdev->dev.of_node);
2791 platform_set_drvdata(pdev, pmc);
2796 tegra_powergate_remove_all(pdev->dev.of_node);
2797 cleanup_restart_handler:
2798 unregister_restart_handler(&tegra_pmc_restart_handler);
2800 debugfs_remove(pmc->debugfs);
2802 device_remove_file(&pdev->dev, &dev_attr_reset_reason);
2803 device_remove_file(&pdev->dev, &dev_attr_reset_level);
2804 clk_notifier_unregister(pmc->clk, &pmc->clk_nb);
2809 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
2810 static int tegra_pmc_suspend(struct device *dev)
2812 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2814 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);
2819 static int tegra_pmc_resume(struct device *dev)
2821 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2823 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);
2828 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
2832 static const char * const tegra20_powergates[] = {
2833 [TEGRA_POWERGATE_CPU] = "cpu",
2834 [TEGRA_POWERGATE_3D] = "3d",
2835 [TEGRA_POWERGATE_VENC] = "venc",
2836 [TEGRA_POWERGATE_VDEC] = "vdec",
2837 [TEGRA_POWERGATE_PCIE] = "pcie",
2838 [TEGRA_POWERGATE_L2] = "l2",
2839 [TEGRA_POWERGATE_MPE] = "mpe",
2842 static const struct tegra_pmc_regs tegra20_pmc_regs = {
2845 .dpd_status = 0x1bc,
2847 .dpd2_status = 0x1c4,
2848 .rst_status = 0x1b4,
2849 .rst_source_shift = 0x0,
2850 .rst_source_mask = 0x7,
2851 .rst_level_shift = 0x0,
2852 .rst_level_mask = 0x0,
2855 static void tegra20_pmc_init(struct tegra_pmc *pmc)
2857 u32 value, osc, pmu, off;
2859 /* Always enable CPU power request */
2860 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2861 value |= PMC_CNTRL_CPU_PWRREQ_OE;
2862 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2864 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2866 if (pmc->sysclkreq_high)
2867 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
2869 value |= PMC_CNTRL_SYSCLK_POLARITY;
2871 if (pmc->corereq_high)
2872 value &= ~PMC_CNTRL_PWRREQ_POLARITY;
2874 value |= PMC_CNTRL_PWRREQ_POLARITY;
2876 /* configure the output polarity while the request is tristated */
2877 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2879 /* now enable the request */
2880 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2881 value |= PMC_CNTRL_SYSCLK_OE;
2882 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2884 /* program core timings which are applicable only for suspend state */
2885 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) {
2886 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000);
2887 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000);
2888 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000);
2889 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),
2890 PMC_COREPWRGOOD_TIMER);
2891 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);
2895 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
2896 struct device_node *np,
2901 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2904 value |= PMC_CNTRL_INTR_POLARITY;
2906 value &= ~PMC_CNTRL_INTR_POLARITY;
2908 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2911 static const struct tegra_pmc_soc tegra20_pmc_soc = {
2912 .num_powergates = ARRAY_SIZE(tegra20_powergates),
2913 .powergates = tegra20_powergates,
2914 .num_cpu_powergates = 0,
2915 .cpu_powergates = NULL,
2916 .has_tsense_reset = false,
2917 .has_gpu_clamps = false,
2918 .needs_mbist_war = false,
2919 .has_impl_33v_pwr = false,
2920 .maybe_tz_only = false,
2925 .regs = &tegra20_pmc_regs,
2926 .init = tegra20_pmc_init,
2927 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2928 .powergate_set = tegra20_powergate_set,
2929 .reset_sources = NULL,
2930 .num_reset_sources = 0,
2931 .reset_levels = NULL,
2932 .num_reset_levels = 0,
2933 .pmc_clks_data = NULL,
2935 .has_blink_output = true,
2936 .has_usb_sleepwalk = false,
2939 static const char * const tegra30_powergates[] = {
2940 [TEGRA_POWERGATE_CPU] = "cpu0",
2941 [TEGRA_POWERGATE_3D] = "3d0",
2942 [TEGRA_POWERGATE_VENC] = "venc",
2943 [TEGRA_POWERGATE_VDEC] = "vdec",
2944 [TEGRA_POWERGATE_PCIE] = "pcie",
2945 [TEGRA_POWERGATE_L2] = "l2",
2946 [TEGRA_POWERGATE_MPE] = "mpe",
2947 [TEGRA_POWERGATE_HEG] = "heg",
2948 [TEGRA_POWERGATE_SATA] = "sata",
2949 [TEGRA_POWERGATE_CPU1] = "cpu1",
2950 [TEGRA_POWERGATE_CPU2] = "cpu2",
2951 [TEGRA_POWERGATE_CPU3] = "cpu3",
2952 [TEGRA_POWERGATE_CELP] = "celp",
2953 [TEGRA_POWERGATE_3D1] = "3d1",
2956 static const u8 tegra30_cpu_powergates[] = {
2957 TEGRA_POWERGATE_CPU,
2958 TEGRA_POWERGATE_CPU1,
2959 TEGRA_POWERGATE_CPU2,
2960 TEGRA_POWERGATE_CPU3,
2963 static const char * const tegra30_reset_sources[] = {
2971 static const struct tegra_pmc_soc tegra30_pmc_soc = {
2972 .num_powergates = ARRAY_SIZE(tegra30_powergates),
2973 .powergates = tegra30_powergates,
2974 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
2975 .cpu_powergates = tegra30_cpu_powergates,
2976 .has_tsense_reset = true,
2977 .has_gpu_clamps = false,
2978 .needs_mbist_war = false,
2979 .has_impl_33v_pwr = false,
2980 .maybe_tz_only = false,
2985 .regs = &tegra20_pmc_regs,
2986 .init = tegra20_pmc_init,
2987 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2988 .powergate_set = tegra20_powergate_set,
2989 .reset_sources = tegra30_reset_sources,
2990 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2991 .reset_levels = NULL,
2992 .num_reset_levels = 0,
2993 .pmc_clks_data = tegra_pmc_clks_data,
2994 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
2995 .has_blink_output = true,
2996 .has_usb_sleepwalk = false,
2999 static const char * const tegra114_powergates[] = {
3000 [TEGRA_POWERGATE_CPU] = "crail",
3001 [TEGRA_POWERGATE_3D] = "3d",
3002 [TEGRA_POWERGATE_VENC] = "venc",
3003 [TEGRA_POWERGATE_VDEC] = "vdec",
3004 [TEGRA_POWERGATE_MPE] = "mpe",
3005 [TEGRA_POWERGATE_HEG] = "heg",
3006 [TEGRA_POWERGATE_CPU1] = "cpu1",
3007 [TEGRA_POWERGATE_CPU2] = "cpu2",
3008 [TEGRA_POWERGATE_CPU3] = "cpu3",
3009 [TEGRA_POWERGATE_CELP] = "celp",
3010 [TEGRA_POWERGATE_CPU0] = "cpu0",
3011 [TEGRA_POWERGATE_C0NC] = "c0nc",
3012 [TEGRA_POWERGATE_C1NC] = "c1nc",
3013 [TEGRA_POWERGATE_DIS] = "dis",
3014 [TEGRA_POWERGATE_DISB] = "disb",
3015 [TEGRA_POWERGATE_XUSBA] = "xusba",
3016 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3017 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3020 static const u8 tegra114_cpu_powergates[] = {
3021 TEGRA_POWERGATE_CPU0,
3022 TEGRA_POWERGATE_CPU1,
3023 TEGRA_POWERGATE_CPU2,
3024 TEGRA_POWERGATE_CPU3,
3027 static const struct tegra_pmc_soc tegra114_pmc_soc = {
3028 .num_powergates = ARRAY_SIZE(tegra114_powergates),
3029 .powergates = tegra114_powergates,
3030 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
3031 .cpu_powergates = tegra114_cpu_powergates,
3032 .has_tsense_reset = true,
3033 .has_gpu_clamps = false,
3034 .needs_mbist_war = false,
3035 .has_impl_33v_pwr = false,
3036 .maybe_tz_only = false,
3041 .regs = &tegra20_pmc_regs,
3042 .init = tegra20_pmc_init,
3043 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3044 .powergate_set = tegra114_powergate_set,
3045 .reset_sources = tegra30_reset_sources,
3046 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3047 .reset_levels = NULL,
3048 .num_reset_levels = 0,
3049 .pmc_clks_data = tegra_pmc_clks_data,
3050 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3051 .has_blink_output = true,
3052 .has_usb_sleepwalk = false,
3055 static const char * const tegra124_powergates[] = {
3056 [TEGRA_POWERGATE_CPU] = "crail",
3057 [TEGRA_POWERGATE_3D] = "3d",
3058 [TEGRA_POWERGATE_VENC] = "venc",
3059 [TEGRA_POWERGATE_PCIE] = "pcie",
3060 [TEGRA_POWERGATE_VDEC] = "vdec",
3061 [TEGRA_POWERGATE_MPE] = "mpe",
3062 [TEGRA_POWERGATE_HEG] = "heg",
3063 [TEGRA_POWERGATE_SATA] = "sata",
3064 [TEGRA_POWERGATE_CPU1] = "cpu1",
3065 [TEGRA_POWERGATE_CPU2] = "cpu2",
3066 [TEGRA_POWERGATE_CPU3] = "cpu3",
3067 [TEGRA_POWERGATE_CELP] = "celp",
3068 [TEGRA_POWERGATE_CPU0] = "cpu0",
3069 [TEGRA_POWERGATE_C0NC] = "c0nc",
3070 [TEGRA_POWERGATE_C1NC] = "c1nc",
3071 [TEGRA_POWERGATE_SOR] = "sor",
3072 [TEGRA_POWERGATE_DIS] = "dis",
3073 [TEGRA_POWERGATE_DISB] = "disb",
3074 [TEGRA_POWERGATE_XUSBA] = "xusba",
3075 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3076 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3077 [TEGRA_POWERGATE_VIC] = "vic",
3078 [TEGRA_POWERGATE_IRAM] = "iram",
3081 static const u8 tegra124_cpu_powergates[] = {
3082 TEGRA_POWERGATE_CPU0,
3083 TEGRA_POWERGATE_CPU1,
3084 TEGRA_POWERGATE_CPU2,
3085 TEGRA_POWERGATE_CPU3,
3088 #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \
3089 ((struct tegra_io_pad_soc) { \
3092 .voltage = (_voltage), \
3096 #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \
3097 ((struct pinctrl_pin_desc) { \
3102 #define TEGRA124_IO_PAD_TABLE(_pad) \
3103 /* .id .dpd .voltage .name */ \
3104 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3105 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \
3106 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \
3107 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \
3108 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3109 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \
3110 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \
3111 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3112 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
3113 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
3114 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
3115 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
3116 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3117 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \
3118 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
3119 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3120 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \
3121 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
3122 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
3123 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3124 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3125 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \
3126 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \
3127 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \
3128 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \
3129 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3130 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3131 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3132 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3133 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias")
3135 static const struct tegra_io_pad_soc tegra124_io_pads[] = {
3136 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD)
3139 static const struct pinctrl_pin_desc tegra124_pin_descs[] = {
3140 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3143 static const struct tegra_pmc_soc tegra124_pmc_soc = {
3144 .num_powergates = ARRAY_SIZE(tegra124_powergates),
3145 .powergates = tegra124_powergates,
3146 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
3147 .cpu_powergates = tegra124_cpu_powergates,
3148 .has_tsense_reset = true,
3149 .has_gpu_clamps = true,
3150 .needs_mbist_war = false,
3151 .has_impl_33v_pwr = false,
3152 .maybe_tz_only = false,
3153 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
3154 .io_pads = tegra124_io_pads,
3155 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs),
3156 .pin_descs = tegra124_pin_descs,
3157 .regs = &tegra20_pmc_regs,
3158 .init = tegra20_pmc_init,
3159 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3160 .powergate_set = tegra114_powergate_set,
3161 .reset_sources = tegra30_reset_sources,
3162 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3163 .reset_levels = NULL,
3164 .num_reset_levels = 0,
3165 .pmc_clks_data = tegra_pmc_clks_data,
3166 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3167 .has_blink_output = true,
3168 .has_usb_sleepwalk = true,
3171 static const char * const tegra210_powergates[] = {
3172 [TEGRA_POWERGATE_CPU] = "crail",
3173 [TEGRA_POWERGATE_3D] = "3d",
3174 [TEGRA_POWERGATE_VENC] = "venc",
3175 [TEGRA_POWERGATE_PCIE] = "pcie",
3176 [TEGRA_POWERGATE_MPE] = "mpe",
3177 [TEGRA_POWERGATE_SATA] = "sata",
3178 [TEGRA_POWERGATE_CPU1] = "cpu1",
3179 [TEGRA_POWERGATE_CPU2] = "cpu2",
3180 [TEGRA_POWERGATE_CPU3] = "cpu3",
3181 [TEGRA_POWERGATE_CPU0] = "cpu0",
3182 [TEGRA_POWERGATE_C0NC] = "c0nc",
3183 [TEGRA_POWERGATE_SOR] = "sor",
3184 [TEGRA_POWERGATE_DIS] = "dis",
3185 [TEGRA_POWERGATE_DISB] = "disb",
3186 [TEGRA_POWERGATE_XUSBA] = "xusba",
3187 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3188 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3189 [TEGRA_POWERGATE_VIC] = "vic",
3190 [TEGRA_POWERGATE_IRAM] = "iram",
3191 [TEGRA_POWERGATE_NVDEC] = "nvdec",
3192 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
3193 [TEGRA_POWERGATE_AUD] = "aud",
3194 [TEGRA_POWERGATE_DFD] = "dfd",
3195 [TEGRA_POWERGATE_VE2] = "ve2",
3198 static const u8 tegra210_cpu_powergates[] = {
3199 TEGRA_POWERGATE_CPU0,
3200 TEGRA_POWERGATE_CPU1,
3201 TEGRA_POWERGATE_CPU2,
3202 TEGRA_POWERGATE_CPU3,
3205 #define TEGRA210_IO_PAD_TABLE(_pad) \
3206 /* .id .dpd .voltage .name */ \
3207 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \
3208 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \
3209 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \
3210 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3211 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3212 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \
3213 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \
3214 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \
3215 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \
3216 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \
3217 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \
3218 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \
3219 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \
3220 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3221 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
3222 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
3223 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
3224 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \
3225 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \
3226 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \
3227 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
3228 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3229 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
3230 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3231 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
3232 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
3233 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3234 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \
3235 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \
3236 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \
3237 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \
3238 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \
3239 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \
3240 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3241 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3242 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3243 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \
3244 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias")
3246 static const struct tegra_io_pad_soc tegra210_io_pads[] = {
3247 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD)
3250 static const struct pinctrl_pin_desc tegra210_pin_descs[] = {
3251 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3254 static const char * const tegra210_reset_sources[] = {
3263 static const struct tegra_wake_event tegra210_wake_events[] = {
3264 TEGRA_WAKE_IRQ("rtc", 16, 2),
3265 TEGRA_WAKE_IRQ("pmu", 51, 86),
3268 static const struct tegra_pmc_soc tegra210_pmc_soc = {
3269 .num_powergates = ARRAY_SIZE(tegra210_powergates),
3270 .powergates = tegra210_powergates,
3271 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
3272 .cpu_powergates = tegra210_cpu_powergates,
3273 .has_tsense_reset = true,
3274 .has_gpu_clamps = true,
3275 .needs_mbist_war = true,
3276 .has_impl_33v_pwr = false,
3277 .maybe_tz_only = true,
3278 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
3279 .io_pads = tegra210_io_pads,
3280 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
3281 .pin_descs = tegra210_pin_descs,
3282 .regs = &tegra20_pmc_regs,
3283 .init = tegra20_pmc_init,
3284 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3285 .powergate_set = tegra114_powergate_set,
3286 .irq_set_wake = tegra210_pmc_irq_set_wake,
3287 .irq_set_type = tegra210_pmc_irq_set_type,
3288 .reset_sources = tegra210_reset_sources,
3289 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
3290 .reset_levels = NULL,
3291 .num_reset_levels = 0,
3292 .num_wake_events = ARRAY_SIZE(tegra210_wake_events),
3293 .wake_events = tegra210_wake_events,
3294 .pmc_clks_data = tegra_pmc_clks_data,
3295 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3296 .has_blink_output = true,
3297 .has_usb_sleepwalk = true,
3300 #define TEGRA186_IO_PAD_TABLE(_pad) \
3301 /* .id .dpd .voltage .name */ \
3302 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3303 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3304 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3305 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3306 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3307 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3308 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3309 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3310 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3311 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3312 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3313 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \
3314 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3315 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3316 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3317 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
3318 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3319 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3320 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3321 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \
3322 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
3323 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
3324 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \
3325 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \
3326 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \
3327 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
3328 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
3329 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
3330 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
3331 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
3332 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
3333 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \
3334 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
3335 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3336 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3337 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
3338 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3339 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3341 static const struct tegra_io_pad_soc tegra186_io_pads[] = {
3342 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD)
3345 static const struct pinctrl_pin_desc tegra186_pin_descs[] = {
3346 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3349 static const struct tegra_pmc_regs tegra186_pmc_regs = {
3354 .dpd2_status = 0x80,
3356 .rst_source_shift = 0x2,
3357 .rst_source_mask = 0x3c,
3358 .rst_level_shift = 0x0,
3359 .rst_level_mask = 0x3,
3362 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3363 struct device_node *np,
3366 struct resource regs;
3371 index = of_property_match_string(np, "reg-names", "wake");
3373 dev_err(pmc->dev, "failed to find PMC wake registers\n");
3377 of_address_to_resource(np, index, ®s);
3379 wake = ioremap(regs.start, resource_size(®s));
3381 dev_err(pmc->dev, "failed to map PMC wake registers\n");
3385 value = readl(wake + WAKE_AOWAKE_CTRL);
3388 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
3390 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
3392 writel(value, wake + WAKE_AOWAKE_CTRL);
3397 static const char * const tegra186_reset_sources[] = {
3415 static const char * const tegra186_reset_levels[] = {
3416 "L0", "L1", "L2", "WARM"
3419 static const struct tegra_wake_event tegra186_wake_events[] = {
3420 TEGRA_WAKE_IRQ("pmu", 24, 209),
3421 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
3422 TEGRA_WAKE_IRQ("rtc", 73, 10),
3425 static const struct tegra_pmc_soc tegra186_pmc_soc = {
3426 .num_powergates = 0,
3428 .num_cpu_powergates = 0,
3429 .cpu_powergates = NULL,
3430 .has_tsense_reset = false,
3431 .has_gpu_clamps = false,
3432 .needs_mbist_war = false,
3433 .has_impl_33v_pwr = true,
3434 .maybe_tz_only = false,
3435 .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
3436 .io_pads = tegra186_io_pads,
3437 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
3438 .pin_descs = tegra186_pin_descs,
3439 .regs = &tegra186_pmc_regs,
3441 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3442 .irq_set_wake = tegra186_pmc_irq_set_wake,
3443 .irq_set_type = tegra186_pmc_irq_set_type,
3444 .reset_sources = tegra186_reset_sources,
3445 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),
3446 .reset_levels = tegra186_reset_levels,
3447 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3448 .num_wake_events = ARRAY_SIZE(tegra186_wake_events),
3449 .wake_events = tegra186_wake_events,
3450 .pmc_clks_data = NULL,
3452 .has_blink_output = false,
3453 .has_usb_sleepwalk = false,
3456 #define TEGRA194_IO_PAD_TABLE(_pad) \
3457 /* .id .dpd .voltage .name */ \
3458 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3459 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3460 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3461 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3462 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3463 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3464 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3465 _pad(TEGRA_IO_PAD_EQOS, 8, UINT_MAX, "eqos"), \
3466 _pad(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, UINT_MAX, "pex-clk-2-bias"), \
3467 _pad(TEGRA_IO_PAD_PEX_CLK_2, 10, UINT_MAX, "pex-clk-2"), \
3468 _pad(TEGRA_IO_PAD_DAP3, 11, UINT_MAX, "dap3"), \
3469 _pad(TEGRA_IO_PAD_DAP5, 12, UINT_MAX, "dap5"), \
3470 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3471 _pad(TEGRA_IO_PAD_PWR_CTL, 15, UINT_MAX, "pwr-ctl"), \
3472 _pad(TEGRA_IO_PAD_SOC_GPIO53, 16, UINT_MAX, "soc-gpio53"), \
3473 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3474 _pad(TEGRA_IO_PAD_GP_PWM2, 18, UINT_MAX, "gp-pwm2"), \
3475 _pad(TEGRA_IO_PAD_GP_PWM3, 19, UINT_MAX, "gp-pwm3"), \
3476 _pad(TEGRA_IO_PAD_SOC_GPIO12, 20, UINT_MAX, "soc-gpio12"), \
3477 _pad(TEGRA_IO_PAD_SOC_GPIO13, 21, UINT_MAX, "soc-gpio13"), \
3478 _pad(TEGRA_IO_PAD_SOC_GPIO10, 22, UINT_MAX, "soc-gpio10"), \
3479 _pad(TEGRA_IO_PAD_UART4, 23, UINT_MAX, "uart4"), \
3480 _pad(TEGRA_IO_PAD_UART5, 24, UINT_MAX, "uart5"), \
3481 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
3482 _pad(TEGRA_IO_PAD_HDMI_DP3, 26, UINT_MAX, "hdmi-dp3"), \
3483 _pad(TEGRA_IO_PAD_HDMI_DP2, 27, UINT_MAX, "hdmi-dp2"), \
3484 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3485 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3486 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3487 _pad(TEGRA_IO_PAD_PEX_CTL2, 33, UINT_MAX, "pex-ctl2"), \
3488 _pad(TEGRA_IO_PAD_PEX_L0_RST_N, 34, UINT_MAX, "pex-l0-rst"), \
3489 _pad(TEGRA_IO_PAD_PEX_L1_RST_N, 35, UINT_MAX, "pex-l1-rst"), \
3490 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
3491 _pad(TEGRA_IO_PAD_PEX_L5_RST_N, 37, UINT_MAX, "pex-l5-rst"), \
3492 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
3493 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
3494 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
3495 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
3496 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
3497 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
3498 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
3499 _pad(TEGRA_IO_PAD_CSIG, 50, UINT_MAX, "csig"), \
3500 _pad(TEGRA_IO_PAD_CSIH, 51, UINT_MAX, "csih"), \
3501 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
3502 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3503 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3504 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
3505 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3506 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3508 static const struct tegra_io_pad_soc tegra194_io_pads[] = {
3509 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PAD)
3512 static const struct pinctrl_pin_desc tegra194_pin_descs[] = {
3513 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3516 static const struct tegra_pmc_regs tegra194_pmc_regs = {
3521 .dpd2_status = 0x80,
3523 .rst_source_shift = 0x2,
3524 .rst_source_mask = 0x7c,
3525 .rst_level_shift = 0x0,
3526 .rst_level_mask = 0x3,
3529 static const char * const tegra194_reset_sources[] = {
3553 static const struct tegra_wake_event tegra194_wake_events[] = {
3554 TEGRA_WAKE_IRQ("pmu", 24, 209),
3555 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)),
3556 TEGRA_WAKE_IRQ("rtc", 73, 10),
3559 static const struct tegra_pmc_soc tegra194_pmc_soc = {
3560 .num_powergates = 0,
3562 .num_cpu_powergates = 0,
3563 .cpu_powergates = NULL,
3564 .has_tsense_reset = false,
3565 .has_gpu_clamps = false,
3566 .needs_mbist_war = false,
3567 .has_impl_33v_pwr = true,
3568 .maybe_tz_only = false,
3569 .num_io_pads = ARRAY_SIZE(tegra194_io_pads),
3570 .io_pads = tegra194_io_pads,
3571 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs),
3572 .pin_descs = tegra194_pin_descs,
3573 .regs = &tegra194_pmc_regs,
3575 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3576 .irq_set_wake = tegra186_pmc_irq_set_wake,
3577 .irq_set_type = tegra186_pmc_irq_set_type,
3578 .reset_sources = tegra194_reset_sources,
3579 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources),
3580 .reset_levels = tegra186_reset_levels,
3581 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3582 .num_wake_events = ARRAY_SIZE(tegra194_wake_events),
3583 .wake_events = tegra194_wake_events,
3584 .pmc_clks_data = NULL,
3586 .has_blink_output = false,
3587 .has_usb_sleepwalk = false,
3590 static const struct tegra_pmc_regs tegra234_pmc_regs = {
3597 .rst_source_shift = 0x2,
3598 .rst_source_mask = 0xfc,
3599 .rst_level_shift = 0x0,
3600 .rst_level_mask = 0x3,
3603 static const char * const tegra234_reset_sources[] = {
3627 static const struct tegra_pmc_soc tegra234_pmc_soc = {
3628 .num_powergates = 0,
3630 .num_cpu_powergates = 0,
3631 .cpu_powergates = NULL,
3632 .has_tsense_reset = false,
3633 .has_gpu_clamps = false,
3634 .needs_mbist_war = false,
3635 .has_impl_33v_pwr = true,
3636 .maybe_tz_only = false,
3641 .regs = &tegra234_pmc_regs,
3643 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3644 .irq_set_wake = tegra186_pmc_irq_set_wake,
3645 .irq_set_type = tegra186_pmc_irq_set_type,
3646 .reset_sources = tegra234_reset_sources,
3647 .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources),
3648 .reset_levels = tegra186_reset_levels,
3649 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3650 .num_wake_events = 0,
3651 .wake_events = NULL,
3652 .pmc_clks_data = NULL,
3654 .has_blink_output = false,
3657 static const struct of_device_id tegra_pmc_match[] = {
3658 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
3659 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
3660 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
3661 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
3662 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
3663 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
3664 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
3665 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
3666 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
3670 static struct platform_driver tegra_pmc_driver = {
3672 .name = "tegra-pmc",
3673 .suppress_bind_attrs = true,
3674 .of_match_table = tegra_pmc_match,
3675 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
3676 .pm = &tegra_pmc_pm_ops,
3679 .probe = tegra_pmc_probe,
3681 builtin_platform_driver(tegra_pmc_driver);
3683 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)
3687 saved = readl(pmc->base + pmc->soc->regs->scratch0);
3688 value = saved ^ 0xffffffff;
3690 if (value == 0xffffffff)
3693 /* write pattern and read it back */
3694 writel(value, pmc->base + pmc->soc->regs->scratch0);
3695 value = readl(pmc->base + pmc->soc->regs->scratch0);
3697 /* if we read all-zeroes, access is restricted to TZ only */
3699 pr_info("access to PMC is restricted to TZ\n");
3703 /* restore original value */
3704 writel(saved, pmc->base + pmc->soc->regs->scratch0);
3710 * Early initialization to allow access to registers in the very early boot
3713 static int __init tegra_pmc_early_init(void)
3715 const struct of_device_id *match;
3716 struct device_node *np;
3717 struct resource regs;
3721 mutex_init(&pmc->powergates_lock);
3723 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
3726 * Fall back to legacy initialization for 32-bit ARM only. All
3727 * 64-bit ARM device tree files for Tegra are required to have
3730 * This is for backwards-compatibility with old device trees
3731 * that didn't contain a PMC node. Note that in this case the
3732 * SoC data can't be matched and therefore powergating is
3735 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
3736 pr_warn("DT node not found, powergating disabled\n");
3738 regs.start = 0x7000e400;
3739 regs.end = 0x7000e7ff;
3740 regs.flags = IORESOURCE_MEM;
3742 pr_warn("Using memory region %pR\n", ®s);
3745 * At this point we're not running on Tegra, so play
3746 * nice with multi-platform kernels.
3752 * Extract information from the device tree if we've found a
3755 if (of_address_to_resource(np, 0, ®s) < 0) {
3756 pr_err("failed to get PMC registers\n");
3762 pmc->base = ioremap(regs.start, resource_size(®s));
3764 pr_err("failed to map PMC registers\n");
3770 pmc->soc = match->data;
3772 if (pmc->soc->maybe_tz_only)
3773 pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
3775 /* Create a bitmap of the available and valid partitions */
3776 for (i = 0; i < pmc->soc->num_powergates; i++)
3777 if (pmc->soc->powergates[i])
3778 set_bit(i, pmc->powergates_available);
3781 * Invert the interrupt polarity if a PMC device tree node
3782 * exists and contains the nvidia,invert-interrupt property.
3784 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
3786 pmc->soc->setup_irq_polarity(pmc, np, invert);
3793 early_initcall(tegra_pmc_early_init);