1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/soc/tegra/pmc.c
5 * Copyright (c) 2010 Google, Inc
6 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
9 * Colin Cross <ccross@google.com>
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
15 #include <linux/clk.h>
16 #include <linux/clk/tegra.h>
17 #include <linux/debugfs.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
23 #include <linux/iopoll.h>
24 #include <linux/irqdomain.h>
25 #include <linux/irq.h>
26 #include <linux/kernel.h>
27 #include <linux/of_address.h>
28 #include <linux/of_clk.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_platform.h>
32 #include <linux/pinctrl/pinconf-generic.h>
33 #include <linux/pinctrl/pinconf.h>
34 #include <linux/pinctrl/pinctrl.h>
35 #include <linux/platform_device.h>
36 #include <linux/pm_domain.h>
37 #include <linux/reboot.h>
38 #include <linux/reset.h>
39 #include <linux/seq_file.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
43 #include <soc/tegra/common.h>
44 #include <soc/tegra/fuse.h>
45 #include <soc/tegra/pmc.h>
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
49 #include <dt-bindings/gpio/tegra186-gpio.h>
50 #include <dt-bindings/gpio/tegra194-gpio.h>
53 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
54 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
55 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
56 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
57 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
58 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
59 #define PMC_CNTRL_MAIN_RST BIT(4)
61 #define DPD_SAMPLE 0x020
62 #define DPD_SAMPLE_ENABLE BIT(0)
63 #define DPD_SAMPLE_DISABLE (0 << 0)
65 #define PWRGATE_TOGGLE 0x30
66 #define PWRGATE_TOGGLE_START BIT(8)
68 #define REMOVE_CLAMPING 0x34
70 #define PWRGATE_STATUS 0x38
72 #define PMC_IMPL_E_33V_PWR 0x40
74 #define PMC_PWR_DET 0x48
76 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
77 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
78 #define PMC_SCRATCH0_MODE_RCM BIT(1)
79 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
80 PMC_SCRATCH0_MODE_BOOTLOADER | \
81 PMC_SCRATCH0_MODE_RCM)
83 #define PMC_CPUPWRGOOD_TIMER 0xc8
84 #define PMC_CPUPWROFF_TIMER 0xcc
86 #define PMC_PWR_DET_VALUE 0xe4
88 #define PMC_SCRATCH41 0x140
90 #define PMC_SENSOR_CTRL 0x1b0
91 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
92 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
94 #define PMC_RST_STATUS_POR 0
95 #define PMC_RST_STATUS_WATCHDOG 1
96 #define PMC_RST_STATUS_SENSOR 2
97 #define PMC_RST_STATUS_SW_MAIN 3
98 #define PMC_RST_STATUS_LP0 4
99 #define PMC_RST_STATUS_AOTAG 5
101 #define IO_DPD_REQ 0x1b8
102 #define IO_DPD_REQ_CODE_IDLE (0U << 30)
103 #define IO_DPD_REQ_CODE_OFF (1U << 30)
104 #define IO_DPD_REQ_CODE_ON (2U << 30)
105 #define IO_DPD_REQ_CODE_MASK (3U << 30)
107 #define IO_DPD_STATUS 0x1bc
108 #define IO_DPD2_REQ 0x1c0
109 #define IO_DPD2_STATUS 0x1c4
110 #define SEL_DPD_TIM 0x1c8
112 #define PMC_SCRATCH54 0x258
113 #define PMC_SCRATCH54_DATA_SHIFT 8
114 #define PMC_SCRATCH54_ADDR_SHIFT 0
116 #define PMC_SCRATCH55 0x25c
117 #define PMC_SCRATCH55_RESET_TEGRA BIT(31)
118 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
119 #define PMC_SCRATCH55_PINMUX_SHIFT 24
120 #define PMC_SCRATCH55_16BITOP BIT(15)
121 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
122 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
124 #define GPU_RG_CNTRL 0x2d4
126 /* Tegra186 and later */
127 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
128 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)
129 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))
130 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))
131 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))
132 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))
133 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
134 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
135 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
137 #define WAKE_AOWAKE_CTRL 0x4f4
138 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
141 #define TEGRA_SMC_PMC 0xc2fffe00
142 #define TEGRA_SMC_PMC_READ 0xaa
143 #define TEGRA_SMC_PMC_WRITE 0xbb
145 struct tegra_powergate {
146 struct generic_pm_domain genpd;
147 struct tegra_pmc *pmc;
150 unsigned int num_clks;
151 struct reset_control *reset;
154 struct tegra_io_pad_soc {
155 enum tegra_io_pad id;
157 unsigned int voltage;
161 struct tegra_pmc_regs {
162 unsigned int scratch0;
163 unsigned int dpd_req;
164 unsigned int dpd_status;
165 unsigned int dpd2_req;
166 unsigned int dpd2_status;
167 unsigned int rst_status;
168 unsigned int rst_source_shift;
169 unsigned int rst_source_mask;
170 unsigned int rst_level_shift;
171 unsigned int rst_level_mask;
174 struct tegra_wake_event {
179 unsigned int instance;
184 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \
190 .instance = UINT_MAX, \
195 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \
201 .instance = _instance, \
206 struct tegra_pmc_soc {
207 unsigned int num_powergates;
208 const char *const *powergates;
209 unsigned int num_cpu_powergates;
210 const u8 *cpu_powergates;
212 bool has_tsense_reset;
214 bool needs_mbist_war;
215 bool has_impl_33v_pwr;
218 const struct tegra_io_pad_soc *io_pads;
219 unsigned int num_io_pads;
221 const struct pinctrl_pin_desc *pin_descs;
222 unsigned int num_pin_descs;
224 const struct tegra_pmc_regs *regs;
225 void (*init)(struct tegra_pmc *pmc);
226 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
227 struct device_node *np,
230 const char * const *reset_sources;
231 unsigned int num_reset_sources;
232 const char * const *reset_levels;
233 unsigned int num_reset_levels;
235 const struct tegra_wake_event *wake_events;
236 unsigned int num_wake_events;
239 static const char * const tegra186_reset_sources[] = {
257 static const char * const tegra186_reset_levels[] = {
258 "L0", "L1", "L2", "WARM"
261 static const char * const tegra30_reset_sources[] = {
269 static const char * const tegra210_reset_sources[] = {
279 * struct tegra_pmc - NVIDIA Tegra PMC
280 * @dev: pointer to PMC device structure
281 * @base: pointer to I/O remapped register region
282 * @wake: pointer to I/O remapped region for WAKE registers
283 * @aotag: pointer to I/O remapped region for AOTAG registers
284 * @scratch: pointer to I/O remapped region for scratch registers
285 * @clk: pointer to pclk clock
286 * @soc: pointer to SoC data structure
287 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone
288 * @debugfs: pointer to debugfs entry
289 * @rate: currently configured rate of pclk
290 * @suspend_mode: lowest suspend mode available
291 * @cpu_good_time: CPU power good time (in microseconds)
292 * @cpu_off_time: CPU power off time (in microsecends)
293 * @core_osc_time: core power good OSC time (in microseconds)
294 * @core_pmu_time: core power good PMU time (in microseconds)
295 * @core_off_time: core power off time (in microseconds)
296 * @corereq_high: core power request is active-high
297 * @sysclkreq_high: system clock request is active-high
298 * @combined_req: combined power request for CPU & core
299 * @cpu_pwr_good_en: CPU power good signal is enabled
300 * @lp0_vec_phys: physical base address of the LP0 warm boot code
301 * @lp0_vec_size: size of the LP0 warm boot code
302 * @powergates_available: Bitmap of available power gates
303 * @powergates_lock: mutex for power gate register access
304 * @pctl_dev: pin controller exposed by the PMC
305 * @domain: IRQ domain provided by the PMC
306 * @irq: chip implementation for the IRQ domain
313 void __iomem *scratch;
315 struct dentry *debugfs;
317 const struct tegra_pmc_soc *soc;
322 enum tegra_suspend_mode suspend_mode;
331 bool cpu_pwr_good_en;
334 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
336 struct mutex powergates_lock;
338 struct pinctrl_dev *pctl_dev;
340 struct irq_domain *domain;
344 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
346 .suspend_mode = TEGRA_SUSPEND_NONE,
349 static inline struct tegra_powergate *
350 to_powergate(struct generic_pm_domain *domain)
352 return container_of(domain, struct tegra_powergate, genpd);
355 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
357 struct arm_smccc_res res;
360 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
364 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
367 pr_warn("%s(): SMC failed: %lu\n", __func__,
374 return readl(pmc->base + offset);
377 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
378 unsigned long offset)
380 struct arm_smccc_res res;
383 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
384 value, 0, 0, 0, 0, &res);
387 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
390 pr_warn("%s(): SMC failed: %lu\n", __func__,
394 writel(value, pmc->base + offset);
398 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)
401 return tegra_pmc_readl(pmc, offset);
403 return readl(pmc->scratch + offset);
406 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
407 unsigned long offset)
410 tegra_pmc_writel(pmc, value, offset);
412 writel(value, pmc->scratch + offset);
416 * TODO Figure out a way to call this with the struct tegra_pmc * passed in.
417 * This currently doesn't work because readx_poll_timeout() can only operate
418 * on functions that take a single argument.
420 static inline bool tegra_powergate_state(int id)
422 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
423 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;
425 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;
428 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id)
430 return (pmc->soc && pmc->soc->powergates[id]);
433 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id)
435 return test_bit(id, pmc->powergates_available);
438 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
442 if (!pmc || !pmc->soc || !name)
445 for (i = 0; i < pmc->soc->num_powergates; i++) {
446 if (!tegra_powergate_is_valid(pmc, i))
449 if (!strcmp(name, pmc->soc->powergates[i]))
457 * tegra_powergate_set() - set the state of a partition
458 * @pmc: power management controller
460 * @new_state: new state of the partition
462 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id,
468 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
471 mutex_lock(&pmc->powergates_lock);
473 if (tegra_powergate_state(id) == new_state) {
474 mutex_unlock(&pmc->powergates_lock);
478 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
480 err = readx_poll_timeout(tegra_powergate_state, id, status,
481 status == new_state, 10, 100000);
483 mutex_unlock(&pmc->powergates_lock);
488 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
493 mutex_lock(&pmc->powergates_lock);
496 * On Tegra124 and later, the clamps for the GPU are controlled by a
497 * separate register (with different semantics).
499 if (id == TEGRA_POWERGATE_3D) {
500 if (pmc->soc->has_gpu_clamps) {
501 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);
507 * Tegra 2 has a bug where PCIE and VDE clamping masks are
508 * swapped relatively to the partition ids
510 if (id == TEGRA_POWERGATE_VDEC)
511 mask = (1 << TEGRA_POWERGATE_PCIE);
512 else if (id == TEGRA_POWERGATE_PCIE)
513 mask = (1 << TEGRA_POWERGATE_VDEC);
517 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);
520 mutex_unlock(&pmc->powergates_lock);
525 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
529 for (i = 0; i < pg->num_clks; i++)
530 clk_disable_unprepare(pg->clks[i]);
533 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
538 for (i = 0; i < pg->num_clks; i++) {
539 err = clk_prepare_enable(pg->clks[i]);
548 clk_disable_unprepare(pg->clks[i]);
553 int __weak tegra210_clk_handle_mbist_war(unsigned int id)
558 static int tegra_powergate_power_up(struct tegra_powergate *pg,
563 err = reset_control_assert(pg->reset);
567 usleep_range(10, 20);
569 err = tegra_powergate_set(pg->pmc, pg->id, true);
573 usleep_range(10, 20);
575 err = tegra_powergate_enable_clocks(pg);
579 usleep_range(10, 20);
581 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
585 usleep_range(10, 20);
587 err = reset_control_deassert(pg->reset);
591 usleep_range(10, 20);
593 if (pg->pmc->soc->needs_mbist_war)
594 err = tegra210_clk_handle_mbist_war(pg->id);
599 tegra_powergate_disable_clocks(pg);
604 tegra_powergate_disable_clocks(pg);
605 usleep_range(10, 20);
608 tegra_powergate_set(pg->pmc, pg->id, false);
613 static int tegra_powergate_power_down(struct tegra_powergate *pg)
617 err = tegra_powergate_enable_clocks(pg);
621 usleep_range(10, 20);
623 err = reset_control_assert(pg->reset);
627 usleep_range(10, 20);
629 tegra_powergate_disable_clocks(pg);
631 usleep_range(10, 20);
633 err = tegra_powergate_set(pg->pmc, pg->id, false);
640 tegra_powergate_enable_clocks(pg);
641 usleep_range(10, 20);
642 reset_control_deassert(pg->reset);
643 usleep_range(10, 20);
646 tegra_powergate_disable_clocks(pg);
651 static int tegra_genpd_power_on(struct generic_pm_domain *domain)
653 struct tegra_powergate *pg = to_powergate(domain);
654 struct device *dev = pg->pmc->dev;
657 err = tegra_powergate_power_up(pg, true);
659 dev_err(dev, "failed to turn on PM domain %s: %d\n",
660 pg->genpd.name, err);
664 reset_control_release(pg->reset);
670 static int tegra_genpd_power_off(struct generic_pm_domain *domain)
672 struct tegra_powergate *pg = to_powergate(domain);
673 struct device *dev = pg->pmc->dev;
676 err = reset_control_acquire(pg->reset);
678 pr_err("failed to acquire resets: %d\n", err);
682 err = tegra_powergate_power_down(pg);
684 dev_err(dev, "failed to turn off PM domain %s: %d\n",
685 pg->genpd.name, err);
686 reset_control_release(pg->reset);
693 * tegra_powergate_power_on() - power on partition
696 int tegra_powergate_power_on(unsigned int id)
698 if (!tegra_powergate_is_available(pmc, id))
701 return tegra_powergate_set(pmc, id, true);
703 EXPORT_SYMBOL(tegra_powergate_power_on);
706 * tegra_powergate_power_off() - power off partition
709 int tegra_powergate_power_off(unsigned int id)
711 if (!tegra_powergate_is_available(pmc, id))
714 return tegra_powergate_set(pmc, id, false);
716 EXPORT_SYMBOL(tegra_powergate_power_off);
719 * tegra_powergate_is_powered() - check if partition is powered
720 * @pmc: power management controller
723 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id)
725 if (!tegra_powergate_is_valid(pmc, id))
728 return tegra_powergate_state(id);
732 * tegra_powergate_remove_clamping() - remove power clamps for partition
735 int tegra_powergate_remove_clamping(unsigned int id)
737 if (!tegra_powergate_is_available(pmc, id))
740 return __tegra_powergate_remove_clamping(pmc, id);
742 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
745 * tegra_powergate_sequence_power_up() - power up partition
747 * @clk: clock for partition
748 * @rst: reset for partition
750 * Must be called with clk disabled, and returns with clk enabled.
752 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
753 struct reset_control *rst)
755 struct tegra_powergate *pg;
758 if (!tegra_powergate_is_available(pmc, id))
761 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
771 err = tegra_powergate_power_up(pg, false);
773 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
780 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
783 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
784 * @pmc: power management controller
785 * @cpuid: CPU partition ID
787 * Returns the partition ID corresponding to the CPU partition ID or a
788 * negative error code on failure.
790 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc,
793 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
794 return pmc->soc->cpu_powergates[cpuid];
800 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
801 * @cpuid: CPU partition ID
803 bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
807 id = tegra_get_cpu_powergate_id(pmc, cpuid);
811 return tegra_powergate_is_powered(pmc, id);
815 * tegra_pmc_cpu_power_on() - power on CPU partition
816 * @cpuid: CPU partition ID
818 int tegra_pmc_cpu_power_on(unsigned int cpuid)
822 id = tegra_get_cpu_powergate_id(pmc, cpuid);
826 return tegra_powergate_set(pmc, id, true);
830 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
831 * @cpuid: CPU partition ID
833 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
837 id = tegra_get_cpu_powergate_id(pmc, cpuid);
841 return tegra_powergate_remove_clamping(id);
844 static int tegra_pmc_restart_notify(struct notifier_block *this,
845 unsigned long action, void *data)
847 const char *cmd = data;
850 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
851 value &= ~PMC_SCRATCH0_MODE_MASK;
854 if (strcmp(cmd, "recovery") == 0)
855 value |= PMC_SCRATCH0_MODE_RECOVERY;
857 if (strcmp(cmd, "bootloader") == 0)
858 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
860 if (strcmp(cmd, "forced-recovery") == 0)
861 value |= PMC_SCRATCH0_MODE_RCM;
864 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
866 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
867 value = tegra_pmc_readl(pmc, PMC_CNTRL);
868 value |= PMC_CNTRL_MAIN_RST;
869 tegra_pmc_writel(pmc, value, PMC_CNTRL);
874 static struct notifier_block tegra_pmc_restart_handler = {
875 .notifier_call = tegra_pmc_restart_notify,
879 static int powergate_show(struct seq_file *s, void *data)
884 seq_printf(s, " powergate powered\n");
885 seq_printf(s, "------------------\n");
887 for (i = 0; i < pmc->soc->num_powergates; i++) {
888 status = tegra_powergate_is_powered(pmc, i);
892 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
893 status ? "yes" : "no");
899 DEFINE_SHOW_ATTRIBUTE(powergate);
901 static int tegra_powergate_debugfs_init(void)
903 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
911 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
912 struct device_node *np)
915 unsigned int i, count;
918 count = of_clk_get_parent_count(np);
922 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
926 for (i = 0; i < count; i++) {
927 pg->clks[i] = of_clk_get(np, i);
928 if (IS_ERR(pg->clks[i])) {
929 err = PTR_ERR(pg->clks[i]);
934 pg->num_clks = count;
940 clk_put(pg->clks[i]);
947 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
948 struct device_node *np, bool off)
950 struct device *dev = pg->pmc->dev;
953 pg->reset = of_reset_control_array_get_exclusive_released(np);
954 if (IS_ERR(pg->reset)) {
955 err = PTR_ERR(pg->reset);
956 dev_err(dev, "failed to get device resets: %d\n", err);
960 err = reset_control_acquire(pg->reset);
962 pr_err("failed to acquire resets: %d\n", err);
967 err = reset_control_assert(pg->reset);
969 err = reset_control_deassert(pg->reset);
973 reset_control_release(pg->reset);
978 reset_control_release(pg->reset);
979 reset_control_put(pg->reset);
985 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
987 struct device *dev = pmc->dev;
988 struct tegra_powergate *pg;
992 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
996 id = tegra_powergate_lookup(pmc, np->name);
998 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id);
1004 * Clear the bit for this powergate so it cannot be managed
1005 * directly via the legacy APIs for controlling powergates.
1007 clear_bit(id, pmc->powergates_available);
1010 pg->genpd.name = np->name;
1011 pg->genpd.power_off = tegra_genpd_power_off;
1012 pg->genpd.power_on = tegra_genpd_power_on;
1015 off = !tegra_powergate_is_powered(pmc, pg->id);
1017 err = tegra_powergate_of_get_clks(pg, np);
1019 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err);
1023 err = tegra_powergate_of_get_resets(pg, np, off);
1025 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err);
1029 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
1031 WARN_ON(tegra_powergate_power_up(pg, true));
1036 err = pm_genpd_init(&pg->genpd, NULL, off);
1038 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np,
1043 err = of_genpd_add_provider_simple(np, &pg->genpd);
1045 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n",
1050 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name);
1055 pm_genpd_remove(&pg->genpd);
1058 reset_control_put(pg->reset);
1061 while (pg->num_clks--)
1062 clk_put(pg->clks[pg->num_clks]);
1067 set_bit(id, pmc->powergates_available);
1075 static int tegra_powergate_init(struct tegra_pmc *pmc,
1076 struct device_node *parent)
1078 struct device_node *np, *child;
1081 np = of_get_child_by_name(parent, "powergates");
1085 for_each_child_of_node(np, child) {
1086 err = tegra_powergate_add(pmc, child);
1098 static void tegra_powergate_remove(struct generic_pm_domain *genpd)
1100 struct tegra_powergate *pg = to_powergate(genpd);
1102 reset_control_put(pg->reset);
1104 while (pg->num_clks--)
1105 clk_put(pg->clks[pg->num_clks]);
1109 set_bit(pg->id, pmc->powergates_available);
1114 static void tegra_powergate_remove_all(struct device_node *parent)
1116 struct generic_pm_domain *genpd;
1117 struct device_node *np, *child;
1119 np = of_get_child_by_name(parent, "powergates");
1123 for_each_child_of_node(np, child) {
1124 of_genpd_del_provider(child);
1126 genpd = of_genpd_remove_last(child);
1130 tegra_powergate_remove(genpd);
1136 static const struct tegra_io_pad_soc *
1137 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
1141 for (i = 0; i < pmc->soc->num_io_pads; i++)
1142 if (pmc->soc->io_pads[i].id == id)
1143 return &pmc->soc->io_pads[i];
1148 static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc,
1149 enum tegra_io_pad id,
1150 unsigned long *request,
1151 unsigned long *status,
1154 const struct tegra_io_pad_soc *pad;
1156 pad = tegra_io_pad_find(pmc, id);
1158 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1162 if (pad->dpd == UINT_MAX)
1165 *mask = BIT(pad->dpd % 32);
1167 if (pad->dpd < 32) {
1168 *status = pmc->soc->regs->dpd_status;
1169 *request = pmc->soc->regs->dpd_req;
1171 *status = pmc->soc->regs->dpd2_status;
1172 *request = pmc->soc->regs->dpd2_req;
1178 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id,
1179 unsigned long *request, unsigned long *status,
1182 unsigned long rate, value;
1185 err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask);
1190 rate = clk_get_rate(pmc->clk);
1192 dev_err(pmc->dev, "failed to get clock rate\n");
1196 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);
1198 /* must be at least 200 ns, in APB (PCLK) clock cycles */
1199 value = DIV_ROUND_UP(1000000000, rate);
1200 value = DIV_ROUND_UP(200, value);
1201 tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
1207 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset,
1208 u32 mask, u32 val, unsigned long timeout)
1212 timeout = jiffies + msecs_to_jiffies(timeout);
1214 while (time_after(timeout, jiffies)) {
1215 value = tegra_pmc_readl(pmc, offset);
1216 if ((value & mask) == val)
1219 usleep_range(250, 1000);
1225 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)
1228 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);
1232 * tegra_io_pad_power_enable() - enable power to I/O pad
1233 * @id: Tegra I/O pad ID for which to enable power
1235 * Returns: 0 on success or a negative error code on failure.
1237 int tegra_io_pad_power_enable(enum tegra_io_pad id)
1239 unsigned long request, status;
1243 mutex_lock(&pmc->powergates_lock);
1245 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1247 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1251 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);
1253 err = tegra_io_pad_poll(pmc, status, mask, 0, 250);
1255 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err);
1259 tegra_io_pad_unprepare(pmc);
1262 mutex_unlock(&pmc->powergates_lock);
1265 EXPORT_SYMBOL(tegra_io_pad_power_enable);
1268 * tegra_io_pad_power_disable() - disable power to I/O pad
1269 * @id: Tegra I/O pad ID for which to disable power
1271 * Returns: 0 on success or a negative error code on failure.
1273 int tegra_io_pad_power_disable(enum tegra_io_pad id)
1275 unsigned long request, status;
1279 mutex_lock(&pmc->powergates_lock);
1281 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1283 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1287 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);
1289 err = tegra_io_pad_poll(pmc, status, mask, mask, 250);
1291 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err);
1295 tegra_io_pad_unprepare(pmc);
1298 mutex_unlock(&pmc->powergates_lock);
1301 EXPORT_SYMBOL(tegra_io_pad_power_disable);
1303 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)
1305 unsigned long request, status;
1309 err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status,
1314 value = tegra_pmc_readl(pmc, status);
1316 return !(value & mask);
1319 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,
1322 const struct tegra_io_pad_soc *pad;
1325 pad = tegra_io_pad_find(pmc, id);
1329 if (pad->voltage == UINT_MAX)
1332 mutex_lock(&pmc->powergates_lock);
1334 if (pmc->soc->has_impl_33v_pwr) {
1335 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1337 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1338 value &= ~BIT(pad->voltage);
1340 value |= BIT(pad->voltage);
1342 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
1344 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1345 value = tegra_pmc_readl(pmc, PMC_PWR_DET);
1346 value |= BIT(pad->voltage);
1347 tegra_pmc_writel(pmc, value, PMC_PWR_DET);
1349 /* update I/O voltage */
1350 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1352 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1353 value &= ~BIT(pad->voltage);
1355 value |= BIT(pad->voltage);
1357 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
1360 mutex_unlock(&pmc->powergates_lock);
1362 usleep_range(100, 250);
1367 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)
1369 const struct tegra_io_pad_soc *pad;
1372 pad = tegra_io_pad_find(pmc, id);
1376 if (pad->voltage == UINT_MAX)
1379 if (pmc->soc->has_impl_33v_pwr)
1380 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1382 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1384 if ((value & BIT(pad->voltage)) == 0)
1385 return TEGRA_IO_PAD_VOLTAGE_1V8;
1387 return TEGRA_IO_PAD_VOLTAGE_3V3;
1391 * tegra_io_rail_power_on() - enable power to I/O rail
1392 * @id: Tegra I/O pad ID for which to enable power
1394 * See also: tegra_io_pad_power_enable()
1396 int tegra_io_rail_power_on(unsigned int id)
1398 return tegra_io_pad_power_enable(id);
1400 EXPORT_SYMBOL(tegra_io_rail_power_on);
1403 * tegra_io_rail_power_off() - disable power to I/O rail
1404 * @id: Tegra I/O pad ID for which to disable power
1406 * See also: tegra_io_pad_power_disable()
1408 int tegra_io_rail_power_off(unsigned int id)
1410 return tegra_io_pad_power_disable(id);
1412 EXPORT_SYMBOL(tegra_io_rail_power_off);
1414 #ifdef CONFIG_PM_SLEEP
1415 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1417 return pmc->suspend_mode;
1420 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1422 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1425 pmc->suspend_mode = mode;
1428 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1430 unsigned long long rate = 0;
1434 case TEGRA_SUSPEND_LP1:
1438 case TEGRA_SUSPEND_LP2:
1439 rate = clk_get_rate(pmc->clk);
1446 if (WARN_ON_ONCE(rate == 0))
1449 if (rate != pmc->rate) {
1452 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1453 do_div(ticks, USEC_PER_SEC);
1454 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
1456 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1457 do_div(ticks, USEC_PER_SEC);
1458 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
1465 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1466 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1467 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1468 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1472 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1474 u32 value, values[2];
1476 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1480 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1484 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1488 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1492 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1497 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1499 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1500 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1502 pmc->cpu_good_time = value;
1504 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1505 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1507 pmc->cpu_off_time = value;
1509 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1510 values, ARRAY_SIZE(values)))
1511 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1513 pmc->core_osc_time = values[0];
1514 pmc->core_pmu_time = values[1];
1516 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1517 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1519 pmc->core_off_time = value;
1521 pmc->corereq_high = of_property_read_bool(np,
1522 "nvidia,core-power-req-active-high");
1524 pmc->sysclkreq_high = of_property_read_bool(np,
1525 "nvidia,sys-clock-req-active-high");
1527 pmc->combined_req = of_property_read_bool(np,
1528 "nvidia,combined-power-req");
1530 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1531 "nvidia,cpu-pwr-good-en");
1533 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1534 ARRAY_SIZE(values)))
1535 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1536 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1538 pmc->lp0_vec_phys = values[0];
1539 pmc->lp0_vec_size = values[1];
1544 static void tegra_pmc_init(struct tegra_pmc *pmc)
1547 pmc->soc->init(pmc);
1550 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1552 static const char disabled[] = "emergency thermal reset disabled";
1553 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1554 struct device *dev = pmc->dev;
1555 struct device_node *np;
1556 u32 value, checksum;
1558 if (!pmc->soc->has_tsense_reset)
1561 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
1563 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1567 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1568 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1572 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1573 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1577 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) {
1578 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1582 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) {
1583 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1587 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1590 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1591 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1592 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1594 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1595 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1596 tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
1598 value = PMC_SCRATCH55_RESET_TEGRA;
1599 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1600 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1601 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1604 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
1605 * contain the checksum and are currently zero, so they are not added.
1607 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1608 + ((value >> 24) & 0xff);
1610 checksum = 0x100 - checksum;
1612 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1614 tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
1616 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1617 value |= PMC_SENSOR_CTRL_ENABLE_RST;
1618 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1620 dev_info(pmc->dev, "emergency thermal reset enabled\n");
1626 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev)
1628 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1630 return pmc->soc->num_io_pads;
1633 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl,
1636 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl);
1638 return pmc->soc->io_pads[group].name;
1641 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev,
1643 const unsigned int **pins,
1644 unsigned int *num_pins)
1646 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1648 *pins = &pmc->soc->io_pads[group].id;
1654 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = {
1655 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count,
1656 .get_group_name = tegra_io_pad_pinctrl_get_group_name,
1657 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins,
1658 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1659 .dt_free_map = pinconf_generic_dt_free_map,
1662 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev,
1663 unsigned int pin, unsigned long *config)
1665 enum pin_config_param param = pinconf_to_config_param(*config);
1666 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1667 const struct tegra_io_pad_soc *pad;
1671 pad = tegra_io_pad_find(pmc, pin);
1676 case PIN_CONFIG_POWER_SOURCE:
1677 ret = tegra_io_pad_get_voltage(pmc, pad->id);
1684 case PIN_CONFIG_LOW_POWER_MODE:
1685 ret = tegra_io_pad_is_powered(pmc, pad->id);
1696 *config = pinconf_to_config_packed(param, arg);
1701 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev,
1702 unsigned int pin, unsigned long *configs,
1703 unsigned int num_configs)
1705 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1706 const struct tegra_io_pad_soc *pad;
1707 enum pin_config_param param;
1712 pad = tegra_io_pad_find(pmc, pin);
1716 for (i = 0; i < num_configs; ++i) {
1717 param = pinconf_to_config_param(configs[i]);
1718 arg = pinconf_to_config_argument(configs[i]);
1721 case PIN_CONFIG_LOW_POWER_MODE:
1723 err = tegra_io_pad_power_disable(pad->id);
1725 err = tegra_io_pad_power_enable(pad->id);
1729 case PIN_CONFIG_POWER_SOURCE:
1730 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 &&
1731 arg != TEGRA_IO_PAD_VOLTAGE_3V3)
1733 err = tegra_io_pad_set_voltage(pmc, pad->id, arg);
1745 static const struct pinconf_ops tegra_io_pad_pinconf_ops = {
1746 .pin_config_get = tegra_io_pad_pinconf_get,
1747 .pin_config_set = tegra_io_pad_pinconf_set,
1751 static struct pinctrl_desc tegra_pmc_pctl_desc = {
1752 .pctlops = &tegra_io_pad_pinctrl_ops,
1753 .confops = &tegra_io_pad_pinconf_ops,
1756 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
1760 if (!pmc->soc->num_pin_descs)
1763 tegra_pmc_pctl_desc.name = dev_name(pmc->dev);
1764 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs;
1765 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs;
1767 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc,
1769 if (IS_ERR(pmc->pctl_dev)) {
1770 err = PTR_ERR(pmc->pctl_dev);
1771 dev_err(pmc->dev, "failed to register pin controller: %d\n",
1779 static ssize_t reset_reason_show(struct device *dev,
1780 struct device_attribute *attr, char *buf)
1784 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
1785 value &= pmc->soc->regs->rst_source_mask;
1786 value >>= pmc->soc->regs->rst_source_shift;
1788 if (WARN_ON(value >= pmc->soc->num_reset_sources))
1789 return sprintf(buf, "%s\n", "UNKNOWN");
1791 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
1794 static DEVICE_ATTR_RO(reset_reason);
1796 static ssize_t reset_level_show(struct device *dev,
1797 struct device_attribute *attr, char *buf)
1801 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
1802 value &= pmc->soc->regs->rst_level_mask;
1803 value >>= pmc->soc->regs->rst_level_shift;
1805 if (WARN_ON(value >= pmc->soc->num_reset_levels))
1806 return sprintf(buf, "%s\n", "UNKNOWN");
1808 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
1811 static DEVICE_ATTR_RO(reset_level);
1813 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
1815 struct device *dev = pmc->dev;
1818 if (pmc->soc->reset_sources) {
1819 err = device_create_file(dev, &dev_attr_reset_reason);
1822 "failed to create attr \"reset_reason\": %d\n",
1826 if (pmc->soc->reset_levels) {
1827 err = device_create_file(dev, &dev_attr_reset_level);
1830 "failed to create attr \"reset_level\": %d\n",
1835 static int tegra_pmc_irq_translate(struct irq_domain *domain,
1836 struct irq_fwspec *fwspec,
1837 unsigned long *hwirq,
1840 if (WARN_ON(fwspec->param_count < 2))
1843 *hwirq = fwspec->param[0];
1844 *type = fwspec->param[1];
1849 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq,
1850 unsigned int num_irqs, void *data)
1852 struct tegra_pmc *pmc = domain->host_data;
1853 const struct tegra_pmc_soc *soc = pmc->soc;
1854 struct irq_fwspec *fwspec = data;
1858 for (i = 0; i < soc->num_wake_events; i++) {
1859 const struct tegra_wake_event *event = &soc->wake_events[i];
1861 if (fwspec->param_count == 2) {
1862 struct irq_fwspec spec;
1864 if (event->id != fwspec->param[0])
1867 err = irq_domain_set_hwirq_and_chip(domain, virq,
1873 spec.fwnode = &pmc->dev->of_node->fwnode;
1874 spec.param_count = 3;
1875 spec.param[0] = GIC_SPI;
1876 spec.param[1] = event->irq;
1877 spec.param[2] = fwspec->param[1];
1879 err = irq_domain_alloc_irqs_parent(domain, virq,
1885 if (fwspec->param_count == 3) {
1886 if (event->gpio.instance != fwspec->param[0] ||
1887 event->gpio.pin != fwspec->param[1])
1890 err = irq_domain_set_hwirq_and_chip(domain, virq,
1898 if (i == soc->num_wake_events)
1899 err = irq_domain_set_hwirq_and_chip(domain, virq, ULONG_MAX,
1905 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {
1906 .translate = tegra_pmc_irq_translate,
1907 .alloc = tegra_pmc_irq_alloc,
1910 static int tegra_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
1912 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
1913 unsigned int offset, bit;
1916 offset = data->hwirq / 32;
1917 bit = data->hwirq % 32;
1919 /* clear wake status */
1920 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
1922 /* route wake to tier 2 */
1923 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
1926 value &= ~(1 << bit);
1930 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
1932 /* enable wakeup event */
1933 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
1938 static int tegra_pmc_irq_set_type(struct irq_data *data, unsigned int type)
1940 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
1943 if (data->hwirq == ULONG_MAX)
1946 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
1949 case IRQ_TYPE_EDGE_RISING:
1950 case IRQ_TYPE_LEVEL_HIGH:
1951 value |= WAKE_AOWAKE_CNTRL_LEVEL;
1954 case IRQ_TYPE_EDGE_FALLING:
1955 case IRQ_TYPE_LEVEL_LOW:
1956 value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
1959 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
1960 value ^= WAKE_AOWAKE_CNTRL_LEVEL;
1967 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
1972 static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
1974 struct irq_domain *parent = NULL;
1975 struct device_node *np;
1977 np = of_irq_find_parent(pmc->dev->of_node);
1979 parent = irq_find_host(np);
1986 pmc->irq.name = dev_name(pmc->dev);
1987 pmc->irq.irq_mask = irq_chip_mask_parent;
1988 pmc->irq.irq_unmask = irq_chip_unmask_parent;
1989 pmc->irq.irq_eoi = irq_chip_eoi_parent;
1990 pmc->irq.irq_set_affinity = irq_chip_set_affinity_parent;
1991 pmc->irq.irq_set_type = tegra_pmc_irq_set_type;
1992 pmc->irq.irq_set_wake = tegra_pmc_irq_set_wake;
1994 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,
1995 &tegra_pmc_irq_domain_ops, pmc);
1997 dev_err(pmc->dev, "failed to allocate domain\n");
2004 static int tegra_pmc_probe(struct platform_device *pdev)
2007 struct resource *res;
2011 * Early initialisation should have configured an initial
2012 * register mapping and setup the soc data pointer. If these
2013 * are not valid then something went badly wrong!
2015 if (WARN_ON(!pmc->base || !pmc->soc))
2018 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
2022 /* take over the memory region from the early initialization */
2023 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2024 base = devm_ioremap_resource(&pdev->dev, res);
2026 return PTR_ERR(base);
2028 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
2030 pmc->wake = devm_ioremap_resource(&pdev->dev, res);
2031 if (IS_ERR(pmc->wake))
2032 return PTR_ERR(pmc->wake);
2037 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
2039 pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
2040 if (IS_ERR(pmc->aotag))
2041 return PTR_ERR(pmc->aotag);
2046 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
2048 pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
2049 if (IS_ERR(pmc->scratch))
2050 return PTR_ERR(pmc->scratch);
2052 pmc->scratch = base;
2055 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
2056 if (IS_ERR(pmc->clk)) {
2057 err = PTR_ERR(pmc->clk);
2059 if (err != -ENOENT) {
2060 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
2067 pmc->dev = &pdev->dev;
2069 tegra_pmc_init(pmc);
2071 tegra_pmc_init_tsense_reset(pmc);
2073 tegra_pmc_reset_sysfs_init(pmc);
2075 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2076 err = tegra_powergate_debugfs_init();
2081 err = register_restart_handler(&tegra_pmc_restart_handler);
2083 dev_err(&pdev->dev, "unable to register restart handler, %d\n",
2085 goto cleanup_debugfs;
2088 err = tegra_pmc_pinctrl_init(pmc);
2090 goto cleanup_restart_handler;
2092 err = tegra_powergate_init(pmc, pdev->dev.of_node);
2094 goto cleanup_powergates;
2096 err = tegra_pmc_irq_init(pmc);
2098 goto cleanup_powergates;
2100 mutex_lock(&pmc->powergates_lock);
2103 mutex_unlock(&pmc->powergates_lock);
2105 platform_set_drvdata(pdev, pmc);
2110 tegra_powergate_remove_all(pdev->dev.of_node);
2111 cleanup_restart_handler:
2112 unregister_restart_handler(&tegra_pmc_restart_handler);
2114 debugfs_remove(pmc->debugfs);
2116 device_remove_file(&pdev->dev, &dev_attr_reset_reason);
2117 device_remove_file(&pdev->dev, &dev_attr_reset_level);
2121 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
2122 static int tegra_pmc_suspend(struct device *dev)
2124 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2126 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);
2131 static int tegra_pmc_resume(struct device *dev)
2133 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2135 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);
2140 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
2144 static const char * const tegra20_powergates[] = {
2145 [TEGRA_POWERGATE_CPU] = "cpu",
2146 [TEGRA_POWERGATE_3D] = "3d",
2147 [TEGRA_POWERGATE_VENC] = "venc",
2148 [TEGRA_POWERGATE_VDEC] = "vdec",
2149 [TEGRA_POWERGATE_PCIE] = "pcie",
2150 [TEGRA_POWERGATE_L2] = "l2",
2151 [TEGRA_POWERGATE_MPE] = "mpe",
2154 static const struct tegra_pmc_regs tegra20_pmc_regs = {
2157 .dpd_status = 0x1bc,
2159 .dpd2_status = 0x1c4,
2160 .rst_status = 0x1b4,
2161 .rst_source_shift = 0x0,
2162 .rst_source_mask = 0x7,
2163 .rst_level_shift = 0x0,
2164 .rst_level_mask = 0x0,
2167 static void tegra20_pmc_init(struct tegra_pmc *pmc)
2171 /* Always enable CPU power request */
2172 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2173 value |= PMC_CNTRL_CPU_PWRREQ_OE;
2174 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2176 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2178 if (pmc->sysclkreq_high)
2179 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
2181 value |= PMC_CNTRL_SYSCLK_POLARITY;
2183 /* configure the output polarity while the request is tristated */
2184 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2186 /* now enable the request */
2187 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2188 value |= PMC_CNTRL_SYSCLK_OE;
2189 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2192 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
2193 struct device_node *np,
2198 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2201 value |= PMC_CNTRL_INTR_POLARITY;
2203 value &= ~PMC_CNTRL_INTR_POLARITY;
2205 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2208 static const struct tegra_pmc_soc tegra20_pmc_soc = {
2209 .num_powergates = ARRAY_SIZE(tegra20_powergates),
2210 .powergates = tegra20_powergates,
2211 .num_cpu_powergates = 0,
2212 .cpu_powergates = NULL,
2213 .has_tsense_reset = false,
2214 .has_gpu_clamps = false,
2215 .needs_mbist_war = false,
2216 .has_impl_33v_pwr = false,
2217 .maybe_tz_only = false,
2222 .regs = &tegra20_pmc_regs,
2223 .init = tegra20_pmc_init,
2224 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2225 .reset_sources = NULL,
2226 .num_reset_sources = 0,
2227 .reset_levels = NULL,
2228 .num_reset_levels = 0,
2231 static const char * const tegra30_powergates[] = {
2232 [TEGRA_POWERGATE_CPU] = "cpu0",
2233 [TEGRA_POWERGATE_3D] = "3d0",
2234 [TEGRA_POWERGATE_VENC] = "venc",
2235 [TEGRA_POWERGATE_VDEC] = "vdec",
2236 [TEGRA_POWERGATE_PCIE] = "pcie",
2237 [TEGRA_POWERGATE_L2] = "l2",
2238 [TEGRA_POWERGATE_MPE] = "mpe",
2239 [TEGRA_POWERGATE_HEG] = "heg",
2240 [TEGRA_POWERGATE_SATA] = "sata",
2241 [TEGRA_POWERGATE_CPU1] = "cpu1",
2242 [TEGRA_POWERGATE_CPU2] = "cpu2",
2243 [TEGRA_POWERGATE_CPU3] = "cpu3",
2244 [TEGRA_POWERGATE_CELP] = "celp",
2245 [TEGRA_POWERGATE_3D1] = "3d1",
2248 static const u8 tegra30_cpu_powergates[] = {
2249 TEGRA_POWERGATE_CPU,
2250 TEGRA_POWERGATE_CPU1,
2251 TEGRA_POWERGATE_CPU2,
2252 TEGRA_POWERGATE_CPU3,
2255 static const struct tegra_pmc_soc tegra30_pmc_soc = {
2256 .num_powergates = ARRAY_SIZE(tegra30_powergates),
2257 .powergates = tegra30_powergates,
2258 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
2259 .cpu_powergates = tegra30_cpu_powergates,
2260 .has_tsense_reset = true,
2261 .has_gpu_clamps = false,
2262 .needs_mbist_war = false,
2263 .has_impl_33v_pwr = false,
2264 .maybe_tz_only = false,
2269 .regs = &tegra20_pmc_regs,
2270 .init = tegra20_pmc_init,
2271 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2272 .reset_sources = tegra30_reset_sources,
2273 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2274 .reset_levels = NULL,
2275 .num_reset_levels = 0,
2278 static const char * const tegra114_powergates[] = {
2279 [TEGRA_POWERGATE_CPU] = "crail",
2280 [TEGRA_POWERGATE_3D] = "3d",
2281 [TEGRA_POWERGATE_VENC] = "venc",
2282 [TEGRA_POWERGATE_VDEC] = "vdec",
2283 [TEGRA_POWERGATE_MPE] = "mpe",
2284 [TEGRA_POWERGATE_HEG] = "heg",
2285 [TEGRA_POWERGATE_CPU1] = "cpu1",
2286 [TEGRA_POWERGATE_CPU2] = "cpu2",
2287 [TEGRA_POWERGATE_CPU3] = "cpu3",
2288 [TEGRA_POWERGATE_CELP] = "celp",
2289 [TEGRA_POWERGATE_CPU0] = "cpu0",
2290 [TEGRA_POWERGATE_C0NC] = "c0nc",
2291 [TEGRA_POWERGATE_C1NC] = "c1nc",
2292 [TEGRA_POWERGATE_DIS] = "dis",
2293 [TEGRA_POWERGATE_DISB] = "disb",
2294 [TEGRA_POWERGATE_XUSBA] = "xusba",
2295 [TEGRA_POWERGATE_XUSBB] = "xusbb",
2296 [TEGRA_POWERGATE_XUSBC] = "xusbc",
2299 static const u8 tegra114_cpu_powergates[] = {
2300 TEGRA_POWERGATE_CPU0,
2301 TEGRA_POWERGATE_CPU1,
2302 TEGRA_POWERGATE_CPU2,
2303 TEGRA_POWERGATE_CPU3,
2306 static const struct tegra_pmc_soc tegra114_pmc_soc = {
2307 .num_powergates = ARRAY_SIZE(tegra114_powergates),
2308 .powergates = tegra114_powergates,
2309 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
2310 .cpu_powergates = tegra114_cpu_powergates,
2311 .has_tsense_reset = true,
2312 .has_gpu_clamps = false,
2313 .needs_mbist_war = false,
2314 .has_impl_33v_pwr = false,
2315 .maybe_tz_only = false,
2320 .regs = &tegra20_pmc_regs,
2321 .init = tegra20_pmc_init,
2322 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2323 .reset_sources = tegra30_reset_sources,
2324 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2325 .reset_levels = NULL,
2326 .num_reset_levels = 0,
2329 static const char * const tegra124_powergates[] = {
2330 [TEGRA_POWERGATE_CPU] = "crail",
2331 [TEGRA_POWERGATE_3D] = "3d",
2332 [TEGRA_POWERGATE_VENC] = "venc",
2333 [TEGRA_POWERGATE_PCIE] = "pcie",
2334 [TEGRA_POWERGATE_VDEC] = "vdec",
2335 [TEGRA_POWERGATE_MPE] = "mpe",
2336 [TEGRA_POWERGATE_HEG] = "heg",
2337 [TEGRA_POWERGATE_SATA] = "sata",
2338 [TEGRA_POWERGATE_CPU1] = "cpu1",
2339 [TEGRA_POWERGATE_CPU2] = "cpu2",
2340 [TEGRA_POWERGATE_CPU3] = "cpu3",
2341 [TEGRA_POWERGATE_CELP] = "celp",
2342 [TEGRA_POWERGATE_CPU0] = "cpu0",
2343 [TEGRA_POWERGATE_C0NC] = "c0nc",
2344 [TEGRA_POWERGATE_C1NC] = "c1nc",
2345 [TEGRA_POWERGATE_SOR] = "sor",
2346 [TEGRA_POWERGATE_DIS] = "dis",
2347 [TEGRA_POWERGATE_DISB] = "disb",
2348 [TEGRA_POWERGATE_XUSBA] = "xusba",
2349 [TEGRA_POWERGATE_XUSBB] = "xusbb",
2350 [TEGRA_POWERGATE_XUSBC] = "xusbc",
2351 [TEGRA_POWERGATE_VIC] = "vic",
2352 [TEGRA_POWERGATE_IRAM] = "iram",
2355 static const u8 tegra124_cpu_powergates[] = {
2356 TEGRA_POWERGATE_CPU0,
2357 TEGRA_POWERGATE_CPU1,
2358 TEGRA_POWERGATE_CPU2,
2359 TEGRA_POWERGATE_CPU3,
2362 #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \
2363 ((struct tegra_io_pad_soc) { \
2366 .voltage = (_voltage), \
2370 #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \
2371 ((struct pinctrl_pin_desc) { \
2376 #define TEGRA124_IO_PAD_TABLE(_pad) \
2377 /* .id .dpd .voltage .name */ \
2378 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
2379 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \
2380 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \
2381 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \
2382 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
2383 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \
2384 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \
2385 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
2386 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
2387 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
2388 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
2389 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
2390 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
2391 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \
2392 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
2393 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
2394 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \
2395 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
2396 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
2397 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
2398 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
2399 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \
2400 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \
2401 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \
2402 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \
2403 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
2404 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
2405 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
2406 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
2407 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias")
2409 static const struct tegra_io_pad_soc tegra124_io_pads[] = {
2410 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD)
2413 static const struct pinctrl_pin_desc tegra124_pin_descs[] = {
2414 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
2417 static const struct tegra_pmc_soc tegra124_pmc_soc = {
2418 .num_powergates = ARRAY_SIZE(tegra124_powergates),
2419 .powergates = tegra124_powergates,
2420 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
2421 .cpu_powergates = tegra124_cpu_powergates,
2422 .has_tsense_reset = true,
2423 .has_gpu_clamps = true,
2424 .needs_mbist_war = false,
2425 .has_impl_33v_pwr = false,
2426 .maybe_tz_only = false,
2427 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
2428 .io_pads = tegra124_io_pads,
2429 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs),
2430 .pin_descs = tegra124_pin_descs,
2431 .regs = &tegra20_pmc_regs,
2432 .init = tegra20_pmc_init,
2433 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2434 .reset_sources = tegra30_reset_sources,
2435 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2436 .reset_levels = NULL,
2437 .num_reset_levels = 0,
2440 static const char * const tegra210_powergates[] = {
2441 [TEGRA_POWERGATE_CPU] = "crail",
2442 [TEGRA_POWERGATE_3D] = "3d",
2443 [TEGRA_POWERGATE_VENC] = "venc",
2444 [TEGRA_POWERGATE_PCIE] = "pcie",
2445 [TEGRA_POWERGATE_MPE] = "mpe",
2446 [TEGRA_POWERGATE_SATA] = "sata",
2447 [TEGRA_POWERGATE_CPU1] = "cpu1",
2448 [TEGRA_POWERGATE_CPU2] = "cpu2",
2449 [TEGRA_POWERGATE_CPU3] = "cpu3",
2450 [TEGRA_POWERGATE_CPU0] = "cpu0",
2451 [TEGRA_POWERGATE_C0NC] = "c0nc",
2452 [TEGRA_POWERGATE_SOR] = "sor",
2453 [TEGRA_POWERGATE_DIS] = "dis",
2454 [TEGRA_POWERGATE_DISB] = "disb",
2455 [TEGRA_POWERGATE_XUSBA] = "xusba",
2456 [TEGRA_POWERGATE_XUSBB] = "xusbb",
2457 [TEGRA_POWERGATE_XUSBC] = "xusbc",
2458 [TEGRA_POWERGATE_VIC] = "vic",
2459 [TEGRA_POWERGATE_IRAM] = "iram",
2460 [TEGRA_POWERGATE_NVDEC] = "nvdec",
2461 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
2462 [TEGRA_POWERGATE_AUD] = "aud",
2463 [TEGRA_POWERGATE_DFD] = "dfd",
2464 [TEGRA_POWERGATE_VE2] = "ve2",
2467 static const u8 tegra210_cpu_powergates[] = {
2468 TEGRA_POWERGATE_CPU0,
2469 TEGRA_POWERGATE_CPU1,
2470 TEGRA_POWERGATE_CPU2,
2471 TEGRA_POWERGATE_CPU3,
2474 #define TEGRA210_IO_PAD_TABLE(_pad) \
2475 /* .id .dpd .voltage .name */ \
2476 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \
2477 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \
2478 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \
2479 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
2480 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
2481 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \
2482 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \
2483 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \
2484 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \
2485 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \
2486 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \
2487 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \
2488 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \
2489 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
2490 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
2491 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
2492 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
2493 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \
2494 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \
2495 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \
2496 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
2497 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
2498 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
2499 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
2500 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
2501 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
2502 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
2503 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \
2504 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \
2505 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \
2506 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \
2507 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \
2508 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \
2509 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
2510 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
2511 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
2512 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \
2513 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias")
2515 static const struct tegra_io_pad_soc tegra210_io_pads[] = {
2516 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD)
2519 static const struct pinctrl_pin_desc tegra210_pin_descs[] = {
2520 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
2523 static const struct tegra_pmc_soc tegra210_pmc_soc = {
2524 .num_powergates = ARRAY_SIZE(tegra210_powergates),
2525 .powergates = tegra210_powergates,
2526 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
2527 .cpu_powergates = tegra210_cpu_powergates,
2528 .has_tsense_reset = true,
2529 .has_gpu_clamps = true,
2530 .needs_mbist_war = true,
2531 .has_impl_33v_pwr = false,
2532 .maybe_tz_only = true,
2533 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
2534 .io_pads = tegra210_io_pads,
2535 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
2536 .pin_descs = tegra210_pin_descs,
2537 .regs = &tegra20_pmc_regs,
2538 .init = tegra20_pmc_init,
2539 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2540 .reset_sources = tegra210_reset_sources,
2541 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
2542 .reset_levels = NULL,
2543 .num_reset_levels = 0,
2546 #define TEGRA186_IO_PAD_TABLE(_pad) \
2547 /* .id .dpd .voltage .name */ \
2548 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
2549 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
2550 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
2551 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
2552 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
2553 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
2554 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
2555 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
2556 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
2557 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
2558 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
2559 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \
2560 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
2561 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
2562 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
2563 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
2564 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
2565 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
2566 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
2567 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \
2568 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
2569 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
2570 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \
2571 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \
2572 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \
2573 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
2574 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
2575 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
2576 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
2577 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
2578 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
2579 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \
2580 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
2581 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
2582 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
2583 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
2584 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
2585 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
2587 static const struct tegra_io_pad_soc tegra186_io_pads[] = {
2588 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD)
2591 static const struct pinctrl_pin_desc tegra186_pin_descs[] = {
2592 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
2595 static const struct tegra_pmc_regs tegra186_pmc_regs = {
2600 .dpd2_status = 0x80,
2602 .rst_source_shift = 0x2,
2603 .rst_source_mask = 0x3C,
2604 .rst_level_shift = 0x0,
2605 .rst_level_mask = 0x3,
2608 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
2609 struct device_node *np,
2612 struct resource regs;
2617 index = of_property_match_string(np, "reg-names", "wake");
2619 dev_err(pmc->dev, "failed to find PMC wake registers\n");
2623 of_address_to_resource(np, index, ®s);
2625 wake = ioremap_nocache(regs.start, resource_size(®s));
2627 dev_err(pmc->dev, "failed to map PMC wake registers\n");
2631 value = readl(wake + WAKE_AOWAKE_CTRL);
2634 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
2636 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
2638 writel(value, wake + WAKE_AOWAKE_CTRL);
2643 static const struct tegra_wake_event tegra186_wake_events[] = {
2644 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
2645 TEGRA_WAKE_IRQ("rtc", 73, 10),
2648 static const struct tegra_pmc_soc tegra186_pmc_soc = {
2649 .num_powergates = 0,
2651 .num_cpu_powergates = 0,
2652 .cpu_powergates = NULL,
2653 .has_tsense_reset = false,
2654 .has_gpu_clamps = false,
2655 .needs_mbist_war = false,
2656 .has_impl_33v_pwr = true,
2657 .maybe_tz_only = false,
2658 .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
2659 .io_pads = tegra186_io_pads,
2660 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
2661 .pin_descs = tegra186_pin_descs,
2662 .regs = &tegra186_pmc_regs,
2664 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
2665 .reset_sources = tegra186_reset_sources,
2666 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),
2667 .reset_levels = tegra186_reset_levels,
2668 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
2669 .num_wake_events = ARRAY_SIZE(tegra186_wake_events),
2670 .wake_events = tegra186_wake_events,
2673 static const struct tegra_io_pad_soc tegra194_io_pads[] = {
2674 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
2675 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
2676 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
2677 { .id = TEGRA_IO_PAD_PEX_CLK_BIAS, .dpd = 4, .voltage = UINT_MAX },
2678 { .id = TEGRA_IO_PAD_PEX_CLK3, .dpd = 5, .voltage = UINT_MAX },
2679 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
2680 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 7, .voltage = UINT_MAX },
2681 { .id = TEGRA_IO_PAD_EQOS, .dpd = 8, .voltage = UINT_MAX },
2682 { .id = TEGRA_IO_PAD_PEX_CLK2_BIAS, .dpd = 9, .voltage = UINT_MAX },
2683 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 10, .voltage = UINT_MAX },
2684 { .id = TEGRA_IO_PAD_DAP3, .dpd = 11, .voltage = UINT_MAX },
2685 { .id = TEGRA_IO_PAD_DAP5, .dpd = 12, .voltage = UINT_MAX },
2686 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX },
2687 { .id = TEGRA_IO_PAD_PWR_CTL, .dpd = 15, .voltage = UINT_MAX },
2688 { .id = TEGRA_IO_PAD_SOC_GPIO53, .dpd = 16, .voltage = UINT_MAX },
2689 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX },
2690 { .id = TEGRA_IO_PAD_GP_PWM2, .dpd = 18, .voltage = UINT_MAX },
2691 { .id = TEGRA_IO_PAD_GP_PWM3, .dpd = 19, .voltage = UINT_MAX },
2692 { .id = TEGRA_IO_PAD_SOC_GPIO12, .dpd = 20, .voltage = UINT_MAX },
2693 { .id = TEGRA_IO_PAD_SOC_GPIO13, .dpd = 21, .voltage = UINT_MAX },
2694 { .id = TEGRA_IO_PAD_SOC_GPIO10, .dpd = 22, .voltage = UINT_MAX },
2695 { .id = TEGRA_IO_PAD_UART4, .dpd = 23, .voltage = UINT_MAX },
2696 { .id = TEGRA_IO_PAD_UART5, .dpd = 24, .voltage = UINT_MAX },
2697 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = UINT_MAX },
2698 { .id = TEGRA_IO_PAD_HDMI_DP3, .dpd = 26, .voltage = UINT_MAX },
2699 { .id = TEGRA_IO_PAD_HDMI_DP2, .dpd = 27, .voltage = UINT_MAX },
2700 { .id = TEGRA_IO_PAD_HDMI_DP0, .dpd = 28, .voltage = UINT_MAX },
2701 { .id = TEGRA_IO_PAD_HDMI_DP1, .dpd = 29, .voltage = UINT_MAX },
2702 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX },
2703 { .id = TEGRA_IO_PAD_PEX_CTL2, .dpd = 33, .voltage = UINT_MAX },
2704 { .id = TEGRA_IO_PAD_PEX_L0_RST_N, .dpd = 34, .voltage = UINT_MAX },
2705 { .id = TEGRA_IO_PAD_PEX_L1_RST_N, .dpd = 35, .voltage = UINT_MAX },
2706 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 36, .voltage = UINT_MAX },
2707 { .id = TEGRA_IO_PAD_PEX_L5_RST_N, .dpd = 37, .voltage = UINT_MAX },
2708 { .id = TEGRA_IO_PAD_CSIC, .dpd = 43, .voltage = UINT_MAX },
2709 { .id = TEGRA_IO_PAD_CSID, .dpd = 44, .voltage = UINT_MAX },
2710 { .id = TEGRA_IO_PAD_CSIE, .dpd = 45, .voltage = UINT_MAX },
2711 { .id = TEGRA_IO_PAD_CSIF, .dpd = 46, .voltage = UINT_MAX },
2712 { .id = TEGRA_IO_PAD_SPI, .dpd = 47, .voltage = UINT_MAX },
2713 { .id = TEGRA_IO_PAD_UFS, .dpd = 49, .voltage = UINT_MAX },
2714 { .id = TEGRA_IO_PAD_CSIG, .dpd = 50, .voltage = UINT_MAX },
2715 { .id = TEGRA_IO_PAD_CSIH, .dpd = 51, .voltage = UINT_MAX },
2716 { .id = TEGRA_IO_PAD_EDP, .dpd = 53, .voltage = UINT_MAX },
2717 { .id = TEGRA_IO_PAD_SDMMC1_HV, .dpd = 55, .voltage = UINT_MAX },
2718 { .id = TEGRA_IO_PAD_SDMMC3_HV, .dpd = 56, .voltage = UINT_MAX },
2719 { .id = TEGRA_IO_PAD_CONN, .dpd = 60, .voltage = UINT_MAX },
2720 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = UINT_MAX },
2723 static const struct tegra_wake_event tegra194_wake_events[] = {
2724 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)),
2725 TEGRA_WAKE_IRQ("rtc", 73, 10),
2728 static const struct tegra_pmc_soc tegra194_pmc_soc = {
2729 .num_powergates = 0,
2731 .num_cpu_powergates = 0,
2732 .cpu_powergates = NULL,
2733 .has_tsense_reset = false,
2734 .has_gpu_clamps = false,
2735 .needs_mbist_war = false,
2736 .has_impl_33v_pwr = false,
2737 .maybe_tz_only = false,
2738 .num_io_pads = ARRAY_SIZE(tegra194_io_pads),
2739 .io_pads = tegra194_io_pads,
2740 .regs = &tegra186_pmc_regs,
2742 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
2743 .num_wake_events = ARRAY_SIZE(tegra194_wake_events),
2744 .wake_events = tegra194_wake_events,
2747 static const struct of_device_id tegra_pmc_match[] = {
2748 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
2749 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
2750 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
2751 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
2752 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
2753 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
2754 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
2755 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
2759 static struct platform_driver tegra_pmc_driver = {
2761 .name = "tegra-pmc",
2762 .suppress_bind_attrs = true,
2763 .of_match_table = tegra_pmc_match,
2764 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
2765 .pm = &tegra_pmc_pm_ops,
2768 .probe = tegra_pmc_probe,
2770 builtin_platform_driver(tegra_pmc_driver);
2772 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)
2776 saved = readl(pmc->base + pmc->soc->regs->scratch0);
2777 value = saved ^ 0xffffffff;
2779 if (value == 0xffffffff)
2782 /* write pattern and read it back */
2783 writel(value, pmc->base + pmc->soc->regs->scratch0);
2784 value = readl(pmc->base + pmc->soc->regs->scratch0);
2786 /* if we read all-zeroes, access is restricted to TZ only */
2788 pr_info("access to PMC is restricted to TZ\n");
2792 /* restore original value */
2793 writel(saved, pmc->base + pmc->soc->regs->scratch0);
2799 * Early initialization to allow access to registers in the very early boot
2802 static int __init tegra_pmc_early_init(void)
2804 const struct of_device_id *match;
2805 struct device_node *np;
2806 struct resource regs;
2810 mutex_init(&pmc->powergates_lock);
2812 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
2815 * Fall back to legacy initialization for 32-bit ARM only. All
2816 * 64-bit ARM device tree files for Tegra are required to have
2819 * This is for backwards-compatibility with old device trees
2820 * that didn't contain a PMC node. Note that in this case the
2821 * SoC data can't be matched and therefore powergating is
2824 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
2825 pr_warn("DT node not found, powergating disabled\n");
2827 regs.start = 0x7000e400;
2828 regs.end = 0x7000e7ff;
2829 regs.flags = IORESOURCE_MEM;
2831 pr_warn("Using memory region %pR\n", ®s);
2834 * At this point we're not running on Tegra, so play
2835 * nice with multi-platform kernels.
2841 * Extract information from the device tree if we've found a
2844 if (of_address_to_resource(np, 0, ®s) < 0) {
2845 pr_err("failed to get PMC registers\n");
2851 pmc->base = ioremap_nocache(regs.start, resource_size(®s));
2853 pr_err("failed to map PMC registers\n");
2859 pmc->soc = match->data;
2861 if (pmc->soc->maybe_tz_only)
2862 pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
2864 /* Create a bitmap of the available and valid partitions */
2865 for (i = 0; i < pmc->soc->num_powergates; i++)
2866 if (pmc->soc->powergates[i])
2867 set_bit(i, pmc->powergates_available);
2870 * Invert the interrupt polarity if a PMC device tree node
2871 * exists and contains the nvidia,invert-interrupt property.
2873 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
2875 pmc->soc->setup_irq_polarity(pmc, np, invert);
2882 early_initcall(tegra_pmc_early_init);