1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/soc/tegra/pmc.c
5 * Copyright (c) 2010 Google, Inc
6 * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
9 * Colin Cross <ccross@google.com>
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/clkdev.h>
18 #include <linux/clk/clk-conf.h>
19 #include <linux/clk/tegra.h>
20 #include <linux/debugfs.h>
21 #include <linux/delay.h>
22 #include <linux/device.h>
23 #include <linux/err.h>
24 #include <linux/export.h>
25 #include <linux/init.h>
27 #include <linux/iopoll.h>
28 #include <linux/irqdomain.h>
29 #include <linux/irq.h>
30 #include <linux/kernel.h>
31 #include <linux/of_address.h>
32 #include <linux/of_clk.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_platform.h>
36 #include <linux/pinctrl/pinconf-generic.h>
37 #include <linux/pinctrl/pinconf.h>
38 #include <linux/pinctrl/pinctrl.h>
39 #include <linux/platform_device.h>
40 #include <linux/pm_domain.h>
41 #include <linux/pm_opp.h>
42 #include <linux/reboot.h>
43 #include <linux/regmap.h>
44 #include <linux/reset.h>
45 #include <linux/seq_file.h>
46 #include <linux/slab.h>
47 #include <linux/spinlock.h>
49 #include <soc/tegra/common.h>
50 #include <soc/tegra/fuse.h>
51 #include <soc/tegra/pmc.h>
53 #include <dt-bindings/interrupt-controller/arm-gic.h>
54 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
55 #include <dt-bindings/gpio/tegra186-gpio.h>
56 #include <dt-bindings/gpio/tegra194-gpio.h>
57 #include <dt-bindings/soc/tegra-pmc.h>
60 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
61 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
62 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
63 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
64 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
65 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
66 #define PMC_CNTRL_PWRREQ_POLARITY BIT(8)
67 #define PMC_CNTRL_BLINK_EN 7
68 #define PMC_CNTRL_MAIN_RST BIT(4)
70 #define PMC_WAKE_MASK 0x0c
71 #define PMC_WAKE_LEVEL 0x10
72 #define PMC_WAKE_STATUS 0x14
73 #define PMC_SW_WAKE_STATUS 0x18
74 #define PMC_DPD_PADS_ORIDE 0x1c
75 #define PMC_DPD_PADS_ORIDE_BLINK 20
77 #define DPD_SAMPLE 0x020
78 #define DPD_SAMPLE_ENABLE BIT(0)
79 #define DPD_SAMPLE_DISABLE (0 << 0)
81 #define PWRGATE_TOGGLE 0x30
82 #define PWRGATE_TOGGLE_START BIT(8)
84 #define REMOVE_CLAMPING 0x34
86 #define PWRGATE_STATUS 0x38
88 #define PMC_BLINK_TIMER 0x40
89 #define PMC_IMPL_E_33V_PWR 0x40
91 #define PMC_PWR_DET 0x48
93 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
94 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
95 #define PMC_SCRATCH0_MODE_RCM BIT(1)
96 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
97 PMC_SCRATCH0_MODE_BOOTLOADER | \
98 PMC_SCRATCH0_MODE_RCM)
100 #define PMC_CPUPWRGOOD_TIMER 0xc8
101 #define PMC_CPUPWROFF_TIMER 0xcc
102 #define PMC_COREPWRGOOD_TIMER 0x3c
103 #define PMC_COREPWROFF_TIMER 0xe0
105 #define PMC_PWR_DET_VALUE 0xe4
107 #define PMC_USB_DEBOUNCE_DEL 0xec
108 #define PMC_USB_AO 0xf0
110 #define PMC_SCRATCH41 0x140
112 #define PMC_WAKE2_MASK 0x160
113 #define PMC_WAKE2_LEVEL 0x164
114 #define PMC_WAKE2_STATUS 0x168
115 #define PMC_SW_WAKE2_STATUS 0x16c
117 #define PMC_CLK_OUT_CNTRL 0x1a8
118 #define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0)
119 #define PMC_SENSOR_CTRL 0x1b0
120 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
121 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
123 #define PMC_RST_STATUS_POR 0
124 #define PMC_RST_STATUS_WATCHDOG 1
125 #define PMC_RST_STATUS_SENSOR 2
126 #define PMC_RST_STATUS_SW_MAIN 3
127 #define PMC_RST_STATUS_LP0 4
128 #define PMC_RST_STATUS_AOTAG 5
130 #define IO_DPD_REQ 0x1b8
131 #define IO_DPD_REQ_CODE_IDLE (0U << 30)
132 #define IO_DPD_REQ_CODE_OFF (1U << 30)
133 #define IO_DPD_REQ_CODE_ON (2U << 30)
134 #define IO_DPD_REQ_CODE_MASK (3U << 30)
136 #define IO_DPD_STATUS 0x1bc
137 #define IO_DPD2_REQ 0x1c0
138 #define IO_DPD2_STATUS 0x1c4
139 #define SEL_DPD_TIM 0x1c8
141 #define PMC_UTMIP_UHSIC_TRIGGERS 0x1ec
142 #define PMC_UTMIP_UHSIC_SAVED_STATE 0x1f0
144 #define PMC_UTMIP_TERM_PAD_CFG 0x1f8
145 #define PMC_UTMIP_UHSIC_SLEEP_CFG 0x1fc
146 #define PMC_UTMIP_UHSIC_FAKE 0x218
148 #define PMC_SCRATCH54 0x258
149 #define PMC_SCRATCH54_DATA_SHIFT 8
150 #define PMC_SCRATCH54_ADDR_SHIFT 0
152 #define PMC_SCRATCH55 0x25c
153 #define PMC_SCRATCH55_RESET_TEGRA BIT(31)
154 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
155 #define PMC_SCRATCH55_PINMUX_SHIFT 24
156 #define PMC_SCRATCH55_16BITOP BIT(15)
157 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
158 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
160 #define PMC_UTMIP_UHSIC_LINE_WAKEUP 0x26c
162 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270
163 #define PMC_UTMIP_MASTER_CONFIG 0x274
164 #define PMC_UTMIP_UHSIC2_TRIGGERS 0x27c
165 #define PMC_UTMIP_MASTER2_CONFIG 0x29c
167 #define GPU_RG_CNTRL 0x2d4
169 #define PMC_UTMIP_PAD_CFG0 0x4c0
170 #define PMC_UTMIP_UHSIC_SLEEP_CFG1 0x4d0
171 #define PMC_UTMIP_SLEEPWALK_P3 0x4e0
172 /* Tegra186 and later */
173 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
174 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)
175 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))
176 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))
177 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))
178 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))
179 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
180 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
181 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
183 #define WAKE_AOWAKE_CTRL 0x4f4
184 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
187 #define TEGRA_SMC_PMC 0xc2fffe00
188 #define TEGRA_SMC_PMC_READ 0xaa
189 #define TEGRA_SMC_PMC_WRITE 0xbb
198 #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
200 struct pmc_clk_gate {
206 #define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
208 struct pmc_clk_init_data {
210 const char *const *parents;
217 static const char * const clk_out1_parents[] = { "osc", "osc_div2",
218 "osc_div4", "extern1",
221 static const char * const clk_out2_parents[] = { "osc", "osc_div2",
222 "osc_div4", "extern2",
225 static const char * const clk_out3_parents[] = { "osc", "osc_div2",
226 "osc_div4", "extern3",
229 static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
231 .name = "pmc_clk_out_1",
232 .parents = clk_out1_parents,
233 .num_parents = ARRAY_SIZE(clk_out1_parents),
234 .clk_id = TEGRA_PMC_CLK_OUT_1,
239 .name = "pmc_clk_out_2",
240 .parents = clk_out2_parents,
241 .num_parents = ARRAY_SIZE(clk_out2_parents),
242 .clk_id = TEGRA_PMC_CLK_OUT_2,
244 .force_en_shift = 10,
247 .name = "pmc_clk_out_3",
248 .parents = clk_out3_parents,
249 .num_parents = ARRAY_SIZE(clk_out3_parents),
250 .clk_id = TEGRA_PMC_CLK_OUT_3,
252 .force_en_shift = 18,
256 struct tegra_powergate {
257 struct generic_pm_domain genpd;
258 struct tegra_pmc *pmc;
261 unsigned int num_clks;
262 unsigned long *clk_rates;
263 struct reset_control *reset;
266 struct tegra_io_pad_soc {
267 enum tegra_io_pad id;
269 unsigned int voltage;
273 struct tegra_pmc_regs {
274 unsigned int scratch0;
275 unsigned int dpd_req;
276 unsigned int dpd_status;
277 unsigned int dpd2_req;
278 unsigned int dpd2_status;
279 unsigned int rst_status;
280 unsigned int rst_source_shift;
281 unsigned int rst_source_mask;
282 unsigned int rst_level_shift;
283 unsigned int rst_level_mask;
286 struct tegra_wake_event {
291 unsigned int instance;
296 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \
302 .instance = UINT_MAX, \
307 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \
313 .instance = _instance, \
318 struct tegra_pmc_soc {
319 unsigned int num_powergates;
320 const char *const *powergates;
321 unsigned int num_cpu_powergates;
322 const u8 *cpu_powergates;
324 bool has_tsense_reset;
326 bool needs_mbist_war;
327 bool has_impl_33v_pwr;
330 const struct tegra_io_pad_soc *io_pads;
331 unsigned int num_io_pads;
333 const struct pinctrl_pin_desc *pin_descs;
334 unsigned int num_pin_descs;
336 const struct tegra_pmc_regs *regs;
337 void (*init)(struct tegra_pmc *pmc);
338 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
339 struct device_node *np,
341 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
342 int (*irq_set_type)(struct irq_data *data, unsigned int type);
343 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id,
346 const char * const *reset_sources;
347 unsigned int num_reset_sources;
348 const char * const *reset_levels;
349 unsigned int num_reset_levels;
352 * These describe events that can wake the system from sleep (i.e.
353 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2)
354 * are dealt with in the LIC.
356 const struct tegra_wake_event *wake_events;
357 unsigned int num_wake_events;
359 const struct pmc_clk_init_data *pmc_clks_data;
360 unsigned int num_pmc_clks;
361 bool has_blink_output;
362 bool has_usb_sleepwalk;
366 * struct tegra_pmc - NVIDIA Tegra PMC
367 * @dev: pointer to PMC device structure
368 * @base: pointer to I/O remapped register region
369 * @wake: pointer to I/O remapped region for WAKE registers
370 * @aotag: pointer to I/O remapped region for AOTAG registers
371 * @scratch: pointer to I/O remapped region for scratch registers
372 * @clk: pointer to pclk clock
373 * @soc: pointer to SoC data structure
374 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone
375 * @debugfs: pointer to debugfs entry
376 * @rate: currently configured rate of pclk
377 * @suspend_mode: lowest suspend mode available
378 * @cpu_good_time: CPU power good time (in microseconds)
379 * @cpu_off_time: CPU power off time (in microsecends)
380 * @core_osc_time: core power good OSC time (in microseconds)
381 * @core_pmu_time: core power good PMU time (in microseconds)
382 * @core_off_time: core power off time (in microseconds)
383 * @corereq_high: core power request is active-high
384 * @sysclkreq_high: system clock request is active-high
385 * @combined_req: combined power request for CPU & core
386 * @cpu_pwr_good_en: CPU power good signal is enabled
387 * @lp0_vec_phys: physical base address of the LP0 warm boot code
388 * @lp0_vec_size: size of the LP0 warm boot code
389 * @powergates_available: Bitmap of available power gates
390 * @powergates_lock: mutex for power gate register access
391 * @pctl_dev: pin controller exposed by the PMC
392 * @domain: IRQ domain provided by the PMC
393 * @irq: chip implementation for the IRQ domain
394 * @clk_nb: pclk clock changes handler
401 void __iomem *scratch;
403 struct dentry *debugfs;
405 const struct tegra_pmc_soc *soc;
410 enum tegra_suspend_mode suspend_mode;
419 bool cpu_pwr_good_en;
422 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
424 struct mutex powergates_lock;
426 struct pinctrl_dev *pctl_dev;
428 struct irq_domain *domain;
431 struct notifier_block clk_nb;
433 bool core_domain_state_synced;
434 bool core_domain_registered;
437 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
439 .suspend_mode = TEGRA_SUSPEND_NOT_READY,
442 static inline struct tegra_powergate *
443 to_powergate(struct generic_pm_domain *domain)
445 return container_of(domain, struct tegra_powergate, genpd);
448 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
450 struct arm_smccc_res res;
453 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
457 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
460 pr_warn("%s(): SMC failed: %lu\n", __func__,
467 return readl(pmc->base + offset);
470 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
471 unsigned long offset)
473 struct arm_smccc_res res;
476 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
477 value, 0, 0, 0, 0, &res);
480 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
483 pr_warn("%s(): SMC failed: %lu\n", __func__,
487 writel(value, pmc->base + offset);
491 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)
494 return tegra_pmc_readl(pmc, offset);
496 return readl(pmc->scratch + offset);
499 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
500 unsigned long offset)
503 tegra_pmc_writel(pmc, value, offset);
505 writel(value, pmc->scratch + offset);
509 * TODO Figure out a way to call this with the struct tegra_pmc * passed in.
510 * This currently doesn't work because readx_poll_timeout() can only operate
511 * on functions that take a single argument.
513 static inline bool tegra_powergate_state(int id)
515 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
516 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;
518 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;
521 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id)
523 return (pmc->soc && pmc->soc->powergates[id]);
526 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id)
528 return test_bit(id, pmc->powergates_available);
531 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
535 if (!pmc || !pmc->soc || !name)
538 for (i = 0; i < pmc->soc->num_powergates; i++) {
539 if (!tegra_powergate_is_valid(pmc, i))
542 if (!strcmp(name, pmc->soc->powergates[i]))
549 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id,
552 unsigned int retries = 100;
557 * As per TRM documentation, the toggle command will be dropped by PMC
558 * if there is contention with a HW-initiated toggling (i.e. CPU core
559 * power-gated), the command should be retried in that case.
562 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
564 /* wait for PMC to execute the command */
565 ret = readx_poll_timeout(tegra_powergate_state, id, status,
566 status == new_state, 1, 10);
567 } while (ret == -ETIMEDOUT && retries--);
572 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc)
574 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START);
577 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id,
583 /* wait while PMC power gating is contended */
584 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
585 status == true, 1, 100);
589 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
591 /* wait for PMC to accept the command */
592 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
593 status == true, 1, 100);
597 /* wait for PMC to execute the command */
598 err = readx_poll_timeout(tegra_powergate_state, id, status,
599 status == new_state, 10, 100000);
607 * tegra_powergate_set() - set the state of a partition
608 * @pmc: power management controller
610 * @new_state: new state of the partition
612 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id,
617 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
620 mutex_lock(&pmc->powergates_lock);
622 if (tegra_powergate_state(id) == new_state) {
623 mutex_unlock(&pmc->powergates_lock);
627 err = pmc->soc->powergate_set(pmc, id, new_state);
629 mutex_unlock(&pmc->powergates_lock);
634 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
639 mutex_lock(&pmc->powergates_lock);
642 * On Tegra124 and later, the clamps for the GPU are controlled by a
643 * separate register (with different semantics).
645 if (id == TEGRA_POWERGATE_3D) {
646 if (pmc->soc->has_gpu_clamps) {
647 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);
653 * Tegra 2 has a bug where PCIE and VDE clamping masks are
654 * swapped relatively to the partition ids
656 if (id == TEGRA_POWERGATE_VDEC)
657 mask = (1 << TEGRA_POWERGATE_PCIE);
658 else if (id == TEGRA_POWERGATE_PCIE)
659 mask = (1 << TEGRA_POWERGATE_VDEC);
663 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);
666 mutex_unlock(&pmc->powergates_lock);
671 static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg)
673 unsigned long safe_rate = 100 * 1000 * 1000;
677 for (i = 0; i < pg->num_clks; i++) {
678 pg->clk_rates[i] = clk_get_rate(pg->clks[i]);
680 if (!pg->clk_rates[i]) {
685 if (pg->clk_rates[i] <= safe_rate)
689 * We don't know whether voltage state is okay for the
690 * current clock rate, hence it's better to temporally
691 * switch clock to a safe rate which is suitable for
692 * all voltages, before enabling the clock.
694 err = clk_set_rate(pg->clks[i], safe_rate);
703 clk_set_rate(pg->clks[i], pg->clk_rates[i]);
708 static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg)
713 for (i = 0; i < pg->num_clks; i++) {
714 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]);
722 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
726 for (i = 0; i < pg->num_clks; i++)
727 clk_disable_unprepare(pg->clks[i]);
730 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
735 for (i = 0; i < pg->num_clks; i++) {
736 err = clk_prepare_enable(pg->clks[i]);
745 clk_disable_unprepare(pg->clks[i]);
750 static int tegra_powergate_power_up(struct tegra_powergate *pg,
755 err = reset_control_assert(pg->reset);
759 usleep_range(10, 20);
761 err = tegra_powergate_set(pg->pmc, pg->id, true);
765 usleep_range(10, 20);
767 err = tegra_powergate_prepare_clocks(pg);
771 err = tegra_powergate_enable_clocks(pg);
775 usleep_range(10, 20);
777 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
781 usleep_range(10, 20);
783 err = reset_control_deassert(pg->reset);
787 usleep_range(10, 20);
789 if (pg->pmc->soc->needs_mbist_war)
790 err = tegra210_clk_handle_mbist_war(pg->id);
795 tegra_powergate_disable_clocks(pg);
797 err = tegra_powergate_unprepare_clocks(pg);
804 tegra_powergate_disable_clocks(pg);
805 usleep_range(10, 20);
808 tegra_powergate_unprepare_clocks(pg);
811 tegra_powergate_set(pg->pmc, pg->id, false);
816 static int tegra_powergate_power_down(struct tegra_powergate *pg)
820 err = tegra_powergate_prepare_clocks(pg);
824 err = tegra_powergate_enable_clocks(pg);
828 usleep_range(10, 20);
830 err = reset_control_assert(pg->reset);
834 usleep_range(10, 20);
836 tegra_powergate_disable_clocks(pg);
838 usleep_range(10, 20);
840 err = tegra_powergate_set(pg->pmc, pg->id, false);
844 err = tegra_powergate_unprepare_clocks(pg);
851 tegra_powergate_enable_clocks(pg);
852 usleep_range(10, 20);
853 reset_control_deassert(pg->reset);
854 usleep_range(10, 20);
857 tegra_powergate_disable_clocks(pg);
860 tegra_powergate_unprepare_clocks(pg);
865 static int tegra_genpd_power_on(struct generic_pm_domain *domain)
867 struct tegra_powergate *pg = to_powergate(domain);
868 struct device *dev = pg->pmc->dev;
871 err = tegra_powergate_power_up(pg, true);
873 dev_err(dev, "failed to turn on PM domain %s: %d\n",
874 pg->genpd.name, err);
878 reset_control_release(pg->reset);
884 static int tegra_genpd_power_off(struct generic_pm_domain *domain)
886 struct tegra_powergate *pg = to_powergate(domain);
887 struct device *dev = pg->pmc->dev;
890 err = reset_control_acquire(pg->reset);
892 dev_err(dev, "failed to acquire resets for PM domain %s: %d\n",
893 pg->genpd.name, err);
897 err = tegra_powergate_power_down(pg);
899 dev_err(dev, "failed to turn off PM domain %s: %d\n",
900 pg->genpd.name, err);
901 reset_control_release(pg->reset);
908 * tegra_powergate_power_on() - power on partition
911 int tegra_powergate_power_on(unsigned int id)
913 if (!tegra_powergate_is_available(pmc, id))
916 return tegra_powergate_set(pmc, id, true);
918 EXPORT_SYMBOL(tegra_powergate_power_on);
921 * tegra_powergate_power_off() - power off partition
924 int tegra_powergate_power_off(unsigned int id)
926 if (!tegra_powergate_is_available(pmc, id))
929 return tegra_powergate_set(pmc, id, false);
931 EXPORT_SYMBOL(tegra_powergate_power_off);
934 * tegra_powergate_is_powered() - check if partition is powered
935 * @pmc: power management controller
938 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id)
940 if (!tegra_powergate_is_valid(pmc, id))
943 return tegra_powergate_state(id);
947 * tegra_powergate_remove_clamping() - remove power clamps for partition
950 int tegra_powergate_remove_clamping(unsigned int id)
952 if (!tegra_powergate_is_available(pmc, id))
955 return __tegra_powergate_remove_clamping(pmc, id);
957 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
960 * tegra_powergate_sequence_power_up() - power up partition
962 * @clk: clock for partition
963 * @rst: reset for partition
965 * Must be called with clk disabled, and returns with clk enabled.
967 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
968 struct reset_control *rst)
970 struct tegra_powergate *pg;
973 if (!tegra_powergate_is_available(pmc, id))
976 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
980 pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL);
981 if (!pg->clk_rates) {
992 err = tegra_powergate_power_up(pg, false);
994 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
997 kfree(pg->clk_rates);
1002 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
1005 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
1006 * @pmc: power management controller
1007 * @cpuid: CPU partition ID
1009 * Returns the partition ID corresponding to the CPU partition ID or a
1010 * negative error code on failure.
1012 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc,
1015 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
1016 return pmc->soc->cpu_powergates[cpuid];
1022 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
1023 * @cpuid: CPU partition ID
1025 bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
1029 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1033 return tegra_powergate_is_powered(pmc, id);
1037 * tegra_pmc_cpu_power_on() - power on CPU partition
1038 * @cpuid: CPU partition ID
1040 int tegra_pmc_cpu_power_on(unsigned int cpuid)
1044 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1048 return tegra_powergate_set(pmc, id, true);
1052 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
1053 * @cpuid: CPU partition ID
1055 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
1059 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1063 return tegra_powergate_remove_clamping(id);
1066 static int tegra_pmc_restart_notify(struct notifier_block *this,
1067 unsigned long action, void *data)
1069 const char *cmd = data;
1072 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
1073 value &= ~PMC_SCRATCH0_MODE_MASK;
1076 if (strcmp(cmd, "recovery") == 0)
1077 value |= PMC_SCRATCH0_MODE_RECOVERY;
1079 if (strcmp(cmd, "bootloader") == 0)
1080 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
1082 if (strcmp(cmd, "forced-recovery") == 0)
1083 value |= PMC_SCRATCH0_MODE_RCM;
1086 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
1088 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
1089 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1090 value |= PMC_CNTRL_MAIN_RST;
1091 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1096 static struct notifier_block tegra_pmc_restart_handler = {
1097 .notifier_call = tegra_pmc_restart_notify,
1101 static int powergate_show(struct seq_file *s, void *data)
1106 seq_printf(s, " powergate powered\n");
1107 seq_printf(s, "------------------\n");
1109 for (i = 0; i < pmc->soc->num_powergates; i++) {
1110 status = tegra_powergate_is_powered(pmc, i);
1114 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
1115 status ? "yes" : "no");
1121 DEFINE_SHOW_ATTRIBUTE(powergate);
1123 static int tegra_powergate_debugfs_init(void)
1125 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
1133 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
1134 struct device_node *np)
1137 unsigned int i, count;
1140 count = of_clk_get_parent_count(np);
1144 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
1148 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL);
1149 if (!pg->clk_rates) {
1154 for (i = 0; i < count; i++) {
1155 pg->clks[i] = of_clk_get(np, i);
1156 if (IS_ERR(pg->clks[i])) {
1157 err = PTR_ERR(pg->clks[i]);
1162 pg->num_clks = count;
1168 clk_put(pg->clks[i]);
1170 kfree(pg->clk_rates);
1176 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
1177 struct device_node *np, bool off)
1179 struct device *dev = pg->pmc->dev;
1182 pg->reset = of_reset_control_array_get_exclusive_released(np);
1183 if (IS_ERR(pg->reset)) {
1184 err = PTR_ERR(pg->reset);
1185 dev_err(dev, "failed to get device resets: %d\n", err);
1189 err = reset_control_acquire(pg->reset);
1191 pr_err("failed to acquire resets: %d\n", err);
1196 err = reset_control_assert(pg->reset);
1198 err = reset_control_deassert(pg->reset);
1202 reset_control_release(pg->reset);
1207 reset_control_release(pg->reset);
1208 reset_control_put(pg->reset);
1214 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
1216 struct device *dev = pmc->dev;
1217 struct tegra_powergate *pg;
1221 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
1225 id = tegra_powergate_lookup(pmc, np->name);
1227 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id);
1233 * Clear the bit for this powergate so it cannot be managed
1234 * directly via the legacy APIs for controlling powergates.
1236 clear_bit(id, pmc->powergates_available);
1239 pg->genpd.name = np->name;
1240 pg->genpd.power_off = tegra_genpd_power_off;
1241 pg->genpd.power_on = tegra_genpd_power_on;
1244 off = !tegra_powergate_is_powered(pmc, pg->id);
1246 err = tegra_powergate_of_get_clks(pg, np);
1248 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err);
1252 err = tegra_powergate_of_get_resets(pg, np, off);
1254 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err);
1258 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
1260 WARN_ON(tegra_powergate_power_up(pg, true));
1265 err = pm_genpd_init(&pg->genpd, NULL, off);
1267 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np,
1272 err = of_genpd_add_provider_simple(np, &pg->genpd);
1274 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n",
1279 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name);
1284 pm_genpd_remove(&pg->genpd);
1287 reset_control_put(pg->reset);
1290 while (pg->num_clks--)
1291 clk_put(pg->clks[pg->num_clks]);
1296 set_bit(id, pmc->powergates_available);
1304 bool tegra_pmc_core_domain_state_synced(void)
1306 return pmc->core_domain_state_synced;
1310 tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain *genpd,
1313 struct dev_pm_opp *opp;
1316 opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level);
1318 dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n",
1320 return PTR_ERR(opp);
1323 mutex_lock(&pmc->powergates_lock);
1324 err = dev_pm_opp_set_opp(pmc->dev, opp);
1325 mutex_unlock(&pmc->powergates_lock);
1327 dev_pm_opp_put(opp);
1330 dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n",
1339 tegra_pmc_core_pd_opp_to_performance_state(struct generic_pm_domain *genpd,
1340 struct dev_pm_opp *opp)
1342 return dev_pm_opp_get_level(opp);
1345 static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np)
1347 struct generic_pm_domain *genpd;
1348 const char *rname = "core";
1351 genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL);
1355 genpd->name = np->name;
1356 genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state;
1357 genpd->opp_to_performance_state = tegra_pmc_core_pd_opp_to_performance_state;
1359 err = devm_pm_opp_set_regulators(pmc->dev, &rname, 1);
1361 return dev_err_probe(pmc->dev, err,
1362 "failed to set core OPP regulator\n");
1364 err = pm_genpd_init(genpd, NULL, false);
1366 dev_err(pmc->dev, "failed to init core genpd: %d\n", err);
1370 err = of_genpd_add_provider_simple(np, genpd);
1372 dev_err(pmc->dev, "failed to add core genpd: %d\n", err);
1376 pmc->core_domain_registered = true;
1381 pm_genpd_remove(genpd);
1386 static int tegra_powergate_init(struct tegra_pmc *pmc,
1387 struct device_node *parent)
1389 struct of_phandle_args child_args, parent_args;
1390 struct device_node *np, *child;
1394 * Core power domain is the parent of powergate domains, hence it
1395 * should be registered first.
1397 np = of_get_child_by_name(parent, "core-domain");
1399 err = tegra_pmc_core_pd_add(pmc, np);
1405 np = of_get_child_by_name(parent, "powergates");
1409 for_each_child_of_node(np, child) {
1410 err = tegra_powergate_add(pmc, child);
1416 if (of_parse_phandle_with_args(child, "power-domains",
1417 "#power-domain-cells",
1421 child_args.np = child;
1422 child_args.args_count = 0;
1424 err = of_genpd_add_subdomain(&parent_args, &child_args);
1425 of_node_put(parent_args.np);
1437 static void tegra_powergate_remove(struct generic_pm_domain *genpd)
1439 struct tegra_powergate *pg = to_powergate(genpd);
1441 reset_control_put(pg->reset);
1443 while (pg->num_clks--)
1444 clk_put(pg->clks[pg->num_clks]);
1448 set_bit(pg->id, pmc->powergates_available);
1453 static void tegra_powergate_remove_all(struct device_node *parent)
1455 struct generic_pm_domain *genpd;
1456 struct device_node *np, *child;
1458 np = of_get_child_by_name(parent, "powergates");
1462 for_each_child_of_node(np, child) {
1463 of_genpd_del_provider(child);
1465 genpd = of_genpd_remove_last(child);
1469 tegra_powergate_remove(genpd);
1474 np = of_get_child_by_name(parent, "core-domain");
1476 of_genpd_del_provider(np);
1477 of_genpd_remove_last(np);
1481 static const struct tegra_io_pad_soc *
1482 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
1486 for (i = 0; i < pmc->soc->num_io_pads; i++)
1487 if (pmc->soc->io_pads[i].id == id)
1488 return &pmc->soc->io_pads[i];
1493 static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc,
1494 enum tegra_io_pad id,
1495 unsigned long *request,
1496 unsigned long *status,
1499 const struct tegra_io_pad_soc *pad;
1501 pad = tegra_io_pad_find(pmc, id);
1503 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1507 if (pad->dpd == UINT_MAX)
1510 *mask = BIT(pad->dpd % 32);
1512 if (pad->dpd < 32) {
1513 *status = pmc->soc->regs->dpd_status;
1514 *request = pmc->soc->regs->dpd_req;
1516 *status = pmc->soc->regs->dpd2_status;
1517 *request = pmc->soc->regs->dpd2_req;
1523 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id,
1524 unsigned long *request, unsigned long *status,
1527 unsigned long rate, value;
1530 err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask);
1537 dev_err(pmc->dev, "failed to get clock rate\n");
1541 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);
1543 /* must be at least 200 ns, in APB (PCLK) clock cycles */
1544 value = DIV_ROUND_UP(1000000000, rate);
1545 value = DIV_ROUND_UP(200, value);
1546 tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
1552 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset,
1553 u32 mask, u32 val, unsigned long timeout)
1557 timeout = jiffies + msecs_to_jiffies(timeout);
1559 while (time_after(timeout, jiffies)) {
1560 value = tegra_pmc_readl(pmc, offset);
1561 if ((value & mask) == val)
1564 usleep_range(250, 1000);
1570 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)
1573 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);
1577 * tegra_io_pad_power_enable() - enable power to I/O pad
1578 * @id: Tegra I/O pad ID for which to enable power
1580 * Returns: 0 on success or a negative error code on failure.
1582 int tegra_io_pad_power_enable(enum tegra_io_pad id)
1584 unsigned long request, status;
1588 mutex_lock(&pmc->powergates_lock);
1590 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1592 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1596 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);
1598 err = tegra_io_pad_poll(pmc, status, mask, 0, 250);
1600 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err);
1604 tegra_io_pad_unprepare(pmc);
1607 mutex_unlock(&pmc->powergates_lock);
1610 EXPORT_SYMBOL(tegra_io_pad_power_enable);
1613 * tegra_io_pad_power_disable() - disable power to I/O pad
1614 * @id: Tegra I/O pad ID for which to disable power
1616 * Returns: 0 on success or a negative error code on failure.
1618 int tegra_io_pad_power_disable(enum tegra_io_pad id)
1620 unsigned long request, status;
1624 mutex_lock(&pmc->powergates_lock);
1626 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1628 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1632 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);
1634 err = tegra_io_pad_poll(pmc, status, mask, mask, 250);
1636 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err);
1640 tegra_io_pad_unprepare(pmc);
1643 mutex_unlock(&pmc->powergates_lock);
1646 EXPORT_SYMBOL(tegra_io_pad_power_disable);
1648 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)
1650 unsigned long request, status;
1654 err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status,
1659 value = tegra_pmc_readl(pmc, status);
1661 return !(value & mask);
1664 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,
1667 const struct tegra_io_pad_soc *pad;
1670 pad = tegra_io_pad_find(pmc, id);
1674 if (pad->voltage == UINT_MAX)
1677 mutex_lock(&pmc->powergates_lock);
1679 if (pmc->soc->has_impl_33v_pwr) {
1680 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1682 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1683 value &= ~BIT(pad->voltage);
1685 value |= BIT(pad->voltage);
1687 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
1689 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1690 value = tegra_pmc_readl(pmc, PMC_PWR_DET);
1691 value |= BIT(pad->voltage);
1692 tegra_pmc_writel(pmc, value, PMC_PWR_DET);
1694 /* update I/O voltage */
1695 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1697 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1698 value &= ~BIT(pad->voltage);
1700 value |= BIT(pad->voltage);
1702 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
1705 mutex_unlock(&pmc->powergates_lock);
1707 usleep_range(100, 250);
1712 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)
1714 const struct tegra_io_pad_soc *pad;
1717 pad = tegra_io_pad_find(pmc, id);
1721 if (pad->voltage == UINT_MAX)
1724 if (pmc->soc->has_impl_33v_pwr)
1725 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1727 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1729 if ((value & BIT(pad->voltage)) == 0)
1730 return TEGRA_IO_PAD_VOLTAGE_1V8;
1732 return TEGRA_IO_PAD_VOLTAGE_3V3;
1736 * tegra_io_rail_power_on() - enable power to I/O rail
1737 * @id: Tegra I/O pad ID for which to enable power
1739 * See also: tegra_io_pad_power_enable()
1741 int tegra_io_rail_power_on(unsigned int id)
1743 return tegra_io_pad_power_enable(id);
1745 EXPORT_SYMBOL(tegra_io_rail_power_on);
1748 * tegra_io_rail_power_off() - disable power to I/O rail
1749 * @id: Tegra I/O pad ID for which to disable power
1751 * See also: tegra_io_pad_power_disable()
1753 int tegra_io_rail_power_off(unsigned int id)
1755 return tegra_io_pad_power_disable(id);
1757 EXPORT_SYMBOL(tegra_io_rail_power_off);
1759 #ifdef CONFIG_PM_SLEEP
1760 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1762 return pmc->suspend_mode;
1765 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1767 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1770 pmc->suspend_mode = mode;
1773 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1775 unsigned long long rate = 0;
1780 case TEGRA_SUSPEND_LP1:
1784 case TEGRA_SUSPEND_LP2:
1792 if (WARN_ON_ONCE(rate == 0))
1795 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1796 do_div(ticks, USEC_PER_SEC);
1797 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
1799 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1800 do_div(ticks, USEC_PER_SEC);
1801 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
1803 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1804 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1805 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1806 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1810 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1812 u32 value, values[2];
1814 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1815 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1819 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1823 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1827 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1831 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1836 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1838 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1839 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1841 pmc->cpu_good_time = value;
1843 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1844 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1846 pmc->cpu_off_time = value;
1848 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1849 values, ARRAY_SIZE(values)))
1850 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1852 pmc->core_osc_time = values[0];
1853 pmc->core_pmu_time = values[1];
1855 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1856 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1858 pmc->core_off_time = value;
1860 pmc->corereq_high = of_property_read_bool(np,
1861 "nvidia,core-power-req-active-high");
1863 pmc->sysclkreq_high = of_property_read_bool(np,
1864 "nvidia,sys-clock-req-active-high");
1866 pmc->combined_req = of_property_read_bool(np,
1867 "nvidia,combined-power-req");
1869 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1870 "nvidia,cpu-pwr-good-en");
1872 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1873 ARRAY_SIZE(values)))
1874 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1875 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1877 pmc->lp0_vec_phys = values[0];
1878 pmc->lp0_vec_size = values[1];
1883 static void tegra_pmc_init(struct tegra_pmc *pmc)
1886 pmc->soc->init(pmc);
1889 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1891 static const char disabled[] = "emergency thermal reset disabled";
1892 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1893 struct device *dev = pmc->dev;
1894 struct device_node *np;
1895 u32 value, checksum;
1897 if (!pmc->soc->has_tsense_reset)
1900 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
1902 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1906 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1907 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1911 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1912 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1916 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) {
1917 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1921 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) {
1922 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1926 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1929 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1930 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1931 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1933 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1934 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1935 tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
1937 value = PMC_SCRATCH55_RESET_TEGRA;
1938 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1939 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1940 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1943 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
1944 * contain the checksum and are currently zero, so they are not added.
1946 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1947 + ((value >> 24) & 0xff);
1949 checksum = 0x100 - checksum;
1951 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1953 tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
1955 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1956 value |= PMC_SENSOR_CTRL_ENABLE_RST;
1957 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1959 dev_info(pmc->dev, "emergency thermal reset enabled\n");
1965 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev)
1967 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1969 return pmc->soc->num_io_pads;
1972 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl,
1975 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl);
1977 return pmc->soc->io_pads[group].name;
1980 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev,
1982 const unsigned int **pins,
1983 unsigned int *num_pins)
1985 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1987 *pins = &pmc->soc->io_pads[group].id;
1993 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = {
1994 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count,
1995 .get_group_name = tegra_io_pad_pinctrl_get_group_name,
1996 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins,
1997 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1998 .dt_free_map = pinconf_generic_dt_free_map,
2001 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev,
2002 unsigned int pin, unsigned long *config)
2004 enum pin_config_param param = pinconf_to_config_param(*config);
2005 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2006 const struct tegra_io_pad_soc *pad;
2010 pad = tegra_io_pad_find(pmc, pin);
2015 case PIN_CONFIG_POWER_SOURCE:
2016 ret = tegra_io_pad_get_voltage(pmc, pad->id);
2023 case PIN_CONFIG_MODE_LOW_POWER:
2024 ret = tegra_io_pad_is_powered(pmc, pad->id);
2035 *config = pinconf_to_config_packed(param, arg);
2040 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev,
2041 unsigned int pin, unsigned long *configs,
2042 unsigned int num_configs)
2044 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2045 const struct tegra_io_pad_soc *pad;
2046 enum pin_config_param param;
2051 pad = tegra_io_pad_find(pmc, pin);
2055 for (i = 0; i < num_configs; ++i) {
2056 param = pinconf_to_config_param(configs[i]);
2057 arg = pinconf_to_config_argument(configs[i]);
2060 case PIN_CONFIG_MODE_LOW_POWER:
2062 err = tegra_io_pad_power_disable(pad->id);
2064 err = tegra_io_pad_power_enable(pad->id);
2068 case PIN_CONFIG_POWER_SOURCE:
2069 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 &&
2070 arg != TEGRA_IO_PAD_VOLTAGE_3V3)
2072 err = tegra_io_pad_set_voltage(pmc, pad->id, arg);
2084 static const struct pinconf_ops tegra_io_pad_pinconf_ops = {
2085 .pin_config_get = tegra_io_pad_pinconf_get,
2086 .pin_config_set = tegra_io_pad_pinconf_set,
2090 static struct pinctrl_desc tegra_pmc_pctl_desc = {
2091 .pctlops = &tegra_io_pad_pinctrl_ops,
2092 .confops = &tegra_io_pad_pinconf_ops,
2095 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
2099 if (!pmc->soc->num_pin_descs)
2102 tegra_pmc_pctl_desc.name = dev_name(pmc->dev);
2103 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs;
2104 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs;
2106 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc,
2108 if (IS_ERR(pmc->pctl_dev)) {
2109 err = PTR_ERR(pmc->pctl_dev);
2110 dev_err(pmc->dev, "failed to register pin controller: %d\n",
2118 static ssize_t reset_reason_show(struct device *dev,
2119 struct device_attribute *attr, char *buf)
2123 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2124 value &= pmc->soc->regs->rst_source_mask;
2125 value >>= pmc->soc->regs->rst_source_shift;
2127 if (WARN_ON(value >= pmc->soc->num_reset_sources))
2128 return sprintf(buf, "%s\n", "UNKNOWN");
2130 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
2133 static DEVICE_ATTR_RO(reset_reason);
2135 static ssize_t reset_level_show(struct device *dev,
2136 struct device_attribute *attr, char *buf)
2140 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2141 value &= pmc->soc->regs->rst_level_mask;
2142 value >>= pmc->soc->regs->rst_level_shift;
2144 if (WARN_ON(value >= pmc->soc->num_reset_levels))
2145 return sprintf(buf, "%s\n", "UNKNOWN");
2147 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
2150 static DEVICE_ATTR_RO(reset_level);
2152 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
2154 struct device *dev = pmc->dev;
2157 if (pmc->soc->reset_sources) {
2158 err = device_create_file(dev, &dev_attr_reset_reason);
2161 "failed to create attr \"reset_reason\": %d\n",
2165 if (pmc->soc->reset_levels) {
2166 err = device_create_file(dev, &dev_attr_reset_level);
2169 "failed to create attr \"reset_level\": %d\n",
2174 static int tegra_pmc_irq_translate(struct irq_domain *domain,
2175 struct irq_fwspec *fwspec,
2176 unsigned long *hwirq,
2179 if (WARN_ON(fwspec->param_count < 2))
2182 *hwirq = fwspec->param[0];
2183 *type = fwspec->param[1];
2188 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq,
2189 unsigned int num_irqs, void *data)
2191 struct tegra_pmc *pmc = domain->host_data;
2192 const struct tegra_pmc_soc *soc = pmc->soc;
2193 struct irq_fwspec *fwspec = data;
2197 if (WARN_ON(num_irqs > 1))
2200 for (i = 0; i < soc->num_wake_events; i++) {
2201 const struct tegra_wake_event *event = &soc->wake_events[i];
2203 if (fwspec->param_count == 2) {
2204 struct irq_fwspec spec;
2206 if (event->id != fwspec->param[0])
2209 err = irq_domain_set_hwirq_and_chip(domain, virq,
2215 spec.fwnode = &pmc->dev->of_node->fwnode;
2216 spec.param_count = 3;
2217 spec.param[0] = GIC_SPI;
2218 spec.param[1] = event->irq;
2219 spec.param[2] = fwspec->param[1];
2221 err = irq_domain_alloc_irqs_parent(domain, virq,
2227 if (fwspec->param_count == 3) {
2228 if (event->gpio.instance != fwspec->param[0] ||
2229 event->gpio.pin != fwspec->param[1])
2232 err = irq_domain_set_hwirq_and_chip(domain, virq,
2236 /* GPIO hierarchies stop at the PMC level */
2237 if (!err && domain->parent)
2238 err = irq_domain_disconnect_hierarchy(domain->parent,
2244 /* If there is no wake-up event, there is no PMC mapping */
2245 if (i == soc->num_wake_events)
2246 err = irq_domain_disconnect_hierarchy(domain, virq);
2251 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {
2252 .translate = tegra_pmc_irq_translate,
2253 .alloc = tegra_pmc_irq_alloc,
2256 static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2258 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2259 unsigned int offset, bit;
2262 offset = data->hwirq / 32;
2263 bit = data->hwirq % 32;
2265 /* clear wake status */
2266 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);
2267 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);
2269 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);
2270 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);
2272 /* enable PMC wake */
2273 if (data->hwirq >= 32)
2274 offset = PMC_WAKE2_MASK;
2276 offset = PMC_WAKE_MASK;
2278 value = tegra_pmc_readl(pmc, offset);
2285 tegra_pmc_writel(pmc, value, offset);
2290 static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2292 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2293 unsigned int offset, bit;
2296 offset = data->hwirq / 32;
2297 bit = data->hwirq % 32;
2299 if (data->hwirq >= 32)
2300 offset = PMC_WAKE2_LEVEL;
2302 offset = PMC_WAKE_LEVEL;
2304 value = tegra_pmc_readl(pmc, offset);
2307 case IRQ_TYPE_EDGE_RISING:
2308 case IRQ_TYPE_LEVEL_HIGH:
2312 case IRQ_TYPE_EDGE_FALLING:
2313 case IRQ_TYPE_LEVEL_LOW:
2317 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2325 tegra_pmc_writel(pmc, value, offset);
2330 static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2332 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2333 unsigned int offset, bit;
2336 offset = data->hwirq / 32;
2337 bit = data->hwirq % 32;
2339 /* clear wake status */
2340 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
2342 /* route wake to tier 2 */
2343 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2346 value &= ~(1 << bit);
2350 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2352 /* enable wakeup event */
2353 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
2358 static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2360 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2363 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2366 case IRQ_TYPE_EDGE_RISING:
2367 case IRQ_TYPE_LEVEL_HIGH:
2368 value |= WAKE_AOWAKE_CNTRL_LEVEL;
2371 case IRQ_TYPE_EDGE_FALLING:
2372 case IRQ_TYPE_LEVEL_LOW:
2373 value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
2376 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2377 value ^= WAKE_AOWAKE_CNTRL_LEVEL;
2384 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2389 static void tegra_irq_mask_parent(struct irq_data *data)
2391 if (data->parent_data)
2392 irq_chip_mask_parent(data);
2395 static void tegra_irq_unmask_parent(struct irq_data *data)
2397 if (data->parent_data)
2398 irq_chip_unmask_parent(data);
2401 static void tegra_irq_eoi_parent(struct irq_data *data)
2403 if (data->parent_data)
2404 irq_chip_eoi_parent(data);
2407 static int tegra_irq_set_affinity_parent(struct irq_data *data,
2408 const struct cpumask *dest,
2411 if (data->parent_data)
2412 return irq_chip_set_affinity_parent(data, dest, force);
2417 static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
2419 struct irq_domain *parent = NULL;
2420 struct device_node *np;
2422 np = of_irq_find_parent(pmc->dev->of_node);
2424 parent = irq_find_host(np);
2431 pmc->irq.name = dev_name(pmc->dev);
2432 pmc->irq.irq_mask = tegra_irq_mask_parent;
2433 pmc->irq.irq_unmask = tegra_irq_unmask_parent;
2434 pmc->irq.irq_eoi = tegra_irq_eoi_parent;
2435 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent;
2436 pmc->irq.irq_set_type = pmc->soc->irq_set_type;
2437 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake;
2439 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,
2440 &tegra_pmc_irq_domain_ops, pmc);
2442 dev_err(pmc->dev, "failed to allocate domain\n");
2449 static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
2450 unsigned long action, void *ptr)
2452 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb);
2453 struct clk_notifier_data *data = ptr;
2456 case PRE_RATE_CHANGE:
2457 mutex_lock(&pmc->powergates_lock);
2460 case POST_RATE_CHANGE:
2461 pmc->rate = data->new_rate;
2464 case ABORT_RATE_CHANGE:
2465 mutex_unlock(&pmc->powergates_lock);
2470 return notifier_from_errno(-EINVAL);
2476 static void pmc_clk_fence_udelay(u32 offset)
2478 tegra_pmc_readl(pmc, offset);
2479 /* pmc clk propagation delay 2 us */
2483 static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
2485 struct pmc_clk *clk = to_pmc_clk(hw);
2488 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
2489 val &= PMC_CLK_OUT_MUX_MASK;
2494 static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
2496 struct pmc_clk *clk = to_pmc_clk(hw);
2499 val = tegra_pmc_readl(pmc, clk->offs);
2500 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift);
2501 val |= index << clk->mux_shift;
2502 tegra_pmc_writel(pmc, val, clk->offs);
2503 pmc_clk_fence_udelay(clk->offs);
2508 static int pmc_clk_is_enabled(struct clk_hw *hw)
2510 struct pmc_clk *clk = to_pmc_clk(hw);
2513 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift);
2518 static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
2522 val = tegra_pmc_readl(pmc, offs);
2523 val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
2524 tegra_pmc_writel(pmc, val, offs);
2525 pmc_clk_fence_udelay(offs);
2528 static int pmc_clk_enable(struct clk_hw *hw)
2530 struct pmc_clk *clk = to_pmc_clk(hw);
2532 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1);
2537 static void pmc_clk_disable(struct clk_hw *hw)
2539 struct pmc_clk *clk = to_pmc_clk(hw);
2541 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0);
2544 static const struct clk_ops pmc_clk_ops = {
2545 .get_parent = pmc_clk_mux_get_parent,
2546 .set_parent = pmc_clk_mux_set_parent,
2547 .determine_rate = __clk_mux_determine_rate,
2548 .is_enabled = pmc_clk_is_enabled,
2549 .enable = pmc_clk_enable,
2550 .disable = pmc_clk_disable,
2554 tegra_pmc_clk_out_register(struct tegra_pmc *pmc,
2555 const struct pmc_clk_init_data *data,
2556 unsigned long offset)
2558 struct clk_init_data init;
2559 struct pmc_clk *pmc_clk;
2561 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL);
2563 return ERR_PTR(-ENOMEM);
2565 init.name = data->name;
2566 init.ops = &pmc_clk_ops;
2567 init.parent_names = data->parents;
2568 init.num_parents = data->num_parents;
2569 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
2570 CLK_SET_PARENT_GATE;
2572 pmc_clk->hw.init = &init;
2573 pmc_clk->offs = offset;
2574 pmc_clk->mux_shift = data->mux_shift;
2575 pmc_clk->force_en_shift = data->force_en_shift;
2577 return clk_register(NULL, &pmc_clk->hw);
2580 static int pmc_clk_gate_is_enabled(struct clk_hw *hw)
2582 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2584 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
2587 static int pmc_clk_gate_enable(struct clk_hw *hw)
2589 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2591 pmc_clk_set_state(gate->offs, gate->shift, 1);
2596 static void pmc_clk_gate_disable(struct clk_hw *hw)
2598 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2600 pmc_clk_set_state(gate->offs, gate->shift, 0);
2603 static const struct clk_ops pmc_clk_gate_ops = {
2604 .is_enabled = pmc_clk_gate_is_enabled,
2605 .enable = pmc_clk_gate_enable,
2606 .disable = pmc_clk_gate_disable,
2610 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name,
2611 const char *parent_name, unsigned long offset,
2614 struct clk_init_data init;
2615 struct pmc_clk_gate *gate;
2617 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL);
2619 return ERR_PTR(-ENOMEM);
2622 init.ops = &pmc_clk_gate_ops;
2623 init.parent_names = &parent_name;
2624 init.num_parents = 1;
2627 gate->hw.init = &init;
2628 gate->offs = offset;
2629 gate->shift = shift;
2631 return clk_register(NULL, &gate->hw);
2634 static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
2635 struct device_node *np)
2638 struct clk_onecell_data *clk_data;
2639 unsigned int num_clks;
2642 num_clks = pmc->soc->num_pmc_clks;
2643 if (pmc->soc->has_blink_output)
2649 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL);
2653 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX,
2654 sizeof(*clk_data->clks), GFP_KERNEL);
2655 if (!clk_data->clks)
2658 clk_data->clk_num = TEGRA_PMC_CLK_MAX;
2660 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
2661 clk_data->clks[i] = ERR_PTR(-ENOENT);
2663 for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
2664 const struct pmc_clk_init_data *data;
2666 data = pmc->soc->pmc_clks_data + i;
2668 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL);
2670 dev_warn(pmc->dev, "unable to register clock %s: %d\n",
2671 data->name, PTR_ERR_OR_ZERO(clk));
2675 err = clk_register_clkdev(clk, data->name, NULL);
2678 "unable to register %s clock lookup: %d\n",
2683 clk_data->clks[data->clk_id] = clk;
2686 if (pmc->soc->has_blink_output) {
2687 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER);
2688 clk = tegra_pmc_clk_gate_register(pmc,
2689 "pmc_blink_override",
2692 PMC_DPD_PADS_ORIDE_BLINK);
2695 "unable to register pmc_blink_override: %d\n",
2696 PTR_ERR_OR_ZERO(clk));
2700 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink",
2701 "pmc_blink_override",
2703 PMC_CNTRL_BLINK_EN);
2706 "unable to register pmc_blink: %d\n",
2707 PTR_ERR_OR_ZERO(clk));
2711 err = clk_register_clkdev(clk, "pmc_blink", NULL);
2714 "unable to register pmc_blink lookup: %d\n",
2719 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk;
2722 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
2724 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n",
2728 static const struct regmap_range pmc_usb_sleepwalk_ranges[] = {
2729 regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO),
2730 regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE),
2731 regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE),
2732 regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP, PMC_UTMIP_UHSIC_LINE_WAKEUP),
2733 regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG),
2734 regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG),
2735 regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1),
2736 regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3),
2739 static const struct regmap_access_table pmc_usb_sleepwalk_table = {
2740 .yes_ranges = pmc_usb_sleepwalk_ranges,
2741 .n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges),
2744 static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value)
2746 struct tegra_pmc *pmc = context;
2748 *value = tegra_pmc_readl(pmc, offset);
2752 static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value)
2754 struct tegra_pmc *pmc = context;
2756 tegra_pmc_writel(pmc, value, offset);
2760 static const struct regmap_config usb_sleepwalk_regmap_config = {
2761 .name = "usb_sleepwalk",
2766 .rd_table = &pmc_usb_sleepwalk_table,
2767 .wr_table = &pmc_usb_sleepwalk_table,
2768 .reg_read = tegra_pmc_regmap_readl,
2769 .reg_write = tegra_pmc_regmap_writel,
2772 static int tegra_pmc_regmap_init(struct tegra_pmc *pmc)
2774 struct regmap *regmap;
2777 if (pmc->soc->has_usb_sleepwalk) {
2778 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config);
2779 if (IS_ERR(regmap)) {
2780 err = PTR_ERR(regmap);
2781 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err);
2789 static void tegra_pmc_reset_suspend_mode(void *data)
2791 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY;
2794 static int tegra_pmc_probe(struct platform_device *pdev)
2797 struct resource *res;
2801 * Early initialisation should have configured an initial
2802 * register mapping and setup the soc data pointer. If these
2803 * are not valid then something went badly wrong!
2805 if (WARN_ON(!pmc->base || !pmc->soc))
2808 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
2812 err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode,
2817 /* take over the memory region from the early initialization */
2818 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2819 base = devm_ioremap_resource(&pdev->dev, res);
2821 return PTR_ERR(base);
2823 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
2825 pmc->wake = devm_ioremap_resource(&pdev->dev, res);
2826 if (IS_ERR(pmc->wake))
2827 return PTR_ERR(pmc->wake);
2832 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
2834 pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
2835 if (IS_ERR(pmc->aotag))
2836 return PTR_ERR(pmc->aotag);
2841 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
2843 pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
2844 if (IS_ERR(pmc->scratch))
2845 return PTR_ERR(pmc->scratch);
2847 pmc->scratch = base;
2850 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
2851 if (IS_ERR(pmc->clk)) {
2852 err = PTR_ERR(pmc->clk);
2854 if (err != -ENOENT) {
2855 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
2863 * PCLK clock rate can't be retrieved using CLK API because it
2864 * causes lockup if CPU enters LP2 idle state from some other
2865 * CLK notifier, hence we're caching the rate's value locally.
2868 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb;
2869 err = clk_notifier_register(pmc->clk, &pmc->clk_nb);
2872 "failed to register clk notifier\n");
2876 pmc->rate = clk_get_rate(pmc->clk);
2879 pmc->dev = &pdev->dev;
2881 tegra_pmc_init(pmc);
2883 tegra_pmc_init_tsense_reset(pmc);
2885 tegra_pmc_reset_sysfs_init(pmc);
2887 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2888 err = tegra_powergate_debugfs_init();
2893 err = register_restart_handler(&tegra_pmc_restart_handler);
2895 dev_err(&pdev->dev, "unable to register restart handler, %d\n",
2897 goto cleanup_debugfs;
2900 err = tegra_pmc_pinctrl_init(pmc);
2902 goto cleanup_restart_handler;
2904 err = tegra_pmc_regmap_init(pmc);
2906 goto cleanup_restart_handler;
2908 err = tegra_powergate_init(pmc, pdev->dev.of_node);
2910 goto cleanup_powergates;
2912 err = tegra_pmc_irq_init(pmc);
2914 goto cleanup_powergates;
2916 mutex_lock(&pmc->powergates_lock);
2919 mutex_unlock(&pmc->powergates_lock);
2921 tegra_pmc_clock_register(pmc, pdev->dev.of_node);
2922 platform_set_drvdata(pdev, pmc);
2923 tegra_pm_init_suspend();
2928 tegra_powergate_remove_all(pdev->dev.of_node);
2929 cleanup_restart_handler:
2930 unregister_restart_handler(&tegra_pmc_restart_handler);
2932 debugfs_remove(pmc->debugfs);
2934 device_remove_file(&pdev->dev, &dev_attr_reset_reason);
2935 device_remove_file(&pdev->dev, &dev_attr_reset_level);
2936 clk_notifier_unregister(pmc->clk, &pmc->clk_nb);
2941 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
2942 static int tegra_pmc_suspend(struct device *dev)
2944 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2946 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);
2951 static int tegra_pmc_resume(struct device *dev)
2953 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2955 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);
2960 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
2964 static const char * const tegra20_powergates[] = {
2965 [TEGRA_POWERGATE_CPU] = "cpu",
2966 [TEGRA_POWERGATE_3D] = "3d",
2967 [TEGRA_POWERGATE_VENC] = "venc",
2968 [TEGRA_POWERGATE_VDEC] = "vdec",
2969 [TEGRA_POWERGATE_PCIE] = "pcie",
2970 [TEGRA_POWERGATE_L2] = "l2",
2971 [TEGRA_POWERGATE_MPE] = "mpe",
2974 static const struct tegra_pmc_regs tegra20_pmc_regs = {
2977 .dpd_status = 0x1bc,
2979 .dpd2_status = 0x1c4,
2980 .rst_status = 0x1b4,
2981 .rst_source_shift = 0x0,
2982 .rst_source_mask = 0x7,
2983 .rst_level_shift = 0x0,
2984 .rst_level_mask = 0x0,
2987 static void tegra20_pmc_init(struct tegra_pmc *pmc)
2989 u32 value, osc, pmu, off;
2991 /* Always enable CPU power request */
2992 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2993 value |= PMC_CNTRL_CPU_PWRREQ_OE;
2994 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2996 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2998 if (pmc->sysclkreq_high)
2999 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
3001 value |= PMC_CNTRL_SYSCLK_POLARITY;
3003 if (pmc->corereq_high)
3004 value &= ~PMC_CNTRL_PWRREQ_POLARITY;
3006 value |= PMC_CNTRL_PWRREQ_POLARITY;
3008 /* configure the output polarity while the request is tristated */
3009 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3011 /* now enable the request */
3012 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3013 value |= PMC_CNTRL_SYSCLK_OE;
3014 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3016 /* program core timings which are applicable only for suspend state */
3017 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) {
3018 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000);
3019 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000);
3020 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000);
3021 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),
3022 PMC_COREPWRGOOD_TIMER);
3023 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);
3027 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3028 struct device_node *np,
3033 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3036 value |= PMC_CNTRL_INTR_POLARITY;
3038 value &= ~PMC_CNTRL_INTR_POLARITY;
3040 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3043 static const struct tegra_pmc_soc tegra20_pmc_soc = {
3044 .num_powergates = ARRAY_SIZE(tegra20_powergates),
3045 .powergates = tegra20_powergates,
3046 .num_cpu_powergates = 0,
3047 .cpu_powergates = NULL,
3048 .has_tsense_reset = false,
3049 .has_gpu_clamps = false,
3050 .needs_mbist_war = false,
3051 .has_impl_33v_pwr = false,
3052 .maybe_tz_only = false,
3057 .regs = &tegra20_pmc_regs,
3058 .init = tegra20_pmc_init,
3059 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3060 .powergate_set = tegra20_powergate_set,
3061 .reset_sources = NULL,
3062 .num_reset_sources = 0,
3063 .reset_levels = NULL,
3064 .num_reset_levels = 0,
3065 .pmc_clks_data = NULL,
3067 .has_blink_output = true,
3068 .has_usb_sleepwalk = false,
3071 static const char * const tegra30_powergates[] = {
3072 [TEGRA_POWERGATE_CPU] = "cpu0",
3073 [TEGRA_POWERGATE_3D] = "3d0",
3074 [TEGRA_POWERGATE_VENC] = "venc",
3075 [TEGRA_POWERGATE_VDEC] = "vdec",
3076 [TEGRA_POWERGATE_PCIE] = "pcie",
3077 [TEGRA_POWERGATE_L2] = "l2",
3078 [TEGRA_POWERGATE_MPE] = "mpe",
3079 [TEGRA_POWERGATE_HEG] = "heg",
3080 [TEGRA_POWERGATE_SATA] = "sata",
3081 [TEGRA_POWERGATE_CPU1] = "cpu1",
3082 [TEGRA_POWERGATE_CPU2] = "cpu2",
3083 [TEGRA_POWERGATE_CPU3] = "cpu3",
3084 [TEGRA_POWERGATE_CELP] = "celp",
3085 [TEGRA_POWERGATE_3D1] = "3d1",
3088 static const u8 tegra30_cpu_powergates[] = {
3089 TEGRA_POWERGATE_CPU,
3090 TEGRA_POWERGATE_CPU1,
3091 TEGRA_POWERGATE_CPU2,
3092 TEGRA_POWERGATE_CPU3,
3095 static const char * const tegra30_reset_sources[] = {
3103 static const struct tegra_pmc_soc tegra30_pmc_soc = {
3104 .num_powergates = ARRAY_SIZE(tegra30_powergates),
3105 .powergates = tegra30_powergates,
3106 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
3107 .cpu_powergates = tegra30_cpu_powergates,
3108 .has_tsense_reset = true,
3109 .has_gpu_clamps = false,
3110 .needs_mbist_war = false,
3111 .has_impl_33v_pwr = false,
3112 .maybe_tz_only = false,
3117 .regs = &tegra20_pmc_regs,
3118 .init = tegra20_pmc_init,
3119 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3120 .powergate_set = tegra20_powergate_set,
3121 .reset_sources = tegra30_reset_sources,
3122 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3123 .reset_levels = NULL,
3124 .num_reset_levels = 0,
3125 .pmc_clks_data = tegra_pmc_clks_data,
3126 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3127 .has_blink_output = true,
3128 .has_usb_sleepwalk = false,
3131 static const char * const tegra114_powergates[] = {
3132 [TEGRA_POWERGATE_CPU] = "crail",
3133 [TEGRA_POWERGATE_3D] = "3d",
3134 [TEGRA_POWERGATE_VENC] = "venc",
3135 [TEGRA_POWERGATE_VDEC] = "vdec",
3136 [TEGRA_POWERGATE_MPE] = "mpe",
3137 [TEGRA_POWERGATE_HEG] = "heg",
3138 [TEGRA_POWERGATE_CPU1] = "cpu1",
3139 [TEGRA_POWERGATE_CPU2] = "cpu2",
3140 [TEGRA_POWERGATE_CPU3] = "cpu3",
3141 [TEGRA_POWERGATE_CELP] = "celp",
3142 [TEGRA_POWERGATE_CPU0] = "cpu0",
3143 [TEGRA_POWERGATE_C0NC] = "c0nc",
3144 [TEGRA_POWERGATE_C1NC] = "c1nc",
3145 [TEGRA_POWERGATE_DIS] = "dis",
3146 [TEGRA_POWERGATE_DISB] = "disb",
3147 [TEGRA_POWERGATE_XUSBA] = "xusba",
3148 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3149 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3152 static const u8 tegra114_cpu_powergates[] = {
3153 TEGRA_POWERGATE_CPU0,
3154 TEGRA_POWERGATE_CPU1,
3155 TEGRA_POWERGATE_CPU2,
3156 TEGRA_POWERGATE_CPU3,
3159 static const struct tegra_pmc_soc tegra114_pmc_soc = {
3160 .num_powergates = ARRAY_SIZE(tegra114_powergates),
3161 .powergates = tegra114_powergates,
3162 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
3163 .cpu_powergates = tegra114_cpu_powergates,
3164 .has_tsense_reset = true,
3165 .has_gpu_clamps = false,
3166 .needs_mbist_war = false,
3167 .has_impl_33v_pwr = false,
3168 .maybe_tz_only = false,
3173 .regs = &tegra20_pmc_regs,
3174 .init = tegra20_pmc_init,
3175 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3176 .powergate_set = tegra114_powergate_set,
3177 .reset_sources = tegra30_reset_sources,
3178 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3179 .reset_levels = NULL,
3180 .num_reset_levels = 0,
3181 .pmc_clks_data = tegra_pmc_clks_data,
3182 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3183 .has_blink_output = true,
3184 .has_usb_sleepwalk = false,
3187 static const char * const tegra124_powergates[] = {
3188 [TEGRA_POWERGATE_CPU] = "crail",
3189 [TEGRA_POWERGATE_3D] = "3d",
3190 [TEGRA_POWERGATE_VENC] = "venc",
3191 [TEGRA_POWERGATE_PCIE] = "pcie",
3192 [TEGRA_POWERGATE_VDEC] = "vdec",
3193 [TEGRA_POWERGATE_MPE] = "mpe",
3194 [TEGRA_POWERGATE_HEG] = "heg",
3195 [TEGRA_POWERGATE_SATA] = "sata",
3196 [TEGRA_POWERGATE_CPU1] = "cpu1",
3197 [TEGRA_POWERGATE_CPU2] = "cpu2",
3198 [TEGRA_POWERGATE_CPU3] = "cpu3",
3199 [TEGRA_POWERGATE_CELP] = "celp",
3200 [TEGRA_POWERGATE_CPU0] = "cpu0",
3201 [TEGRA_POWERGATE_C0NC] = "c0nc",
3202 [TEGRA_POWERGATE_C1NC] = "c1nc",
3203 [TEGRA_POWERGATE_SOR] = "sor",
3204 [TEGRA_POWERGATE_DIS] = "dis",
3205 [TEGRA_POWERGATE_DISB] = "disb",
3206 [TEGRA_POWERGATE_XUSBA] = "xusba",
3207 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3208 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3209 [TEGRA_POWERGATE_VIC] = "vic",
3210 [TEGRA_POWERGATE_IRAM] = "iram",
3213 static const u8 tegra124_cpu_powergates[] = {
3214 TEGRA_POWERGATE_CPU0,
3215 TEGRA_POWERGATE_CPU1,
3216 TEGRA_POWERGATE_CPU2,
3217 TEGRA_POWERGATE_CPU3,
3220 #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \
3221 ((struct tegra_io_pad_soc) { \
3224 .voltage = (_voltage), \
3228 #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \
3229 ((struct pinctrl_pin_desc) { \
3234 #define TEGRA124_IO_PAD_TABLE(_pad) \
3235 /* .id .dpd .voltage .name */ \
3236 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3237 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \
3238 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \
3239 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \
3240 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3241 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \
3242 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \
3243 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3244 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
3245 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
3246 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
3247 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
3248 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3249 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \
3250 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
3251 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3252 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \
3253 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
3254 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
3255 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3256 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3257 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \
3258 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \
3259 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \
3260 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \
3261 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3262 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3263 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3264 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3265 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias")
3267 static const struct tegra_io_pad_soc tegra124_io_pads[] = {
3268 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD)
3271 static const struct pinctrl_pin_desc tegra124_pin_descs[] = {
3272 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3275 static const struct tegra_pmc_soc tegra124_pmc_soc = {
3276 .num_powergates = ARRAY_SIZE(tegra124_powergates),
3277 .powergates = tegra124_powergates,
3278 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
3279 .cpu_powergates = tegra124_cpu_powergates,
3280 .has_tsense_reset = true,
3281 .has_gpu_clamps = true,
3282 .needs_mbist_war = false,
3283 .has_impl_33v_pwr = false,
3284 .maybe_tz_only = false,
3285 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
3286 .io_pads = tegra124_io_pads,
3287 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs),
3288 .pin_descs = tegra124_pin_descs,
3289 .regs = &tegra20_pmc_regs,
3290 .init = tegra20_pmc_init,
3291 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3292 .powergate_set = tegra114_powergate_set,
3293 .reset_sources = tegra30_reset_sources,
3294 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3295 .reset_levels = NULL,
3296 .num_reset_levels = 0,
3297 .pmc_clks_data = tegra_pmc_clks_data,
3298 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3299 .has_blink_output = true,
3300 .has_usb_sleepwalk = true,
3303 static const char * const tegra210_powergates[] = {
3304 [TEGRA_POWERGATE_CPU] = "crail",
3305 [TEGRA_POWERGATE_3D] = "3d",
3306 [TEGRA_POWERGATE_VENC] = "venc",
3307 [TEGRA_POWERGATE_PCIE] = "pcie",
3308 [TEGRA_POWERGATE_MPE] = "mpe",
3309 [TEGRA_POWERGATE_SATA] = "sata",
3310 [TEGRA_POWERGATE_CPU1] = "cpu1",
3311 [TEGRA_POWERGATE_CPU2] = "cpu2",
3312 [TEGRA_POWERGATE_CPU3] = "cpu3",
3313 [TEGRA_POWERGATE_CPU0] = "cpu0",
3314 [TEGRA_POWERGATE_C0NC] = "c0nc",
3315 [TEGRA_POWERGATE_SOR] = "sor",
3316 [TEGRA_POWERGATE_DIS] = "dis",
3317 [TEGRA_POWERGATE_DISB] = "disb",
3318 [TEGRA_POWERGATE_XUSBA] = "xusba",
3319 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3320 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3321 [TEGRA_POWERGATE_VIC] = "vic",
3322 [TEGRA_POWERGATE_IRAM] = "iram",
3323 [TEGRA_POWERGATE_NVDEC] = "nvdec",
3324 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
3325 [TEGRA_POWERGATE_AUD] = "aud",
3326 [TEGRA_POWERGATE_DFD] = "dfd",
3327 [TEGRA_POWERGATE_VE2] = "ve2",
3330 static const u8 tegra210_cpu_powergates[] = {
3331 TEGRA_POWERGATE_CPU0,
3332 TEGRA_POWERGATE_CPU1,
3333 TEGRA_POWERGATE_CPU2,
3334 TEGRA_POWERGATE_CPU3,
3337 #define TEGRA210_IO_PAD_TABLE(_pad) \
3338 /* .id .dpd .voltage .name */ \
3339 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \
3340 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \
3341 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \
3342 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3343 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3344 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \
3345 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \
3346 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \
3347 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \
3348 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \
3349 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \
3350 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \
3351 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \
3352 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3353 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
3354 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
3355 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
3356 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \
3357 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \
3358 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \
3359 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
3360 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3361 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
3362 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3363 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
3364 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
3365 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3366 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \
3367 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \
3368 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \
3369 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \
3370 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \
3371 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \
3372 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3373 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3374 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3375 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \
3376 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias")
3378 static const struct tegra_io_pad_soc tegra210_io_pads[] = {
3379 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD)
3382 static const struct pinctrl_pin_desc tegra210_pin_descs[] = {
3383 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3386 static const char * const tegra210_reset_sources[] = {
3395 static const struct tegra_wake_event tegra210_wake_events[] = {
3396 TEGRA_WAKE_IRQ("rtc", 16, 2),
3397 TEGRA_WAKE_IRQ("pmu", 51, 86),
3400 static const struct tegra_pmc_soc tegra210_pmc_soc = {
3401 .num_powergates = ARRAY_SIZE(tegra210_powergates),
3402 .powergates = tegra210_powergates,
3403 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
3404 .cpu_powergates = tegra210_cpu_powergates,
3405 .has_tsense_reset = true,
3406 .has_gpu_clamps = true,
3407 .needs_mbist_war = true,
3408 .has_impl_33v_pwr = false,
3409 .maybe_tz_only = true,
3410 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
3411 .io_pads = tegra210_io_pads,
3412 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
3413 .pin_descs = tegra210_pin_descs,
3414 .regs = &tegra20_pmc_regs,
3415 .init = tegra20_pmc_init,
3416 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3417 .powergate_set = tegra114_powergate_set,
3418 .irq_set_wake = tegra210_pmc_irq_set_wake,
3419 .irq_set_type = tegra210_pmc_irq_set_type,
3420 .reset_sources = tegra210_reset_sources,
3421 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
3422 .reset_levels = NULL,
3423 .num_reset_levels = 0,
3424 .num_wake_events = ARRAY_SIZE(tegra210_wake_events),
3425 .wake_events = tegra210_wake_events,
3426 .pmc_clks_data = tegra_pmc_clks_data,
3427 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3428 .has_blink_output = true,
3429 .has_usb_sleepwalk = true,
3432 #define TEGRA186_IO_PAD_TABLE(_pad) \
3433 /* .id .dpd .voltage .name */ \
3434 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3435 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3436 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3437 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3438 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3439 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3440 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3441 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3442 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3443 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3444 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3445 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \
3446 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3447 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3448 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3449 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
3450 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3451 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3452 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3453 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \
3454 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
3455 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
3456 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \
3457 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \
3458 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \
3459 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
3460 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
3461 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
3462 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
3463 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
3464 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
3465 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \
3466 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
3467 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3468 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3469 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
3470 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3471 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3473 static const struct tegra_io_pad_soc tegra186_io_pads[] = {
3474 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD)
3477 static const struct pinctrl_pin_desc tegra186_pin_descs[] = {
3478 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3481 static const struct tegra_pmc_regs tegra186_pmc_regs = {
3486 .dpd2_status = 0x80,
3488 .rst_source_shift = 0x2,
3489 .rst_source_mask = 0x3c,
3490 .rst_level_shift = 0x0,
3491 .rst_level_mask = 0x3,
3494 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3495 struct device_node *np,
3498 struct resource regs;
3503 index = of_property_match_string(np, "reg-names", "wake");
3505 dev_err(pmc->dev, "failed to find PMC wake registers\n");
3509 of_address_to_resource(np, index, ®s);
3511 wake = ioremap(regs.start, resource_size(®s));
3513 dev_err(pmc->dev, "failed to map PMC wake registers\n");
3517 value = readl(wake + WAKE_AOWAKE_CTRL);
3520 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
3522 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
3524 writel(value, wake + WAKE_AOWAKE_CTRL);
3529 static const char * const tegra186_reset_sources[] = {
3547 static const char * const tegra186_reset_levels[] = {
3548 "L0", "L1", "L2", "WARM"
3551 static const struct tegra_wake_event tegra186_wake_events[] = {
3552 TEGRA_WAKE_IRQ("pmu", 24, 209),
3553 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
3554 TEGRA_WAKE_IRQ("rtc", 73, 10),
3557 static const struct tegra_pmc_soc tegra186_pmc_soc = {
3558 .num_powergates = 0,
3560 .num_cpu_powergates = 0,
3561 .cpu_powergates = NULL,
3562 .has_tsense_reset = false,
3563 .has_gpu_clamps = false,
3564 .needs_mbist_war = false,
3565 .has_impl_33v_pwr = true,
3566 .maybe_tz_only = false,
3567 .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
3568 .io_pads = tegra186_io_pads,
3569 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
3570 .pin_descs = tegra186_pin_descs,
3571 .regs = &tegra186_pmc_regs,
3573 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3574 .irq_set_wake = tegra186_pmc_irq_set_wake,
3575 .irq_set_type = tegra186_pmc_irq_set_type,
3576 .reset_sources = tegra186_reset_sources,
3577 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),
3578 .reset_levels = tegra186_reset_levels,
3579 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3580 .num_wake_events = ARRAY_SIZE(tegra186_wake_events),
3581 .wake_events = tegra186_wake_events,
3582 .pmc_clks_data = NULL,
3584 .has_blink_output = false,
3585 .has_usb_sleepwalk = false,
3588 #define TEGRA194_IO_PAD_TABLE(_pad) \
3589 /* .id .dpd .voltage .name */ \
3590 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3591 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3592 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3593 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3594 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3595 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3596 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3597 _pad(TEGRA_IO_PAD_EQOS, 8, UINT_MAX, "eqos"), \
3598 _pad(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, UINT_MAX, "pex-clk-2-bias"), \
3599 _pad(TEGRA_IO_PAD_PEX_CLK_2, 10, UINT_MAX, "pex-clk-2"), \
3600 _pad(TEGRA_IO_PAD_DAP3, 11, UINT_MAX, "dap3"), \
3601 _pad(TEGRA_IO_PAD_DAP5, 12, UINT_MAX, "dap5"), \
3602 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3603 _pad(TEGRA_IO_PAD_PWR_CTL, 15, UINT_MAX, "pwr-ctl"), \
3604 _pad(TEGRA_IO_PAD_SOC_GPIO53, 16, UINT_MAX, "soc-gpio53"), \
3605 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3606 _pad(TEGRA_IO_PAD_GP_PWM2, 18, UINT_MAX, "gp-pwm2"), \
3607 _pad(TEGRA_IO_PAD_GP_PWM3, 19, UINT_MAX, "gp-pwm3"), \
3608 _pad(TEGRA_IO_PAD_SOC_GPIO12, 20, UINT_MAX, "soc-gpio12"), \
3609 _pad(TEGRA_IO_PAD_SOC_GPIO13, 21, UINT_MAX, "soc-gpio13"), \
3610 _pad(TEGRA_IO_PAD_SOC_GPIO10, 22, UINT_MAX, "soc-gpio10"), \
3611 _pad(TEGRA_IO_PAD_UART4, 23, UINT_MAX, "uart4"), \
3612 _pad(TEGRA_IO_PAD_UART5, 24, UINT_MAX, "uart5"), \
3613 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
3614 _pad(TEGRA_IO_PAD_HDMI_DP3, 26, UINT_MAX, "hdmi-dp3"), \
3615 _pad(TEGRA_IO_PAD_HDMI_DP2, 27, UINT_MAX, "hdmi-dp2"), \
3616 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3617 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3618 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3619 _pad(TEGRA_IO_PAD_PEX_CTL2, 33, UINT_MAX, "pex-ctl2"), \
3620 _pad(TEGRA_IO_PAD_PEX_L0_RST_N, 34, UINT_MAX, "pex-l0-rst"), \
3621 _pad(TEGRA_IO_PAD_PEX_L1_RST_N, 35, UINT_MAX, "pex-l1-rst"), \
3622 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
3623 _pad(TEGRA_IO_PAD_PEX_L5_RST_N, 37, UINT_MAX, "pex-l5-rst"), \
3624 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
3625 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
3626 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
3627 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
3628 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
3629 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
3630 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
3631 _pad(TEGRA_IO_PAD_CSIG, 50, UINT_MAX, "csig"), \
3632 _pad(TEGRA_IO_PAD_CSIH, 51, UINT_MAX, "csih"), \
3633 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
3634 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3635 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3636 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
3637 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3638 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3640 static const struct tegra_io_pad_soc tegra194_io_pads[] = {
3641 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PAD)
3644 static const struct pinctrl_pin_desc tegra194_pin_descs[] = {
3645 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3648 static const struct tegra_pmc_regs tegra194_pmc_regs = {
3653 .dpd2_status = 0x80,
3655 .rst_source_shift = 0x2,
3656 .rst_source_mask = 0x7c,
3657 .rst_level_shift = 0x0,
3658 .rst_level_mask = 0x3,
3661 static const char * const tegra194_reset_sources[] = {
3685 static const struct tegra_wake_event tegra194_wake_events[] = {
3686 TEGRA_WAKE_IRQ("pmu", 24, 209),
3687 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)),
3688 TEGRA_WAKE_IRQ("rtc", 73, 10),
3691 static const struct tegra_pmc_soc tegra194_pmc_soc = {
3692 .num_powergates = 0,
3694 .num_cpu_powergates = 0,
3695 .cpu_powergates = NULL,
3696 .has_tsense_reset = false,
3697 .has_gpu_clamps = false,
3698 .needs_mbist_war = false,
3699 .has_impl_33v_pwr = true,
3700 .maybe_tz_only = false,
3701 .num_io_pads = ARRAY_SIZE(tegra194_io_pads),
3702 .io_pads = tegra194_io_pads,
3703 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs),
3704 .pin_descs = tegra194_pin_descs,
3705 .regs = &tegra194_pmc_regs,
3707 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3708 .irq_set_wake = tegra186_pmc_irq_set_wake,
3709 .irq_set_type = tegra186_pmc_irq_set_type,
3710 .reset_sources = tegra194_reset_sources,
3711 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources),
3712 .reset_levels = tegra186_reset_levels,
3713 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3714 .num_wake_events = ARRAY_SIZE(tegra194_wake_events),
3715 .wake_events = tegra194_wake_events,
3716 .pmc_clks_data = NULL,
3718 .has_blink_output = false,
3719 .has_usb_sleepwalk = false,
3722 static const struct tegra_pmc_regs tegra234_pmc_regs = {
3729 .rst_source_shift = 0x2,
3730 .rst_source_mask = 0xfc,
3731 .rst_level_shift = 0x0,
3732 .rst_level_mask = 0x3,
3735 static const char * const tegra234_reset_sources[] = {
3759 static const struct tegra_pmc_soc tegra234_pmc_soc = {
3760 .num_powergates = 0,
3762 .num_cpu_powergates = 0,
3763 .cpu_powergates = NULL,
3764 .has_tsense_reset = false,
3765 .has_gpu_clamps = false,
3766 .needs_mbist_war = false,
3767 .has_impl_33v_pwr = true,
3768 .maybe_tz_only = false,
3773 .regs = &tegra234_pmc_regs,
3775 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3776 .irq_set_wake = tegra186_pmc_irq_set_wake,
3777 .irq_set_type = tegra186_pmc_irq_set_type,
3778 .reset_sources = tegra234_reset_sources,
3779 .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources),
3780 .reset_levels = tegra186_reset_levels,
3781 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3782 .num_wake_events = 0,
3783 .wake_events = NULL,
3784 .pmc_clks_data = NULL,
3786 .has_blink_output = false,
3789 static const struct of_device_id tegra_pmc_match[] = {
3790 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
3791 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
3792 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
3793 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
3794 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
3795 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
3796 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
3797 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
3798 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
3802 static void tegra_pmc_sync_state(struct device *dev)
3807 * Older device-trees don't have core PD, and thus, there are
3808 * no dependencies that will block the state syncing. We shouldn't
3809 * mark the domain as synced in this case.
3811 if (!pmc->core_domain_registered)
3814 pmc->core_domain_state_synced = true;
3816 /* this is a no-op if core regulator isn't used */
3817 mutex_lock(&pmc->powergates_lock);
3818 err = dev_pm_opp_sync_regulators(dev);
3819 mutex_unlock(&pmc->powergates_lock);
3822 dev_err(dev, "failed to sync regulators: %d\n", err);
3825 static struct platform_driver tegra_pmc_driver = {
3827 .name = "tegra-pmc",
3828 .suppress_bind_attrs = true,
3829 .of_match_table = tegra_pmc_match,
3830 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
3831 .pm = &tegra_pmc_pm_ops,
3833 .sync_state = tegra_pmc_sync_state,
3835 .probe = tegra_pmc_probe,
3837 builtin_platform_driver(tegra_pmc_driver);
3839 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)
3843 saved = readl(pmc->base + pmc->soc->regs->scratch0);
3844 value = saved ^ 0xffffffff;
3846 if (value == 0xffffffff)
3849 /* write pattern and read it back */
3850 writel(value, pmc->base + pmc->soc->regs->scratch0);
3851 value = readl(pmc->base + pmc->soc->regs->scratch0);
3853 /* if we read all-zeroes, access is restricted to TZ only */
3855 pr_info("access to PMC is restricted to TZ\n");
3859 /* restore original value */
3860 writel(saved, pmc->base + pmc->soc->regs->scratch0);
3866 * Early initialization to allow access to registers in the very early boot
3869 static int __init tegra_pmc_early_init(void)
3871 const struct of_device_id *match;
3872 struct device_node *np;
3873 struct resource regs;
3877 mutex_init(&pmc->powergates_lock);
3879 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
3882 * Fall back to legacy initialization for 32-bit ARM only. All
3883 * 64-bit ARM device tree files for Tegra are required to have
3886 * This is for backwards-compatibility with old device trees
3887 * that didn't contain a PMC node. Note that in this case the
3888 * SoC data can't be matched and therefore powergating is
3891 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
3892 pr_warn("DT node not found, powergating disabled\n");
3894 regs.start = 0x7000e400;
3895 regs.end = 0x7000e7ff;
3896 regs.flags = IORESOURCE_MEM;
3898 pr_warn("Using memory region %pR\n", ®s);
3901 * At this point we're not running on Tegra, so play
3902 * nice with multi-platform kernels.
3908 * Extract information from the device tree if we've found a
3911 if (of_address_to_resource(np, 0, ®s) < 0) {
3912 pr_err("failed to get PMC registers\n");
3918 pmc->base = ioremap(regs.start, resource_size(®s));
3920 pr_err("failed to map PMC registers\n");
3926 pmc->soc = match->data;
3928 if (pmc->soc->maybe_tz_only)
3929 pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
3931 /* Create a bitmap of the available and valid partitions */
3932 for (i = 0; i < pmc->soc->num_powergates; i++)
3933 if (pmc->soc->powergates[i])
3934 set_bit(i, pmc->powergates_available);
3937 * Invert the interrupt polarity if a PMC device tree node
3938 * exists and contains the nvidia,invert-interrupt property.
3940 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
3942 pmc->soc->setup_irq_polarity(pmc, np, invert);
3949 early_initcall(tegra_pmc_early_init);