1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/soc/tegra/pmc.c
5 * Copyright (c) 2010 Google, Inc
6 * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
9 * Colin Cross <ccross@google.com>
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/clkdev.h>
18 #include <linux/clk/clk-conf.h>
19 #include <linux/clk/tegra.h>
20 #include <linux/debugfs.h>
21 #include <linux/delay.h>
22 #include <linux/device.h>
23 #include <linux/err.h>
24 #include <linux/export.h>
25 #include <linux/init.h>
27 #include <linux/iopoll.h>
28 #include <linux/irqdomain.h>
29 #include <linux/irq.h>
30 #include <linux/kernel.h>
31 #include <linux/of_address.h>
32 #include <linux/of_clk.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_platform.h>
36 #include <linux/pinctrl/pinconf-generic.h>
37 #include <linux/pinctrl/pinconf.h>
38 #include <linux/pinctrl/pinctrl.h>
39 #include <linux/platform_device.h>
40 #include <linux/pm_domain.h>
41 #include <linux/reboot.h>
42 #include <linux/regmap.h>
43 #include <linux/reset.h>
44 #include <linux/seq_file.h>
45 #include <linux/slab.h>
46 #include <linux/spinlock.h>
48 #include <soc/tegra/common.h>
49 #include <soc/tegra/fuse.h>
50 #include <soc/tegra/pmc.h>
52 #include <dt-bindings/interrupt-controller/arm-gic.h>
53 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
54 #include <dt-bindings/gpio/tegra186-gpio.h>
55 #include <dt-bindings/gpio/tegra194-gpio.h>
56 #include <dt-bindings/soc/tegra-pmc.h>
59 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
60 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
61 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
62 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
63 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
64 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
65 #define PMC_CNTRL_PWRREQ_POLARITY BIT(8)
66 #define PMC_CNTRL_BLINK_EN 7
67 #define PMC_CNTRL_MAIN_RST BIT(4)
69 #define PMC_WAKE_MASK 0x0c
70 #define PMC_WAKE_LEVEL 0x10
71 #define PMC_WAKE_STATUS 0x14
72 #define PMC_SW_WAKE_STATUS 0x18
73 #define PMC_DPD_PADS_ORIDE 0x1c
74 #define PMC_DPD_PADS_ORIDE_BLINK 20
76 #define DPD_SAMPLE 0x020
77 #define DPD_SAMPLE_ENABLE BIT(0)
78 #define DPD_SAMPLE_DISABLE (0 << 0)
80 #define PWRGATE_TOGGLE 0x30
81 #define PWRGATE_TOGGLE_START BIT(8)
83 #define REMOVE_CLAMPING 0x34
85 #define PWRGATE_STATUS 0x38
87 #define PMC_BLINK_TIMER 0x40
88 #define PMC_IMPL_E_33V_PWR 0x40
90 #define PMC_PWR_DET 0x48
92 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
93 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
94 #define PMC_SCRATCH0_MODE_RCM BIT(1)
95 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
96 PMC_SCRATCH0_MODE_BOOTLOADER | \
97 PMC_SCRATCH0_MODE_RCM)
99 #define PMC_CPUPWRGOOD_TIMER 0xc8
100 #define PMC_CPUPWROFF_TIMER 0xcc
101 #define PMC_COREPWRGOOD_TIMER 0x3c
102 #define PMC_COREPWROFF_TIMER 0xe0
104 #define PMC_PWR_DET_VALUE 0xe4
106 #define PMC_USB_DEBOUNCE_DEL 0xec
107 #define PMC_USB_AO 0xf0
109 #define PMC_SCRATCH41 0x140
111 #define PMC_WAKE2_MASK 0x160
112 #define PMC_WAKE2_LEVEL 0x164
113 #define PMC_WAKE2_STATUS 0x168
114 #define PMC_SW_WAKE2_STATUS 0x16c
116 #define PMC_CLK_OUT_CNTRL 0x1a8
117 #define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0)
118 #define PMC_SENSOR_CTRL 0x1b0
119 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
120 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
122 #define PMC_RST_STATUS_POR 0
123 #define PMC_RST_STATUS_WATCHDOG 1
124 #define PMC_RST_STATUS_SENSOR 2
125 #define PMC_RST_STATUS_SW_MAIN 3
126 #define PMC_RST_STATUS_LP0 4
127 #define PMC_RST_STATUS_AOTAG 5
129 #define IO_DPD_REQ 0x1b8
130 #define IO_DPD_REQ_CODE_IDLE (0U << 30)
131 #define IO_DPD_REQ_CODE_OFF (1U << 30)
132 #define IO_DPD_REQ_CODE_ON (2U << 30)
133 #define IO_DPD_REQ_CODE_MASK (3U << 30)
135 #define IO_DPD_STATUS 0x1bc
136 #define IO_DPD2_REQ 0x1c0
137 #define IO_DPD2_STATUS 0x1c4
138 #define SEL_DPD_TIM 0x1c8
140 #define PMC_UTMIP_UHSIC_TRIGGERS 0x1ec
141 #define PMC_UTMIP_UHSIC_SAVED_STATE 0x1f0
143 #define PMC_UTMIP_TERM_PAD_CFG 0x1f8
144 #define PMC_UTMIP_UHSIC_SLEEP_CFG 0x1fc
145 #define PMC_UTMIP_UHSIC_FAKE 0x218
147 #define PMC_SCRATCH54 0x258
148 #define PMC_SCRATCH54_DATA_SHIFT 8
149 #define PMC_SCRATCH54_ADDR_SHIFT 0
151 #define PMC_SCRATCH55 0x25c
152 #define PMC_SCRATCH55_RESET_TEGRA BIT(31)
153 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
154 #define PMC_SCRATCH55_PINMUX_SHIFT 24
155 #define PMC_SCRATCH55_16BITOP BIT(15)
156 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
157 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
159 #define PMC_UTMIP_UHSIC_LINE_WAKEUP 0x26c
161 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270
162 #define PMC_UTMIP_MASTER_CONFIG 0x274
163 #define PMC_UTMIP_UHSIC2_TRIGGERS 0x27c
164 #define PMC_UTMIP_MASTER2_CONFIG 0x29c
166 #define GPU_RG_CNTRL 0x2d4
168 #define PMC_UTMIP_PAD_CFG0 0x4c0
169 #define PMC_UTMIP_UHSIC_SLEEP_CFG1 0x4d0
170 #define PMC_UTMIP_SLEEPWALK_P3 0x4e0
171 /* Tegra186 and later */
172 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
173 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)
174 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))
175 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))
176 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))
177 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))
178 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
179 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
180 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
182 #define WAKE_AOWAKE_CTRL 0x4f4
183 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
186 #define TEGRA_SMC_PMC 0xc2fffe00
187 #define TEGRA_SMC_PMC_READ 0xaa
188 #define TEGRA_SMC_PMC_WRITE 0xbb
197 #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
199 struct pmc_clk_gate {
205 #define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
207 struct pmc_clk_init_data {
209 const char *const *parents;
216 static const char * const clk_out1_parents[] = { "osc", "osc_div2",
217 "osc_div4", "extern1",
220 static const char * const clk_out2_parents[] = { "osc", "osc_div2",
221 "osc_div4", "extern2",
224 static const char * const clk_out3_parents[] = { "osc", "osc_div2",
225 "osc_div4", "extern3",
228 static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
230 .name = "pmc_clk_out_1",
231 .parents = clk_out1_parents,
232 .num_parents = ARRAY_SIZE(clk_out1_parents),
233 .clk_id = TEGRA_PMC_CLK_OUT_1,
238 .name = "pmc_clk_out_2",
239 .parents = clk_out2_parents,
240 .num_parents = ARRAY_SIZE(clk_out2_parents),
241 .clk_id = TEGRA_PMC_CLK_OUT_2,
243 .force_en_shift = 10,
246 .name = "pmc_clk_out_3",
247 .parents = clk_out3_parents,
248 .num_parents = ARRAY_SIZE(clk_out3_parents),
249 .clk_id = TEGRA_PMC_CLK_OUT_3,
251 .force_en_shift = 18,
255 struct tegra_powergate {
256 struct generic_pm_domain genpd;
257 struct tegra_pmc *pmc;
260 unsigned int num_clks;
261 struct reset_control *reset;
264 struct tegra_io_pad_soc {
265 enum tegra_io_pad id;
267 unsigned int voltage;
271 struct tegra_pmc_regs {
272 unsigned int scratch0;
273 unsigned int dpd_req;
274 unsigned int dpd_status;
275 unsigned int dpd2_req;
276 unsigned int dpd2_status;
277 unsigned int rst_status;
278 unsigned int rst_source_shift;
279 unsigned int rst_source_mask;
280 unsigned int rst_level_shift;
281 unsigned int rst_level_mask;
284 struct tegra_wake_event {
289 unsigned int instance;
294 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \
300 .instance = UINT_MAX, \
305 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \
311 .instance = _instance, \
316 struct tegra_pmc_soc {
317 unsigned int num_powergates;
318 const char *const *powergates;
319 unsigned int num_cpu_powergates;
320 const u8 *cpu_powergates;
322 bool has_tsense_reset;
324 bool needs_mbist_war;
325 bool has_impl_33v_pwr;
328 const struct tegra_io_pad_soc *io_pads;
329 unsigned int num_io_pads;
331 const struct pinctrl_pin_desc *pin_descs;
332 unsigned int num_pin_descs;
334 const struct tegra_pmc_regs *regs;
335 void (*init)(struct tegra_pmc *pmc);
336 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
337 struct device_node *np,
339 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
340 int (*irq_set_type)(struct irq_data *data, unsigned int type);
342 const char * const *reset_sources;
343 unsigned int num_reset_sources;
344 const char * const *reset_levels;
345 unsigned int num_reset_levels;
348 * These describe events that can wake the system from sleep (i.e.
349 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2)
350 * are dealt with in the LIC.
352 const struct tegra_wake_event *wake_events;
353 unsigned int num_wake_events;
355 const struct pmc_clk_init_data *pmc_clks_data;
356 unsigned int num_pmc_clks;
357 bool has_blink_output;
358 bool has_usb_sleepwalk;
362 * struct tegra_pmc - NVIDIA Tegra PMC
363 * @dev: pointer to PMC device structure
364 * @base: pointer to I/O remapped register region
365 * @wake: pointer to I/O remapped region for WAKE registers
366 * @aotag: pointer to I/O remapped region for AOTAG registers
367 * @scratch: pointer to I/O remapped region for scratch registers
368 * @clk: pointer to pclk clock
369 * @soc: pointer to SoC data structure
370 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone
371 * @debugfs: pointer to debugfs entry
372 * @rate: currently configured rate of pclk
373 * @suspend_mode: lowest suspend mode available
374 * @cpu_good_time: CPU power good time (in microseconds)
375 * @cpu_off_time: CPU power off time (in microsecends)
376 * @core_osc_time: core power good OSC time (in microseconds)
377 * @core_pmu_time: core power good PMU time (in microseconds)
378 * @core_off_time: core power off time (in microseconds)
379 * @corereq_high: core power request is active-high
380 * @sysclkreq_high: system clock request is active-high
381 * @combined_req: combined power request for CPU & core
382 * @cpu_pwr_good_en: CPU power good signal is enabled
383 * @lp0_vec_phys: physical base address of the LP0 warm boot code
384 * @lp0_vec_size: size of the LP0 warm boot code
385 * @powergates_available: Bitmap of available power gates
386 * @powergates_lock: mutex for power gate register access
387 * @pctl_dev: pin controller exposed by the PMC
388 * @domain: IRQ domain provided by the PMC
389 * @irq: chip implementation for the IRQ domain
390 * @clk_nb: pclk clock changes handler
397 void __iomem *scratch;
399 struct dentry *debugfs;
401 const struct tegra_pmc_soc *soc;
406 enum tegra_suspend_mode suspend_mode;
415 bool cpu_pwr_good_en;
418 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
420 struct mutex powergates_lock;
422 struct pinctrl_dev *pctl_dev;
424 struct irq_domain *domain;
427 struct notifier_block clk_nb;
430 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
432 .suspend_mode = TEGRA_SUSPEND_NONE,
435 static inline struct tegra_powergate *
436 to_powergate(struct generic_pm_domain *domain)
438 return container_of(domain, struct tegra_powergate, genpd);
441 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
443 struct arm_smccc_res res;
446 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
450 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
453 pr_warn("%s(): SMC failed: %lu\n", __func__,
460 return readl(pmc->base + offset);
463 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
464 unsigned long offset)
466 struct arm_smccc_res res;
469 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
470 value, 0, 0, 0, 0, &res);
473 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
476 pr_warn("%s(): SMC failed: %lu\n", __func__,
480 writel(value, pmc->base + offset);
484 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)
487 return tegra_pmc_readl(pmc, offset);
489 return readl(pmc->scratch + offset);
492 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
493 unsigned long offset)
496 tegra_pmc_writel(pmc, value, offset);
498 writel(value, pmc->scratch + offset);
502 * TODO Figure out a way to call this with the struct tegra_pmc * passed in.
503 * This currently doesn't work because readx_poll_timeout() can only operate
504 * on functions that take a single argument.
506 static inline bool tegra_powergate_state(int id)
508 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
509 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;
511 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;
514 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id)
516 return (pmc->soc && pmc->soc->powergates[id]);
519 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id)
521 return test_bit(id, pmc->powergates_available);
524 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
528 if (!pmc || !pmc->soc || !name)
531 for (i = 0; i < pmc->soc->num_powergates; i++) {
532 if (!tegra_powergate_is_valid(pmc, i))
535 if (!strcmp(name, pmc->soc->powergates[i]))
543 * tegra_powergate_set() - set the state of a partition
544 * @pmc: power management controller
546 * @new_state: new state of the partition
548 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id,
554 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
557 mutex_lock(&pmc->powergates_lock);
559 if (tegra_powergate_state(id) == new_state) {
560 mutex_unlock(&pmc->powergates_lock);
564 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
566 err = readx_poll_timeout(tegra_powergate_state, id, status,
567 status == new_state, 10, 100000);
569 mutex_unlock(&pmc->powergates_lock);
574 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
579 mutex_lock(&pmc->powergates_lock);
582 * On Tegra124 and later, the clamps for the GPU are controlled by a
583 * separate register (with different semantics).
585 if (id == TEGRA_POWERGATE_3D) {
586 if (pmc->soc->has_gpu_clamps) {
587 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);
593 * Tegra 2 has a bug where PCIE and VDE clamping masks are
594 * swapped relatively to the partition ids
596 if (id == TEGRA_POWERGATE_VDEC)
597 mask = (1 << TEGRA_POWERGATE_PCIE);
598 else if (id == TEGRA_POWERGATE_PCIE)
599 mask = (1 << TEGRA_POWERGATE_VDEC);
603 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);
606 mutex_unlock(&pmc->powergates_lock);
611 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
615 for (i = 0; i < pg->num_clks; i++)
616 clk_disable_unprepare(pg->clks[i]);
619 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
624 for (i = 0; i < pg->num_clks; i++) {
625 err = clk_prepare_enable(pg->clks[i]);
634 clk_disable_unprepare(pg->clks[i]);
639 int __weak tegra210_clk_handle_mbist_war(unsigned int id)
644 static int tegra_powergate_power_up(struct tegra_powergate *pg,
649 err = reset_control_assert(pg->reset);
653 usleep_range(10, 20);
655 err = tegra_powergate_set(pg->pmc, pg->id, true);
659 usleep_range(10, 20);
661 err = tegra_powergate_enable_clocks(pg);
665 usleep_range(10, 20);
667 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
671 usleep_range(10, 20);
673 err = reset_control_deassert(pg->reset);
677 usleep_range(10, 20);
679 if (pg->pmc->soc->needs_mbist_war)
680 err = tegra210_clk_handle_mbist_war(pg->id);
685 tegra_powergate_disable_clocks(pg);
690 tegra_powergate_disable_clocks(pg);
691 usleep_range(10, 20);
694 tegra_powergate_set(pg->pmc, pg->id, false);
699 static int tegra_powergate_power_down(struct tegra_powergate *pg)
703 err = tegra_powergate_enable_clocks(pg);
707 usleep_range(10, 20);
709 err = reset_control_assert(pg->reset);
713 usleep_range(10, 20);
715 tegra_powergate_disable_clocks(pg);
717 usleep_range(10, 20);
719 err = tegra_powergate_set(pg->pmc, pg->id, false);
726 tegra_powergate_enable_clocks(pg);
727 usleep_range(10, 20);
728 reset_control_deassert(pg->reset);
729 usleep_range(10, 20);
732 tegra_powergate_disable_clocks(pg);
737 static int tegra_genpd_power_on(struct generic_pm_domain *domain)
739 struct tegra_powergate *pg = to_powergate(domain);
740 struct device *dev = pg->pmc->dev;
743 err = tegra_powergate_power_up(pg, true);
745 dev_err(dev, "failed to turn on PM domain %s: %d\n",
746 pg->genpd.name, err);
750 reset_control_release(pg->reset);
756 static int tegra_genpd_power_off(struct generic_pm_domain *domain)
758 struct tegra_powergate *pg = to_powergate(domain);
759 struct device *dev = pg->pmc->dev;
762 err = reset_control_acquire(pg->reset);
764 pr_err("failed to acquire resets: %d\n", err);
768 err = tegra_powergate_power_down(pg);
770 dev_err(dev, "failed to turn off PM domain %s: %d\n",
771 pg->genpd.name, err);
772 reset_control_release(pg->reset);
779 * tegra_powergate_power_on() - power on partition
782 int tegra_powergate_power_on(unsigned int id)
784 if (!tegra_powergate_is_available(pmc, id))
787 return tegra_powergate_set(pmc, id, true);
789 EXPORT_SYMBOL(tegra_powergate_power_on);
792 * tegra_powergate_power_off() - power off partition
795 int tegra_powergate_power_off(unsigned int id)
797 if (!tegra_powergate_is_available(pmc, id))
800 return tegra_powergate_set(pmc, id, false);
802 EXPORT_SYMBOL(tegra_powergate_power_off);
805 * tegra_powergate_is_powered() - check if partition is powered
806 * @pmc: power management controller
809 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id)
811 if (!tegra_powergate_is_valid(pmc, id))
814 return tegra_powergate_state(id);
818 * tegra_powergate_remove_clamping() - remove power clamps for partition
821 int tegra_powergate_remove_clamping(unsigned int id)
823 if (!tegra_powergate_is_available(pmc, id))
826 return __tegra_powergate_remove_clamping(pmc, id);
828 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
831 * tegra_powergate_sequence_power_up() - power up partition
833 * @clk: clock for partition
834 * @rst: reset for partition
836 * Must be called with clk disabled, and returns with clk enabled.
838 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
839 struct reset_control *rst)
841 struct tegra_powergate *pg;
844 if (!tegra_powergate_is_available(pmc, id))
847 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
857 err = tegra_powergate_power_up(pg, false);
859 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
866 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
869 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
870 * @pmc: power management controller
871 * @cpuid: CPU partition ID
873 * Returns the partition ID corresponding to the CPU partition ID or a
874 * negative error code on failure.
876 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc,
879 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
880 return pmc->soc->cpu_powergates[cpuid];
886 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
887 * @cpuid: CPU partition ID
889 bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
893 id = tegra_get_cpu_powergate_id(pmc, cpuid);
897 return tegra_powergate_is_powered(pmc, id);
901 * tegra_pmc_cpu_power_on() - power on CPU partition
902 * @cpuid: CPU partition ID
904 int tegra_pmc_cpu_power_on(unsigned int cpuid)
908 id = tegra_get_cpu_powergate_id(pmc, cpuid);
912 return tegra_powergate_set(pmc, id, true);
916 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
917 * @cpuid: CPU partition ID
919 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
923 id = tegra_get_cpu_powergate_id(pmc, cpuid);
927 return tegra_powergate_remove_clamping(id);
930 static int tegra_pmc_restart_notify(struct notifier_block *this,
931 unsigned long action, void *data)
933 const char *cmd = data;
936 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
937 value &= ~PMC_SCRATCH0_MODE_MASK;
940 if (strcmp(cmd, "recovery") == 0)
941 value |= PMC_SCRATCH0_MODE_RECOVERY;
943 if (strcmp(cmd, "bootloader") == 0)
944 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
946 if (strcmp(cmd, "forced-recovery") == 0)
947 value |= PMC_SCRATCH0_MODE_RCM;
950 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
952 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
953 value = tegra_pmc_readl(pmc, PMC_CNTRL);
954 value |= PMC_CNTRL_MAIN_RST;
955 tegra_pmc_writel(pmc, value, PMC_CNTRL);
960 static struct notifier_block tegra_pmc_restart_handler = {
961 .notifier_call = tegra_pmc_restart_notify,
965 static int powergate_show(struct seq_file *s, void *data)
970 seq_printf(s, " powergate powered\n");
971 seq_printf(s, "------------------\n");
973 for (i = 0; i < pmc->soc->num_powergates; i++) {
974 status = tegra_powergate_is_powered(pmc, i);
978 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
979 status ? "yes" : "no");
985 DEFINE_SHOW_ATTRIBUTE(powergate);
987 static int tegra_powergate_debugfs_init(void)
989 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
997 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
998 struct device_node *np)
1001 unsigned int i, count;
1004 count = of_clk_get_parent_count(np);
1008 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
1012 for (i = 0; i < count; i++) {
1013 pg->clks[i] = of_clk_get(np, i);
1014 if (IS_ERR(pg->clks[i])) {
1015 err = PTR_ERR(pg->clks[i]);
1020 pg->num_clks = count;
1026 clk_put(pg->clks[i]);
1033 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
1034 struct device_node *np, bool off)
1036 struct device *dev = pg->pmc->dev;
1039 pg->reset = of_reset_control_array_get_exclusive_released(np);
1040 if (IS_ERR(pg->reset)) {
1041 err = PTR_ERR(pg->reset);
1042 dev_err(dev, "failed to get device resets: %d\n", err);
1046 err = reset_control_acquire(pg->reset);
1048 pr_err("failed to acquire resets: %d\n", err);
1053 err = reset_control_assert(pg->reset);
1055 err = reset_control_deassert(pg->reset);
1059 reset_control_release(pg->reset);
1064 reset_control_release(pg->reset);
1065 reset_control_put(pg->reset);
1071 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
1073 struct device *dev = pmc->dev;
1074 struct tegra_powergate *pg;
1078 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
1082 id = tegra_powergate_lookup(pmc, np->name);
1084 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id);
1090 * Clear the bit for this powergate so it cannot be managed
1091 * directly via the legacy APIs for controlling powergates.
1093 clear_bit(id, pmc->powergates_available);
1096 pg->genpd.name = np->name;
1097 pg->genpd.power_off = tegra_genpd_power_off;
1098 pg->genpd.power_on = tegra_genpd_power_on;
1101 off = !tegra_powergate_is_powered(pmc, pg->id);
1103 err = tegra_powergate_of_get_clks(pg, np);
1105 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err);
1109 err = tegra_powergate_of_get_resets(pg, np, off);
1111 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err);
1115 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
1117 WARN_ON(tegra_powergate_power_up(pg, true));
1122 err = pm_genpd_init(&pg->genpd, NULL, off);
1124 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np,
1129 err = of_genpd_add_provider_simple(np, &pg->genpd);
1131 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n",
1136 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name);
1141 pm_genpd_remove(&pg->genpd);
1144 reset_control_put(pg->reset);
1147 while (pg->num_clks--)
1148 clk_put(pg->clks[pg->num_clks]);
1153 set_bit(id, pmc->powergates_available);
1161 static int tegra_powergate_init(struct tegra_pmc *pmc,
1162 struct device_node *parent)
1164 struct device_node *np, *child;
1167 np = of_get_child_by_name(parent, "powergates");
1171 for_each_child_of_node(np, child) {
1172 err = tegra_powergate_add(pmc, child);
1184 static void tegra_powergate_remove(struct generic_pm_domain *genpd)
1186 struct tegra_powergate *pg = to_powergate(genpd);
1188 reset_control_put(pg->reset);
1190 while (pg->num_clks--)
1191 clk_put(pg->clks[pg->num_clks]);
1195 set_bit(pg->id, pmc->powergates_available);
1200 static void tegra_powergate_remove_all(struct device_node *parent)
1202 struct generic_pm_domain *genpd;
1203 struct device_node *np, *child;
1205 np = of_get_child_by_name(parent, "powergates");
1209 for_each_child_of_node(np, child) {
1210 of_genpd_del_provider(child);
1212 genpd = of_genpd_remove_last(child);
1216 tegra_powergate_remove(genpd);
1222 static const struct tegra_io_pad_soc *
1223 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
1227 for (i = 0; i < pmc->soc->num_io_pads; i++)
1228 if (pmc->soc->io_pads[i].id == id)
1229 return &pmc->soc->io_pads[i];
1234 static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc,
1235 enum tegra_io_pad id,
1236 unsigned long *request,
1237 unsigned long *status,
1240 const struct tegra_io_pad_soc *pad;
1242 pad = tegra_io_pad_find(pmc, id);
1244 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1248 if (pad->dpd == UINT_MAX)
1251 *mask = BIT(pad->dpd % 32);
1253 if (pad->dpd < 32) {
1254 *status = pmc->soc->regs->dpd_status;
1255 *request = pmc->soc->regs->dpd_req;
1257 *status = pmc->soc->regs->dpd2_status;
1258 *request = pmc->soc->regs->dpd2_req;
1264 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id,
1265 unsigned long *request, unsigned long *status,
1268 unsigned long rate, value;
1271 err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask);
1278 dev_err(pmc->dev, "failed to get clock rate\n");
1282 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);
1284 /* must be at least 200 ns, in APB (PCLK) clock cycles */
1285 value = DIV_ROUND_UP(1000000000, rate);
1286 value = DIV_ROUND_UP(200, value);
1287 tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
1293 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset,
1294 u32 mask, u32 val, unsigned long timeout)
1298 timeout = jiffies + msecs_to_jiffies(timeout);
1300 while (time_after(timeout, jiffies)) {
1301 value = tegra_pmc_readl(pmc, offset);
1302 if ((value & mask) == val)
1305 usleep_range(250, 1000);
1311 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)
1314 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);
1318 * tegra_io_pad_power_enable() - enable power to I/O pad
1319 * @id: Tegra I/O pad ID for which to enable power
1321 * Returns: 0 on success or a negative error code on failure.
1323 int tegra_io_pad_power_enable(enum tegra_io_pad id)
1325 unsigned long request, status;
1329 mutex_lock(&pmc->powergates_lock);
1331 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1333 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1337 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);
1339 err = tegra_io_pad_poll(pmc, status, mask, 0, 250);
1341 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err);
1345 tegra_io_pad_unprepare(pmc);
1348 mutex_unlock(&pmc->powergates_lock);
1351 EXPORT_SYMBOL(tegra_io_pad_power_enable);
1354 * tegra_io_pad_power_disable() - disable power to I/O pad
1355 * @id: Tegra I/O pad ID for which to disable power
1357 * Returns: 0 on success or a negative error code on failure.
1359 int tegra_io_pad_power_disable(enum tegra_io_pad id)
1361 unsigned long request, status;
1365 mutex_lock(&pmc->powergates_lock);
1367 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1369 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1373 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);
1375 err = tegra_io_pad_poll(pmc, status, mask, mask, 250);
1377 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err);
1381 tegra_io_pad_unprepare(pmc);
1384 mutex_unlock(&pmc->powergates_lock);
1387 EXPORT_SYMBOL(tegra_io_pad_power_disable);
1389 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)
1391 unsigned long request, status;
1395 err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status,
1400 value = tegra_pmc_readl(pmc, status);
1402 return !(value & mask);
1405 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,
1408 const struct tegra_io_pad_soc *pad;
1411 pad = tegra_io_pad_find(pmc, id);
1415 if (pad->voltage == UINT_MAX)
1418 mutex_lock(&pmc->powergates_lock);
1420 if (pmc->soc->has_impl_33v_pwr) {
1421 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1423 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1424 value &= ~BIT(pad->voltage);
1426 value |= BIT(pad->voltage);
1428 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
1430 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1431 value = tegra_pmc_readl(pmc, PMC_PWR_DET);
1432 value |= BIT(pad->voltage);
1433 tegra_pmc_writel(pmc, value, PMC_PWR_DET);
1435 /* update I/O voltage */
1436 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1438 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1439 value &= ~BIT(pad->voltage);
1441 value |= BIT(pad->voltage);
1443 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
1446 mutex_unlock(&pmc->powergates_lock);
1448 usleep_range(100, 250);
1453 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)
1455 const struct tegra_io_pad_soc *pad;
1458 pad = tegra_io_pad_find(pmc, id);
1462 if (pad->voltage == UINT_MAX)
1465 if (pmc->soc->has_impl_33v_pwr)
1466 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1468 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1470 if ((value & BIT(pad->voltage)) == 0)
1471 return TEGRA_IO_PAD_VOLTAGE_1V8;
1473 return TEGRA_IO_PAD_VOLTAGE_3V3;
1477 * tegra_io_rail_power_on() - enable power to I/O rail
1478 * @id: Tegra I/O pad ID for which to enable power
1480 * See also: tegra_io_pad_power_enable()
1482 int tegra_io_rail_power_on(unsigned int id)
1484 return tegra_io_pad_power_enable(id);
1486 EXPORT_SYMBOL(tegra_io_rail_power_on);
1489 * tegra_io_rail_power_off() - disable power to I/O rail
1490 * @id: Tegra I/O pad ID for which to disable power
1492 * See also: tegra_io_pad_power_disable()
1494 int tegra_io_rail_power_off(unsigned int id)
1496 return tegra_io_pad_power_disable(id);
1498 EXPORT_SYMBOL(tegra_io_rail_power_off);
1500 #ifdef CONFIG_PM_SLEEP
1501 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1503 return pmc->suspend_mode;
1506 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1508 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1511 pmc->suspend_mode = mode;
1514 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1516 unsigned long long rate = 0;
1521 case TEGRA_SUSPEND_LP1:
1525 case TEGRA_SUSPEND_LP2:
1533 if (WARN_ON_ONCE(rate == 0))
1536 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1537 do_div(ticks, USEC_PER_SEC);
1538 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
1540 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1541 do_div(ticks, USEC_PER_SEC);
1542 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
1544 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1545 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1546 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1547 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1551 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1553 u32 value, values[2];
1555 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1559 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1563 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1567 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1571 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1576 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1578 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1579 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1581 pmc->cpu_good_time = value;
1583 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1584 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1586 pmc->cpu_off_time = value;
1588 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1589 values, ARRAY_SIZE(values)))
1590 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1592 pmc->core_osc_time = values[0];
1593 pmc->core_pmu_time = values[1];
1595 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1596 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1598 pmc->core_off_time = value;
1600 pmc->corereq_high = of_property_read_bool(np,
1601 "nvidia,core-power-req-active-high");
1603 pmc->sysclkreq_high = of_property_read_bool(np,
1604 "nvidia,sys-clock-req-active-high");
1606 pmc->combined_req = of_property_read_bool(np,
1607 "nvidia,combined-power-req");
1609 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1610 "nvidia,cpu-pwr-good-en");
1612 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1613 ARRAY_SIZE(values)))
1614 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1615 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1617 pmc->lp0_vec_phys = values[0];
1618 pmc->lp0_vec_size = values[1];
1623 static void tegra_pmc_init(struct tegra_pmc *pmc)
1626 pmc->soc->init(pmc);
1629 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1631 static const char disabled[] = "emergency thermal reset disabled";
1632 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1633 struct device *dev = pmc->dev;
1634 struct device_node *np;
1635 u32 value, checksum;
1637 if (!pmc->soc->has_tsense_reset)
1640 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
1642 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1646 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1647 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1651 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1652 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1656 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) {
1657 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1661 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) {
1662 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1666 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1669 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1670 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1671 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1673 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1674 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1675 tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
1677 value = PMC_SCRATCH55_RESET_TEGRA;
1678 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1679 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1680 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1683 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
1684 * contain the checksum and are currently zero, so they are not added.
1686 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1687 + ((value >> 24) & 0xff);
1689 checksum = 0x100 - checksum;
1691 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1693 tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
1695 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1696 value |= PMC_SENSOR_CTRL_ENABLE_RST;
1697 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1699 dev_info(pmc->dev, "emergency thermal reset enabled\n");
1705 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev)
1707 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1709 return pmc->soc->num_io_pads;
1712 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl,
1715 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl);
1717 return pmc->soc->io_pads[group].name;
1720 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev,
1722 const unsigned int **pins,
1723 unsigned int *num_pins)
1725 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1727 *pins = &pmc->soc->io_pads[group].id;
1733 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = {
1734 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count,
1735 .get_group_name = tegra_io_pad_pinctrl_get_group_name,
1736 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins,
1737 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1738 .dt_free_map = pinconf_generic_dt_free_map,
1741 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev,
1742 unsigned int pin, unsigned long *config)
1744 enum pin_config_param param = pinconf_to_config_param(*config);
1745 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1746 const struct tegra_io_pad_soc *pad;
1750 pad = tegra_io_pad_find(pmc, pin);
1755 case PIN_CONFIG_POWER_SOURCE:
1756 ret = tegra_io_pad_get_voltage(pmc, pad->id);
1763 case PIN_CONFIG_LOW_POWER_MODE:
1764 ret = tegra_io_pad_is_powered(pmc, pad->id);
1775 *config = pinconf_to_config_packed(param, arg);
1780 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev,
1781 unsigned int pin, unsigned long *configs,
1782 unsigned int num_configs)
1784 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1785 const struct tegra_io_pad_soc *pad;
1786 enum pin_config_param param;
1791 pad = tegra_io_pad_find(pmc, pin);
1795 for (i = 0; i < num_configs; ++i) {
1796 param = pinconf_to_config_param(configs[i]);
1797 arg = pinconf_to_config_argument(configs[i]);
1800 case PIN_CONFIG_LOW_POWER_MODE:
1802 err = tegra_io_pad_power_disable(pad->id);
1804 err = tegra_io_pad_power_enable(pad->id);
1808 case PIN_CONFIG_POWER_SOURCE:
1809 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 &&
1810 arg != TEGRA_IO_PAD_VOLTAGE_3V3)
1812 err = tegra_io_pad_set_voltage(pmc, pad->id, arg);
1824 static const struct pinconf_ops tegra_io_pad_pinconf_ops = {
1825 .pin_config_get = tegra_io_pad_pinconf_get,
1826 .pin_config_set = tegra_io_pad_pinconf_set,
1830 static struct pinctrl_desc tegra_pmc_pctl_desc = {
1831 .pctlops = &tegra_io_pad_pinctrl_ops,
1832 .confops = &tegra_io_pad_pinconf_ops,
1835 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
1839 if (!pmc->soc->num_pin_descs)
1842 tegra_pmc_pctl_desc.name = dev_name(pmc->dev);
1843 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs;
1844 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs;
1846 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc,
1848 if (IS_ERR(pmc->pctl_dev)) {
1849 err = PTR_ERR(pmc->pctl_dev);
1850 dev_err(pmc->dev, "failed to register pin controller: %d\n",
1858 static ssize_t reset_reason_show(struct device *dev,
1859 struct device_attribute *attr, char *buf)
1863 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
1864 value &= pmc->soc->regs->rst_source_mask;
1865 value >>= pmc->soc->regs->rst_source_shift;
1867 if (WARN_ON(value >= pmc->soc->num_reset_sources))
1868 return sprintf(buf, "%s\n", "UNKNOWN");
1870 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
1873 static DEVICE_ATTR_RO(reset_reason);
1875 static ssize_t reset_level_show(struct device *dev,
1876 struct device_attribute *attr, char *buf)
1880 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
1881 value &= pmc->soc->regs->rst_level_mask;
1882 value >>= pmc->soc->regs->rst_level_shift;
1884 if (WARN_ON(value >= pmc->soc->num_reset_levels))
1885 return sprintf(buf, "%s\n", "UNKNOWN");
1887 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
1890 static DEVICE_ATTR_RO(reset_level);
1892 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
1894 struct device *dev = pmc->dev;
1897 if (pmc->soc->reset_sources) {
1898 err = device_create_file(dev, &dev_attr_reset_reason);
1901 "failed to create attr \"reset_reason\": %d\n",
1905 if (pmc->soc->reset_levels) {
1906 err = device_create_file(dev, &dev_attr_reset_level);
1909 "failed to create attr \"reset_level\": %d\n",
1914 static int tegra_pmc_irq_translate(struct irq_domain *domain,
1915 struct irq_fwspec *fwspec,
1916 unsigned long *hwirq,
1919 if (WARN_ON(fwspec->param_count < 2))
1922 *hwirq = fwspec->param[0];
1923 *type = fwspec->param[1];
1928 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq,
1929 unsigned int num_irqs, void *data)
1931 struct tegra_pmc *pmc = domain->host_data;
1932 const struct tegra_pmc_soc *soc = pmc->soc;
1933 struct irq_fwspec *fwspec = data;
1937 if (WARN_ON(num_irqs > 1))
1940 for (i = 0; i < soc->num_wake_events; i++) {
1941 const struct tegra_wake_event *event = &soc->wake_events[i];
1943 if (fwspec->param_count == 2) {
1944 struct irq_fwspec spec;
1946 if (event->id != fwspec->param[0])
1949 err = irq_domain_set_hwirq_and_chip(domain, virq,
1955 spec.fwnode = &pmc->dev->of_node->fwnode;
1956 spec.param_count = 3;
1957 spec.param[0] = GIC_SPI;
1958 spec.param[1] = event->irq;
1959 spec.param[2] = fwspec->param[1];
1961 err = irq_domain_alloc_irqs_parent(domain, virq,
1967 if (fwspec->param_count == 3) {
1968 if (event->gpio.instance != fwspec->param[0] ||
1969 event->gpio.pin != fwspec->param[1])
1972 err = irq_domain_set_hwirq_and_chip(domain, virq,
1976 /* GPIO hierarchies stop at the PMC level */
1977 if (!err && domain->parent)
1978 err = irq_domain_disconnect_hierarchy(domain->parent,
1984 /* If there is no wake-up event, there is no PMC mapping */
1985 if (i == soc->num_wake_events)
1986 err = irq_domain_disconnect_hierarchy(domain, virq);
1991 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {
1992 .translate = tegra_pmc_irq_translate,
1993 .alloc = tegra_pmc_irq_alloc,
1996 static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
1998 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
1999 unsigned int offset, bit;
2002 offset = data->hwirq / 32;
2003 bit = data->hwirq % 32;
2005 /* clear wake status */
2006 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);
2007 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);
2009 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);
2010 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);
2012 /* enable PMC wake */
2013 if (data->hwirq >= 32)
2014 offset = PMC_WAKE2_MASK;
2016 offset = PMC_WAKE_MASK;
2018 value = tegra_pmc_readl(pmc, offset);
2025 tegra_pmc_writel(pmc, value, offset);
2030 static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2032 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2033 unsigned int offset, bit;
2036 offset = data->hwirq / 32;
2037 bit = data->hwirq % 32;
2039 if (data->hwirq >= 32)
2040 offset = PMC_WAKE2_LEVEL;
2042 offset = PMC_WAKE_LEVEL;
2044 value = tegra_pmc_readl(pmc, offset);
2047 case IRQ_TYPE_EDGE_RISING:
2048 case IRQ_TYPE_LEVEL_HIGH:
2052 case IRQ_TYPE_EDGE_FALLING:
2053 case IRQ_TYPE_LEVEL_LOW:
2057 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2065 tegra_pmc_writel(pmc, value, offset);
2070 static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2072 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2073 unsigned int offset, bit;
2076 offset = data->hwirq / 32;
2077 bit = data->hwirq % 32;
2079 /* clear wake status */
2080 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
2082 /* route wake to tier 2 */
2083 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2086 value &= ~(1 << bit);
2090 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2092 /* enable wakeup event */
2093 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
2098 static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2100 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2103 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2106 case IRQ_TYPE_EDGE_RISING:
2107 case IRQ_TYPE_LEVEL_HIGH:
2108 value |= WAKE_AOWAKE_CNTRL_LEVEL;
2111 case IRQ_TYPE_EDGE_FALLING:
2112 case IRQ_TYPE_LEVEL_LOW:
2113 value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
2116 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2117 value ^= WAKE_AOWAKE_CNTRL_LEVEL;
2124 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2129 static void tegra_irq_mask_parent(struct irq_data *data)
2131 if (data->parent_data)
2132 irq_chip_mask_parent(data);
2135 static void tegra_irq_unmask_parent(struct irq_data *data)
2137 if (data->parent_data)
2138 irq_chip_unmask_parent(data);
2141 static void tegra_irq_eoi_parent(struct irq_data *data)
2143 if (data->parent_data)
2144 irq_chip_eoi_parent(data);
2147 static int tegra_irq_set_affinity_parent(struct irq_data *data,
2148 const struct cpumask *dest,
2151 if (data->parent_data)
2152 return irq_chip_set_affinity_parent(data, dest, force);
2157 static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
2159 struct irq_domain *parent = NULL;
2160 struct device_node *np;
2162 np = of_irq_find_parent(pmc->dev->of_node);
2164 parent = irq_find_host(np);
2171 pmc->irq.name = dev_name(pmc->dev);
2172 pmc->irq.irq_mask = tegra_irq_mask_parent;
2173 pmc->irq.irq_unmask = tegra_irq_unmask_parent;
2174 pmc->irq.irq_eoi = tegra_irq_eoi_parent;
2175 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent;
2176 pmc->irq.irq_set_type = pmc->soc->irq_set_type;
2177 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake;
2179 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,
2180 &tegra_pmc_irq_domain_ops, pmc);
2182 dev_err(pmc->dev, "failed to allocate domain\n");
2189 static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
2190 unsigned long action, void *ptr)
2192 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb);
2193 struct clk_notifier_data *data = ptr;
2196 case PRE_RATE_CHANGE:
2197 mutex_lock(&pmc->powergates_lock);
2200 case POST_RATE_CHANGE:
2201 pmc->rate = data->new_rate;
2204 case ABORT_RATE_CHANGE:
2205 mutex_unlock(&pmc->powergates_lock);
2210 return notifier_from_errno(-EINVAL);
2216 static void pmc_clk_fence_udelay(u32 offset)
2218 tegra_pmc_readl(pmc, offset);
2219 /* pmc clk propagation delay 2 us */
2223 static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
2225 struct pmc_clk *clk = to_pmc_clk(hw);
2228 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
2229 val &= PMC_CLK_OUT_MUX_MASK;
2234 static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
2236 struct pmc_clk *clk = to_pmc_clk(hw);
2239 val = tegra_pmc_readl(pmc, clk->offs);
2240 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift);
2241 val |= index << clk->mux_shift;
2242 tegra_pmc_writel(pmc, val, clk->offs);
2243 pmc_clk_fence_udelay(clk->offs);
2248 static int pmc_clk_is_enabled(struct clk_hw *hw)
2250 struct pmc_clk *clk = to_pmc_clk(hw);
2253 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift);
2258 static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
2262 val = tegra_pmc_readl(pmc, offs);
2263 val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
2264 tegra_pmc_writel(pmc, val, offs);
2265 pmc_clk_fence_udelay(offs);
2268 static int pmc_clk_enable(struct clk_hw *hw)
2270 struct pmc_clk *clk = to_pmc_clk(hw);
2272 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1);
2277 static void pmc_clk_disable(struct clk_hw *hw)
2279 struct pmc_clk *clk = to_pmc_clk(hw);
2281 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0);
2284 static const struct clk_ops pmc_clk_ops = {
2285 .get_parent = pmc_clk_mux_get_parent,
2286 .set_parent = pmc_clk_mux_set_parent,
2287 .determine_rate = __clk_mux_determine_rate,
2288 .is_enabled = pmc_clk_is_enabled,
2289 .enable = pmc_clk_enable,
2290 .disable = pmc_clk_disable,
2294 tegra_pmc_clk_out_register(struct tegra_pmc *pmc,
2295 const struct pmc_clk_init_data *data,
2296 unsigned long offset)
2298 struct clk_init_data init;
2299 struct pmc_clk *pmc_clk;
2301 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL);
2303 return ERR_PTR(-ENOMEM);
2305 init.name = data->name;
2306 init.ops = &pmc_clk_ops;
2307 init.parent_names = data->parents;
2308 init.num_parents = data->num_parents;
2309 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
2310 CLK_SET_PARENT_GATE;
2312 pmc_clk->hw.init = &init;
2313 pmc_clk->offs = offset;
2314 pmc_clk->mux_shift = data->mux_shift;
2315 pmc_clk->force_en_shift = data->force_en_shift;
2317 return clk_register(NULL, &pmc_clk->hw);
2320 static int pmc_clk_gate_is_enabled(struct clk_hw *hw)
2322 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2324 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
2327 static int pmc_clk_gate_enable(struct clk_hw *hw)
2329 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2331 pmc_clk_set_state(gate->offs, gate->shift, 1);
2336 static void pmc_clk_gate_disable(struct clk_hw *hw)
2338 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2340 pmc_clk_set_state(gate->offs, gate->shift, 0);
2343 static const struct clk_ops pmc_clk_gate_ops = {
2344 .is_enabled = pmc_clk_gate_is_enabled,
2345 .enable = pmc_clk_gate_enable,
2346 .disable = pmc_clk_gate_disable,
2350 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name,
2351 const char *parent_name, unsigned long offset,
2354 struct clk_init_data init;
2355 struct pmc_clk_gate *gate;
2357 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL);
2359 return ERR_PTR(-ENOMEM);
2362 init.ops = &pmc_clk_gate_ops;
2363 init.parent_names = &parent_name;
2364 init.num_parents = 1;
2367 gate->hw.init = &init;
2368 gate->offs = offset;
2369 gate->shift = shift;
2371 return clk_register(NULL, &gate->hw);
2374 static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
2375 struct device_node *np)
2378 struct clk_onecell_data *clk_data;
2379 unsigned int num_clks;
2382 num_clks = pmc->soc->num_pmc_clks;
2383 if (pmc->soc->has_blink_output)
2389 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL);
2393 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX,
2394 sizeof(*clk_data->clks), GFP_KERNEL);
2395 if (!clk_data->clks)
2398 clk_data->clk_num = TEGRA_PMC_CLK_MAX;
2400 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
2401 clk_data->clks[i] = ERR_PTR(-ENOENT);
2403 for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
2404 const struct pmc_clk_init_data *data;
2406 data = pmc->soc->pmc_clks_data + i;
2408 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL);
2410 dev_warn(pmc->dev, "unable to register clock %s: %d\n",
2411 data->name, PTR_ERR_OR_ZERO(clk));
2415 err = clk_register_clkdev(clk, data->name, NULL);
2418 "unable to register %s clock lookup: %d\n",
2423 clk_data->clks[data->clk_id] = clk;
2426 if (pmc->soc->has_blink_output) {
2427 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER);
2428 clk = tegra_pmc_clk_gate_register(pmc,
2429 "pmc_blink_override",
2432 PMC_DPD_PADS_ORIDE_BLINK);
2435 "unable to register pmc_blink_override: %d\n",
2436 PTR_ERR_OR_ZERO(clk));
2440 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink",
2441 "pmc_blink_override",
2443 PMC_CNTRL_BLINK_EN);
2446 "unable to register pmc_blink: %d\n",
2447 PTR_ERR_OR_ZERO(clk));
2451 err = clk_register_clkdev(clk, "pmc_blink", NULL);
2454 "unable to register pmc_blink lookup: %d\n",
2459 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk;
2462 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
2464 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n",
2468 static const struct regmap_range pmc_usb_sleepwalk_ranges[] = {
2469 regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO),
2470 regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE),
2471 regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE),
2472 regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP, PMC_UTMIP_UHSIC_LINE_WAKEUP),
2473 regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG),
2474 regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG),
2475 regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1),
2476 regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3),
2479 static const struct regmap_access_table pmc_usb_sleepwalk_table = {
2480 .yes_ranges = pmc_usb_sleepwalk_ranges,
2481 .n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges),
2484 static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value)
2486 struct tegra_pmc *pmc = context;
2488 *value = tegra_pmc_readl(pmc, offset);
2492 static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value)
2494 struct tegra_pmc *pmc = context;
2496 tegra_pmc_writel(pmc, value, offset);
2500 static const struct regmap_config usb_sleepwalk_regmap_config = {
2501 .name = "usb_sleepwalk",
2506 .rd_table = &pmc_usb_sleepwalk_table,
2507 .wr_table = &pmc_usb_sleepwalk_table,
2508 .reg_read = tegra_pmc_regmap_readl,
2509 .reg_write = tegra_pmc_regmap_writel,
2512 static int tegra_pmc_regmap_init(struct tegra_pmc *pmc)
2514 struct regmap *regmap;
2517 if (pmc->soc->has_usb_sleepwalk) {
2518 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config);
2519 if (IS_ERR(regmap)) {
2520 err = PTR_ERR(regmap);
2521 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err);
2529 static int tegra_pmc_probe(struct platform_device *pdev)
2532 struct resource *res;
2536 * Early initialisation should have configured an initial
2537 * register mapping and setup the soc data pointer. If these
2538 * are not valid then something went badly wrong!
2540 if (WARN_ON(!pmc->base || !pmc->soc))
2543 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
2547 /* take over the memory region from the early initialization */
2548 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2549 base = devm_ioremap_resource(&pdev->dev, res);
2551 return PTR_ERR(base);
2553 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
2555 pmc->wake = devm_ioremap_resource(&pdev->dev, res);
2556 if (IS_ERR(pmc->wake))
2557 return PTR_ERR(pmc->wake);
2562 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
2564 pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
2565 if (IS_ERR(pmc->aotag))
2566 return PTR_ERR(pmc->aotag);
2571 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
2573 pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
2574 if (IS_ERR(pmc->scratch))
2575 return PTR_ERR(pmc->scratch);
2577 pmc->scratch = base;
2580 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
2581 if (IS_ERR(pmc->clk)) {
2582 err = PTR_ERR(pmc->clk);
2584 if (err != -ENOENT) {
2585 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
2593 * PCLK clock rate can't be retrieved using CLK API because it
2594 * causes lockup if CPU enters LP2 idle state from some other
2595 * CLK notifier, hence we're caching the rate's value locally.
2598 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb;
2599 err = clk_notifier_register(pmc->clk, &pmc->clk_nb);
2602 "failed to register clk notifier\n");
2606 pmc->rate = clk_get_rate(pmc->clk);
2609 pmc->dev = &pdev->dev;
2611 tegra_pmc_init(pmc);
2613 tegra_pmc_init_tsense_reset(pmc);
2615 tegra_pmc_reset_sysfs_init(pmc);
2617 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2618 err = tegra_powergate_debugfs_init();
2623 err = register_restart_handler(&tegra_pmc_restart_handler);
2625 dev_err(&pdev->dev, "unable to register restart handler, %d\n",
2627 goto cleanup_debugfs;
2630 err = tegra_pmc_pinctrl_init(pmc);
2632 goto cleanup_restart_handler;
2634 err = tegra_pmc_regmap_init(pmc);
2636 goto cleanup_restart_handler;
2638 err = tegra_powergate_init(pmc, pdev->dev.of_node);
2640 goto cleanup_powergates;
2642 err = tegra_pmc_irq_init(pmc);
2644 goto cleanup_powergates;
2646 mutex_lock(&pmc->powergates_lock);
2649 mutex_unlock(&pmc->powergates_lock);
2651 tegra_pmc_clock_register(pmc, pdev->dev.of_node);
2652 platform_set_drvdata(pdev, pmc);
2657 tegra_powergate_remove_all(pdev->dev.of_node);
2658 cleanup_restart_handler:
2659 unregister_restart_handler(&tegra_pmc_restart_handler);
2661 debugfs_remove(pmc->debugfs);
2663 device_remove_file(&pdev->dev, &dev_attr_reset_reason);
2664 device_remove_file(&pdev->dev, &dev_attr_reset_level);
2665 clk_notifier_unregister(pmc->clk, &pmc->clk_nb);
2670 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
2671 static int tegra_pmc_suspend(struct device *dev)
2673 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2675 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);
2680 static int tegra_pmc_resume(struct device *dev)
2682 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2684 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);
2689 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
2693 static const char * const tegra20_powergates[] = {
2694 [TEGRA_POWERGATE_CPU] = "cpu",
2695 [TEGRA_POWERGATE_3D] = "3d",
2696 [TEGRA_POWERGATE_VENC] = "venc",
2697 [TEGRA_POWERGATE_VDEC] = "vdec",
2698 [TEGRA_POWERGATE_PCIE] = "pcie",
2699 [TEGRA_POWERGATE_L2] = "l2",
2700 [TEGRA_POWERGATE_MPE] = "mpe",
2703 static const struct tegra_pmc_regs tegra20_pmc_regs = {
2706 .dpd_status = 0x1bc,
2708 .dpd2_status = 0x1c4,
2709 .rst_status = 0x1b4,
2710 .rst_source_shift = 0x0,
2711 .rst_source_mask = 0x7,
2712 .rst_level_shift = 0x0,
2713 .rst_level_mask = 0x0,
2716 static void tegra20_pmc_init(struct tegra_pmc *pmc)
2718 u32 value, osc, pmu, off;
2720 /* Always enable CPU power request */
2721 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2722 value |= PMC_CNTRL_CPU_PWRREQ_OE;
2723 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2725 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2727 if (pmc->sysclkreq_high)
2728 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
2730 value |= PMC_CNTRL_SYSCLK_POLARITY;
2732 if (pmc->corereq_high)
2733 value &= ~PMC_CNTRL_PWRREQ_POLARITY;
2735 value |= PMC_CNTRL_PWRREQ_POLARITY;
2737 /* configure the output polarity while the request is tristated */
2738 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2740 /* now enable the request */
2741 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2742 value |= PMC_CNTRL_SYSCLK_OE;
2743 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2745 /* program core timings which are applicable only for suspend state */
2746 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) {
2747 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000);
2748 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000);
2749 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000);
2750 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),
2751 PMC_COREPWRGOOD_TIMER);
2752 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);
2756 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
2757 struct device_node *np,
2762 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2765 value |= PMC_CNTRL_INTR_POLARITY;
2767 value &= ~PMC_CNTRL_INTR_POLARITY;
2769 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2772 static const struct tegra_pmc_soc tegra20_pmc_soc = {
2773 .num_powergates = ARRAY_SIZE(tegra20_powergates),
2774 .powergates = tegra20_powergates,
2775 .num_cpu_powergates = 0,
2776 .cpu_powergates = NULL,
2777 .has_tsense_reset = false,
2778 .has_gpu_clamps = false,
2779 .needs_mbist_war = false,
2780 .has_impl_33v_pwr = false,
2781 .maybe_tz_only = false,
2786 .regs = &tegra20_pmc_regs,
2787 .init = tegra20_pmc_init,
2788 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2789 .reset_sources = NULL,
2790 .num_reset_sources = 0,
2791 .reset_levels = NULL,
2792 .num_reset_levels = 0,
2793 .pmc_clks_data = NULL,
2795 .has_blink_output = true,
2796 .has_usb_sleepwalk = false,
2799 static const char * const tegra30_powergates[] = {
2800 [TEGRA_POWERGATE_CPU] = "cpu0",
2801 [TEGRA_POWERGATE_3D] = "3d0",
2802 [TEGRA_POWERGATE_VENC] = "venc",
2803 [TEGRA_POWERGATE_VDEC] = "vdec",
2804 [TEGRA_POWERGATE_PCIE] = "pcie",
2805 [TEGRA_POWERGATE_L2] = "l2",
2806 [TEGRA_POWERGATE_MPE] = "mpe",
2807 [TEGRA_POWERGATE_HEG] = "heg",
2808 [TEGRA_POWERGATE_SATA] = "sata",
2809 [TEGRA_POWERGATE_CPU1] = "cpu1",
2810 [TEGRA_POWERGATE_CPU2] = "cpu2",
2811 [TEGRA_POWERGATE_CPU3] = "cpu3",
2812 [TEGRA_POWERGATE_CELP] = "celp",
2813 [TEGRA_POWERGATE_3D1] = "3d1",
2816 static const u8 tegra30_cpu_powergates[] = {
2817 TEGRA_POWERGATE_CPU,
2818 TEGRA_POWERGATE_CPU1,
2819 TEGRA_POWERGATE_CPU2,
2820 TEGRA_POWERGATE_CPU3,
2823 static const char * const tegra30_reset_sources[] = {
2831 static const struct tegra_pmc_soc tegra30_pmc_soc = {
2832 .num_powergates = ARRAY_SIZE(tegra30_powergates),
2833 .powergates = tegra30_powergates,
2834 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
2835 .cpu_powergates = tegra30_cpu_powergates,
2836 .has_tsense_reset = true,
2837 .has_gpu_clamps = false,
2838 .needs_mbist_war = false,
2839 .has_impl_33v_pwr = false,
2840 .maybe_tz_only = false,
2845 .regs = &tegra20_pmc_regs,
2846 .init = tegra20_pmc_init,
2847 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2848 .reset_sources = tegra30_reset_sources,
2849 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2850 .reset_levels = NULL,
2851 .num_reset_levels = 0,
2852 .pmc_clks_data = tegra_pmc_clks_data,
2853 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
2854 .has_blink_output = true,
2855 .has_usb_sleepwalk = false,
2858 static const char * const tegra114_powergates[] = {
2859 [TEGRA_POWERGATE_CPU] = "crail",
2860 [TEGRA_POWERGATE_3D] = "3d",
2861 [TEGRA_POWERGATE_VENC] = "venc",
2862 [TEGRA_POWERGATE_VDEC] = "vdec",
2863 [TEGRA_POWERGATE_MPE] = "mpe",
2864 [TEGRA_POWERGATE_HEG] = "heg",
2865 [TEGRA_POWERGATE_CPU1] = "cpu1",
2866 [TEGRA_POWERGATE_CPU2] = "cpu2",
2867 [TEGRA_POWERGATE_CPU3] = "cpu3",
2868 [TEGRA_POWERGATE_CELP] = "celp",
2869 [TEGRA_POWERGATE_CPU0] = "cpu0",
2870 [TEGRA_POWERGATE_C0NC] = "c0nc",
2871 [TEGRA_POWERGATE_C1NC] = "c1nc",
2872 [TEGRA_POWERGATE_DIS] = "dis",
2873 [TEGRA_POWERGATE_DISB] = "disb",
2874 [TEGRA_POWERGATE_XUSBA] = "xusba",
2875 [TEGRA_POWERGATE_XUSBB] = "xusbb",
2876 [TEGRA_POWERGATE_XUSBC] = "xusbc",
2879 static const u8 tegra114_cpu_powergates[] = {
2880 TEGRA_POWERGATE_CPU0,
2881 TEGRA_POWERGATE_CPU1,
2882 TEGRA_POWERGATE_CPU2,
2883 TEGRA_POWERGATE_CPU3,
2886 static const struct tegra_pmc_soc tegra114_pmc_soc = {
2887 .num_powergates = ARRAY_SIZE(tegra114_powergates),
2888 .powergates = tegra114_powergates,
2889 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
2890 .cpu_powergates = tegra114_cpu_powergates,
2891 .has_tsense_reset = true,
2892 .has_gpu_clamps = false,
2893 .needs_mbist_war = false,
2894 .has_impl_33v_pwr = false,
2895 .maybe_tz_only = false,
2900 .regs = &tegra20_pmc_regs,
2901 .init = tegra20_pmc_init,
2902 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2903 .reset_sources = tegra30_reset_sources,
2904 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2905 .reset_levels = NULL,
2906 .num_reset_levels = 0,
2907 .pmc_clks_data = tegra_pmc_clks_data,
2908 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
2909 .has_blink_output = true,
2910 .has_usb_sleepwalk = false,
2913 static const char * const tegra124_powergates[] = {
2914 [TEGRA_POWERGATE_CPU] = "crail",
2915 [TEGRA_POWERGATE_3D] = "3d",
2916 [TEGRA_POWERGATE_VENC] = "venc",
2917 [TEGRA_POWERGATE_PCIE] = "pcie",
2918 [TEGRA_POWERGATE_VDEC] = "vdec",
2919 [TEGRA_POWERGATE_MPE] = "mpe",
2920 [TEGRA_POWERGATE_HEG] = "heg",
2921 [TEGRA_POWERGATE_SATA] = "sata",
2922 [TEGRA_POWERGATE_CPU1] = "cpu1",
2923 [TEGRA_POWERGATE_CPU2] = "cpu2",
2924 [TEGRA_POWERGATE_CPU3] = "cpu3",
2925 [TEGRA_POWERGATE_CELP] = "celp",
2926 [TEGRA_POWERGATE_CPU0] = "cpu0",
2927 [TEGRA_POWERGATE_C0NC] = "c0nc",
2928 [TEGRA_POWERGATE_C1NC] = "c1nc",
2929 [TEGRA_POWERGATE_SOR] = "sor",
2930 [TEGRA_POWERGATE_DIS] = "dis",
2931 [TEGRA_POWERGATE_DISB] = "disb",
2932 [TEGRA_POWERGATE_XUSBA] = "xusba",
2933 [TEGRA_POWERGATE_XUSBB] = "xusbb",
2934 [TEGRA_POWERGATE_XUSBC] = "xusbc",
2935 [TEGRA_POWERGATE_VIC] = "vic",
2936 [TEGRA_POWERGATE_IRAM] = "iram",
2939 static const u8 tegra124_cpu_powergates[] = {
2940 TEGRA_POWERGATE_CPU0,
2941 TEGRA_POWERGATE_CPU1,
2942 TEGRA_POWERGATE_CPU2,
2943 TEGRA_POWERGATE_CPU3,
2946 #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \
2947 ((struct tegra_io_pad_soc) { \
2950 .voltage = (_voltage), \
2954 #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \
2955 ((struct pinctrl_pin_desc) { \
2960 #define TEGRA124_IO_PAD_TABLE(_pad) \
2961 /* .id .dpd .voltage .name */ \
2962 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
2963 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \
2964 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \
2965 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \
2966 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
2967 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \
2968 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \
2969 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
2970 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
2971 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
2972 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
2973 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
2974 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
2975 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \
2976 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
2977 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
2978 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \
2979 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
2980 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
2981 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
2982 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
2983 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \
2984 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \
2985 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \
2986 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \
2987 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
2988 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
2989 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
2990 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
2991 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias")
2993 static const struct tegra_io_pad_soc tegra124_io_pads[] = {
2994 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD)
2997 static const struct pinctrl_pin_desc tegra124_pin_descs[] = {
2998 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3001 static const struct tegra_pmc_soc tegra124_pmc_soc = {
3002 .num_powergates = ARRAY_SIZE(tegra124_powergates),
3003 .powergates = tegra124_powergates,
3004 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
3005 .cpu_powergates = tegra124_cpu_powergates,
3006 .has_tsense_reset = true,
3007 .has_gpu_clamps = true,
3008 .needs_mbist_war = false,
3009 .has_impl_33v_pwr = false,
3010 .maybe_tz_only = false,
3011 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
3012 .io_pads = tegra124_io_pads,
3013 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs),
3014 .pin_descs = tegra124_pin_descs,
3015 .regs = &tegra20_pmc_regs,
3016 .init = tegra20_pmc_init,
3017 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3018 .reset_sources = tegra30_reset_sources,
3019 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3020 .reset_levels = NULL,
3021 .num_reset_levels = 0,
3022 .pmc_clks_data = tegra_pmc_clks_data,
3023 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3024 .has_blink_output = true,
3025 .has_usb_sleepwalk = true,
3028 static const char * const tegra210_powergates[] = {
3029 [TEGRA_POWERGATE_CPU] = "crail",
3030 [TEGRA_POWERGATE_3D] = "3d",
3031 [TEGRA_POWERGATE_VENC] = "venc",
3032 [TEGRA_POWERGATE_PCIE] = "pcie",
3033 [TEGRA_POWERGATE_MPE] = "mpe",
3034 [TEGRA_POWERGATE_SATA] = "sata",
3035 [TEGRA_POWERGATE_CPU1] = "cpu1",
3036 [TEGRA_POWERGATE_CPU2] = "cpu2",
3037 [TEGRA_POWERGATE_CPU3] = "cpu3",
3038 [TEGRA_POWERGATE_CPU0] = "cpu0",
3039 [TEGRA_POWERGATE_C0NC] = "c0nc",
3040 [TEGRA_POWERGATE_SOR] = "sor",
3041 [TEGRA_POWERGATE_DIS] = "dis",
3042 [TEGRA_POWERGATE_DISB] = "disb",
3043 [TEGRA_POWERGATE_XUSBA] = "xusba",
3044 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3045 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3046 [TEGRA_POWERGATE_VIC] = "vic",
3047 [TEGRA_POWERGATE_IRAM] = "iram",
3048 [TEGRA_POWERGATE_NVDEC] = "nvdec",
3049 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
3050 [TEGRA_POWERGATE_AUD] = "aud",
3051 [TEGRA_POWERGATE_DFD] = "dfd",
3052 [TEGRA_POWERGATE_VE2] = "ve2",
3055 static const u8 tegra210_cpu_powergates[] = {
3056 TEGRA_POWERGATE_CPU0,
3057 TEGRA_POWERGATE_CPU1,
3058 TEGRA_POWERGATE_CPU2,
3059 TEGRA_POWERGATE_CPU3,
3062 #define TEGRA210_IO_PAD_TABLE(_pad) \
3063 /* .id .dpd .voltage .name */ \
3064 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \
3065 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \
3066 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \
3067 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3068 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3069 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \
3070 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \
3071 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \
3072 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \
3073 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \
3074 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \
3075 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \
3076 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \
3077 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3078 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
3079 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
3080 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
3081 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \
3082 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \
3083 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \
3084 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
3085 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3086 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
3087 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3088 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
3089 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
3090 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3091 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \
3092 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \
3093 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \
3094 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \
3095 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \
3096 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \
3097 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3098 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3099 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3100 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \
3101 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias")
3103 static const struct tegra_io_pad_soc tegra210_io_pads[] = {
3104 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD)
3107 static const struct pinctrl_pin_desc tegra210_pin_descs[] = {
3108 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3111 static const char * const tegra210_reset_sources[] = {
3120 static const struct tegra_wake_event tegra210_wake_events[] = {
3121 TEGRA_WAKE_IRQ("rtc", 16, 2),
3122 TEGRA_WAKE_IRQ("pmu", 51, 86),
3125 static const struct tegra_pmc_soc tegra210_pmc_soc = {
3126 .num_powergates = ARRAY_SIZE(tegra210_powergates),
3127 .powergates = tegra210_powergates,
3128 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
3129 .cpu_powergates = tegra210_cpu_powergates,
3130 .has_tsense_reset = true,
3131 .has_gpu_clamps = true,
3132 .needs_mbist_war = true,
3133 .has_impl_33v_pwr = false,
3134 .maybe_tz_only = true,
3135 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
3136 .io_pads = tegra210_io_pads,
3137 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
3138 .pin_descs = tegra210_pin_descs,
3139 .regs = &tegra20_pmc_regs,
3140 .init = tegra20_pmc_init,
3141 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3142 .irq_set_wake = tegra210_pmc_irq_set_wake,
3143 .irq_set_type = tegra210_pmc_irq_set_type,
3144 .reset_sources = tegra210_reset_sources,
3145 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
3146 .reset_levels = NULL,
3147 .num_reset_levels = 0,
3148 .num_wake_events = ARRAY_SIZE(tegra210_wake_events),
3149 .wake_events = tegra210_wake_events,
3150 .pmc_clks_data = tegra_pmc_clks_data,
3151 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3152 .has_blink_output = true,
3153 .has_usb_sleepwalk = true,
3156 #define TEGRA186_IO_PAD_TABLE(_pad) \
3157 /* .id .dpd .voltage .name */ \
3158 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3159 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3160 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3161 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3162 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3163 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3164 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3165 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3166 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3167 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3168 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3169 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \
3170 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3171 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3172 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3173 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
3174 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3175 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3176 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3177 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \
3178 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
3179 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
3180 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \
3181 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \
3182 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \
3183 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
3184 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
3185 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
3186 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
3187 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
3188 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
3189 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \
3190 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
3191 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3192 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3193 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
3194 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3195 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3197 static const struct tegra_io_pad_soc tegra186_io_pads[] = {
3198 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD)
3201 static const struct pinctrl_pin_desc tegra186_pin_descs[] = {
3202 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3205 static const struct tegra_pmc_regs tegra186_pmc_regs = {
3210 .dpd2_status = 0x80,
3212 .rst_source_shift = 0x2,
3213 .rst_source_mask = 0x3c,
3214 .rst_level_shift = 0x0,
3215 .rst_level_mask = 0x3,
3218 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3219 struct device_node *np,
3222 struct resource regs;
3227 index = of_property_match_string(np, "reg-names", "wake");
3229 dev_err(pmc->dev, "failed to find PMC wake registers\n");
3233 of_address_to_resource(np, index, ®s);
3235 wake = ioremap(regs.start, resource_size(®s));
3237 dev_err(pmc->dev, "failed to map PMC wake registers\n");
3241 value = readl(wake + WAKE_AOWAKE_CTRL);
3244 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
3246 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
3248 writel(value, wake + WAKE_AOWAKE_CTRL);
3253 static const char * const tegra186_reset_sources[] = {
3271 static const char * const tegra186_reset_levels[] = {
3272 "L0", "L1", "L2", "WARM"
3275 static const struct tegra_wake_event tegra186_wake_events[] = {
3276 TEGRA_WAKE_IRQ("pmu", 24, 209),
3277 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
3278 TEGRA_WAKE_IRQ("rtc", 73, 10),
3281 static const struct tegra_pmc_soc tegra186_pmc_soc = {
3282 .num_powergates = 0,
3284 .num_cpu_powergates = 0,
3285 .cpu_powergates = NULL,
3286 .has_tsense_reset = false,
3287 .has_gpu_clamps = false,
3288 .needs_mbist_war = false,
3289 .has_impl_33v_pwr = true,
3290 .maybe_tz_only = false,
3291 .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
3292 .io_pads = tegra186_io_pads,
3293 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
3294 .pin_descs = tegra186_pin_descs,
3295 .regs = &tegra186_pmc_regs,
3297 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3298 .irq_set_wake = tegra186_pmc_irq_set_wake,
3299 .irq_set_type = tegra186_pmc_irq_set_type,
3300 .reset_sources = tegra186_reset_sources,
3301 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),
3302 .reset_levels = tegra186_reset_levels,
3303 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3304 .num_wake_events = ARRAY_SIZE(tegra186_wake_events),
3305 .wake_events = tegra186_wake_events,
3306 .pmc_clks_data = NULL,
3308 .has_blink_output = false,
3309 .has_usb_sleepwalk = false,
3312 #define TEGRA194_IO_PAD_TABLE(_pad) \
3313 /* .id .dpd .voltage .name */ \
3314 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3315 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3316 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3317 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3318 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3319 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3320 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3321 _pad(TEGRA_IO_PAD_EQOS, 8, UINT_MAX, "eqos"), \
3322 _pad(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, UINT_MAX, "pex-clk-2-bias"), \
3323 _pad(TEGRA_IO_PAD_PEX_CLK_2, 10, UINT_MAX, "pex-clk-2"), \
3324 _pad(TEGRA_IO_PAD_DAP3, 11, UINT_MAX, "dap3"), \
3325 _pad(TEGRA_IO_PAD_DAP5, 12, UINT_MAX, "dap5"), \
3326 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3327 _pad(TEGRA_IO_PAD_PWR_CTL, 15, UINT_MAX, "pwr-ctl"), \
3328 _pad(TEGRA_IO_PAD_SOC_GPIO53, 16, UINT_MAX, "soc-gpio53"), \
3329 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3330 _pad(TEGRA_IO_PAD_GP_PWM2, 18, UINT_MAX, "gp-pwm2"), \
3331 _pad(TEGRA_IO_PAD_GP_PWM3, 19, UINT_MAX, "gp-pwm3"), \
3332 _pad(TEGRA_IO_PAD_SOC_GPIO12, 20, UINT_MAX, "soc-gpio12"), \
3333 _pad(TEGRA_IO_PAD_SOC_GPIO13, 21, UINT_MAX, "soc-gpio13"), \
3334 _pad(TEGRA_IO_PAD_SOC_GPIO10, 22, UINT_MAX, "soc-gpio10"), \
3335 _pad(TEGRA_IO_PAD_UART4, 23, UINT_MAX, "uart4"), \
3336 _pad(TEGRA_IO_PAD_UART5, 24, UINT_MAX, "uart5"), \
3337 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
3338 _pad(TEGRA_IO_PAD_HDMI_DP3, 26, UINT_MAX, "hdmi-dp3"), \
3339 _pad(TEGRA_IO_PAD_HDMI_DP2, 27, UINT_MAX, "hdmi-dp2"), \
3340 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3341 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3342 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3343 _pad(TEGRA_IO_PAD_PEX_CTL2, 33, UINT_MAX, "pex-ctl2"), \
3344 _pad(TEGRA_IO_PAD_PEX_L0_RST_N, 34, UINT_MAX, "pex-l0-rst"), \
3345 _pad(TEGRA_IO_PAD_PEX_L1_RST_N, 35, UINT_MAX, "pex-l1-rst"), \
3346 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
3347 _pad(TEGRA_IO_PAD_PEX_L5_RST_N, 37, UINT_MAX, "pex-l5-rst"), \
3348 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
3349 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
3350 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
3351 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
3352 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
3353 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
3354 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
3355 _pad(TEGRA_IO_PAD_CSIG, 50, UINT_MAX, "csig"), \
3356 _pad(TEGRA_IO_PAD_CSIH, 51, UINT_MAX, "csih"), \
3357 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
3358 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3359 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3360 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
3361 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3362 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3364 static const struct tegra_io_pad_soc tegra194_io_pads[] = {
3365 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PAD)
3368 static const struct pinctrl_pin_desc tegra194_pin_descs[] = {
3369 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3372 static const struct tegra_pmc_regs tegra194_pmc_regs = {
3377 .dpd2_status = 0x80,
3379 .rst_source_shift = 0x2,
3380 .rst_source_mask = 0x7c,
3381 .rst_level_shift = 0x0,
3382 .rst_level_mask = 0x3,
3385 static const char * const tegra194_reset_sources[] = {
3409 static const struct tegra_wake_event tegra194_wake_events[] = {
3410 TEGRA_WAKE_IRQ("pmu", 24, 209),
3411 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)),
3412 TEGRA_WAKE_IRQ("rtc", 73, 10),
3415 static const struct tegra_pmc_soc tegra194_pmc_soc = {
3416 .num_powergates = 0,
3418 .num_cpu_powergates = 0,
3419 .cpu_powergates = NULL,
3420 .has_tsense_reset = false,
3421 .has_gpu_clamps = false,
3422 .needs_mbist_war = false,
3423 .has_impl_33v_pwr = true,
3424 .maybe_tz_only = false,
3425 .num_io_pads = ARRAY_SIZE(tegra194_io_pads),
3426 .io_pads = tegra194_io_pads,
3427 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs),
3428 .pin_descs = tegra194_pin_descs,
3429 .regs = &tegra194_pmc_regs,
3431 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3432 .irq_set_wake = tegra186_pmc_irq_set_wake,
3433 .irq_set_type = tegra186_pmc_irq_set_type,
3434 .reset_sources = tegra194_reset_sources,
3435 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources),
3436 .reset_levels = tegra186_reset_levels,
3437 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3438 .num_wake_events = ARRAY_SIZE(tegra194_wake_events),
3439 .wake_events = tegra194_wake_events,
3440 .pmc_clks_data = NULL,
3442 .has_blink_output = false,
3443 .has_usb_sleepwalk = false,
3446 static const struct tegra_pmc_regs tegra234_pmc_regs = {
3453 .rst_source_shift = 0x2,
3454 .rst_source_mask = 0xfc,
3455 .rst_level_shift = 0x0,
3456 .rst_level_mask = 0x3,
3459 static const char * const tegra234_reset_sources[] = {
3483 static const struct tegra_pmc_soc tegra234_pmc_soc = {
3484 .num_powergates = 0,
3486 .num_cpu_powergates = 0,
3487 .cpu_powergates = NULL,
3488 .has_tsense_reset = false,
3489 .has_gpu_clamps = false,
3490 .needs_mbist_war = false,
3491 .has_impl_33v_pwr = true,
3492 .maybe_tz_only = false,
3497 .regs = &tegra234_pmc_regs,
3499 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3500 .irq_set_wake = tegra186_pmc_irq_set_wake,
3501 .irq_set_type = tegra186_pmc_irq_set_type,
3502 .reset_sources = tegra234_reset_sources,
3503 .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources),
3504 .reset_levels = tegra186_reset_levels,
3505 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3506 .num_wake_events = 0,
3507 .wake_events = NULL,
3508 .pmc_clks_data = NULL,
3510 .has_blink_output = false,
3513 static const struct of_device_id tegra_pmc_match[] = {
3514 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
3515 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
3516 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
3517 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
3518 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
3519 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
3520 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
3521 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
3522 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
3526 static struct platform_driver tegra_pmc_driver = {
3528 .name = "tegra-pmc",
3529 .suppress_bind_attrs = true,
3530 .of_match_table = tegra_pmc_match,
3531 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
3532 .pm = &tegra_pmc_pm_ops,
3535 .probe = tegra_pmc_probe,
3537 builtin_platform_driver(tegra_pmc_driver);
3539 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)
3543 saved = readl(pmc->base + pmc->soc->regs->scratch0);
3544 value = saved ^ 0xffffffff;
3546 if (value == 0xffffffff)
3549 /* write pattern and read it back */
3550 writel(value, pmc->base + pmc->soc->regs->scratch0);
3551 value = readl(pmc->base + pmc->soc->regs->scratch0);
3553 /* if we read all-zeroes, access is restricted to TZ only */
3555 pr_info("access to PMC is restricted to TZ\n");
3559 /* restore original value */
3560 writel(saved, pmc->base + pmc->soc->regs->scratch0);
3566 * Early initialization to allow access to registers in the very early boot
3569 static int __init tegra_pmc_early_init(void)
3571 const struct of_device_id *match;
3572 struct device_node *np;
3573 struct resource regs;
3577 mutex_init(&pmc->powergates_lock);
3579 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
3582 * Fall back to legacy initialization for 32-bit ARM only. All
3583 * 64-bit ARM device tree files for Tegra are required to have
3586 * This is for backwards-compatibility with old device trees
3587 * that didn't contain a PMC node. Note that in this case the
3588 * SoC data can't be matched and therefore powergating is
3591 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
3592 pr_warn("DT node not found, powergating disabled\n");
3594 regs.start = 0x7000e400;
3595 regs.end = 0x7000e7ff;
3596 regs.flags = IORESOURCE_MEM;
3598 pr_warn("Using memory region %pR\n", ®s);
3601 * At this point we're not running on Tegra, so play
3602 * nice with multi-platform kernels.
3608 * Extract information from the device tree if we've found a
3611 if (of_address_to_resource(np, 0, ®s) < 0) {
3612 pr_err("failed to get PMC registers\n");
3618 pmc->base = ioremap(regs.start, resource_size(®s));
3620 pr_err("failed to map PMC registers\n");
3626 pmc->soc = match->data;
3628 if (pmc->soc->maybe_tz_only)
3629 pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
3631 /* Create a bitmap of the available and valid partitions */
3632 for (i = 0; i < pmc->soc->num_powergates; i++)
3633 if (pmc->soc->powergates[i])
3634 set_bit(i, pmc->powergates_available);
3637 * Invert the interrupt polarity if a PMC device tree node
3638 * exists and contains the nvidia,invert-interrupt property.
3640 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
3642 pmc->soc->setup_irq_polarity(pmc, np, invert);
3649 early_initcall(tegra_pmc_early_init);