drivers/soc/rockchip/pm_domains.c

   1 /*
   2  * Rockchip Generic power domain support.
   3  *
   4  * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/io.h>
  12 #include <linux/err.h>
  13 #include <linux/pm_clock.h>
  14 #include <linux/pm_domain.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_platform.h>
  17 #include <linux/clk.h>
  18 #include <linux/regmap.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <dt-bindings/power/rk3288-power.h>
  21 #include <dt-bindings/power/rk3368-power.h>
  22
  23 struct rockchip_domain_info {
  24         int pwr_mask;
  25         int status_mask;
  26         int req_mask;
  27         int idle_mask;
  28         int ack_mask;
  29 };
  30
  31 struct rockchip_pmu_info {
  32         u32 pwr_offset;
  33         u32 status_offset;
  34         u32 req_offset;
  35         u32 idle_offset;
  36         u32 ack_offset;
  37
  38         u32 core_pwrcnt_offset;
  39         u32 gpu_pwrcnt_offset;
  40
  41         unsigned int core_power_transition_time;
  42         unsigned int gpu_power_transition_time;
  43
  44         int num_domains;
  45         const struct rockchip_domain_info *domain_info;
  46 };
  47
  48 struct rockchip_pm_domain {
  49         struct generic_pm_domain genpd;
  50         const struct rockchip_domain_info *info;
  51         struct rockchip_pmu *pmu;
  52         int num_clks;
  53         struct clk *clks[];
  54 };
  55
  56 struct rockchip_pmu {
  57         struct device *dev;
  58         struct regmap *regmap;
  59         const struct rockchip_pmu_info *info;
  60         struct mutex mutex; /* mutex lock for pmu */
  61         struct genpd_onecell_data genpd_data;
  62         struct generic_pm_domain *domains[];
  63 };
  64
  65 #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
  66
  67 #define DOMAIN(pwr, status, req, idle, ack)     \
  68 {                                               \
  69         .pwr_mask = (pwr >= 0) ? BIT(pwr) : 0,          \
  70         .status_mask = (status >= 0) ? BIT(status) : 0, \
  71         .req_mask = (req >= 0) ? BIT(req) : 0,          \
  72         .idle_mask = (idle >= 0) ? BIT(idle) : 0,       \
  73         .ack_mask = (ack >= 0) ? BIT(ack) : 0,          \
  74 }
  75
  76 #define DOMAIN_RK3288(pwr, status, req)         \
  77         DOMAIN(pwr, status, req, req, (req) + 16)
  78
  79 #define DOMAIN_RK3368(pwr, status, req)         \
  80         DOMAIN(pwr, status, req, (req) + 16, req)
  81
  82 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
  83 {
  84         struct rockchip_pmu *pmu = pd->pmu;
  85         const struct rockchip_domain_info *pd_info = pd->info;
  86         unsigned int val;
  87
  88         regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
  89         return (val & pd_info->idle_mask) == pd_info->idle_mask;
  90 }
  91
  92 static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
  93                                          bool idle)
  94 {
  95         const struct rockchip_domain_info *pd_info = pd->info;
  96         struct rockchip_pmu *pmu = pd->pmu;
  97         unsigned int val;
  98
  99         if (pd_info->req_mask == 0)
 100                 return 0;
 101
 102         regmap_update_bits(pmu->regmap, pmu->info->req_offset,
 103                            pd_info->req_mask, idle ? -1U : 0);
 104
 105         dsb(sy);
 106
 107         do {
 108                 regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
 109         } while ((val & pd_info->ack_mask) != (idle ? pd_info->ack_mask : 0));
 110
 111         while (rockchip_pmu_domain_is_idle(pd) != idle)
 112                 cpu_relax();
 113
 114         return 0;
 115 }
 116
 117 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
 118 {
 119         struct rockchip_pmu *pmu = pd->pmu;
 120         unsigned int val;
 121
 122         /* check idle status for idle-only domains */
 123         if (pd->info->status_mask == 0)
 124                 return !rockchip_pmu_domain_is_idle(pd);
 125
 126         regmap_read(pmu->regmap, pmu->info->status_offset, &val);
 127
 128         /* 1'b0: power on, 1'b1: power off */
 129         return !(val & pd->info->status_mask);
 130 }
 131
 132 static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
 133                                              bool on)
 134 {
 135         struct rockchip_pmu *pmu = pd->pmu;
 136
 137         if (pd->info->pwr_mask == 0)
 138                 return;
 139
 140         regmap_update_bits(pmu->regmap, pmu->info->pwr_offset,
 141                            pd->info->pwr_mask, on ? 0 : -1U);
 142
 143         dsb(sy);
 144
 145         while (rockchip_pmu_domain_is_on(pd) != on)
 146                 cpu_relax();
 147 }
 148
 149 static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
 150 {
 151         int i;
 152
 153         mutex_lock(&pd->pmu->mutex);
 154
 155         if (rockchip_pmu_domain_is_on(pd) != power_on) {
 156                 for (i = 0; i < pd->num_clks; i++)
 157                         clk_enable(pd->clks[i]);
 158
 159                 if (!power_on) {
 160                         /* FIXME: add code to save AXI_QOS */
 161
 162                         /* if powering down, idle request to NIU first */
 163                         rockchip_pmu_set_idle_request(pd, true);
 164                 }
 165
 166                 rockchip_do_pmu_set_power_domain(pd, power_on);
 167
 168                 if (power_on) {
 169                         /* if powering up, leave idle mode */
 170                         rockchip_pmu_set_idle_request(pd, false);
 171
 172                         /* FIXME: add code to restore AXI_QOS */
 173                 }
 174
 175                 for (i = pd->num_clks - 1; i >= 0; i--)
 176                         clk_disable(pd->clks[i]);
 177         }
 178
 179         mutex_unlock(&pd->pmu->mutex);
 180         return 0;
 181 }
 182
 183 static int rockchip_pd_power_on(struct generic_pm_domain *domain)
 184 {
 185         struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
 186
 187         return rockchip_pd_power(pd, true);
 188 }
 189
 190 static int rockchip_pd_power_off(struct generic_pm_domain *domain)
 191 {
 192         struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
 193
 194         return rockchip_pd_power(pd, false);
 195 }
 196
 197 static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd,
 198                                   struct device *dev)
 199 {
 200         struct clk *clk;
 201         int i;
 202         int error;
 203
 204         dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name);
 205
 206         error = pm_clk_create(dev);
 207         if (error) {
 208                 dev_err(dev, "pm_clk_create failed %d\n", error);
 209                 return error;
 210         }
 211
 212         i = 0;
 213         while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) {
 214                 dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk);
 215                 error = pm_clk_add_clk(dev, clk);
 216                 if (error) {
 217                         dev_err(dev, "pm_clk_add_clk failed %d\n", error);
 218                         clk_put(clk);
 219                         pm_clk_destroy(dev);
 220                         return error;
 221                 }
 222         }
 223
 224         return 0;
 225 }
 226
 227 static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd,
 228                                    struct device *dev)
 229 {
 230         dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name);
 231
 232         pm_clk_destroy(dev);
 233 }
 234
 235 static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
 236                                       struct device_node *node)
 237 {
 238         const struct rockchip_domain_info *pd_info;
 239         struct rockchip_pm_domain *pd;
 240         struct clk *clk;
 241         int clk_cnt;
 242         int i;
 243         u32 id;
 244         int error;
 245
 246         error = of_property_read_u32(node, "reg", &id);
 247         if (error) {
 248                 dev_err(pmu->dev,
 249                         "%s: failed to retrieve domain id (reg): %d\n",
 250                         node->name, error);
 251                 return -EINVAL;
 252         }
 253
 254         if (id >= pmu->info->num_domains) {
 255                 dev_err(pmu->dev, "%s: invalid domain id %d\n",
 256                         node->name, id);
 257                 return -EINVAL;
 258         }
 259
 260         pd_info = &pmu->info->domain_info[id];
 261         if (!pd_info) {
 262                 dev_err(pmu->dev, "%s: undefined domain id %d\n",
 263                         node->name, id);
 264                 return -EINVAL;
 265         }
 266
 267         clk_cnt = of_count_phandle_with_args(node, "clocks", "#clock-cells");
 268         pd = devm_kzalloc(pmu->dev,
 269                           sizeof(*pd) + clk_cnt * sizeof(pd->clks[0]),
 270                           GFP_KERNEL);
 271         if (!pd)
 272                 return -ENOMEM;
 273
 274         pd->info = pd_info;
 275         pd->pmu = pmu;
 276
 277         for (i = 0; i < clk_cnt; i++) {
 278                 clk = of_clk_get(node, i);
 279                 if (IS_ERR(clk)) {
 280                         error = PTR_ERR(clk);
 281                         dev_err(pmu->dev,
 282                                 "%s: failed to get clk at index %d: %d\n",
 283                                 node->name, i, error);
 284                         goto err_out;
 285                 }
 286
 287                 error = clk_prepare(clk);
 288                 if (error) {
 289                         dev_err(pmu->dev,
 290                                 "%s: failed to prepare clk %pC (index %d): %d\n",
 291                                 node->name, clk, i, error);
 292                         clk_put(clk);
 293                         goto err_out;
 294                 }
 295
 296                 pd->clks[pd->num_clks++] = clk;
 297
 298                 dev_dbg(pmu->dev, "added clock '%pC' to domain '%s'\n",
 299                         clk, node->name);
 300         }
 301
 302         error = rockchip_pd_power(pd, true);
 303         if (error) {
 304                 dev_err(pmu->dev,
 305                         "failed to power on domain '%s': %d\n",
 306                         node->name, error);
 307                 goto err_out;
 308         }
 309
 310         pd->genpd.name = node->name;
 311         pd->genpd.power_off = rockchip_pd_power_off;
 312         pd->genpd.power_on = rockchip_pd_power_on;
 313         pd->genpd.attach_dev = rockchip_pd_attach_dev;
 314         pd->genpd.detach_dev = rockchip_pd_detach_dev;
 315         pd->genpd.flags = GENPD_FLAG_PM_CLK;
 316         pm_genpd_init(&pd->genpd, NULL, false);
 317
 318         pmu->genpd_data.domains[id] = &pd->genpd;
 319         return 0;
 320
 321 err_out:
 322         while (--i >= 0) {
 323                 clk_unprepare(pd->clks[i]);
 324                 clk_put(pd->clks[i]);
 325         }
 326         return error;
 327 }
 328
 329 static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
 330 {
 331         int i;
 332
 333         for (i = 0; i < pd->num_clks; i++) {
 334                 clk_unprepare(pd->clks[i]);
 335                 clk_put(pd->clks[i]);
 336         }
 337
 338         /* protect the zeroing of pm->num_clks */
 339         mutex_lock(&pd->pmu->mutex);
 340         pd->num_clks = 0;
 341         mutex_unlock(&pd->pmu->mutex);
 342
 343         /* devm will free our memory */
 344 }
 345
 346 static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu)
 347 {
 348         struct generic_pm_domain *genpd;
 349         struct rockchip_pm_domain *pd;
 350         int i;
 351
 352         for (i = 0; i < pmu->genpd_data.num_domains; i++) {
 353                 genpd = pmu->genpd_data.domains[i];
 354                 if (genpd) {
 355                         pd = to_rockchip_pd(genpd);
 356                         rockchip_pm_remove_one_domain(pd);
 357                 }
 358         }
 359
 360         /* devm will free our memory */
 361 }
 362
 363 static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu,
 364                                       u32 domain_reg_offset,
 365                                       unsigned int count)
 366 {
 367         /* First configure domain power down transition count ... */
 368         regmap_write(pmu->regmap, domain_reg_offset, count);
 369         /* ... and then power up count. */
 370         regmap_write(pmu->regmap, domain_reg_offset + 4, count);
 371 }
 372
 373 static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
 374                                      struct device_node *parent)
 375 {
 376         struct device_node *np;
 377         struct generic_pm_domain *child_domain, *parent_domain;
 378         int error;
 379
 380         for_each_child_of_node(parent, np) {
 381                 u32 idx;
 382
 383                 error = of_property_read_u32(parent, "reg", &idx);
 384                 if (error) {
 385                         dev_err(pmu->dev,
 386                                 "%s: failed to retrieve domain id (reg): %d\n",
 387                                 parent->name, error);
 388                         goto err_out;
 389                 }
 390                 parent_domain = pmu->genpd_data.domains[idx];
 391
 392                 error = rockchip_pm_add_one_domain(pmu, np);
 393                 if (error) {
 394                         dev_err(pmu->dev, "failed to handle node %s: %d\n",
 395                                 np->name, error);
 396                         goto err_out;
 397                 }
 398
 399                 error = of_property_read_u32(np, "reg", &idx);
 400                 if (error) {
 401                         dev_err(pmu->dev,
 402                                 "%s: failed to retrieve domain id (reg): %d\n",
 403                                 np->name, error);
 404                         goto err_out;
 405                 }
 406                 child_domain = pmu->genpd_data.domains[idx];
 407
 408                 error = pm_genpd_add_subdomain(parent_domain, child_domain);
 409                 if (error) {
 410                         dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n",
 411                                 parent_domain->name, child_domain->name, error);
 412                         goto err_out;
 413                 } else {
 414                         dev_dbg(pmu->dev, "%s add subdomain: %s\n",
 415                                 parent_domain->name, child_domain->name);
 416                 }
 417
 418                 rockchip_pm_add_subdomain(pmu, np);
 419         }
 420
 421         return 0;
 422
 423 err_out:
 424         of_node_put(np);
 425         return error;
 426 }
 427
 428 static int rockchip_pm_domain_probe(struct platform_device *pdev)
 429 {
 430         struct device *dev = &pdev->dev;
 431         struct device_node *np = dev->of_node;
 432         struct device_node *node;
 433         struct device *parent;
 434         struct rockchip_pmu *pmu;
 435         const struct of_device_id *match;
 436         const struct rockchip_pmu_info *pmu_info;
 437         int error;
 438
 439         if (!np) {
 440                 dev_err(dev, "device tree node not found\n");
 441                 return -ENODEV;
 442         }
 443
 444         match = of_match_device(dev->driver->of_match_table, dev);
 445         if (!match || !match->data) {
 446                 dev_err(dev, "missing pmu data\n");
 447                 return -EINVAL;
 448         }
 449
 450         pmu_info = match->data;
 451
 452         pmu = devm_kzalloc(dev,
 453                            sizeof(*pmu) +
 454                                 pmu_info->num_domains * sizeof(pmu->domains[0]),
 455                            GFP_KERNEL);
 456         if (!pmu)
 457                 return -ENOMEM;
 458
 459         pmu->dev = &pdev->dev;
 460         mutex_init(&pmu->mutex);
 461
 462         pmu->info = pmu_info;
 463
 464         pmu->genpd_data.domains = pmu->domains;
 465         pmu->genpd_data.num_domains = pmu_info->num_domains;
 466
 467         parent = dev->parent;
 468         if (!parent) {
 469                 dev_err(dev, "no parent for syscon devices\n");
 470                 return -ENODEV;
 471         }
 472
 473         pmu->regmap = syscon_node_to_regmap(parent->of_node);
 474
 475         /*
 476          * Configure power up and down transition delays for CORE
 477          * and GPU domains.
 478          */
 479         rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
 480                                   pmu_info->core_power_transition_time);
 481         rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
 482                                   pmu_info->gpu_power_transition_time);
 483
 484         error = -ENODEV;
 485
 486         for_each_available_child_of_node(np, node) {
 487                 error = rockchip_pm_add_one_domain(pmu, node);
 488                 if (error) {
 489                         dev_err(dev, "failed to handle node %s: %d\n",
 490                                 node->name, error);
 491                         of_node_put(node);
 492                         goto err_out;
 493                 }
 494
 495                 error = rockchip_pm_add_subdomain(pmu, node);
 496                 if (error < 0) {
 497                         dev_err(dev, "failed to handle subdomain node %s: %d\n",
 498                                 node->name, error);
 499                         of_node_put(node);
 500                         goto err_out;
 501                 }
 502         }
 503
 504         if (error) {
 505                 dev_dbg(dev, "no power domains defined\n");
 506                 goto err_out;
 507         }
 508
 509         of_genpd_add_provider_onecell(np, &pmu->genpd_data);
 510
 511         return 0;
 512
 513 err_out:
 514         rockchip_pm_domain_cleanup(pmu);
 515         return error;
 516 }
 517
 518 static const struct rockchip_domain_info rk3288_pm_domains[] = {
 519         [RK3288_PD_VIO]         = DOMAIN_RK3288(7, 7, 4),
 520         [RK3288_PD_HEVC]        = DOMAIN_RK3288(14, 10, 9),
 521         [RK3288_PD_VIDEO]       = DOMAIN_RK3288(8, 8, 3),
 522         [RK3288_PD_GPU]         = DOMAIN_RK3288(9, 9, 2),
 523 };
 524
 525 static const struct rockchip_domain_info rk3368_pm_domains[] = {
 526         [RK3368_PD_PERI]        = DOMAIN_RK3368(13, 12, 6),
 527         [RK3368_PD_VIO]         = DOMAIN_RK3368(15, 14, 8),
 528         [RK3368_PD_VIDEO]       = DOMAIN_RK3368(14, 13, 7),
 529         [RK3368_PD_GPU_0]       = DOMAIN_RK3368(16, 15, 2),
 530         [RK3368_PD_GPU_1]       = DOMAIN_RK3368(17, 16, 2),
 531 };
 532
 533 static const struct rockchip_pmu_info rk3288_pmu = {
 534         .pwr_offset = 0x08,
 535         .status_offset = 0x0c,
 536         .req_offset = 0x10,
 537         .idle_offset = 0x14,
 538         .ack_offset = 0x14,
 539
 540         .core_pwrcnt_offset = 0x34,
 541         .gpu_pwrcnt_offset = 0x3c,
 542
 543         .core_power_transition_time = 24, /* 1us */
 544         .gpu_power_transition_time = 24, /* 1us */
 545
 546         .num_domains = ARRAY_SIZE(rk3288_pm_domains),
 547         .domain_info = rk3288_pm_domains,
 548 };
 549
 550 static const struct rockchip_pmu_info rk3368_pmu = {
 551         .pwr_offset = 0x0c,
 552         .status_offset = 0x10,
 553         .req_offset = 0x3c,
 554         .idle_offset = 0x40,
 555         .ack_offset = 0x40,
 556
 557         .core_pwrcnt_offset = 0x48,
 558         .gpu_pwrcnt_offset = 0x50,
 559
 560         .core_power_transition_time = 24,
 561         .gpu_power_transition_time = 24,
 562
 563         .num_domains = ARRAY_SIZE(rk3368_pm_domains),
 564         .domain_info = rk3368_pm_domains,
 565 };
 566
 567 static const struct of_device_id rockchip_pm_domain_dt_match[] = {
 568         {
 569                 .compatible = "rockchip,rk3288-power-controller",
 570                 .data = (void *)&rk3288_pmu,
 571         },
 572         {
 573                 .compatible = "rockchip,rk3368-power-controller",
 574                 .data = (void *)&rk3368_pmu,
 575         },
 576         { /* sentinel */ },
 577 };
 578
 579 static struct platform_driver rockchip_pm_domain_driver = {
 580         .probe = rockchip_pm_domain_probe,
 581         .driver = {
 582                 .name   = "rockchip-pm-domain",
 583                 .of_match_table = rockchip_pm_domain_dt_match,
 584                 /*
 585                  * We can't forcibly eject devices form power domain,
 586                  * so we can't really remove power domains once they
 587                  * were added.
 588                  */
 589                 .suppress_bind_attrs = true,
 590         },
 591 };
 592
 593 static int __init rockchip_pm_domain_drv_register(void)
 594 {
 595         return platform_driver_register(&rockchip_pm_domain_driver);
 596 }
 597 postcore_initcall(rockchip_pm_domain_drv_register);