1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car SYSC Power management support
5 * Copyright (C) 2014 Magnus Damm
6 * Copyright (C) 2015-2017 Glider bvba
9 #include <linux/clk/renesas.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
13 #include <linux/of_address.h>
14 #include <linux/pm_domain.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
18 #include <linux/soc/renesas/rcar-sysc.h>
20 #include "rcar-sysc.h"
23 #define SYSCSR 0x00 /* SYSC Status Register */
24 #define SYSCISR 0x04 /* Interrupt Status Register */
25 #define SYSCISCR 0x08 /* Interrupt Status Clear Register */
26 #define SYSCIER 0x0c /* Interrupt Enable Register */
27 #define SYSCIMR 0x10 /* Interrupt Mask Register */
29 /* SYSC Status Register */
30 #define SYSCSR_PONENB 1 /* Ready for power resume requests */
31 #define SYSCSR_POFFENB 0 /* Ready for power shutoff requests */
34 * Power Control Register Offsets inside the register block for each domain
35 * Note: The "CR" registers for ARM cores exist on H1 only
36 * Use WFI to power off, CPG/APMU to resume ARM cores on R-Car Gen2
37 * Use PSCI on R-Car Gen3
39 #define PWRSR_OFFS 0x00 /* Power Status Register */
40 #define PWROFFCR_OFFS 0x04 /* Power Shutoff Control Register */
41 #define PWROFFSR_OFFS 0x08 /* Power Shutoff Status Register */
42 #define PWRONCR_OFFS 0x0c /* Power Resume Control Register */
43 #define PWRONSR_OFFS 0x10 /* Power Resume Status Register */
44 #define PWRER_OFFS 0x14 /* Power Shutoff/Resume Error */
47 #define SYSCSR_RETRIES 100
48 #define SYSCSR_DELAY_US 1
50 #define PWRER_RETRIES 100
51 #define PWRER_DELAY_US 1
53 #define SYSCISR_RETRIES 1000
54 #define SYSCISR_DELAY_US 1
56 #define RCAR_PD_ALWAYS_ON 32 /* Always-on power area */
64 static void __iomem *rcar_sysc_base;
65 static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
66 static u32 rcar_sysc_extmask_offs, rcar_sysc_extmask_val;
68 static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on)
70 unsigned int sr_bit, reg_offs;
74 sr_bit = SYSCSR_PONENB;
75 reg_offs = PWRONCR_OFFS;
77 sr_bit = SYSCSR_POFFENB;
78 reg_offs = PWROFFCR_OFFS;
81 /* Wait until SYSC is ready to accept a power request */
82 for (k = 0; k < SYSCSR_RETRIES; k++) {
83 if (ioread32(rcar_sysc_base + SYSCSR) & BIT(sr_bit))
85 udelay(SYSCSR_DELAY_US);
88 if (k == SYSCSR_RETRIES)
91 /* Submit power shutoff or power resume request */
92 iowrite32(BIT(sysc_ch->chan_bit),
93 rcar_sysc_base + sysc_ch->chan_offs + reg_offs);
98 static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on)
100 unsigned int isr_mask = BIT(sysc_ch->isr_bit);
101 unsigned int chan_mask = BIT(sysc_ch->chan_bit);
107 spin_lock_irqsave(&rcar_sysc_lock, flags);
110 * Mask external power requests for CPU or 3DG domains
112 if (rcar_sysc_extmask_val) {
113 iowrite32(rcar_sysc_extmask_val,
114 rcar_sysc_base + rcar_sysc_extmask_offs);
118 * The interrupt source needs to be enabled, but masked, to prevent the
119 * CPU from receiving it.
121 iowrite32(ioread32(rcar_sysc_base + SYSCIMR) | isr_mask,
122 rcar_sysc_base + SYSCIMR);
123 iowrite32(ioread32(rcar_sysc_base + SYSCIER) | isr_mask,
124 rcar_sysc_base + SYSCIER);
126 iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
128 /* Submit power shutoff or resume request until it was accepted */
129 for (k = 0; k < PWRER_RETRIES; k++) {
130 ret = rcar_sysc_pwr_on_off(sysc_ch, on);
134 status = ioread32(rcar_sysc_base +
135 sysc_ch->chan_offs + PWRER_OFFS);
136 if (!(status & chan_mask))
139 udelay(PWRER_DELAY_US);
142 if (k == PWRER_RETRIES) {
147 /* Wait until the power shutoff or resume request has completed * */
148 for (k = 0; k < SYSCISR_RETRIES; k++) {
149 if (ioread32(rcar_sysc_base + SYSCISR) & isr_mask)
151 udelay(SYSCISR_DELAY_US);
154 if (k == SYSCISR_RETRIES)
157 iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
160 if (rcar_sysc_extmask_val)
161 iowrite32(0, rcar_sysc_base + rcar_sysc_extmask_offs);
163 spin_unlock_irqrestore(&rcar_sysc_lock, flags);
165 pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off",
166 sysc_ch->isr_bit, ioread32(rcar_sysc_base + SYSCISR), ret);
170 static bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch)
174 st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS);
175 if (st & BIT(sysc_ch->chan_bit))
181 struct rcar_sysc_pd {
182 struct generic_pm_domain genpd;
183 struct rcar_sysc_ch ch;
188 static inline struct rcar_sysc_pd *to_rcar_pd(struct generic_pm_domain *d)
190 return container_of(d, struct rcar_sysc_pd, genpd);
193 static int rcar_sysc_pd_power_off(struct generic_pm_domain *genpd)
195 struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
197 pr_debug("%s: %s\n", __func__, genpd->name);
198 return rcar_sysc_power(&pd->ch, false);
201 static int rcar_sysc_pd_power_on(struct generic_pm_domain *genpd)
203 struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
205 pr_debug("%s: %s\n", __func__, genpd->name);
206 return rcar_sysc_power(&pd->ch, true);
209 static bool has_cpg_mstp;
211 static int __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
213 struct generic_pm_domain *genpd = &pd->genpd;
214 const char *name = pd->genpd.name;
217 if (pd->flags & PD_CPU) {
219 * This domain contains a CPU core and therefore it should
220 * only be turned off if the CPU is not in use.
222 pr_debug("PM domain %s contains %s\n", name, "CPU");
223 genpd->flags |= GENPD_FLAG_ALWAYS_ON;
224 } else if (pd->flags & PD_SCU) {
226 * This domain contains an SCU and cache-controller, and
227 * therefore it should only be turned off if the CPU cores are
230 pr_debug("PM domain %s contains %s\n", name, "SCU");
231 genpd->flags |= GENPD_FLAG_ALWAYS_ON;
232 } else if (pd->flags & PD_NO_CR) {
234 * This domain cannot be turned off.
236 genpd->flags |= GENPD_FLAG_ALWAYS_ON;
239 if (!(pd->flags & (PD_CPU | PD_SCU))) {
240 /* Enable Clock Domain for I/O devices */
241 genpd->flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
243 genpd->attach_dev = cpg_mstp_attach_dev;
244 genpd->detach_dev = cpg_mstp_detach_dev;
246 genpd->attach_dev = cpg_mssr_attach_dev;
247 genpd->detach_dev = cpg_mssr_detach_dev;
251 genpd->power_off = rcar_sysc_pd_power_off;
252 genpd->power_on = rcar_sysc_pd_power_on;
254 if (pd->flags & (PD_CPU | PD_NO_CR)) {
255 /* Skip CPUs (handled by SMP code) and areas without control */
256 pr_debug("%s: Not touching %s\n", __func__, genpd->name);
260 if (!rcar_sysc_power_is_off(&pd->ch)) {
261 pr_debug("%s: %s is already powered\n", __func__, genpd->name);
265 rcar_sysc_power(&pd->ch, true);
268 error = pm_genpd_init(genpd, &simple_qos_governor, false);
270 pr_err("Failed to init PM domain %s: %d\n", name, error);
275 static const struct of_device_id rcar_sysc_matches[] __initconst = {
276 #ifdef CONFIG_SYSC_R8A7742
277 { .compatible = "renesas,r8a7742-sysc", .data = &r8a7742_sysc_info },
279 #ifdef CONFIG_SYSC_R8A7743
280 { .compatible = "renesas,r8a7743-sysc", .data = &r8a7743_sysc_info },
281 /* RZ/G1N is identical to RZ/G2M w.r.t. power domains. */
282 { .compatible = "renesas,r8a7744-sysc", .data = &r8a7743_sysc_info },
284 #ifdef CONFIG_SYSC_R8A7745
285 { .compatible = "renesas,r8a7745-sysc", .data = &r8a7745_sysc_info },
287 #ifdef CONFIG_SYSC_R8A77470
288 { .compatible = "renesas,r8a77470-sysc", .data = &r8a77470_sysc_info },
290 #ifdef CONFIG_SYSC_R8A774A1
291 { .compatible = "renesas,r8a774a1-sysc", .data = &r8a774a1_sysc_info },
293 #ifdef CONFIG_SYSC_R8A774B1
294 { .compatible = "renesas,r8a774b1-sysc", .data = &r8a774b1_sysc_info },
296 #ifdef CONFIG_SYSC_R8A774C0
297 { .compatible = "renesas,r8a774c0-sysc", .data = &r8a774c0_sysc_info },
299 #ifdef CONFIG_SYSC_R8A774E1
300 { .compatible = "renesas,r8a774e1-sysc", .data = &r8a774e1_sysc_info },
302 #ifdef CONFIG_SYSC_R8A7779
303 { .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
305 #ifdef CONFIG_SYSC_R8A7790
306 { .compatible = "renesas,r8a7790-sysc", .data = &r8a7790_sysc_info },
308 #ifdef CONFIG_SYSC_R8A7791
309 { .compatible = "renesas,r8a7791-sysc", .data = &r8a7791_sysc_info },
310 /* R-Car M2-N is identical to R-Car M2-W w.r.t. power domains. */
311 { .compatible = "renesas,r8a7793-sysc", .data = &r8a7791_sysc_info },
313 #ifdef CONFIG_SYSC_R8A7792
314 { .compatible = "renesas,r8a7792-sysc", .data = &r8a7792_sysc_info },
316 #ifdef CONFIG_SYSC_R8A7794
317 { .compatible = "renesas,r8a7794-sysc", .data = &r8a7794_sysc_info },
319 #ifdef CONFIG_SYSC_R8A7795
320 { .compatible = "renesas,r8a7795-sysc", .data = &r8a7795_sysc_info },
322 #ifdef CONFIG_SYSC_R8A77960
323 { .compatible = "renesas,r8a7796-sysc", .data = &r8a77960_sysc_info },
325 #ifdef CONFIG_SYSC_R8A77961
326 { .compatible = "renesas,r8a77961-sysc", .data = &r8a77961_sysc_info },
328 #ifdef CONFIG_SYSC_R8A77965
329 { .compatible = "renesas,r8a77965-sysc", .data = &r8a77965_sysc_info },
331 #ifdef CONFIG_SYSC_R8A77970
332 { .compatible = "renesas,r8a77970-sysc", .data = &r8a77970_sysc_info },
334 #ifdef CONFIG_SYSC_R8A77980
335 { .compatible = "renesas,r8a77980-sysc", .data = &r8a77980_sysc_info },
337 #ifdef CONFIG_SYSC_R8A77990
338 { .compatible = "renesas,r8a77990-sysc", .data = &r8a77990_sysc_info },
340 #ifdef CONFIG_SYSC_R8A77995
341 { .compatible = "renesas,r8a77995-sysc", .data = &r8a77995_sysc_info },
346 struct rcar_pm_domains {
347 struct genpd_onecell_data onecell_data;
348 struct generic_pm_domain *domains[RCAR_PD_ALWAYS_ON + 1];
351 static struct genpd_onecell_data *rcar_sysc_onecell_data;
353 static int __init rcar_sysc_pd_init(void)
355 const struct rcar_sysc_info *info;
356 const struct of_device_id *match;
357 struct rcar_pm_domains *domains;
358 struct device_node *np;
363 np = of_find_matching_node_and_match(NULL, rcar_sysc_matches, &match);
370 error = info->init();
375 has_cpg_mstp = of_find_compatible_node(NULL, NULL,
376 "renesas,cpg-mstp-clocks");
378 base = of_iomap(np, 0);
380 pr_warn("%pOF: Cannot map regs\n", np);
385 rcar_sysc_base = base;
387 /* Optional External Request Mask Register */
388 rcar_sysc_extmask_offs = info->extmask_offs;
389 rcar_sysc_extmask_val = info->extmask_val;
391 domains = kzalloc(sizeof(*domains), GFP_KERNEL);
397 domains->onecell_data.domains = domains->domains;
398 domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains);
399 rcar_sysc_onecell_data = &domains->onecell_data;
401 for (i = 0; i < info->num_areas; i++) {
402 const struct rcar_sysc_area *area = &info->areas[i];
403 struct rcar_sysc_pd *pd;
406 /* Skip NULLified area */
410 pd = kzalloc(sizeof(*pd) + strlen(area->name) + 1, GFP_KERNEL);
416 strcpy(pd->name, area->name);
417 pd->genpd.name = pd->name;
418 pd->ch.chan_offs = area->chan_offs;
419 pd->ch.chan_bit = area->chan_bit;
420 pd->ch.isr_bit = area->isr_bit;
421 pd->flags = area->flags;
423 error = rcar_sysc_pd_setup(pd);
427 domains->domains[area->isr_bit] = &pd->genpd;
429 if (area->parent < 0)
432 error = pm_genpd_add_subdomain(domains->domains[area->parent],
435 pr_warn("Failed to add PM subdomain %s to parent %u\n",
436 area->name, area->parent);
441 error = of_genpd_add_provider_onecell(np, &domains->onecell_data);
447 early_initcall(rcar_sysc_pd_init);
449 void __init rcar_sysc_nullify(struct rcar_sysc_area *areas,
450 unsigned int num_areas, u8 id)
454 for (i = 0; i < num_areas; i++)
455 if (areas[i].isr_bit == id) {
456 areas[i].name = NULL;
461 #ifdef CONFIG_ARCH_R8A7779
462 static int rcar_sysc_power_cpu(unsigned int idx, bool on)
464 struct generic_pm_domain *genpd;
465 struct rcar_sysc_pd *pd;
468 if (!rcar_sysc_onecell_data)
471 for (i = 0; i < rcar_sysc_onecell_data->num_domains; i++) {
472 genpd = rcar_sysc_onecell_data->domains[i];
476 pd = to_rcar_pd(genpd);
477 if (!(pd->flags & PD_CPU) || pd->ch.chan_bit != idx)
480 return rcar_sysc_power(&pd->ch, on);
486 int rcar_sysc_power_down_cpu(unsigned int cpu)
488 return rcar_sysc_power_cpu(cpu, false);
491 int rcar_sysc_power_up_cpu(unsigned int cpu)
493 return rcar_sysc_power_cpu(cpu, true);
495 #endif /* CONFIG_ARCH_R8A7779 */