drivers/soc/qcom/spm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2014,2015, Linaro Ltd.
   5  *
   6  * SAW power controller driver
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/init.h>
  11 #include <linux/io.h>
  12 #include <linux/module.h>
  13 #include <linux/slab.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_device.h>
  17 #include <linux/err.h>
  18 #include <linux/platform_device.h>
  19 #include <soc/qcom/spm.h>
  20
  21 #define SPM_CTL_INDEX           0x7f
  22 #define SPM_CTL_INDEX_SHIFT     4
  23 #define SPM_CTL_EN              BIT(0)
  24
  25 enum spm_reg {
  26         SPM_REG_CFG,
  27         SPM_REG_SPM_CTL,
  28         SPM_REG_DLY,
  29         SPM_REG_PMIC_DLY,
  30         SPM_REG_PMIC_DATA_0,
  31         SPM_REG_PMIC_DATA_1,
  32         SPM_REG_VCTL,
  33         SPM_REG_SEQ_ENTRY,
  34         SPM_REG_SPM_STS,
  35         SPM_REG_PMIC_STS,
  36         SPM_REG_AVS_CTL,
  37         SPM_REG_AVS_LIMIT,
  38         SPM_REG_NR,
  39 };
  40
  41 static const u16 spm_reg_offset_v4_1[SPM_REG_NR] = {
  42         [SPM_REG_AVS_CTL]       = 0x904,
  43         [SPM_REG_AVS_LIMIT]     = 0x908,
  44 };
  45
  46 static const struct spm_reg_data spm_reg_660_gold_l2  = {
  47         .reg_offset = spm_reg_offset_v4_1,
  48         .avs_ctl = 0x1010031,
  49         .avs_limit = 0x4580458,
  50 };
  51
  52 static const struct spm_reg_data spm_reg_660_silver_l2  = {
  53         .reg_offset = spm_reg_offset_v4_1,
  54         .avs_ctl = 0x101c031,
  55         .avs_limit = 0x4580458,
  56 };
  57
  58 static const struct spm_reg_data spm_reg_8998_gold_l2  = {
  59         .reg_offset = spm_reg_offset_v4_1,
  60         .avs_ctl = 0x1010031,
  61         .avs_limit = 0x4700470,
  62 };
  63
  64 static const struct spm_reg_data spm_reg_8998_silver_l2  = {
  65         .reg_offset = spm_reg_offset_v4_1,
  66         .avs_ctl = 0x1010031,
  67         .avs_limit = 0x4200420,
  68 };
  69
  70 static const u16 spm_reg_offset_v3_0[SPM_REG_NR] = {
  71         [SPM_REG_CFG]           = 0x08,
  72         [SPM_REG_SPM_CTL]       = 0x30,
  73         [SPM_REG_DLY]           = 0x34,
  74         [SPM_REG_SEQ_ENTRY]     = 0x400,
  75 };
  76
  77 /* SPM register data for 8909 */
  78 static const struct spm_reg_data spm_reg_8909_cpu = {
  79         .reg_offset = spm_reg_offset_v3_0,
  80         .spm_cfg = 0x1,
  81         .spm_dly = 0x3C102800,
  82         .seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90,
  83                 0x5B, 0x60, 0x03, 0x60, 0x76, 0x76, 0x0B, 0x94, 0x5B, 0x80,
  84                 0x10, 0x26, 0x30, 0x0F },
  85         .start_index[PM_SLEEP_MODE_STBY] = 0,
  86         .start_index[PM_SLEEP_MODE_SPC] = 5,
  87 };
  88
  89 /* SPM register data for 8916 */
  90 static const struct spm_reg_data spm_reg_8916_cpu = {
  91         .reg_offset = spm_reg_offset_v3_0,
  92         .spm_cfg = 0x1,
  93         .spm_dly = 0x3C102800,
  94         .seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90,
  95                 0x5B, 0x60, 0x03, 0x60, 0x3B, 0x76, 0x76, 0x0B, 0x94, 0x5B,
  96                 0x80, 0x10, 0x26, 0x30, 0x0F },
  97         .start_index[PM_SLEEP_MODE_STBY] = 0,
  98         .start_index[PM_SLEEP_MODE_SPC] = 5,
  99 };
 100
 101 static const u16 spm_reg_offset_v2_1[SPM_REG_NR] = {
 102         [SPM_REG_CFG]           = 0x08,
 103         [SPM_REG_SPM_CTL]       = 0x30,
 104         [SPM_REG_DLY]           = 0x34,
 105         [SPM_REG_SEQ_ENTRY]     = 0x80,
 106 };
 107
 108 /* SPM register data for 8974, 8084 */
 109 static const struct spm_reg_data spm_reg_8974_8084_cpu  = {
 110         .reg_offset = spm_reg_offset_v2_1,
 111         .spm_cfg = 0x1,
 112         .spm_dly = 0x3C102800,
 113         .seq = { 0x03, 0x0B, 0x0F, 0x00, 0x20, 0x80, 0x10, 0xE8, 0x5B, 0x03,
 114                 0x3B, 0xE8, 0x5B, 0x82, 0x10, 0x0B, 0x30, 0x06, 0x26, 0x30,
 115                 0x0F },
 116         .start_index[PM_SLEEP_MODE_STBY] = 0,
 117         .start_index[PM_SLEEP_MODE_SPC] = 3,
 118 };
 119
 120 /* SPM register data for 8226 */
 121 static const struct spm_reg_data spm_reg_8226_cpu  = {
 122         .reg_offset = spm_reg_offset_v2_1,
 123         .spm_cfg = 0x0,
 124         .spm_dly = 0x3C102800,
 125         .seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90,
 126                 0x5B, 0x60, 0x03, 0x60, 0x3B, 0x76, 0x76, 0x0B, 0x94, 0x5B,
 127                 0x80, 0x10, 0x26, 0x30, 0x0F },
 128         .start_index[PM_SLEEP_MODE_STBY] = 0,
 129         .start_index[PM_SLEEP_MODE_SPC] = 5,
 130 };
 131
 132 static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = {
 133         [SPM_REG_CFG]           = 0x08,
 134         [SPM_REG_SPM_CTL]       = 0x20,
 135         [SPM_REG_PMIC_DLY]      = 0x24,
 136         [SPM_REG_PMIC_DATA_0]   = 0x28,
 137         [SPM_REG_PMIC_DATA_1]   = 0x2C,
 138         [SPM_REG_SEQ_ENTRY]     = 0x80,
 139 };
 140
 141 /* SPM register data for 8064 */
 142 static const struct spm_reg_data spm_reg_8064_cpu = {
 143         .reg_offset = spm_reg_offset_v1_1,
 144         .spm_cfg = 0x1F,
 145         .pmic_dly = 0x02020004,
 146         .pmic_data[0] = 0x0084009C,
 147         .pmic_data[1] = 0x00A4001C,
 148         .seq = { 0x03, 0x0F, 0x00, 0x24, 0x54, 0x10, 0x09, 0x03, 0x01,
 149                 0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F },
 150         .start_index[PM_SLEEP_MODE_STBY] = 0,
 151         .start_index[PM_SLEEP_MODE_SPC] = 2,
 152 };
 153
 154 static inline void spm_register_write(struct spm_driver_data *drv,
 155                                         enum spm_reg reg, u32 val)
 156 {
 157         if (drv->reg_data->reg_offset[reg])
 158                 writel_relaxed(val, drv->reg_base +
 159                                 drv->reg_data->reg_offset[reg]);
 160 }
 161
 162 /* Ensure a guaranteed write, before return */
 163 static inline void spm_register_write_sync(struct spm_driver_data *drv,
 164                                         enum spm_reg reg, u32 val)
 165 {
 166         u32 ret;
 167
 168         if (!drv->reg_data->reg_offset[reg])
 169                 return;
 170
 171         do {
 172                 writel_relaxed(val, drv->reg_base +
 173                                 drv->reg_data->reg_offset[reg]);
 174                 ret = readl_relaxed(drv->reg_base +
 175                                 drv->reg_data->reg_offset[reg]);
 176                 if (ret == val)
 177                         break;
 178                 cpu_relax();
 179         } while (1);
 180 }
 181
 182 static inline u32 spm_register_read(struct spm_driver_data *drv,
 183                                     enum spm_reg reg)
 184 {
 185         return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]);
 186 }
 187
 188 void spm_set_low_power_mode(struct spm_driver_data *drv,
 189                             enum pm_sleep_mode mode)
 190 {
 191         u32 start_index;
 192         u32 ctl_val;
 193
 194         start_index = drv->reg_data->start_index[mode];
 195
 196         ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL);
 197         ctl_val &= ~(SPM_CTL_INDEX << SPM_CTL_INDEX_SHIFT);
 198         ctl_val |= start_index << SPM_CTL_INDEX_SHIFT;
 199         ctl_val |= SPM_CTL_EN;
 200         spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val);
 201 }
 202
 203 static const struct of_device_id spm_match_table[] = {
 204         { .compatible = "qcom,sdm660-gold-saw2-v4.1-l2",
 205           .data = &spm_reg_660_gold_l2 },
 206         { .compatible = "qcom,sdm660-silver-saw2-v4.1-l2",
 207           .data = &spm_reg_660_silver_l2 },
 208         { .compatible = "qcom,msm8226-saw2-v2.1-cpu",
 209           .data = &spm_reg_8226_cpu },
 210         { .compatible = "qcom,msm8909-saw2-v3.0-cpu",
 211           .data = &spm_reg_8909_cpu },
 212         { .compatible = "qcom,msm8916-saw2-v3.0-cpu",
 213           .data = &spm_reg_8916_cpu },
 214         { .compatible = "qcom,msm8974-saw2-v2.1-cpu",
 215           .data = &spm_reg_8974_8084_cpu },
 216         { .compatible = "qcom,msm8998-gold-saw2-v4.1-l2",
 217           .data = &spm_reg_8998_gold_l2 },
 218         { .compatible = "qcom,msm8998-silver-saw2-v4.1-l2",
 219           .data = &spm_reg_8998_silver_l2 },
 220         { .compatible = "qcom,apq8084-saw2-v2.1-cpu",
 221           .data = &spm_reg_8974_8084_cpu },
 222         { .compatible = "qcom,apq8064-saw2-v1.1-cpu",
 223           .data = &spm_reg_8064_cpu },
 224         { },
 225 };
 226 MODULE_DEVICE_TABLE(of, spm_match_table);
 227
 228 static int spm_dev_probe(struct platform_device *pdev)
 229 {
 230         const struct of_device_id *match_id;
 231         struct spm_driver_data *drv;
 232         struct resource *res;
 233         void __iomem *addr;
 234
 235         drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
 236         if (!drv)
 237                 return -ENOMEM;
 238
 239         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 240         drv->reg_base = devm_ioremap_resource(&pdev->dev, res);
 241         if (IS_ERR(drv->reg_base))
 242                 return PTR_ERR(drv->reg_base);
 243
 244         match_id = of_match_node(spm_match_table, pdev->dev.of_node);
 245         if (!match_id)
 246                 return -ENODEV;
 247
 248         drv->reg_data = match_id->data;
 249         platform_set_drvdata(pdev, drv);
 250
 251         /* Write the SPM sequences first.. */
 252         addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY];
 253         __iowrite32_copy(addr, drv->reg_data->seq,
 254                         ARRAY_SIZE(drv->reg_data->seq) / 4);
 255
 256         /*
 257          * ..and then the control registers.
 258          * On some SoC if the control registers are written first and if the
 259          * CPU was held in reset, the reset signal could trigger the SPM state
 260          * machine, before the sequences are completely written.
 261          */
 262         spm_register_write(drv, SPM_REG_AVS_CTL, drv->reg_data->avs_ctl);
 263         spm_register_write(drv, SPM_REG_AVS_LIMIT, drv->reg_data->avs_limit);
 264         spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg);
 265         spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly);
 266         spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly);
 267         spm_register_write(drv, SPM_REG_PMIC_DATA_0,
 268                                 drv->reg_data->pmic_data[0]);
 269         spm_register_write(drv, SPM_REG_PMIC_DATA_1,
 270                                 drv->reg_data->pmic_data[1]);
 271
 272         /* Set up Standby as the default low power mode */
 273         if (drv->reg_data->reg_offset[SPM_REG_SPM_CTL])
 274                 spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
 275
 276         return 0;
 277 }
 278
 279 static struct platform_driver spm_driver = {
 280         .probe = spm_dev_probe,
 281         .driver = {
 282                 .name = "qcom_spm",
 283                 .of_match_table = spm_match_table,
 284         },
 285 };
 286
 287 static int __init qcom_spm_init(void)
 288 {
 289         return platform_driver_register(&spm_driver);
 290 }
 291 arch_initcall(qcom_spm_init);
 292
 293 MODULE_LICENSE("GPL v2");