1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
7 #include <linux/bitfield.h>
8 #include <linux/bitmap.h>
9 #include <linux/bitops.h>
10 #include <linux/device.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/mutex.h>
16 #include <linux/of_device.h>
17 #include <linux/regmap.h>
18 #include <linux/sizes.h>
19 #include <linux/slab.h>
20 #include <linux/soc/qcom/llcc-qcom.h>
22 #define ACTIVATE BIT(0)
23 #define DEACTIVATE BIT(1)
24 #define ACT_CTRL_OPCODE_ACTIVATE BIT(0)
25 #define ACT_CTRL_OPCODE_DEACTIVATE BIT(1)
26 #define ACT_CTRL_ACT_TRIG BIT(0)
27 #define ACT_CTRL_OPCODE_SHIFT 0x01
28 #define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02
29 #define ATTR1_FIXED_SIZE_SHIFT 0x03
30 #define ATTR1_PRIORITY_SHIFT 0x04
31 #define ATTR1_MAX_CAP_SHIFT 0x10
32 #define ATTR0_RES_WAYS_MASK GENMASK(11, 0)
33 #define ATTR0_BONUS_WAYS_MASK GENMASK(27, 16)
34 #define ATTR0_BONUS_WAYS_SHIFT 0x10
35 #define LLCC_STATUS_READ_DELAY 100
37 #define CACHE_LINE_SIZE_SHIFT 6
39 #define LLCC_COMMON_HW_INFO 0x00030000
40 #define LLCC_MAJOR_VERSION_MASK GENMASK(31, 24)
42 #define LLCC_COMMON_STATUS0 0x0003000c
43 #define LLCC_LB_CNT_MASK GENMASK(31, 28)
44 #define LLCC_LB_CNT_SHIFT 28
46 #define MAX_CAP_TO_BYTES(n) (n * SZ_1K)
47 #define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K)
48 #define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K)
49 #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n)
50 #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n)
52 #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00
53 #define LLCC_TRP_PCB_ACT 0x21f04
55 #define BANK_OFFSET_STRIDE 0x80000
58 * struct llcc_slice_config - Data associated with the llcc slice
59 * @usecase_id: Unique id for the client's use case
60 * @slice_id: llcc slice id for each client
61 * @max_cap: The maximum capacity of the cache slice provided in KB
62 * @priority: Priority of the client used to select victim line for replacement
63 * @fixed_size: Boolean indicating if the slice has a fixed capacity
64 * @bonus_ways: Bonus ways are additional ways to be used for any slice,
65 * if client ends up using more than reserved cache ways. Bonus
66 * ways are allocated only if they are not reserved for some
68 * @res_ways: Reserved ways for the cache slice, the reserved ways cannot
69 * be used by any other client than the one its assigned to.
70 * @cache_mode: Each slice operates as a cache, this controls the mode of the
71 * slice: normal or TCM(Tightly Coupled Memory)
72 * @probe_target_ways: Determines what ways to probe for access hit. When
73 * configured to 1 only bonus and reserved ways are probed.
74 * When configured to 0 all ways in llcc are probed.
75 * @dis_cap_alloc: Disable capacity based allocation for a client
76 * @retain_on_pc: If this bit is set and client has maintained active vote
77 * then the ways assigned to this client are not flushed on power
79 * @activate_on_init: Activate the slice immediately after it is programmed
81 struct llcc_slice_config {
90 u32 probe_target_ways;
93 bool activate_on_init;
96 struct qcom_llcc_config {
97 const struct llcc_slice_config *sct_data;
102 static const struct llcc_slice_config sc7180_data[] = {
103 { LLCC_CPUSS, 1, 256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 },
104 { LLCC_MDM, 8, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
105 { LLCC_GPUHTW, 11, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
106 { LLCC_GPU, 12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
109 static const struct llcc_slice_config sdm845_data[] = {
110 { LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1 },
111 { LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 },
112 { LLCC_VIDSC1, 3, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 },
113 { LLCC_ROTATOR, 4, 563, 2, 1, 0x0, 0x00e, 2, 0, 1, 1, 0 },
114 { LLCC_VOICE, 5, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
115 { LLCC_AUDIO, 6, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
116 { LLCC_MDMHPGRW, 7, 1024, 2, 0, 0xfc, 0xf00, 0, 0, 1, 1, 0 },
117 { LLCC_MDM, 8, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
118 { LLCC_CMPT, 10, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
119 { LLCC_GPUHTW, 11, 512, 1, 1, 0xc, 0x0, 0, 0, 1, 1, 0 },
120 { LLCC_GPU, 12, 2304, 1, 0, 0xff0, 0x2, 0, 0, 1, 1, 0 },
121 { LLCC_MMUHWT, 13, 256, 2, 0, 0x0, 0x1, 0, 0, 1, 0, 1 },
122 { LLCC_CMPTDMA, 15, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
123 { LLCC_DISP, 16, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
124 { LLCC_VIDFW, 17, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
125 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0x0, 0xf00, 0, 0, 1, 1, 0 },
126 { LLCC_MDMPNG, 21, 1024, 0, 1, 0x1e, 0x0, 0, 0, 1, 1, 0 },
127 { LLCC_AUDHW, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0 },
130 static const struct llcc_slice_config sm8150_data[] = {
131 { LLCC_CPUSS, 1, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 1 },
132 { LLCC_VIDSC0, 2, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
133 { LLCC_VIDSC1, 3, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
134 { LLCC_AUDIO, 6, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
135 { LLCC_MDMHPGRW, 7, 3072, 1, 0, 0xFF, 0xF00, 0, 0, 0, 1, 0 },
136 { LLCC_MDM, 8, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
137 { LLCC_MODHW, 9, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
138 { LLCC_CMPT, 10, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
139 { LLCC_GPUHTW , 11, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
140 { LLCC_GPU, 12, 2560, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
141 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1 },
142 { LLCC_CMPTDMA, 15, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
143 { LLCC_DISP, 16, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
144 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
145 { LLCC_MDMHPFX, 21, 1024, 0, 1, 0xF, 0x0, 0, 0, 0, 1, 0 },
146 { LLCC_AUDHW, 22, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
147 { LLCC_NPU, 23, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
148 { LLCC_WLHW, 24, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
149 { LLCC_MODPE, 29, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 },
150 { LLCC_APTCM, 30, 256, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0 },
151 { LLCC_WRCACHE, 31, 128, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0 },
154 static const struct qcom_llcc_config sc7180_cfg = {
155 .sct_data = sc7180_data,
156 .size = ARRAY_SIZE(sc7180_data),
157 .need_llcc_cfg = true,
160 static const struct qcom_llcc_config sdm845_cfg = {
161 .sct_data = sdm845_data,
162 .size = ARRAY_SIZE(sdm845_data),
163 .need_llcc_cfg = false,
166 static const struct qcom_llcc_config sm8150_cfg = {
167 .sct_data = sm8150_data,
168 .size = ARRAY_SIZE(sm8150_data),
171 static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
174 * llcc_slice_getd - get llcc slice descriptor
175 * @uid: usecase_id for the client
177 * A pointer to llcc slice descriptor will be returned on success and
178 * and error pointer is returned on failure
180 struct llcc_slice_desc *llcc_slice_getd(u32 uid)
182 const struct llcc_slice_config *cfg;
183 struct llcc_slice_desc *desc;
186 if (IS_ERR(drv_data))
187 return ERR_CAST(drv_data);
190 sz = drv_data->cfg_size;
192 for (count = 0; cfg && count < sz; count++, cfg++)
193 if (cfg->usecase_id == uid)
196 if (count == sz || !cfg)
197 return ERR_PTR(-ENODEV);
199 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
201 return ERR_PTR(-ENOMEM);
203 desc->slice_id = cfg->slice_id;
204 desc->slice_size = cfg->max_cap;
208 EXPORT_SYMBOL_GPL(llcc_slice_getd);
211 * llcc_slice_putd - llcc slice descritpor
212 * @desc: Pointer to llcc slice descriptor
214 void llcc_slice_putd(struct llcc_slice_desc *desc)
216 if (!IS_ERR_OR_NULL(desc))
219 EXPORT_SYMBOL_GPL(llcc_slice_putd);
221 static int llcc_update_act_ctrl(u32 sid,
222 u32 act_ctrl_reg_val, u32 status)
229 if (IS_ERR(drv_data))
230 return PTR_ERR(drv_data);
232 act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid);
233 status_reg = LLCC_TRP_STATUSn(sid);
235 /* Set the ACTIVE trigger */
236 act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG;
237 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg,
242 /* Clear the ACTIVE trigger */
243 act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG;
244 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg,
249 ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg,
250 slice_status, !(slice_status & status),
251 0, LLCC_STATUS_READ_DELAY);
256 * llcc_slice_activate - Activate the llcc slice
257 * @desc: Pointer to llcc slice descriptor
259 * A value of zero will be returned on success and a negative errno will
260 * be returned in error cases
262 int llcc_slice_activate(struct llcc_slice_desc *desc)
267 if (IS_ERR(drv_data))
268 return PTR_ERR(drv_data);
270 if (IS_ERR_OR_NULL(desc))
273 mutex_lock(&drv_data->lock);
274 if (test_bit(desc->slice_id, drv_data->bitmap)) {
275 mutex_unlock(&drv_data->lock);
279 act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT;
281 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
284 mutex_unlock(&drv_data->lock);
288 __set_bit(desc->slice_id, drv_data->bitmap);
289 mutex_unlock(&drv_data->lock);
293 EXPORT_SYMBOL_GPL(llcc_slice_activate);
296 * llcc_slice_deactivate - Deactivate the llcc slice
297 * @desc: Pointer to llcc slice descriptor
299 * A value of zero will be returned on success and a negative errno will
300 * be returned in error cases
302 int llcc_slice_deactivate(struct llcc_slice_desc *desc)
307 if (IS_ERR(drv_data))
308 return PTR_ERR(drv_data);
310 if (IS_ERR_OR_NULL(desc))
313 mutex_lock(&drv_data->lock);
314 if (!test_bit(desc->slice_id, drv_data->bitmap)) {
315 mutex_unlock(&drv_data->lock);
318 act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE << ACT_CTRL_OPCODE_SHIFT;
320 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
323 mutex_unlock(&drv_data->lock);
327 __clear_bit(desc->slice_id, drv_data->bitmap);
328 mutex_unlock(&drv_data->lock);
332 EXPORT_SYMBOL_GPL(llcc_slice_deactivate);
335 * llcc_get_slice_id - return the slice id
336 * @desc: Pointer to llcc slice descriptor
338 int llcc_get_slice_id(struct llcc_slice_desc *desc)
340 if (IS_ERR_OR_NULL(desc))
343 return desc->slice_id;
345 EXPORT_SYMBOL_GPL(llcc_get_slice_id);
348 * llcc_get_slice_size - return the slice id
349 * @desc: Pointer to llcc slice descriptor
351 size_t llcc_get_slice_size(struct llcc_slice_desc *desc)
353 if (IS_ERR_OR_NULL(desc))
356 return desc->slice_size;
358 EXPORT_SYMBOL_GPL(llcc_get_slice_size);
360 static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config,
361 const struct qcom_llcc_config *cfg)
368 u32 max_cap_cacheline;
369 struct llcc_slice_desc desc;
371 attr1_val = config->cache_mode;
372 attr1_val |= config->probe_target_ways << ATTR1_PROBE_TARGET_WAYS_SHIFT;
373 attr1_val |= config->fixed_size << ATTR1_FIXED_SIZE_SHIFT;
374 attr1_val |= config->priority << ATTR1_PRIORITY_SHIFT;
376 max_cap_cacheline = MAX_CAP_TO_BYTES(config->max_cap);
379 * LLCC instances can vary for each target.
380 * The SW writes to broadcast register which gets propagated
381 * to each llcc instance (llcc0,.. llccN).
382 * Since the size of the memory is divided equally amongst the
383 * llcc instances, we need to configure the max cap accordingly.
385 max_cap_cacheline = max_cap_cacheline / drv_data->num_banks;
386 max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT;
387 attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT;
389 attr1_cfg = LLCC_TRP_ATTR1_CFGn(config->slice_id);
391 ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val);
395 attr0_val = config->res_ways & ATTR0_RES_WAYS_MASK;
396 attr0_val |= config->bonus_ways << ATTR0_BONUS_WAYS_SHIFT;
398 attr0_cfg = LLCC_TRP_ATTR0_CFGn(config->slice_id);
400 ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val);
404 if (cfg->need_llcc_cfg) {
405 u32 disable_cap_alloc, retain_pc;
407 disable_cap_alloc = config->dis_cap_alloc << config->slice_id;
408 ret = regmap_write(drv_data->bcast_regmap,
409 LLCC_TRP_SCID_DIS_CAP_ALLOC, disable_cap_alloc);
413 retain_pc = config->retain_on_pc << config->slice_id;
414 ret = regmap_write(drv_data->bcast_regmap,
415 LLCC_TRP_PCB_ACT, retain_pc);
420 if (config->activate_on_init) {
421 desc.slice_id = config->slice_id;
422 ret = llcc_slice_activate(&desc);
428 static int qcom_llcc_cfg_program(struct platform_device *pdev,
429 const struct qcom_llcc_config *cfg)
434 const struct llcc_slice_config *llcc_table;
436 sz = drv_data->cfg_size;
437 llcc_table = drv_data->cfg;
439 for (i = 0; i < sz; i++) {
440 ret = _qcom_llcc_cfg_program(&llcc_table[i], cfg);
448 static int qcom_llcc_remove(struct platform_device *pdev)
450 /* Set the global pointer to a error code to avoid referencing it */
451 drv_data = ERR_PTR(-ENODEV);
455 static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev,
459 struct regmap_config llcc_regmap_config = {
466 base = devm_platform_ioremap_resource_byname(pdev, name);
468 return ERR_CAST(base);
470 llcc_regmap_config.name = name;
471 return devm_regmap_init_mmio(&pdev->dev, base, &llcc_regmap_config);
474 static int qcom_llcc_probe(struct platform_device *pdev)
477 struct device *dev = &pdev->dev;
479 struct platform_device *llcc_edac;
480 const struct qcom_llcc_config *cfg;
481 const struct llcc_slice_config *llcc_cfg;
485 drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
491 drv_data->regmap = qcom_llcc_init_mmio(pdev, "llcc_base");
492 if (IS_ERR(drv_data->regmap)) {
493 ret = PTR_ERR(drv_data->regmap);
497 drv_data->bcast_regmap =
498 qcom_llcc_init_mmio(pdev, "llcc_broadcast_base");
499 if (IS_ERR(drv_data->bcast_regmap)) {
500 ret = PTR_ERR(drv_data->bcast_regmap);
504 /* Extract major version of the IP */
505 ret = regmap_read(drv_data->bcast_regmap, LLCC_COMMON_HW_INFO, &version);
509 drv_data->major_version = FIELD_GET(LLCC_MAJOR_VERSION_MASK, version);
511 ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0,
516 num_banks &= LLCC_LB_CNT_MASK;
517 num_banks >>= LLCC_LB_CNT_SHIFT;
518 drv_data->num_banks = num_banks;
520 cfg = of_device_get_match_data(&pdev->dev);
521 llcc_cfg = cfg->sct_data;
524 for (i = 0; i < sz; i++)
525 if (llcc_cfg[i].slice_id > drv_data->max_slices)
526 drv_data->max_slices = llcc_cfg[i].slice_id;
528 drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32),
530 if (!drv_data->offsets) {
535 for (i = 0; i < num_banks; i++)
536 drv_data->offsets[i] = i * BANK_OFFSET_STRIDE;
538 drv_data->bitmap = devm_kcalloc(dev,
539 BITS_TO_LONGS(drv_data->max_slices), sizeof(unsigned long),
541 if (!drv_data->bitmap) {
546 drv_data->cfg = llcc_cfg;
547 drv_data->cfg_size = sz;
548 mutex_init(&drv_data->lock);
549 platform_set_drvdata(pdev, drv_data);
551 ret = qcom_llcc_cfg_program(pdev, cfg);
555 drv_data->ecc_irq = platform_get_irq(pdev, 0);
556 if (drv_data->ecc_irq >= 0) {
557 llcc_edac = platform_device_register_data(&pdev->dev,
558 "qcom_llcc_edac", -1, drv_data,
560 if (IS_ERR(llcc_edac))
561 dev_err(dev, "Failed to register llcc edac driver\n");
566 drv_data = ERR_PTR(-ENODEV);
570 static const struct of_device_id qcom_llcc_of_match[] = {
571 { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg },
572 { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg },
573 { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg },
577 static struct platform_driver qcom_llcc_driver = {
580 .of_match_table = qcom_llcc_of_match,
582 .probe = qcom_llcc_probe,
583 .remove = qcom_llcc_remove,
585 module_platform_driver(qcom_llcc_driver);
587 MODULE_DESCRIPTION("Qualcomm Last Level Cache Controller");
588 MODULE_LICENSE("GPL v2");