drivers/soc/mediatek/mtk-pmic-wrap.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014 MediaTek Inc.
   4  * Author: Flora Fu, MediaTek
   5  */
   6 #include <linux/clk.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/io.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/regmap.h>
  14 #include <linux/reset.h>
  15
  16 #define PWRAP_MT8135_BRIDGE_IORD_ARB_EN         0x4
  17 #define PWRAP_MT8135_BRIDGE_WACS3_EN            0x10
  18 #define PWRAP_MT8135_BRIDGE_INIT_DONE3          0x14
  19 #define PWRAP_MT8135_BRIDGE_WACS4_EN            0x24
  20 #define PWRAP_MT8135_BRIDGE_INIT_DONE4          0x28
  21 #define PWRAP_MT8135_BRIDGE_INT_EN              0x38
  22 #define PWRAP_MT8135_BRIDGE_TIMER_EN            0x48
  23 #define PWRAP_MT8135_BRIDGE_WDT_UNIT            0x50
  24 #define PWRAP_MT8135_BRIDGE_WDT_SRC_EN          0x54
  25
  26 /* macro for wrapper status */
  27 #define PWRAP_GET_WACS_RDATA(x)         (((x) >> 0) & 0x0000ffff)
  28 #define PWRAP_GET_WACS_ARB_FSM(x)       (((x) >> 1) & 0x00000007)
  29 #define PWRAP_GET_WACS_FSM(x)           (((x) >> 16) & 0x00000007)
  30 #define PWRAP_GET_WACS_REQ(x)           (((x) >> 19) & 0x00000001)
  31 #define PWRAP_STATE_SYNC_IDLE0          BIT(20)
  32 #define PWRAP_STATE_INIT_DONE0          BIT(21)
  33 #define PWRAP_STATE_INIT_DONE1          BIT(15)
  34
  35 /* macro for WACS FSM */
  36 #define PWRAP_WACS_FSM_IDLE             0x00
  37 #define PWRAP_WACS_FSM_REQ              0x02
  38 #define PWRAP_WACS_FSM_WFDLE            0x04
  39 #define PWRAP_WACS_FSM_WFVLDCLR         0x06
  40 #define PWRAP_WACS_INIT_DONE            0x01
  41 #define PWRAP_WACS_WACS_SYNC_IDLE       0x01
  42 #define PWRAP_WACS_SYNC_BUSY            0x00
  43
  44 /* macro for device wrapper default value */
  45 #define PWRAP_DEW_READ_TEST_VAL         0x5aa5
  46 #define PWRAP_DEW_WRITE_TEST_VAL        0xa55a
  47
  48 /* macro for manual command */
  49 #define PWRAP_MAN_CMD_SPI_WRITE_NEW     (1 << 14)
  50 #define PWRAP_MAN_CMD_SPI_WRITE         (1 << 13)
  51 #define PWRAP_MAN_CMD_OP_CSH            (0x0 << 8)
  52 #define PWRAP_MAN_CMD_OP_CSL            (0x1 << 8)
  53 #define PWRAP_MAN_CMD_OP_CK             (0x2 << 8)
  54 #define PWRAP_MAN_CMD_OP_OUTS           (0x8 << 8)
  55 #define PWRAP_MAN_CMD_OP_OUTD           (0x9 << 8)
  56 #define PWRAP_MAN_CMD_OP_OUTQ           (0xa << 8)
  57
  58 /* macro for Watch Dog Timer Source */
  59 #define PWRAP_WDT_SRC_EN_STAUPD_TRIG            (1 << 25)
  60 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE        (1 << 20)
  61 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE        (1 << 6)
  62 #define PWRAP_WDT_SRC_MASK_ALL                  0xffffffff
  63 #define PWRAP_WDT_SRC_MASK_NO_STAUPD    ~(PWRAP_WDT_SRC_EN_STAUPD_TRIG | \
  64                                           PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \
  65                                           PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)
  66
  67 /* Group of bits used for shown slave capability */
  68 #define PWRAP_SLV_CAP_SPI       BIT(0)
  69 #define PWRAP_SLV_CAP_DUALIO    BIT(1)
  70 #define PWRAP_SLV_CAP_SECURITY  BIT(2)
  71 #define HAS_CAP(_c, _x) (((_c) & (_x)) == (_x))
  72
  73 /* Group of bits used for shown pwrap capability */
  74 #define PWRAP_CAP_BRIDGE        BIT(0)
  75 #define PWRAP_CAP_RESET         BIT(1)
  76 #define PWRAP_CAP_DCM           BIT(2)
  77 #define PWRAP_CAP_INT1_EN       BIT(3)
  78 #define PWRAP_CAP_WDT_SRC1      BIT(4)
  79 #define PWRAP_CAP_ARB           BIT(5)
  80
  81 /* defines for slave device wrapper registers */
  82 enum dew_regs {
  83         PWRAP_DEW_BASE,
  84         PWRAP_DEW_DIO_EN,
  85         PWRAP_DEW_READ_TEST,
  86         PWRAP_DEW_WRITE_TEST,
  87         PWRAP_DEW_CRC_EN,
  88         PWRAP_DEW_CRC_VAL,
  89         PWRAP_DEW_MON_GRP_SEL,
  90         PWRAP_DEW_CIPHER_KEY_SEL,
  91         PWRAP_DEW_CIPHER_IV_SEL,
  92         PWRAP_DEW_CIPHER_RDY,
  93         PWRAP_DEW_CIPHER_MODE,
  94         PWRAP_DEW_CIPHER_SWRST,
  95
  96         /* MT6323 only regs */
  97         PWRAP_DEW_CIPHER_EN,
  98         PWRAP_DEW_RDDMY_NO,
  99
 100         /* MT6358 only regs */
 101         PWRAP_SMT_CON1,
 102         PWRAP_DRV_CON1,
 103         PWRAP_FILTER_CON0,
 104         PWRAP_GPIO_PULLEN0_CLR,
 105         PWRAP_RG_SPI_CON0,
 106         PWRAP_RG_SPI_RECORD0,
 107         PWRAP_RG_SPI_CON2,
 108         PWRAP_RG_SPI_CON3,
 109         PWRAP_RG_SPI_CON4,
 110         PWRAP_RG_SPI_CON5,
 111         PWRAP_RG_SPI_CON6,
 112         PWRAP_RG_SPI_CON7,
 113         PWRAP_RG_SPI_CON8,
 114         PWRAP_RG_SPI_CON13,
 115         PWRAP_SPISLV_KEY,
 116
 117         /* MT6359 only regs */
 118         PWRAP_DEW_CRC_SWRST,
 119         PWRAP_DEW_RG_EN_RECORD,
 120         PWRAP_DEW_RECORD_CMD0,
 121         PWRAP_DEW_RECORD_CMD1,
 122         PWRAP_DEW_RECORD_CMD2,
 123         PWRAP_DEW_RECORD_CMD3,
 124         PWRAP_DEW_RECORD_CMD4,
 125         PWRAP_DEW_RECORD_CMD5,
 126         PWRAP_DEW_RECORD_WDATA0,
 127         PWRAP_DEW_RECORD_WDATA1,
 128         PWRAP_DEW_RECORD_WDATA2,
 129         PWRAP_DEW_RECORD_WDATA3,
 130         PWRAP_DEW_RECORD_WDATA4,
 131         PWRAP_DEW_RECORD_WDATA5,
 132         PWRAP_DEW_RG_ADDR_TARGET,
 133         PWRAP_DEW_RG_ADDR_MASK,
 134         PWRAP_DEW_RG_WDATA_TARGET,
 135         PWRAP_DEW_RG_WDATA_MASK,
 136         PWRAP_DEW_RG_SPI_RECORD_CLR,
 137         PWRAP_DEW_RG_CMD_ALERT_CLR,
 138
 139         /* MT6397 only regs */
 140         PWRAP_DEW_EVENT_OUT_EN,
 141         PWRAP_DEW_EVENT_SRC_EN,
 142         PWRAP_DEW_EVENT_SRC,
 143         PWRAP_DEW_EVENT_FLAG,
 144         PWRAP_DEW_MON_FLAG_SEL,
 145         PWRAP_DEW_EVENT_TEST,
 146         PWRAP_DEW_CIPHER_LOAD,
 147         PWRAP_DEW_CIPHER_START,
 148 };
 149
 150 static const u32 mt6323_regs[] = {
 151         [PWRAP_DEW_BASE] =              0x0000,
 152         [PWRAP_DEW_DIO_EN] =            0x018a,
 153         [PWRAP_DEW_READ_TEST] =         0x018c,
 154         [PWRAP_DEW_WRITE_TEST] =        0x018e,
 155         [PWRAP_DEW_CRC_EN] =            0x0192,
 156         [PWRAP_DEW_CRC_VAL] =           0x0194,
 157         [PWRAP_DEW_MON_GRP_SEL] =       0x0196,
 158         [PWRAP_DEW_CIPHER_KEY_SEL] =    0x0198,
 159         [PWRAP_DEW_CIPHER_IV_SEL] =     0x019a,
 160         [PWRAP_DEW_CIPHER_EN] =         0x019c,
 161         [PWRAP_DEW_CIPHER_RDY] =        0x019e,
 162         [PWRAP_DEW_CIPHER_MODE] =       0x01a0,
 163         [PWRAP_DEW_CIPHER_SWRST] =      0x01a2,
 164         [PWRAP_DEW_RDDMY_NO] =          0x01a4,
 165 };
 166
 167 static const u32 mt6351_regs[] = {
 168         [PWRAP_DEW_DIO_EN] =            0x02F2,
 169         [PWRAP_DEW_READ_TEST] =         0x02F4,
 170         [PWRAP_DEW_WRITE_TEST] =        0x02F6,
 171         [PWRAP_DEW_CRC_EN] =            0x02FA,
 172         [PWRAP_DEW_CRC_VAL] =           0x02FC,
 173         [PWRAP_DEW_CIPHER_KEY_SEL] =    0x0300,
 174         [PWRAP_DEW_CIPHER_IV_SEL] =     0x0302,
 175         [PWRAP_DEW_CIPHER_EN] =         0x0304,
 176         [PWRAP_DEW_CIPHER_RDY] =        0x0306,
 177         [PWRAP_DEW_CIPHER_MODE] =       0x0308,
 178         [PWRAP_DEW_CIPHER_SWRST] =      0x030A,
 179         [PWRAP_DEW_RDDMY_NO] =          0x030C,
 180 };
 181
 182 static const u32 mt6357_regs[] = {
 183         [PWRAP_DEW_DIO_EN] =            0x040A,
 184         [PWRAP_DEW_READ_TEST] =         0x040C,
 185         [PWRAP_DEW_WRITE_TEST] =        0x040E,
 186         [PWRAP_DEW_CRC_EN] =            0x0412,
 187         [PWRAP_DEW_CRC_VAL] =           0x0414,
 188         [PWRAP_DEW_CIPHER_KEY_SEL] =    0x0418,
 189         [PWRAP_DEW_CIPHER_IV_SEL] =     0x041A,
 190         [PWRAP_DEW_CIPHER_EN] =         0x041C,
 191         [PWRAP_DEW_CIPHER_RDY] =        0x041E,
 192         [PWRAP_DEW_CIPHER_MODE] =       0x0420,
 193         [PWRAP_DEW_CIPHER_SWRST] =      0x0422,
 194         [PWRAP_DEW_RDDMY_NO] =          0x0424,
 195 };
 196
 197 static const u32 mt6358_regs[] = {
 198         [PWRAP_SMT_CON1] =              0x0030,
 199         [PWRAP_DRV_CON1] =              0x0038,
 200         [PWRAP_FILTER_CON0] =           0x0040,
 201         [PWRAP_GPIO_PULLEN0_CLR] =      0x0098,
 202         [PWRAP_RG_SPI_CON0] =           0x0408,
 203         [PWRAP_RG_SPI_RECORD0] =        0x040a,
 204         [PWRAP_DEW_DIO_EN] =            0x040c,
 205         [PWRAP_DEW_READ_TEST]   =       0x040e,
 206         [PWRAP_DEW_WRITE_TEST]  =       0x0410,
 207         [PWRAP_DEW_CRC_EN] =            0x0414,
 208         [PWRAP_DEW_CIPHER_KEY_SEL] =    0x041a,
 209         [PWRAP_DEW_CIPHER_IV_SEL] =     0x041c,
 210         [PWRAP_DEW_CIPHER_EN]   =       0x041e,
 211         [PWRAP_DEW_CIPHER_RDY] =        0x0420,
 212         [PWRAP_DEW_CIPHER_MODE] =       0x0422,
 213         [PWRAP_DEW_CIPHER_SWRST] =      0x0424,
 214         [PWRAP_RG_SPI_CON2] =           0x0432,
 215         [PWRAP_RG_SPI_CON3] =           0x0434,
 216         [PWRAP_RG_SPI_CON4] =           0x0436,
 217         [PWRAP_RG_SPI_CON5] =           0x0438,
 218         [PWRAP_RG_SPI_CON6] =           0x043a,
 219         [PWRAP_RG_SPI_CON7] =           0x043c,
 220         [PWRAP_RG_SPI_CON8] =           0x043e,
 221         [PWRAP_RG_SPI_CON13] =          0x0448,
 222         [PWRAP_SPISLV_KEY] =            0x044a,
 223 };
 224
 225 static const u32 mt6359_regs[] = {
 226         [PWRAP_DEW_RG_EN_RECORD] =      0x040a,
 227         [PWRAP_DEW_DIO_EN] =            0x040c,
 228         [PWRAP_DEW_READ_TEST] =         0x040e,
 229         [PWRAP_DEW_WRITE_TEST] =        0x0410,
 230         [PWRAP_DEW_CRC_SWRST] =         0x0412,
 231         [PWRAP_DEW_CRC_EN] =            0x0414,
 232         [PWRAP_DEW_CRC_VAL] =           0x0416,
 233         [PWRAP_DEW_CIPHER_KEY_SEL] =    0x0418,
 234         [PWRAP_DEW_CIPHER_IV_SEL] =     0x041a,
 235         [PWRAP_DEW_CIPHER_EN] =         0x041c,
 236         [PWRAP_DEW_CIPHER_RDY] =        0x041e,
 237         [PWRAP_DEW_CIPHER_MODE] =       0x0420,
 238         [PWRAP_DEW_CIPHER_SWRST] =      0x0422,
 239         [PWRAP_DEW_RDDMY_NO] =          0x0424,
 240         [PWRAP_DEW_RECORD_CMD0] =       0x0428,
 241         [PWRAP_DEW_RECORD_CMD1] =       0x042a,
 242         [PWRAP_DEW_RECORD_CMD2] =       0x042c,
 243         [PWRAP_DEW_RECORD_CMD3] =       0x042e,
 244         [PWRAP_DEW_RECORD_CMD4] =       0x0430,
 245         [PWRAP_DEW_RECORD_CMD5] =       0x0432,
 246         [PWRAP_DEW_RECORD_WDATA0] =     0x0434,
 247         [PWRAP_DEW_RECORD_WDATA1] =     0x0436,
 248         [PWRAP_DEW_RECORD_WDATA2] =     0x0438,
 249         [PWRAP_DEW_RECORD_WDATA3] =     0x043a,
 250         [PWRAP_DEW_RECORD_WDATA4] =     0x043c,
 251         [PWRAP_DEW_RECORD_WDATA5] =     0x043e,
 252         [PWRAP_DEW_RG_ADDR_TARGET] =    0x0440,
 253         [PWRAP_DEW_RG_ADDR_MASK] =      0x0442,
 254         [PWRAP_DEW_RG_WDATA_TARGET] =   0x0444,
 255         [PWRAP_DEW_RG_WDATA_MASK] =     0x0446,
 256         [PWRAP_DEW_RG_SPI_RECORD_CLR] = 0x0448,
 257         [PWRAP_DEW_RG_CMD_ALERT_CLR] =  0x0448,
 258         [PWRAP_SPISLV_KEY] =            0x044a,
 259 };
 260
 261 static const u32 mt6397_regs[] = {
 262         [PWRAP_DEW_BASE] =              0xbc00,
 263         [PWRAP_DEW_EVENT_OUT_EN] =      0xbc00,
 264         [PWRAP_DEW_DIO_EN] =            0xbc02,
 265         [PWRAP_DEW_EVENT_SRC_EN] =      0xbc04,
 266         [PWRAP_DEW_EVENT_SRC] =         0xbc06,
 267         [PWRAP_DEW_EVENT_FLAG] =        0xbc08,
 268         [PWRAP_DEW_READ_TEST] =         0xbc0a,
 269         [PWRAP_DEW_WRITE_TEST] =        0xbc0c,
 270         [PWRAP_DEW_CRC_EN] =            0xbc0e,
 271         [PWRAP_DEW_CRC_VAL] =           0xbc10,
 272         [PWRAP_DEW_MON_GRP_SEL] =       0xbc12,
 273         [PWRAP_DEW_MON_FLAG_SEL] =      0xbc14,
 274         [PWRAP_DEW_EVENT_TEST] =        0xbc16,
 275         [PWRAP_DEW_CIPHER_KEY_SEL] =    0xbc18,
 276         [PWRAP_DEW_CIPHER_IV_SEL] =     0xbc1a,
 277         [PWRAP_DEW_CIPHER_LOAD] =       0xbc1c,
 278         [PWRAP_DEW_CIPHER_START] =      0xbc1e,
 279         [PWRAP_DEW_CIPHER_RDY] =        0xbc20,
 280         [PWRAP_DEW_CIPHER_MODE] =       0xbc22,
 281         [PWRAP_DEW_CIPHER_SWRST] =      0xbc24,
 282 };
 283
 284 enum pwrap_regs {
 285         PWRAP_MUX_SEL,
 286         PWRAP_WRAP_EN,
 287         PWRAP_DIO_EN,
 288         PWRAP_SIDLY,
 289         PWRAP_CSHEXT_WRITE,
 290         PWRAP_CSHEXT_READ,
 291         PWRAP_CSLEXT_START,
 292         PWRAP_CSLEXT_END,
 293         PWRAP_STAUPD_PRD,
 294         PWRAP_STAUPD_GRPEN,
 295         PWRAP_STAUPD_MAN_TRIG,
 296         PWRAP_STAUPD_STA,
 297         PWRAP_WRAP_STA,
 298         PWRAP_HARB_INIT,
 299         PWRAP_HARB_HPRIO,
 300         PWRAP_HIPRIO_ARB_EN,
 301         PWRAP_HARB_STA0,
 302         PWRAP_HARB_STA1,
 303         PWRAP_MAN_EN,
 304         PWRAP_MAN_CMD,
 305         PWRAP_MAN_RDATA,
 306         PWRAP_MAN_VLDCLR,
 307         PWRAP_WACS0_EN,
 308         PWRAP_INIT_DONE0,
 309         PWRAP_WACS0_CMD,
 310         PWRAP_WACS0_RDATA,
 311         PWRAP_WACS0_VLDCLR,
 312         PWRAP_WACS1_EN,
 313         PWRAP_INIT_DONE1,
 314         PWRAP_WACS1_CMD,
 315         PWRAP_WACS1_RDATA,
 316         PWRAP_WACS1_VLDCLR,
 317         PWRAP_WACS2_EN,
 318         PWRAP_INIT_DONE2,
 319         PWRAP_WACS2_CMD,
 320         PWRAP_WACS2_RDATA,
 321         PWRAP_WACS2_VLDCLR,
 322         PWRAP_INT_EN,
 323         PWRAP_INT_FLG_RAW,
 324         PWRAP_INT_FLG,
 325         PWRAP_INT_CLR,
 326         PWRAP_SIG_ADR,
 327         PWRAP_SIG_MODE,
 328         PWRAP_SIG_VALUE,
 329         PWRAP_SIG_ERRVAL,
 330         PWRAP_CRC_EN,
 331         PWRAP_TIMER_EN,
 332         PWRAP_TIMER_STA,
 333         PWRAP_WDT_UNIT,
 334         PWRAP_WDT_SRC_EN,
 335         PWRAP_WDT_FLG,
 336         PWRAP_DEBUG_INT_SEL,
 337         PWRAP_CIPHER_KEY_SEL,
 338         PWRAP_CIPHER_IV_SEL,
 339         PWRAP_CIPHER_RDY,
 340         PWRAP_CIPHER_MODE,
 341         PWRAP_CIPHER_SWRST,
 342         PWRAP_DCM_EN,
 343         PWRAP_DCM_DBC_PRD,
 344         PWRAP_EINT_STA0_ADR,
 345         PWRAP_EINT_STA1_ADR,
 346         PWRAP_SWINF_2_WDATA_31_0,
 347         PWRAP_SWINF_2_RDATA_31_0,
 348
 349         /* MT2701 only regs */
 350         PWRAP_ADC_CMD_ADDR,
 351         PWRAP_PWRAP_ADC_CMD,
 352         PWRAP_ADC_RDY_ADDR,
 353         PWRAP_ADC_RDATA_ADDR1,
 354         PWRAP_ADC_RDATA_ADDR2,
 355
 356         /* MT7622 only regs */
 357         PWRAP_STA,
 358         PWRAP_CLR,
 359         PWRAP_DVFS_ADR8,
 360         PWRAP_DVFS_WDATA8,
 361         PWRAP_DVFS_ADR9,
 362         PWRAP_DVFS_WDATA9,
 363         PWRAP_DVFS_ADR10,
 364         PWRAP_DVFS_WDATA10,
 365         PWRAP_DVFS_ADR11,
 366         PWRAP_DVFS_WDATA11,
 367         PWRAP_DVFS_ADR12,
 368         PWRAP_DVFS_WDATA12,
 369         PWRAP_DVFS_ADR13,
 370         PWRAP_DVFS_WDATA13,
 371         PWRAP_DVFS_ADR14,
 372         PWRAP_DVFS_WDATA14,
 373         PWRAP_DVFS_ADR15,
 374         PWRAP_DVFS_WDATA15,
 375         PWRAP_EXT_CK,
 376         PWRAP_ADC_RDATA_ADDR,
 377         PWRAP_GPS_STA,
 378         PWRAP_SW_RST,
 379         PWRAP_DVFS_STEP_CTRL0,
 380         PWRAP_DVFS_STEP_CTRL1,
 381         PWRAP_DVFS_STEP_CTRL2,
 382         PWRAP_SPI2_CTRL,
 383
 384         /* MT8135 only regs */
 385         PWRAP_CSHEXT,
 386         PWRAP_EVENT_IN_EN,
 387         PWRAP_EVENT_DST_EN,
 388         PWRAP_RRARB_INIT,
 389         PWRAP_RRARB_EN,
 390         PWRAP_RRARB_STA0,
 391         PWRAP_RRARB_STA1,
 392         PWRAP_EVENT_STA,
 393         PWRAP_EVENT_STACLR,
 394         PWRAP_CIPHER_LOAD,
 395         PWRAP_CIPHER_START,
 396
 397         /* MT8173 only regs */
 398         PWRAP_RDDMY,
 399         PWRAP_SI_CK_CON,
 400         PWRAP_DVFS_ADR0,
 401         PWRAP_DVFS_WDATA0,
 402         PWRAP_DVFS_ADR1,
 403         PWRAP_DVFS_WDATA1,
 404         PWRAP_DVFS_ADR2,
 405         PWRAP_DVFS_WDATA2,
 406         PWRAP_DVFS_ADR3,
 407         PWRAP_DVFS_WDATA3,
 408         PWRAP_DVFS_ADR4,
 409         PWRAP_DVFS_WDATA4,
 410         PWRAP_DVFS_ADR5,
 411         PWRAP_DVFS_WDATA5,
 412         PWRAP_DVFS_ADR6,
 413         PWRAP_DVFS_WDATA6,
 414         PWRAP_DVFS_ADR7,
 415         PWRAP_DVFS_WDATA7,
 416         PWRAP_SPMINF_STA,
 417         PWRAP_CIPHER_EN,
 418
 419         /* MT8183 only regs */
 420         PWRAP_SI_SAMPLE_CTRL,
 421         PWRAP_CSLEXT_WRITE,
 422         PWRAP_CSLEXT_READ,
 423         PWRAP_EXT_CK_WRITE,
 424         PWRAP_STAUPD_CTRL,
 425         PWRAP_WACS_P2P_EN,
 426         PWRAP_INIT_DONE_P2P,
 427         PWRAP_WACS_MD32_EN,
 428         PWRAP_INIT_DONE_MD32,
 429         PWRAP_INT1_EN,
 430         PWRAP_INT1_FLG,
 431         PWRAP_INT1_CLR,
 432         PWRAP_WDT_SRC_EN_1,
 433         PWRAP_INT_GPS_AUXADC_CMD_ADDR,
 434         PWRAP_INT_GPS_AUXADC_CMD,
 435         PWRAP_INT_GPS_AUXADC_RDATA_ADDR,
 436         PWRAP_EXT_GPS_AUXADC_RDATA_ADDR,
 437         PWRAP_GPSINF_0_STA,
 438         PWRAP_GPSINF_1_STA,
 439
 440         /* MT8516 only regs */
 441         PWRAP_OP_TYPE,
 442         PWRAP_MSB_FIRST,
 443 };
 444
 445 static int mt2701_regs[] = {
 446         [PWRAP_MUX_SEL] =               0x0,
 447         [PWRAP_WRAP_EN] =               0x4,
 448         [PWRAP_DIO_EN] =                0x8,
 449         [PWRAP_SIDLY] =                 0xc,
 450         [PWRAP_RDDMY] =                 0x18,
 451         [PWRAP_SI_CK_CON] =             0x1c,
 452         [PWRAP_CSHEXT_WRITE] =          0x20,
 453         [PWRAP_CSHEXT_READ] =           0x24,
 454         [PWRAP_CSLEXT_START] =          0x28,
 455         [PWRAP_CSLEXT_END] =            0x2c,
 456         [PWRAP_STAUPD_PRD] =            0x30,
 457         [PWRAP_STAUPD_GRPEN] =          0x34,
 458         [PWRAP_STAUPD_MAN_TRIG] =       0x38,
 459         [PWRAP_STAUPD_STA] =            0x3c,
 460         [PWRAP_WRAP_STA] =              0x44,
 461         [PWRAP_HARB_INIT] =             0x48,
 462         [PWRAP_HARB_HPRIO] =            0x4c,
 463         [PWRAP_HIPRIO_ARB_EN] =         0x50,
 464         [PWRAP_HARB_STA0] =             0x54,
 465         [PWRAP_HARB_STA1] =             0x58,
 466         [PWRAP_MAN_EN] =                0x5c,
 467         [PWRAP_MAN_CMD] =               0x60,
 468         [PWRAP_MAN_RDATA] =             0x64,
 469         [PWRAP_MAN_VLDCLR] =            0x68,
 470         [PWRAP_WACS0_EN] =              0x6c,
 471         [PWRAP_INIT_DONE0] =            0x70,
 472         [PWRAP_WACS0_CMD] =             0x74,
 473         [PWRAP_WACS0_RDATA] =           0x78,
 474         [PWRAP_WACS0_VLDCLR] =          0x7c,
 475         [PWRAP_WACS1_EN] =              0x80,
 476         [PWRAP_INIT_DONE1] =            0x84,
 477         [PWRAP_WACS1_CMD] =             0x88,
 478         [PWRAP_WACS1_RDATA] =           0x8c,
 479         [PWRAP_WACS1_VLDCLR] =          0x90,
 480         [PWRAP_WACS2_EN] =              0x94,
 481         [PWRAP_INIT_DONE2] =            0x98,
 482         [PWRAP_WACS2_CMD] =             0x9c,
 483         [PWRAP_WACS2_RDATA] =           0xa0,
 484         [PWRAP_WACS2_VLDCLR] =          0xa4,
 485         [PWRAP_INT_EN] =                0xa8,
 486         [PWRAP_INT_FLG_RAW] =           0xac,
 487         [PWRAP_INT_FLG] =               0xb0,
 488         [PWRAP_INT_CLR] =               0xb4,
 489         [PWRAP_SIG_ADR] =               0xb8,
 490         [PWRAP_SIG_MODE] =              0xbc,
 491         [PWRAP_SIG_VALUE] =             0xc0,
 492         [PWRAP_SIG_ERRVAL] =            0xc4,
 493         [PWRAP_CRC_EN] =                0xc8,
 494         [PWRAP_TIMER_EN] =              0xcc,
 495         [PWRAP_TIMER_STA] =             0xd0,
 496         [PWRAP_WDT_UNIT] =              0xd4,
 497         [PWRAP_WDT_SRC_EN] =            0xd8,
 498         [PWRAP_WDT_FLG] =               0xdc,
 499         [PWRAP_DEBUG_INT_SEL] =         0xe0,
 500         [PWRAP_DVFS_ADR0] =             0xe4,
 501         [PWRAP_DVFS_WDATA0] =           0xe8,
 502         [PWRAP_DVFS_ADR1] =             0xec,
 503         [PWRAP_DVFS_WDATA1] =           0xf0,
 504         [PWRAP_DVFS_ADR2] =             0xf4,
 505         [PWRAP_DVFS_WDATA2] =           0xf8,
 506         [PWRAP_DVFS_ADR3] =             0xfc,
 507         [PWRAP_DVFS_WDATA3] =           0x100,
 508         [PWRAP_DVFS_ADR4] =             0x104,
 509         [PWRAP_DVFS_WDATA4] =           0x108,
 510         [PWRAP_DVFS_ADR5] =             0x10c,
 511         [PWRAP_DVFS_WDATA5] =           0x110,
 512         [PWRAP_DVFS_ADR6] =             0x114,
 513         [PWRAP_DVFS_WDATA6] =           0x118,
 514         [PWRAP_DVFS_ADR7] =             0x11c,
 515         [PWRAP_DVFS_WDATA7] =           0x120,
 516         [PWRAP_CIPHER_KEY_SEL] =        0x124,
 517         [PWRAP_CIPHER_IV_SEL] =         0x128,
 518         [PWRAP_CIPHER_EN] =             0x12c,
 519         [PWRAP_CIPHER_RDY] =            0x130,
 520         [PWRAP_CIPHER_MODE] =           0x134,
 521         [PWRAP_CIPHER_SWRST] =          0x138,
 522         [PWRAP_DCM_EN] =                0x13c,
 523         [PWRAP_DCM_DBC_PRD] =           0x140,
 524         [PWRAP_ADC_CMD_ADDR] =          0x144,
 525         [PWRAP_PWRAP_ADC_CMD] =         0x148,
 526         [PWRAP_ADC_RDY_ADDR] =          0x14c,
 527         [PWRAP_ADC_RDATA_ADDR1] =       0x150,
 528         [PWRAP_ADC_RDATA_ADDR2] =       0x154,
 529 };
 530
 531 static int mt6765_regs[] = {
 532         [PWRAP_MUX_SEL] =               0x0,
 533         [PWRAP_WRAP_EN] =               0x4,
 534         [PWRAP_DIO_EN] =                0x8,
 535         [PWRAP_RDDMY] =                 0x20,
 536         [PWRAP_CSHEXT_WRITE] =          0x24,
 537         [PWRAP_CSHEXT_READ] =           0x28,
 538         [PWRAP_CSLEXT_START] =          0x2C,
 539         [PWRAP_CSLEXT_END] =            0x30,
 540         [PWRAP_STAUPD_PRD] =            0x3C,
 541         [PWRAP_HARB_HPRIO] =            0x68,
 542         [PWRAP_HIPRIO_ARB_EN] =         0x6C,
 543         [PWRAP_MAN_EN] =                0x7C,
 544         [PWRAP_MAN_CMD] =               0x80,
 545         [PWRAP_WACS0_EN] =              0x8C,
 546         [PWRAP_WACS1_EN] =              0x94,
 547         [PWRAP_WACS2_EN] =              0x9C,
 548         [PWRAP_INIT_DONE2] =            0xA0,
 549         [PWRAP_WACS2_CMD] =             0xC20,
 550         [PWRAP_WACS2_RDATA] =           0xC24,
 551         [PWRAP_WACS2_VLDCLR] =          0xC28,
 552         [PWRAP_INT_EN] =                0xB4,
 553         [PWRAP_INT_FLG_RAW] =           0xB8,
 554         [PWRAP_INT_FLG] =               0xBC,
 555         [PWRAP_INT_CLR] =               0xC0,
 556         [PWRAP_TIMER_EN] =              0xE8,
 557         [PWRAP_WDT_UNIT] =              0xF0,
 558         [PWRAP_WDT_SRC_EN] =            0xF4,
 559         [PWRAP_DCM_EN] =                0x1DC,
 560         [PWRAP_DCM_DBC_PRD] =           0x1E0,
 561 };
 562
 563 static int mt6779_regs[] = {
 564         [PWRAP_MUX_SEL] =               0x0,
 565         [PWRAP_WRAP_EN] =               0x4,
 566         [PWRAP_DIO_EN] =                0x8,
 567         [PWRAP_RDDMY] =                 0x20,
 568         [PWRAP_CSHEXT_WRITE] =          0x24,
 569         [PWRAP_CSHEXT_READ] =           0x28,
 570         [PWRAP_CSLEXT_WRITE] =          0x2C,
 571         [PWRAP_CSLEXT_READ] =           0x30,
 572         [PWRAP_EXT_CK_WRITE] =          0x34,
 573         [PWRAP_STAUPD_CTRL] =           0x3C,
 574         [PWRAP_STAUPD_GRPEN] =          0x40,
 575         [PWRAP_EINT_STA0_ADR] =         0x44,
 576         [PWRAP_HARB_HPRIO] =            0x68,
 577         [PWRAP_HIPRIO_ARB_EN] =         0x6C,
 578         [PWRAP_MAN_EN] =                0x7C,
 579         [PWRAP_MAN_CMD] =               0x80,
 580         [PWRAP_WACS0_EN] =              0x8C,
 581         [PWRAP_INIT_DONE0] =            0x90,
 582         [PWRAP_WACS1_EN] =              0x94,
 583         [PWRAP_WACS2_EN] =              0x9C,
 584         [PWRAP_INIT_DONE1] =            0x98,
 585         [PWRAP_INIT_DONE2] =            0xA0,
 586         [PWRAP_INT_EN] =                0xBC,
 587         [PWRAP_INT_FLG_RAW] =           0xC0,
 588         [PWRAP_INT_FLG] =               0xC4,
 589         [PWRAP_INT_CLR] =               0xC8,
 590         [PWRAP_INT1_EN] =               0xCC,
 591         [PWRAP_INT1_FLG] =              0xD4,
 592         [PWRAP_INT1_CLR] =              0xD8,
 593         [PWRAP_TIMER_EN] =              0xF0,
 594         [PWRAP_WDT_UNIT] =              0xF8,
 595         [PWRAP_WDT_SRC_EN] =            0xFC,
 596         [PWRAP_WDT_SRC_EN_1] =          0x100,
 597         [PWRAP_WACS2_CMD] =             0xC20,
 598         [PWRAP_WACS2_RDATA] =           0xC24,
 599         [PWRAP_WACS2_VLDCLR] =          0xC28,
 600 };
 601
 602 static int mt6797_regs[] = {
 603         [PWRAP_MUX_SEL] =               0x0,
 604         [PWRAP_WRAP_EN] =               0x4,
 605         [PWRAP_DIO_EN] =                0x8,
 606         [PWRAP_SIDLY] =                 0xC,
 607         [PWRAP_RDDMY] =                 0x10,
 608         [PWRAP_CSHEXT_WRITE] =          0x18,
 609         [PWRAP_CSHEXT_READ] =           0x1C,
 610         [PWRAP_CSLEXT_START] =          0x20,
 611         [PWRAP_CSLEXT_END] =            0x24,
 612         [PWRAP_STAUPD_PRD] =            0x28,
 613         [PWRAP_HARB_HPRIO] =            0x50,
 614         [PWRAP_HIPRIO_ARB_EN] =         0x54,
 615         [PWRAP_MAN_EN] =                0x60,
 616         [PWRAP_MAN_CMD] =               0x64,
 617         [PWRAP_WACS0_EN] =              0x70,
 618         [PWRAP_WACS1_EN] =              0x84,
 619         [PWRAP_WACS2_EN] =              0x98,
 620         [PWRAP_INIT_DONE2] =            0x9C,
 621         [PWRAP_WACS2_CMD] =             0xA0,
 622         [PWRAP_WACS2_RDATA] =           0xA4,
 623         [PWRAP_WACS2_VLDCLR] =          0xA8,
 624         [PWRAP_INT_EN] =                0xC0,
 625         [PWRAP_INT_FLG_RAW] =           0xC4,
 626         [PWRAP_INT_FLG] =               0xC8,
 627         [PWRAP_INT_CLR] =               0xCC,
 628         [PWRAP_TIMER_EN] =              0xF4,
 629         [PWRAP_WDT_UNIT] =              0xFC,
 630         [PWRAP_WDT_SRC_EN] =            0x100,
 631         [PWRAP_DCM_EN] =                0x1CC,
 632         [PWRAP_DCM_DBC_PRD] =           0x1D4,
 633 };
 634
 635 static int mt6873_regs[] = {
 636         [PWRAP_INIT_DONE2] =            0x0,
 637         [PWRAP_TIMER_EN] =              0x3E0,
 638         [PWRAP_INT_EN] =                0x448,
 639         [PWRAP_WACS2_CMD] =             0xC80,
 640         [PWRAP_SWINF_2_WDATA_31_0] =    0xC84,
 641         [PWRAP_SWINF_2_RDATA_31_0] =    0xC94,
 642         [PWRAP_WACS2_VLDCLR] =          0xCA4,
 643         [PWRAP_WACS2_RDATA] =           0xCA8,
 644 };
 645
 646 static int mt7622_regs[] = {
 647         [PWRAP_MUX_SEL] =               0x0,
 648         [PWRAP_WRAP_EN] =               0x4,
 649         [PWRAP_DIO_EN] =                0x8,
 650         [PWRAP_SIDLY] =                 0xC,
 651         [PWRAP_RDDMY] =                 0x10,
 652         [PWRAP_SI_CK_CON] =             0x14,
 653         [PWRAP_CSHEXT_WRITE] =          0x18,
 654         [PWRAP_CSHEXT_READ] =           0x1C,
 655         [PWRAP_CSLEXT_START] =          0x20,
 656         [PWRAP_CSLEXT_END] =            0x24,
 657         [PWRAP_STAUPD_PRD] =            0x28,
 658         [PWRAP_STAUPD_GRPEN] =          0x2C,
 659         [PWRAP_EINT_STA0_ADR] =         0x30,
 660         [PWRAP_EINT_STA1_ADR] =         0x34,
 661         [PWRAP_STA] =                   0x38,
 662         [PWRAP_CLR] =                   0x3C,
 663         [PWRAP_STAUPD_MAN_TRIG] =       0x40,
 664         [PWRAP_STAUPD_STA] =            0x44,
 665         [PWRAP_WRAP_STA] =              0x48,
 666         [PWRAP_HARB_INIT] =             0x4C,
 667         [PWRAP_HARB_HPRIO] =            0x50,
 668         [PWRAP_HIPRIO_ARB_EN] =         0x54,
 669         [PWRAP_HARB_STA0] =             0x58,
 670         [PWRAP_HARB_STA1] =             0x5C,
 671         [PWRAP_MAN_EN] =                0x60,
 672         [PWRAP_MAN_CMD] =               0x64,
 673         [PWRAP_MAN_RDATA] =             0x68,
 674         [PWRAP_MAN_VLDCLR] =            0x6C,
 675         [PWRAP_WACS0_EN] =              0x70,
 676         [PWRAP_INIT_DONE0] =            0x74,
 677         [PWRAP_WACS0_CMD] =             0x78,
 678         [PWRAP_WACS0_RDATA] =           0x7C,
 679         [PWRAP_WACS0_VLDCLR] =          0x80,
 680         [PWRAP_WACS1_EN] =              0x84,
 681         [PWRAP_INIT_DONE1] =            0x88,
 682         [PWRAP_WACS1_CMD] =             0x8C,
 683         [PWRAP_WACS1_RDATA] =           0x90,
 684         [PWRAP_WACS1_VLDCLR] =          0x94,
 685         [PWRAP_WACS2_EN] =              0x98,
 686         [PWRAP_INIT_DONE2] =            0x9C,
 687         [PWRAP_WACS2_CMD] =             0xA0,
 688         [PWRAP_WACS2_RDATA] =           0xA4,
 689         [PWRAP_WACS2_VLDCLR] =          0xA8,
 690         [PWRAP_INT_EN] =                0xAC,
 691         [PWRAP_INT_FLG_RAW] =           0xB0,
 692         [PWRAP_INT_FLG] =               0xB4,
 693         [PWRAP_INT_CLR] =               0xB8,
 694         [PWRAP_SIG_ADR] =               0xBC,
 695         [PWRAP_SIG_MODE] =              0xC0,
 696         [PWRAP_SIG_VALUE] =             0xC4,
 697         [PWRAP_SIG_ERRVAL] =            0xC8,
 698         [PWRAP_CRC_EN] =                0xCC,
 699         [PWRAP_TIMER_EN] =              0xD0,
 700         [PWRAP_TIMER_STA] =             0xD4,
 701         [PWRAP_WDT_UNIT] =              0xD8,
 702         [PWRAP_WDT_SRC_EN] =            0xDC,
 703         [PWRAP_WDT_FLG] =               0xE0,
 704         [PWRAP_DEBUG_INT_SEL] =         0xE4,
 705         [PWRAP_DVFS_ADR0] =             0xE8,
 706         [PWRAP_DVFS_WDATA0] =           0xEC,
 707         [PWRAP_DVFS_ADR1] =             0xF0,
 708         [PWRAP_DVFS_WDATA1] =           0xF4,
 709         [PWRAP_DVFS_ADR2] =             0xF8,
 710         [PWRAP_DVFS_WDATA2] =           0xFC,
 711         [PWRAP_DVFS_ADR3] =             0x100,
 712         [PWRAP_DVFS_WDATA3] =           0x104,
 713         [PWRAP_DVFS_ADR4] =             0x108,
 714         [PWRAP_DVFS_WDATA4] =           0x10C,
 715         [PWRAP_DVFS_ADR5] =             0x110,
 716         [PWRAP_DVFS_WDATA5] =           0x114,
 717         [PWRAP_DVFS_ADR6] =             0x118,
 718         [PWRAP_DVFS_WDATA6] =           0x11C,
 719         [PWRAP_DVFS_ADR7] =             0x120,
 720         [PWRAP_DVFS_WDATA7] =           0x124,
 721         [PWRAP_DVFS_ADR8] =             0x128,
 722         [PWRAP_DVFS_WDATA8] =           0x12C,
 723         [PWRAP_DVFS_ADR9] =             0x130,
 724         [PWRAP_DVFS_WDATA9] =           0x134,
 725         [PWRAP_DVFS_ADR10] =            0x138,
 726         [PWRAP_DVFS_WDATA10] =          0x13C,
 727         [PWRAP_DVFS_ADR11] =            0x140,
 728         [PWRAP_DVFS_WDATA11] =          0x144,
 729         [PWRAP_DVFS_ADR12] =            0x148,
 730         [PWRAP_DVFS_WDATA12] =          0x14C,
 731         [PWRAP_DVFS_ADR13] =            0x150,
 732         [PWRAP_DVFS_WDATA13] =          0x154,
 733         [PWRAP_DVFS_ADR14] =            0x158,
 734         [PWRAP_DVFS_WDATA14] =          0x15C,
 735         [PWRAP_DVFS_ADR15] =            0x160,
 736         [PWRAP_DVFS_WDATA15] =          0x164,
 737         [PWRAP_SPMINF_STA] =            0x168,
 738         [PWRAP_CIPHER_KEY_SEL] =        0x16C,
 739         [PWRAP_CIPHER_IV_SEL] =         0x170,
 740         [PWRAP_CIPHER_EN] =             0x174,
 741         [PWRAP_CIPHER_RDY] =            0x178,
 742         [PWRAP_CIPHER_MODE] =           0x17C,
 743         [PWRAP_CIPHER_SWRST] =          0x180,
 744         [PWRAP_DCM_EN] =                0x184,
 745         [PWRAP_DCM_DBC_PRD] =           0x188,
 746         [PWRAP_EXT_CK] =                0x18C,
 747         [PWRAP_ADC_CMD_ADDR] =          0x190,
 748         [PWRAP_PWRAP_ADC_CMD] =         0x194,
 749         [PWRAP_ADC_RDATA_ADDR] =        0x198,
 750         [PWRAP_GPS_STA] =               0x19C,
 751         [PWRAP_SW_RST] =                0x1A0,
 752         [PWRAP_DVFS_STEP_CTRL0] =       0x238,
 753         [PWRAP_DVFS_STEP_CTRL1] =       0x23C,
 754         [PWRAP_DVFS_STEP_CTRL2] =       0x240,
 755         [PWRAP_SPI2_CTRL] =             0x244,
 756 };
 757
 758 static int mt8135_regs[] = {
 759         [PWRAP_MUX_SEL] =               0x0,
 760         [PWRAP_WRAP_EN] =               0x4,
 761         [PWRAP_DIO_EN] =                0x8,
 762         [PWRAP_SIDLY] =                 0xc,
 763         [PWRAP_CSHEXT] =                0x10,
 764         [PWRAP_CSHEXT_WRITE] =          0x14,
 765         [PWRAP_CSHEXT_READ] =           0x18,
 766         [PWRAP_CSLEXT_START] =          0x1c,
 767         [PWRAP_CSLEXT_END] =            0x20,
 768         [PWRAP_STAUPD_PRD] =            0x24,
 769         [PWRAP_STAUPD_GRPEN] =          0x28,
 770         [PWRAP_STAUPD_MAN_TRIG] =       0x2c,
 771         [PWRAP_STAUPD_STA] =            0x30,
 772         [PWRAP_EVENT_IN_EN] =           0x34,
 773         [PWRAP_EVENT_DST_EN] =          0x38,
 774         [PWRAP_WRAP_STA] =              0x3c,
 775         [PWRAP_RRARB_INIT] =            0x40,
 776         [PWRAP_RRARB_EN] =              0x44,
 777         [PWRAP_RRARB_STA0] =            0x48,
 778         [PWRAP_RRARB_STA1] =            0x4c,
 779         [PWRAP_HARB_INIT] =             0x50,
 780         [PWRAP_HARB_HPRIO] =            0x54,
 781         [PWRAP_HIPRIO_ARB_EN] =         0x58,
 782         [PWRAP_HARB_STA0] =             0x5c,
 783         [PWRAP_HARB_STA1] =             0x60,
 784         [PWRAP_MAN_EN] =                0x64,
 785         [PWRAP_MAN_CMD] =               0x68,
 786         [PWRAP_MAN_RDATA] =             0x6c,
 787         [PWRAP_MAN_VLDCLR] =            0x70,
 788         [PWRAP_WACS0_EN] =              0x74,
 789         [PWRAP_INIT_DONE0] =            0x78,
 790         [PWRAP_WACS0_CMD] =             0x7c,
 791         [PWRAP_WACS0_RDATA] =           0x80,
 792         [PWRAP_WACS0_VLDCLR] =          0x84,
 793         [PWRAP_WACS1_EN] =              0x88,
 794         [PWRAP_INIT_DONE1] =            0x8c,
 795         [PWRAP_WACS1_CMD] =             0x90,
 796         [PWRAP_WACS1_RDATA] =           0x94,
 797         [PWRAP_WACS1_VLDCLR] =          0x98,
 798         [PWRAP_WACS2_EN] =              0x9c,
 799         [PWRAP_INIT_DONE2] =            0xa0,
 800         [PWRAP_WACS2_CMD] =             0xa4,
 801         [PWRAP_WACS2_RDATA] =           0xa8,
 802         [PWRAP_WACS2_VLDCLR] =          0xac,
 803         [PWRAP_INT_EN] =                0xb0,
 804         [PWRAP_INT_FLG_RAW] =           0xb4,
 805         [PWRAP_INT_FLG] =               0xb8,
 806         [PWRAP_INT_CLR] =               0xbc,
 807         [PWRAP_SIG_ADR] =               0xc0,
 808         [PWRAP_SIG_MODE] =              0xc4,
 809         [PWRAP_SIG_VALUE] =             0xc8,
 810         [PWRAP_SIG_ERRVAL] =            0xcc,
 811         [PWRAP_CRC_EN] =                0xd0,
 812         [PWRAP_EVENT_STA] =             0xd4,
 813         [PWRAP_EVENT_STACLR] =          0xd8,
 814         [PWRAP_TIMER_EN] =              0xdc,
 815         [PWRAP_TIMER_STA] =             0xe0,
 816         [PWRAP_WDT_UNIT] =              0xe4,
 817         [PWRAP_WDT_SRC_EN] =            0xe8,
 818         [PWRAP_WDT_FLG] =               0xec,
 819         [PWRAP_DEBUG_INT_SEL] =         0xf0,
 820         [PWRAP_CIPHER_KEY_SEL] =        0x134,
 821         [PWRAP_CIPHER_IV_SEL] =         0x138,
 822         [PWRAP_CIPHER_LOAD] =           0x13c,
 823         [PWRAP_CIPHER_START] =          0x140,
 824         [PWRAP_CIPHER_RDY] =            0x144,
 825         [PWRAP_CIPHER_MODE] =           0x148,
 826         [PWRAP_CIPHER_SWRST] =          0x14c,
 827         [PWRAP_DCM_EN] =                0x15c,
 828         [PWRAP_DCM_DBC_PRD] =           0x160,
 829 };
 830
 831 static int mt8173_regs[] = {
 832         [PWRAP_MUX_SEL] =               0x0,
 833         [PWRAP_WRAP_EN] =               0x4,
 834         [PWRAP_DIO_EN] =                0x8,
 835         [PWRAP_SIDLY] =                 0xc,
 836         [PWRAP_RDDMY] =                 0x10,
 837         [PWRAP_SI_CK_CON] =             0x14,
 838         [PWRAP_CSHEXT_WRITE] =          0x18,
 839         [PWRAP_CSHEXT_READ] =           0x1c,
 840         [PWRAP_CSLEXT_START] =          0x20,
 841         [PWRAP_CSLEXT_END] =            0x24,
 842         [PWRAP_STAUPD_PRD] =            0x28,
 843         [PWRAP_STAUPD_GRPEN] =          0x2c,
 844         [PWRAP_STAUPD_MAN_TRIG] =       0x40,
 845         [PWRAP_STAUPD_STA] =            0x44,
 846         [PWRAP_WRAP_STA] =              0x48,
 847         [PWRAP_HARB_INIT] =             0x4c,
 848         [PWRAP_HARB_HPRIO] =            0x50,
 849         [PWRAP_HIPRIO_ARB_EN] =         0x54,
 850         [PWRAP_HARB_STA0] =             0x58,
 851         [PWRAP_HARB_STA1] =             0x5c,
 852         [PWRAP_MAN_EN] =                0x60,
 853         [PWRAP_MAN_CMD] =               0x64,
 854         [PWRAP_MAN_RDATA] =             0x68,
 855         [PWRAP_MAN_VLDCLR] =            0x6c,
 856         [PWRAP_WACS0_EN] =              0x70,
 857         [PWRAP_INIT_DONE0] =            0x74,
 858         [PWRAP_WACS0_CMD] =             0x78,
 859         [PWRAP_WACS0_RDATA] =           0x7c,
 860         [PWRAP_WACS0_VLDCLR] =          0x80,
 861         [PWRAP_WACS1_EN] =              0x84,
 862         [PWRAP_INIT_DONE1] =            0x88,
 863         [PWRAP_WACS1_CMD] =             0x8c,
 864         [PWRAP_WACS1_RDATA] =           0x90,
 865         [PWRAP_WACS1_VLDCLR] =          0x94,
 866         [PWRAP_WACS2_EN] =              0x98,
 867         [PWRAP_INIT_DONE2] =            0x9c,
 868         [PWRAP_WACS2_CMD] =             0xa0,
 869         [PWRAP_WACS2_RDATA] =           0xa4,
 870         [PWRAP_WACS2_VLDCLR] =          0xa8,
 871         [PWRAP_INT_EN] =                0xac,
 872         [PWRAP_INT_FLG_RAW] =           0xb0,
 873         [PWRAP_INT_FLG] =               0xb4,
 874         [PWRAP_INT_CLR] =               0xb8,
 875         [PWRAP_SIG_ADR] =               0xbc,
 876         [PWRAP_SIG_MODE] =              0xc0,
 877         [PWRAP_SIG_VALUE] =             0xc4,
 878         [PWRAP_SIG_ERRVAL] =            0xc8,
 879         [PWRAP_CRC_EN] =                0xcc,
 880         [PWRAP_TIMER_EN] =              0xd0,
 881         [PWRAP_TIMER_STA] =             0xd4,
 882         [PWRAP_WDT_UNIT] =              0xd8,
 883         [PWRAP_WDT_SRC_EN] =            0xdc,
 884         [PWRAP_WDT_FLG] =               0xe0,
 885         [PWRAP_DEBUG_INT_SEL] =         0xe4,
 886         [PWRAP_DVFS_ADR0] =             0xe8,
 887         [PWRAP_DVFS_WDATA0] =           0xec,
 888         [PWRAP_DVFS_ADR1] =             0xf0,
 889         [PWRAP_DVFS_WDATA1] =           0xf4,
 890         [PWRAP_DVFS_ADR2] =             0xf8,
 891         [PWRAP_DVFS_WDATA2] =           0xfc,
 892         [PWRAP_DVFS_ADR3] =             0x100,
 893         [PWRAP_DVFS_WDATA3] =           0x104,
 894         [PWRAP_DVFS_ADR4] =             0x108,
 895         [PWRAP_DVFS_WDATA4] =           0x10c,
 896         [PWRAP_DVFS_ADR5] =             0x110,
 897         [PWRAP_DVFS_WDATA5] =           0x114,
 898         [PWRAP_DVFS_ADR6] =             0x118,
 899         [PWRAP_DVFS_WDATA6] =           0x11c,
 900         [PWRAP_DVFS_ADR7] =             0x120,
 901         [PWRAP_DVFS_WDATA7] =           0x124,
 902         [PWRAP_SPMINF_STA] =            0x128,
 903         [PWRAP_CIPHER_KEY_SEL] =        0x12c,
 904         [PWRAP_CIPHER_IV_SEL] =         0x130,
 905         [PWRAP_CIPHER_EN] =             0x134,
 906         [PWRAP_CIPHER_RDY] =            0x138,
 907         [PWRAP_CIPHER_MODE] =           0x13c,
 908         [PWRAP_CIPHER_SWRST] =          0x140,
 909         [PWRAP_DCM_EN] =                0x144,
 910         [PWRAP_DCM_DBC_PRD] =           0x148,
 911 };
 912
 913 static int mt8183_regs[] = {
 914         [PWRAP_MUX_SEL] =                       0x0,
 915         [PWRAP_WRAP_EN] =                       0x4,
 916         [PWRAP_DIO_EN] =                        0x8,
 917         [PWRAP_SI_SAMPLE_CTRL] =                0xC,
 918         [PWRAP_RDDMY] =                         0x14,
 919         [PWRAP_CSHEXT_WRITE] =                  0x18,
 920         [PWRAP_CSHEXT_READ] =                   0x1C,
 921         [PWRAP_CSLEXT_WRITE] =                  0x20,
 922         [PWRAP_CSLEXT_READ] =                   0x24,
 923         [PWRAP_EXT_CK_WRITE] =                  0x28,
 924         [PWRAP_STAUPD_CTRL] =                   0x30,
 925         [PWRAP_STAUPD_GRPEN] =                  0x34,
 926         [PWRAP_EINT_STA0_ADR] =                 0x38,
 927         [PWRAP_HARB_HPRIO] =                    0x5C,
 928         [PWRAP_HIPRIO_ARB_EN] =                 0x60,
 929         [PWRAP_MAN_EN] =                        0x70,
 930         [PWRAP_MAN_CMD] =                       0x74,
 931         [PWRAP_WACS0_EN] =                      0x80,
 932         [PWRAP_INIT_DONE0] =                    0x84,
 933         [PWRAP_WACS1_EN] =                      0x88,
 934         [PWRAP_INIT_DONE1] =                    0x8C,
 935         [PWRAP_WACS2_EN] =                      0x90,
 936         [PWRAP_INIT_DONE2] =                    0x94,
 937         [PWRAP_WACS_P2P_EN] =                   0xA0,
 938         [PWRAP_INIT_DONE_P2P] =                 0xA4,
 939         [PWRAP_WACS_MD32_EN] =                  0xA8,
 940         [PWRAP_INIT_DONE_MD32] =                0xAC,
 941         [PWRAP_INT_EN] =                        0xB0,
 942         [PWRAP_INT_FLG] =                       0xB8,
 943         [PWRAP_INT_CLR] =                       0xBC,
 944         [PWRAP_INT1_EN] =                       0xC0,
 945         [PWRAP_INT1_FLG] =                      0xC8,
 946         [PWRAP_INT1_CLR] =                      0xCC,
 947         [PWRAP_SIG_ADR] =                       0xD0,
 948         [PWRAP_CRC_EN] =                        0xE0,
 949         [PWRAP_TIMER_EN] =                      0xE4,
 950         [PWRAP_WDT_UNIT] =                      0xEC,
 951         [PWRAP_WDT_SRC_EN] =                    0xF0,
 952         [PWRAP_WDT_SRC_EN_1] =                  0xF4,
 953         [PWRAP_INT_GPS_AUXADC_CMD_ADDR] =       0x1DC,
 954         [PWRAP_INT_GPS_AUXADC_CMD] =            0x1E0,
 955         [PWRAP_INT_GPS_AUXADC_RDATA_ADDR] =     0x1E4,
 956         [PWRAP_EXT_GPS_AUXADC_RDATA_ADDR] =     0x1E8,
 957         [PWRAP_GPSINF_0_STA] =                  0x1EC,
 958         [PWRAP_GPSINF_1_STA] =                  0x1F0,
 959         [PWRAP_WACS2_CMD] =                     0xC20,
 960         [PWRAP_WACS2_RDATA] =                   0xC24,
 961         [PWRAP_WACS2_VLDCLR] =                  0xC28,
 962 };
 963
 964 static int mt8516_regs[] = {
 965         [PWRAP_MUX_SEL] =               0x0,
 966         [PWRAP_WRAP_EN] =               0x4,
 967         [PWRAP_DIO_EN] =                0x8,
 968         [PWRAP_SIDLY] =                 0xc,
 969         [PWRAP_RDDMY] =                 0x10,
 970         [PWRAP_SI_CK_CON] =             0x14,
 971         [PWRAP_CSHEXT_WRITE] =          0x18,
 972         [PWRAP_CSHEXT_READ] =           0x1c,
 973         [PWRAP_CSLEXT_START] =          0x20,
 974         [PWRAP_CSLEXT_END] =            0x24,
 975         [PWRAP_STAUPD_PRD] =            0x28,
 976         [PWRAP_STAUPD_GRPEN] =          0x2c,
 977         [PWRAP_STAUPD_MAN_TRIG] =       0x40,
 978         [PWRAP_STAUPD_STA] =            0x44,
 979         [PWRAP_WRAP_STA] =              0x48,
 980         [PWRAP_HARB_INIT] =             0x4c,
 981         [PWRAP_HARB_HPRIO] =            0x50,
 982         [PWRAP_HIPRIO_ARB_EN] =         0x54,
 983         [PWRAP_HARB_STA0] =             0x58,
 984         [PWRAP_HARB_STA1] =             0x5c,
 985         [PWRAP_MAN_EN] =                0x60,
 986         [PWRAP_MAN_CMD] =               0x64,
 987         [PWRAP_MAN_RDATA] =             0x68,
 988         [PWRAP_MAN_VLDCLR] =            0x6c,
 989         [PWRAP_WACS0_EN] =              0x70,
 990         [PWRAP_INIT_DONE0] =            0x74,
 991         [PWRAP_WACS0_CMD] =             0x78,
 992         [PWRAP_WACS0_RDATA] =           0x7c,
 993         [PWRAP_WACS0_VLDCLR] =          0x80,
 994         [PWRAP_WACS1_EN] =              0x84,
 995         [PWRAP_INIT_DONE1] =            0x88,
 996         [PWRAP_WACS1_CMD] =             0x8c,
 997         [PWRAP_WACS1_RDATA] =           0x90,
 998         [PWRAP_WACS1_VLDCLR] =          0x94,
 999         [PWRAP_WACS2_EN] =              0x98,
1000         [PWRAP_INIT_DONE2] =            0x9c,
1001         [PWRAP_WACS2_CMD] =             0xa0,
1002         [PWRAP_WACS2_RDATA] =           0xa4,
1003         [PWRAP_WACS2_VLDCLR] =          0xa8,
1004         [PWRAP_INT_EN] =                0xac,
1005         [PWRAP_INT_FLG_RAW] =           0xb0,
1006         [PWRAP_INT_FLG] =               0xb4,
1007         [PWRAP_INT_CLR] =               0xb8,
1008         [PWRAP_SIG_ADR] =               0xbc,
1009         [PWRAP_SIG_MODE] =              0xc0,
1010         [PWRAP_SIG_VALUE] =             0xc4,
1011         [PWRAP_SIG_ERRVAL] =            0xc8,
1012         [PWRAP_CRC_EN] =                0xcc,
1013         [PWRAP_TIMER_EN] =              0xd0,
1014         [PWRAP_TIMER_STA] =             0xd4,
1015         [PWRAP_WDT_UNIT] =              0xd8,
1016         [PWRAP_WDT_SRC_EN] =            0xdc,
1017         [PWRAP_WDT_FLG] =               0xe0,
1018         [PWRAP_DEBUG_INT_SEL] =         0xe4,
1019         [PWRAP_DVFS_ADR0] =             0xe8,
1020         [PWRAP_DVFS_WDATA0] =           0xec,
1021         [PWRAP_DVFS_ADR1] =             0xf0,
1022         [PWRAP_DVFS_WDATA1] =           0xf4,
1023         [PWRAP_DVFS_ADR2] =             0xf8,
1024         [PWRAP_DVFS_WDATA2] =           0xfc,
1025         [PWRAP_DVFS_ADR3] =             0x100,
1026         [PWRAP_DVFS_WDATA3] =           0x104,
1027         [PWRAP_DVFS_ADR4] =             0x108,
1028         [PWRAP_DVFS_WDATA4] =           0x10c,
1029         [PWRAP_DVFS_ADR5] =             0x110,
1030         [PWRAP_DVFS_WDATA5] =           0x114,
1031         [PWRAP_DVFS_ADR6] =             0x118,
1032         [PWRAP_DVFS_WDATA6] =           0x11c,
1033         [PWRAP_DVFS_ADR7] =             0x120,
1034         [PWRAP_DVFS_WDATA7] =           0x124,
1035         [PWRAP_SPMINF_STA] =            0x128,
1036         [PWRAP_CIPHER_KEY_SEL] =        0x12c,
1037         [PWRAP_CIPHER_IV_SEL] =         0x130,
1038         [PWRAP_CIPHER_EN] =             0x134,
1039         [PWRAP_CIPHER_RDY] =            0x138,
1040         [PWRAP_CIPHER_MODE] =           0x13c,
1041         [PWRAP_CIPHER_SWRST] =          0x140,
1042         [PWRAP_DCM_EN] =                0x144,
1043         [PWRAP_DCM_DBC_PRD] =           0x148,
1044         [PWRAP_SW_RST] =                0x168,
1045         [PWRAP_OP_TYPE] =               0x16c,
1046         [PWRAP_MSB_FIRST] =             0x170,
1047 };
1048
1049 enum pmic_type {
1050         PMIC_MT6323,
1051         PMIC_MT6351,
1052         PMIC_MT6357,
1053         PMIC_MT6358,
1054         PMIC_MT6359,
1055         PMIC_MT6380,
1056         PMIC_MT6397,
1057 };
1058
1059 enum pwrap_type {
1060         PWRAP_MT2701,
1061         PWRAP_MT6765,
1062         PWRAP_MT6779,
1063         PWRAP_MT6797,
1064         PWRAP_MT6873,
1065         PWRAP_MT7622,
1066         PWRAP_MT8135,
1067         PWRAP_MT8173,
1068         PWRAP_MT8183,
1069         PWRAP_MT8516,
1070 };
1071
1072 struct pmic_wrapper;
1073 struct pwrap_slv_type {
1074         const u32 *dew_regs;
1075         enum pmic_type type;
1076         const struct regmap_config *regmap;
1077         /* Flags indicating the capability for the target slave */
1078         u32 caps;
1079         /*
1080          * pwrap operations are highly associated with the PMIC types,
1081          * so the pointers added increases flexibility allowing determination
1082          * which type is used by the detection through device tree.
1083          */
1084         int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
1085         int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata);
1086 };
1087
1088 struct pmic_wrapper {
1089         struct device *dev;
1090         void __iomem *base;
1091         struct regmap *regmap;
1092         const struct pmic_wrapper_type *master;
1093         const struct pwrap_slv_type *slave;
1094         struct clk *clk_spi;
1095         struct clk *clk_wrap;
1096         struct reset_control *rstc;
1097
1098         struct reset_control *rstc_bridge;
1099         void __iomem *bridge_base;
1100 };
1101
1102 struct pmic_wrapper_type {
1103         int *regs;
1104         enum pwrap_type type;
1105         u32 arb_en_all;
1106         u32 int_en_all;
1107         u32 int1_en_all;
1108         u32 spi_w;
1109         u32 wdt_src;
1110         /* Flags indicating the capability for the target pwrap */
1111         u32 caps;
1112         int (*init_reg_clock)(struct pmic_wrapper *wrp);
1113         int (*init_soc_specific)(struct pmic_wrapper *wrp);
1114 };
1115
1116 static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)
1117 {
1118         return readl(wrp->base + wrp->master->regs[reg]);
1119 }
1120
1121 static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg)
1122 {
1123         writel(val, wrp->base + wrp->master->regs[reg]);
1124 }
1125
1126 static u32 pwrap_get_fsm_state(struct pmic_wrapper *wrp)
1127 {
1128         u32 val;
1129
1130         val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1131         if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
1132                 return PWRAP_GET_WACS_ARB_FSM(val);
1133         else
1134                 return PWRAP_GET_WACS_FSM(val);
1135 }
1136
1137 static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
1138 {
1139         return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_IDLE;
1140 }
1141
1142 static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
1143 {
1144         return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_WFVLDCLR;
1145 }
1146
1147 /*
1148  * Timeout issue sometimes caused by the last read command
1149  * failed because pmic wrap could not got the FSM_VLDCLR
1150  * in time after finishing WACS2_CMD. It made state machine
1151  * still on FSM_VLDCLR and timeout next time.
1152  * Check the status of FSM and clear the vldclr to recovery the
1153  * error.
1154  */
1155 static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp)
1156 {
1157         if (pwrap_is_fsm_vldclr(wrp))
1158                 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1159 }
1160
1161 static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp)
1162 {
1163         return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0;
1164 }
1165
1166 static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp)
1167 {
1168         u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1169
1170         return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) &&
1171                 (val & PWRAP_STATE_SYNC_IDLE0);
1172 }
1173
1174 static int pwrap_wait_for_state(struct pmic_wrapper *wrp,
1175                 bool (*fp)(struct pmic_wrapper *))
1176 {
1177         unsigned long timeout;
1178
1179         timeout = jiffies + usecs_to_jiffies(10000);
1180
1181         do {
1182                 if (time_after(jiffies, timeout))
1183                         return fp(wrp) ? 0 : -ETIMEDOUT;
1184                 if (fp(wrp))
1185                         return 0;
1186         } while (1);
1187 }
1188
1189 static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1190 {
1191         int ret;
1192         u32 val;
1193
1194         ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1195         if (ret) {
1196                 pwrap_leave_fsm_vldclr(wrp);
1197                 return ret;
1198         }
1199
1200         if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
1201                 val = adr;
1202         else
1203                 val = (adr >> 1) << 16;
1204         pwrap_writel(wrp, val, PWRAP_WACS2_CMD);
1205
1206         ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
1207         if (ret)
1208                 return ret;
1209
1210         if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
1211                 val = pwrap_readl(wrp, PWRAP_SWINF_2_RDATA_31_0);
1212         else
1213                 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1214         *rdata = PWRAP_GET_WACS_RDATA(val);
1215
1216         pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1217
1218         return 0;
1219 }
1220
1221 static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1222 {
1223         int ret, msb;
1224
1225         *rdata = 0;
1226         for (msb = 0; msb < 2; msb++) {
1227                 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1228                 if (ret) {
1229                         pwrap_leave_fsm_vldclr(wrp);
1230                         return ret;
1231                 }
1232
1233                 pwrap_writel(wrp, ((msb << 30) | (adr << 16)),
1234                              PWRAP_WACS2_CMD);
1235
1236                 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
1237                 if (ret)
1238                         return ret;
1239
1240                 *rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp,
1241                            PWRAP_WACS2_RDATA)) << (16 * msb));
1242
1243                 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1244         }
1245
1246         return 0;
1247 }
1248
1249 static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1250 {
1251         return wrp->slave->pwrap_read(wrp, adr, rdata);
1252 }
1253
1254 static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1255 {
1256         int ret;
1257
1258         ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1259         if (ret) {
1260                 pwrap_leave_fsm_vldclr(wrp);
1261                 return ret;
1262         }
1263
1264         if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) {
1265                 pwrap_writel(wrp, wdata, PWRAP_SWINF_2_WDATA_31_0);
1266                 pwrap_writel(wrp, BIT(29) | adr, PWRAP_WACS2_CMD);
1267         } else {
1268                 pwrap_writel(wrp, BIT(31) | ((adr >> 1) << 16) | wdata,
1269                              PWRAP_WACS2_CMD);
1270         }
1271
1272         return 0;
1273 }
1274
1275 static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1276 {
1277         int ret, msb, rdata;
1278
1279         for (msb = 0; msb < 2; msb++) {
1280                 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1281                 if (ret) {
1282                         pwrap_leave_fsm_vldclr(wrp);
1283                         return ret;
1284                 }
1285
1286                 pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) |
1287                              ((wdata >> (msb * 16)) & 0xffff),
1288                              PWRAP_WACS2_CMD);
1289
1290                 /*
1291                  * The pwrap_read operation is the requirement of hardware used
1292                  * for the synchronization between two successive 16-bit
1293                  * pwrap_writel operations composing one 32-bit bus writing.
1294                  * Otherwise, we'll find the result fails on the lower 16-bit
1295                  * pwrap writing.
1296                  */
1297                 if (!msb)
1298                         pwrap_read(wrp, adr, &rdata);
1299         }
1300
1301         return 0;
1302 }
1303
1304 static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1305 {
1306         return wrp->slave->pwrap_write(wrp, adr, wdata);
1307 }
1308
1309 static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
1310 {
1311         return pwrap_read(context, adr, rdata);
1312 }
1313
1314 static int pwrap_regmap_write(void *context, u32 adr, u32 wdata)
1315 {
1316         return pwrap_write(context, adr, wdata);
1317 }
1318
1319 static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
1320 {
1321         int ret, i;
1322
1323         pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN);
1324         pwrap_writel(wrp, 0, PWRAP_WRAP_EN);
1325         pwrap_writel(wrp, 1, PWRAP_MUX_SEL);
1326         pwrap_writel(wrp, 1, PWRAP_MAN_EN);
1327         pwrap_writel(wrp, 0, PWRAP_DIO_EN);
1328
1329         pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL,
1330                         PWRAP_MAN_CMD);
1331         pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
1332                         PWRAP_MAN_CMD);
1333         pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH,
1334                         PWRAP_MAN_CMD);
1335
1336         for (i = 0; i < 4; i++)
1337                 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
1338                                 PWRAP_MAN_CMD);
1339
1340         ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle);
1341         if (ret) {
1342                 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
1343                 return ret;
1344         }
1345
1346         pwrap_writel(wrp, 0, PWRAP_MAN_EN);
1347         pwrap_writel(wrp, 0, PWRAP_MUX_SEL);
1348
1349         return 0;
1350 }
1351
1352 /*
1353  * pwrap_init_sidly - configure serial input delay
1354  *
1355  * This configures the serial input delay. We can configure 0, 2, 4 or 6ns
1356  * delay. Do a read test with all possible values and chose the best delay.
1357  */
1358 static int pwrap_init_sidly(struct pmic_wrapper *wrp)
1359 {
1360         u32 rdata;
1361         u32 i;
1362         u32 pass = 0;
1363         signed char dly[16] = {
1364                 -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1
1365         };
1366
1367         for (i = 0; i < 4; i++) {
1368                 pwrap_writel(wrp, i, PWRAP_SIDLY);
1369                 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST],
1370                            &rdata);
1371                 if (rdata == PWRAP_DEW_READ_TEST_VAL) {
1372                         dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
1373                         pass |= 1 << i;
1374                 }
1375         }
1376
1377         if (dly[pass] < 0) {
1378                 dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n",
1379                                 pass);
1380                 return -EIO;
1381         }
1382
1383         pwrap_writel(wrp, dly[pass], PWRAP_SIDLY);
1384
1385         return 0;
1386 }
1387
1388 static int pwrap_init_dual_io(struct pmic_wrapper *wrp)
1389 {
1390         int ret;
1391         u32 rdata;
1392
1393         /* Enable dual IO mode */
1394         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
1395
1396         /* Check IDLE & INIT_DONE in advance */
1397         ret = pwrap_wait_for_state(wrp,
1398                                    pwrap_is_fsm_idle_and_sync_idle);
1399         if (ret) {
1400                 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
1401                 return ret;
1402         }
1403
1404         pwrap_writel(wrp, 1, PWRAP_DIO_EN);
1405
1406         /* Read Test */
1407         pwrap_read(wrp,
1408                    wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
1409         if (rdata != PWRAP_DEW_READ_TEST_VAL) {
1410                 dev_err(wrp->dev,
1411                         "Read failed on DIO mode: 0x%04x!=0x%04x\n",
1412                         PWRAP_DEW_READ_TEST_VAL, rdata);
1413                 return -EFAULT;
1414         }
1415
1416         return 0;
1417 }
1418
1419 /*
1420  * pwrap_init_chip_select_ext is used to configure CS extension time for each
1421  * phase during data transactions on the pwrap bus.
1422  */
1423 static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
1424                                        u8 hext_read, u8 lext_start,
1425                                        u8 lext_end)
1426 {
1427         /*
1428          * After finishing a write and read transaction, extends CS high time
1429          * to be at least xT of BUS CLK as hext_write and hext_read specifies
1430          * respectively.
1431          */
1432         pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE);
1433         pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ);
1434
1435         /*
1436          * Extends CS low time after CSL and before CSH command to be at
1437          * least xT of BUS CLK as lext_start and lext_end specifies
1438          * respectively.
1439          */
1440         pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START);
1441         pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END);
1442 }
1443
1444 static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
1445 {
1446         switch (wrp->master->type) {
1447         case PWRAP_MT8173:
1448                 pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);
1449                 break;
1450         case PWRAP_MT8135:
1451                 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
1452                 pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0);
1453                 break;
1454         default:
1455                 break;
1456         }
1457
1458         return 0;
1459 }
1460
1461 static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp)
1462 {
1463         switch (wrp->slave->type) {
1464         case PMIC_MT6397:
1465                 pwrap_writel(wrp, 0xc, PWRAP_RDDMY);
1466                 pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2);
1467                 break;
1468
1469         case PMIC_MT6323:
1470                 pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
1471                 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO],
1472                             0x8);
1473                 pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2);
1474                 break;
1475         default:
1476                 break;
1477         }
1478
1479         return 0;
1480 }
1481
1482 static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
1483 {
1484         return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
1485 }
1486
1487 static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
1488 {
1489         u32 rdata;
1490         int ret;
1491
1492         ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY],
1493                          &rdata);
1494         if (ret)
1495                 return false;
1496
1497         return rdata == 1;
1498 }
1499
1500 static int pwrap_init_cipher(struct pmic_wrapper *wrp)
1501 {
1502         int ret;
1503         u32 rdata = 0;
1504
1505         pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST);
1506         pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST);
1507         pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);
1508         pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);
1509
1510         switch (wrp->master->type) {
1511         case PWRAP_MT8135:
1512                 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
1513                 pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
1514                 break;
1515         case PWRAP_MT2701:
1516         case PWRAP_MT6765:
1517         case PWRAP_MT6779:
1518         case PWRAP_MT6797:
1519         case PWRAP_MT8173:
1520         case PWRAP_MT8516:
1521                 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
1522                 break;
1523         case PWRAP_MT7622:
1524                 pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
1525                 break;
1526         case PWRAP_MT6873:
1527         case PWRAP_MT8183:
1528                 break;
1529         }
1530
1531         /* Config cipher mode @PMIC */
1532         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1);
1533         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);
1534         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);
1535         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);
1536
1537         switch (wrp->slave->type) {
1538         case PMIC_MT6397:
1539                 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD],
1540                             0x1);
1541                 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START],
1542                             0x1);
1543                 break;
1544         case PMIC_MT6323:
1545         case PMIC_MT6351:
1546         case PMIC_MT6357:
1547                 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
1548                             0x1);
1549                 break;
1550         default:
1551                 break;
1552         }
1553
1554         /* wait for cipher data ready@AP */
1555         ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
1556         if (ret) {
1557                 dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret);
1558                 return ret;
1559         }
1560
1561         /* wait for cipher data ready@PMIC */
1562         ret = pwrap_wait_for_state(wrp, pwrap_is_pmic_cipher_ready);
1563         if (ret) {
1564                 dev_err(wrp->dev,
1565                         "timeout waiting for cipher data ready@PMIC\n");
1566                 return ret;
1567         }
1568
1569         /* wait for cipher mode idle */
1570         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1);
1571         ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
1572         if (ret) {
1573                 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
1574                 return ret;
1575         }
1576
1577         pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
1578
1579         /* Write Test */
1580         if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1581                         PWRAP_DEW_WRITE_TEST_VAL) ||
1582             pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1583                        &rdata) ||
1584             (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
1585                 dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
1586                 return -EFAULT;
1587         }
1588
1589         return 0;
1590 }
1591
1592 static int pwrap_init_security(struct pmic_wrapper *wrp)
1593 {
1594         int ret;
1595
1596         /* Enable encryption */
1597         ret = pwrap_init_cipher(wrp);
1598         if (ret)
1599                 return ret;
1600
1601         /* Signature checking - using CRC */
1602         if (pwrap_write(wrp,
1603                         wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
1604                 return -EFAULT;
1605
1606         pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
1607         pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
1608         pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
1609                      PWRAP_SIG_ADR);
1610         pwrap_writel(wrp,
1611                      wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
1612
1613         return 0;
1614 }
1615
1616 static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
1617 {
1618         /* enable pwrap events and pwrap bridge in AP side */
1619         pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN);
1620         pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN);
1621         writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN);
1622         writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN);
1623         writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN);
1624         writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT);
1625         writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN);
1626         writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN);
1627         writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
1628
1629         /* enable PMIC event out and sources */
1630         if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
1631                         0x1) ||
1632             pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
1633                         0xffff)) {
1634                 dev_err(wrp->dev, "enable dewrap fail\n");
1635                 return -EFAULT;
1636         }
1637
1638         return 0;
1639 }
1640
1641 static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
1642 {
1643         /* PMIC_DEWRAP enables */
1644         if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
1645                         0x1) ||
1646             pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
1647                         0xffff)) {
1648                 dev_err(wrp->dev, "enable dewrap fail\n");
1649                 return -EFAULT;
1650         }
1651
1652         return 0;
1653 }
1654
1655 static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
1656 {
1657         /* GPS_INTF initialization */
1658         switch (wrp->slave->type) {
1659         case PMIC_MT6323:
1660                 pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR);
1661                 pwrap_writel(wrp, 0x8000, PWRAP_PWRAP_ADC_CMD);
1662                 pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR);
1663                 pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1);
1664                 pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2);
1665                 break;
1666         default:
1667                 break;
1668         }
1669
1670         return 0;
1671 }
1672
1673 static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
1674 {
1675         pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);
1676         /* enable 2wire SPI master */
1677         pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL);
1678
1679         return 0;
1680 }
1681
1682 static int pwrap_mt8183_init_soc_specific(struct pmic_wrapper *wrp)
1683 {
1684         pwrap_writel(wrp, 0xf5, PWRAP_STAUPD_GRPEN);
1685
1686         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1);
1687         pwrap_writel(wrp, 1, PWRAP_CRC_EN);
1688         pwrap_writel(wrp, 0x416, PWRAP_SIG_ADR);
1689         pwrap_writel(wrp, 0x42e, PWRAP_EINT_STA0_ADR);
1690
1691         pwrap_writel(wrp, 1, PWRAP_WACS_P2P_EN);
1692         pwrap_writel(wrp, 1, PWRAP_WACS_MD32_EN);
1693         pwrap_writel(wrp, 1, PWRAP_INIT_DONE_P2P);
1694         pwrap_writel(wrp, 1, PWRAP_INIT_DONE_MD32);
1695
1696         return 0;
1697 }
1698
1699 static int pwrap_init(struct pmic_wrapper *wrp)
1700 {
1701         int ret;
1702
1703         if (wrp->rstc)
1704                 reset_control_reset(wrp->rstc);
1705         if (wrp->rstc_bridge)
1706                 reset_control_reset(wrp->rstc_bridge);
1707
1708         if (wrp->master->type == PWRAP_MT8173) {
1709                 /* Enable DCM */
1710                 pwrap_writel(wrp, 3, PWRAP_DCM_EN);
1711                 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
1712         }
1713
1714         if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
1715                 /* Reset SPI slave */
1716                 ret = pwrap_reset_spislave(wrp);
1717                 if (ret)
1718                         return ret;
1719         }
1720
1721         pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
1722
1723         pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
1724
1725         pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
1726
1727         ret = wrp->master->init_reg_clock(wrp);
1728         if (ret)
1729                 return ret;
1730
1731         if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
1732                 /* Setup serial input delay */
1733                 ret = pwrap_init_sidly(wrp);
1734                 if (ret)
1735                         return ret;
1736         }
1737
1738         if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) {
1739                 /* Enable dual I/O mode */
1740                 ret = pwrap_init_dual_io(wrp);
1741                 if (ret)
1742                         return ret;
1743         }
1744
1745         if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) {
1746                 /* Enable security on bus */
1747                 ret = pwrap_init_security(wrp);
1748                 if (ret)
1749                         return ret;
1750         }
1751
1752         if (wrp->master->type == PWRAP_MT8135)
1753                 pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
1754
1755         pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);
1756         pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN);
1757         pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN);
1758         pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);
1759         pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);
1760
1761         if (wrp->master->init_soc_specific) {
1762                 ret = wrp->master->init_soc_specific(wrp);
1763                 if (ret)
1764                         return ret;
1765         }
1766
1767         /* Setup the init done registers */
1768         pwrap_writel(wrp, 1, PWRAP_INIT_DONE2);
1769         pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
1770         pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
1771
1772         if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
1773                 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
1774                 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
1775         }
1776
1777         return 0;
1778 }
1779
1780 static irqreturn_t pwrap_interrupt(int irqno, void *dev_id)
1781 {
1782         u32 rdata;
1783         struct pmic_wrapper *wrp = dev_id;
1784
1785         rdata = pwrap_readl(wrp, PWRAP_INT_FLG);
1786         dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata);
1787         pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR);
1788
1789         if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) {
1790                 rdata = pwrap_readl(wrp, PWRAP_INT1_FLG);
1791                 dev_err(wrp->dev, "unexpected interrupt int1=0x%x\n", rdata);
1792                 pwrap_writel(wrp, 0xffffffff, PWRAP_INT1_CLR);
1793         }
1794
1795         return IRQ_HANDLED;
1796 }
1797
1798 static const struct regmap_config pwrap_regmap_config16 = {
1799         .reg_bits = 16,
1800         .val_bits = 16,
1801         .reg_stride = 2,
1802         .reg_read = pwrap_regmap_read,
1803         .reg_write = pwrap_regmap_write,
1804         .max_register = 0xffff,
1805 };
1806
1807 static const struct regmap_config pwrap_regmap_config32 = {
1808         .reg_bits = 32,
1809         .val_bits = 32,
1810         .reg_stride = 4,
1811         .reg_read = pwrap_regmap_read,
1812         .reg_write = pwrap_regmap_write,
1813         .max_register = 0xffff,
1814 };
1815
1816 static const struct pwrap_slv_type pmic_mt6323 = {
1817         .dew_regs = mt6323_regs,
1818         .type = PMIC_MT6323,
1819         .regmap = &pwrap_regmap_config16,
1820         .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
1821                 PWRAP_SLV_CAP_SECURITY,
1822         .pwrap_read = pwrap_read16,
1823         .pwrap_write = pwrap_write16,
1824 };
1825
1826 static const struct pwrap_slv_type pmic_mt6351 = {
1827         .dew_regs = mt6351_regs,
1828         .type = PMIC_MT6351,
1829         .regmap = &pwrap_regmap_config16,
1830         .caps = 0,
1831         .pwrap_read = pwrap_read16,
1832         .pwrap_write = pwrap_write16,
1833 };
1834
1835 static const struct pwrap_slv_type pmic_mt6357 = {
1836         .dew_regs = mt6357_regs,
1837         .type = PMIC_MT6357,
1838         .regmap = &pwrap_regmap_config16,
1839         .caps = 0,
1840         .pwrap_read = pwrap_read16,
1841         .pwrap_write = pwrap_write16,
1842 };
1843
1844 static const struct pwrap_slv_type pmic_mt6358 = {
1845         .dew_regs = mt6358_regs,
1846         .type = PMIC_MT6358,
1847         .regmap = &pwrap_regmap_config16,
1848         .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO,
1849         .pwrap_read = pwrap_read16,
1850         .pwrap_write = pwrap_write16,
1851 };
1852
1853 static const struct pwrap_slv_type pmic_mt6359 = {
1854         .dew_regs = mt6359_regs,
1855         .type = PMIC_MT6359,
1856         .regmap = &pwrap_regmap_config16,
1857         .caps = PWRAP_SLV_CAP_DUALIO,
1858         .pwrap_read = pwrap_read16,
1859         .pwrap_write = pwrap_write16,
1860 };
1861
1862 static const struct pwrap_slv_type pmic_mt6380 = {
1863         .dew_regs = NULL,
1864         .type = PMIC_MT6380,
1865         .regmap = &pwrap_regmap_config32,
1866         .caps = 0,
1867         .pwrap_read = pwrap_read32,
1868         .pwrap_write = pwrap_write32,
1869 };
1870
1871 static const struct pwrap_slv_type pmic_mt6397 = {
1872         .dew_regs = mt6397_regs,
1873         .type = PMIC_MT6397,
1874         .regmap = &pwrap_regmap_config16,
1875         .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
1876                 PWRAP_SLV_CAP_SECURITY,
1877         .pwrap_read = pwrap_read16,
1878         .pwrap_write = pwrap_write16,
1879 };
1880
1881 static const struct of_device_id of_slave_match_tbl[] = {
1882         {
1883                 .compatible = "mediatek,mt6323",
1884                 .data = &pmic_mt6323,
1885         }, {
1886                 .compatible = "mediatek,mt6351",
1887                 .data = &pmic_mt6351,
1888         }, {
1889                 .compatible = "mediatek,mt6357",
1890                 .data = &pmic_mt6357,
1891         }, {
1892                 .compatible = "mediatek,mt6358",
1893                 .data = &pmic_mt6358,
1894         }, {
1895                 .compatible = "mediatek,mt6359",
1896                 .data = &pmic_mt6359,
1897         }, {
1898                 /* The MT6380 PMIC only implements a regulator, so we bind it
1899                  * directly instead of using a MFD.
1900                  */
1901                 .compatible = "mediatek,mt6380-regulator",
1902                 .data = &pmic_mt6380,
1903         }, {
1904                 .compatible = "mediatek,mt6397",
1905                 .data = &pmic_mt6397,
1906         }, {
1907                 /* sentinel */
1908         }
1909 };
1910 MODULE_DEVICE_TABLE(of, of_slave_match_tbl);
1911
1912 static const struct pmic_wrapper_type pwrap_mt2701 = {
1913         .regs = mt2701_regs,
1914         .type = PWRAP_MT2701,
1915         .arb_en_all = 0x3f,
1916         .int_en_all = ~(u32)(BIT(31) | BIT(2)),
1917         .int1_en_all = 0,
1918         .spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW,
1919         .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1920         .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1921         .init_reg_clock = pwrap_mt2701_init_reg_clock,
1922         .init_soc_specific = pwrap_mt2701_init_soc_specific,
1923 };
1924
1925 static const struct pmic_wrapper_type pwrap_mt6765 = {
1926         .regs = mt6765_regs,
1927         .type = PWRAP_MT6765,
1928         .arb_en_all = 0x3fd35,
1929         .int_en_all = 0xffffffff,
1930         .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1931         .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1932         .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1933         .init_reg_clock = pwrap_common_init_reg_clock,
1934         .init_soc_specific = NULL,
1935 };
1936
1937 static const struct pmic_wrapper_type pwrap_mt6779 = {
1938         .regs = mt6779_regs,
1939         .type = PWRAP_MT6779,
1940         .arb_en_all = 0xfbb7f,
1941         .int_en_all = 0xfffffffe,
1942         .int1_en_all = 0,
1943         .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1944         .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1945         .caps = 0,
1946         .init_reg_clock = pwrap_common_init_reg_clock,
1947         .init_soc_specific = NULL,
1948 };
1949
1950 static const struct pmic_wrapper_type pwrap_mt6797 = {
1951         .regs = mt6797_regs,
1952         .type = PWRAP_MT6797,
1953         .arb_en_all = 0x01fff,
1954         .int_en_all = 0xffffffc6,
1955         .int1_en_all = 0,
1956         .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1957         .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1958         .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1959         .init_reg_clock = pwrap_common_init_reg_clock,
1960         .init_soc_specific = NULL,
1961 };
1962
1963 static const struct pmic_wrapper_type pwrap_mt6873 = {
1964         .regs = mt6873_regs,
1965         .type = PWRAP_MT6873,
1966         .arb_en_all = 0x777f,
1967         .int_en_all = BIT(4) | BIT(5),
1968         .int1_en_all = 0,
1969         .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1970         .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1971         .caps = PWRAP_CAP_ARB,
1972         .init_reg_clock = pwrap_common_init_reg_clock,
1973         .init_soc_specific = NULL,
1974 };
1975
1976 static const struct pmic_wrapper_type pwrap_mt7622 = {
1977         .regs = mt7622_regs,
1978         .type = PWRAP_MT7622,
1979         .arb_en_all = 0xff,
1980         .int_en_all = ~(u32)BIT(31),
1981         .int1_en_all = 0,
1982         .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1983         .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1984         .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1985         .init_reg_clock = pwrap_common_init_reg_clock,
1986         .init_soc_specific = pwrap_mt7622_init_soc_specific,
1987 };
1988
1989 static const struct pmic_wrapper_type pwrap_mt8135 = {
1990         .regs = mt8135_regs,
1991         .type = PWRAP_MT8135,
1992         .arb_en_all = 0x1ff,
1993         .int_en_all = ~(u32)(BIT(31) | BIT(1)),
1994         .int1_en_all = 0,
1995         .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1996         .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1997         .caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1998         .init_reg_clock = pwrap_common_init_reg_clock,
1999         .init_soc_specific = pwrap_mt8135_init_soc_specific,
2000 };
2001
2002 static const struct pmic_wrapper_type pwrap_mt8173 = {
2003         .regs = mt8173_regs,
2004         .type = PWRAP_MT8173,
2005         .arb_en_all = 0x3f,
2006         .int_en_all = ~(u32)(BIT(31) | BIT(1)),
2007         .int1_en_all = 0,
2008         .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2009         .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
2010         .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
2011         .init_reg_clock = pwrap_common_init_reg_clock,
2012         .init_soc_specific = pwrap_mt8173_init_soc_specific,
2013 };
2014
2015 static const struct pmic_wrapper_type pwrap_mt8183 = {
2016         .regs = mt8183_regs,
2017         .type = PWRAP_MT8183,
2018         .arb_en_all = 0x3fa75,
2019         .int_en_all = 0xffffffff,
2020         .int1_en_all = 0xeef7ffff,
2021         .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2022         .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2023         .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1,
2024         .init_reg_clock = pwrap_common_init_reg_clock,
2025         .init_soc_specific = pwrap_mt8183_init_soc_specific,
2026 };
2027
2028 static struct pmic_wrapper_type pwrap_mt8516 = {
2029         .regs = mt8516_regs,
2030         .type = PWRAP_MT8516,
2031         .arb_en_all = 0xff,
2032         .int_en_all = ~(u32)(BIT(31) | BIT(2)),
2033         .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2034         .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2035         .caps = PWRAP_CAP_DCM,
2036         .init_reg_clock = pwrap_mt2701_init_reg_clock,
2037         .init_soc_specific = NULL,
2038 };
2039
2040 static const struct of_device_id of_pwrap_match_tbl[] = {
2041         {
2042                 .compatible = "mediatek,mt2701-pwrap",
2043                 .data = &pwrap_mt2701,
2044         }, {
2045                 .compatible = "mediatek,mt6765-pwrap",
2046                 .data = &pwrap_mt6765,
2047         }, {
2048                 .compatible = "mediatek,mt6779-pwrap",
2049                 .data = &pwrap_mt6779,
2050         }, {
2051                 .compatible = "mediatek,mt6797-pwrap",
2052                 .data = &pwrap_mt6797,
2053         }, {
2054                 .compatible = "mediatek,mt6873-pwrap",
2055                 .data = &pwrap_mt6873,
2056         }, {
2057                 .compatible = "mediatek,mt7622-pwrap",
2058                 .data = &pwrap_mt7622,
2059         }, {
2060                 .compatible = "mediatek,mt8135-pwrap",
2061                 .data = &pwrap_mt8135,
2062         }, {
2063                 .compatible = "mediatek,mt8173-pwrap",
2064                 .data = &pwrap_mt8173,
2065         }, {
2066                 .compatible = "mediatek,mt8183-pwrap",
2067                 .data = &pwrap_mt8183,
2068         }, {
2069                 .compatible = "mediatek,mt8516-pwrap",
2070                 .data = &pwrap_mt8516,
2071         }, {
2072                 /* sentinel */
2073         }
2074 };
2075 MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
2076
2077 static int pwrap_probe(struct platform_device *pdev)
2078 {
2079         int ret, irq;
2080         u32 mask_done;
2081         struct pmic_wrapper *wrp;
2082         struct device_node *np = pdev->dev.of_node;
2083         const struct of_device_id *of_slave_id = NULL;
2084         struct resource *res;
2085
2086         if (np->child)
2087                 of_slave_id = of_match_node(of_slave_match_tbl, np->child);
2088
2089         if (!of_slave_id) {
2090                 dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n");
2091                 return -EINVAL;
2092         }
2093
2094         wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
2095         if (!wrp)
2096                 return -ENOMEM;
2097
2098         platform_set_drvdata(pdev, wrp);
2099
2100         wrp->master = of_device_get_match_data(&pdev->dev);
2101         wrp->slave = of_slave_id->data;
2102         wrp->dev = &pdev->dev;
2103
2104         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
2105         wrp->base = devm_ioremap_resource(wrp->dev, res);
2106         if (IS_ERR(wrp->base))
2107                 return PTR_ERR(wrp->base);
2108
2109         if (HAS_CAP(wrp->master->caps, PWRAP_CAP_RESET)) {
2110                 wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
2111                 if (IS_ERR(wrp->rstc)) {
2112                         ret = PTR_ERR(wrp->rstc);
2113                         dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);
2114                         return ret;
2115                 }
2116         }
2117
2118         if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
2119                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2120                                 "pwrap-bridge");
2121                 wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);
2122                 if (IS_ERR(wrp->bridge_base))
2123                         return PTR_ERR(wrp->bridge_base);
2124
2125                 wrp->rstc_bridge = devm_reset_control_get(wrp->dev,
2126                                                           "pwrap-bridge");
2127                 if (IS_ERR(wrp->rstc_bridge)) {
2128                         ret = PTR_ERR(wrp->rstc_bridge);
2129                         dev_dbg(wrp->dev,
2130                                 "cannot get pwrap-bridge reset: %d\n", ret);
2131                         return ret;
2132                 }
2133         }
2134
2135         wrp->clk_spi = devm_clk_get(wrp->dev, "spi");
2136         if (IS_ERR(wrp->clk_spi)) {
2137                 dev_dbg(wrp->dev, "failed to get clock: %ld\n",
2138                         PTR_ERR(wrp->clk_spi));
2139                 return PTR_ERR(wrp->clk_spi);
2140         }
2141
2142         wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap");
2143         if (IS_ERR(wrp->clk_wrap)) {
2144                 dev_dbg(wrp->dev, "failed to get clock: %ld\n",
2145                         PTR_ERR(wrp->clk_wrap));
2146                 return PTR_ERR(wrp->clk_wrap);
2147         }
2148
2149         ret = clk_prepare_enable(wrp->clk_spi);
2150         if (ret)
2151                 return ret;
2152
2153         ret = clk_prepare_enable(wrp->clk_wrap);
2154         if (ret)
2155                 goto err_out1;
2156
2157         /* Enable internal dynamic clock */
2158         if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) {
2159                 pwrap_writel(wrp, 1, PWRAP_DCM_EN);
2160                 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
2161         }
2162
2163         /*
2164          * The PMIC could already be initialized by the bootloader.
2165          * Skip initialization here in this case.
2166          */
2167         if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) {
2168                 ret = pwrap_init(wrp);
2169                 if (ret) {
2170                         dev_dbg(wrp->dev, "init failed with %d\n", ret);
2171                         goto err_out2;
2172                 }
2173         }
2174
2175         if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
2176                 mask_done = PWRAP_STATE_INIT_DONE1;
2177         else
2178                 mask_done = PWRAP_STATE_INIT_DONE0;
2179
2180         if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & mask_done)) {
2181                 dev_dbg(wrp->dev, "initialization isn't finished\n");
2182                 ret = -ENODEV;
2183                 goto err_out2;
2184         }
2185
2186         /* Initialize watchdog, may not be done by the bootloader */
2187         if (!HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
2188                 pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
2189
2190         /*
2191          * Since STAUPD was not used on mt8173 platform,
2192          * so STAUPD of WDT_SRC which should be turned off
2193          */
2194         pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN);
2195         if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1))
2196                 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1);
2197
2198         if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
2199                 pwrap_writel(wrp, 0x3, PWRAP_TIMER_EN);
2200         else
2201                 pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
2202
2203         pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
2204         /*
2205          * We add INT1 interrupt to handle starvation and request exception
2206          * If we support it, we should enable it here.
2207          */
2208         if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN))
2209                 pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN);
2210
2211         irq = platform_get_irq(pdev, 0);
2212         ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt,
2213                                IRQF_TRIGGER_HIGH,
2214                                "mt-pmic-pwrap", wrp);
2215         if (ret)
2216                 goto err_out2;
2217
2218         wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regmap);
2219         if (IS_ERR(wrp->regmap)) {
2220                 ret = PTR_ERR(wrp->regmap);
2221                 goto err_out2;
2222         }
2223
2224         ret = of_platform_populate(np, NULL, NULL, wrp->dev);
2225         if (ret) {
2226                 dev_dbg(wrp->dev, "failed to create child devices at %pOF\n",
2227                                 np);
2228                 goto err_out2;
2229         }
2230
2231         return 0;
2232
2233 err_out2:
2234         clk_disable_unprepare(wrp->clk_wrap);
2235 err_out1:
2236         clk_disable_unprepare(wrp->clk_spi);
2237
2238         return ret;
2239 }
2240
2241 static struct platform_driver pwrap_drv = {
2242         .driver = {
2243                 .name = "mt-pmic-pwrap",
2244                 .of_match_table = of_match_ptr(of_pwrap_match_tbl),
2245         },
2246         .probe = pwrap_probe,
2247 };
2248
2249 module_platform_driver(pwrap_drv);
2250
2251 MODULE_AUTHOR("Flora Fu, MediaTek");
2252 MODULE_DESCRIPTION("MediaTek MT8135 PMIC Wrapper Driver");
2253 MODULE_LICENSE("GPL v2");