drivers/soc/mediatek/mtk-pmic-wrap.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014 MediaTek Inc.
   4  * Author: Flora Fu, MediaTek
   5  */
   6 #include <linux/clk.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/io.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/regmap.h>
  14 #include <linux/reset.h>
  15
  16 #define PWRAP_MT8135_BRIDGE_IORD_ARB_EN         0x4
  17 #define PWRAP_MT8135_BRIDGE_WACS3_EN            0x10
  18 #define PWRAP_MT8135_BRIDGE_INIT_DONE3          0x14
  19 #define PWRAP_MT8135_BRIDGE_WACS4_EN            0x24
  20 #define PWRAP_MT8135_BRIDGE_INIT_DONE4          0x28
  21 #define PWRAP_MT8135_BRIDGE_INT_EN              0x38
  22 #define PWRAP_MT8135_BRIDGE_TIMER_EN            0x48
  23 #define PWRAP_MT8135_BRIDGE_WDT_UNIT            0x50
  24 #define PWRAP_MT8135_BRIDGE_WDT_SRC_EN          0x54
  25
  26 /* macro for wrapper status */
  27 #define PWRAP_GET_WACS_RDATA(x)         (((x) >> 0) & 0x0000ffff)
  28 #define PWRAP_GET_WACS_FSM(x)           (((x) >> 16) & 0x00000007)
  29 #define PWRAP_GET_WACS_REQ(x)           (((x) >> 19) & 0x00000001)
  30 #define PWRAP_STATE_SYNC_IDLE0          (1 << 20)
  31 #define PWRAP_STATE_INIT_DONE0          (1 << 21)
  32
  33 /* macro for WACS FSM */
  34 #define PWRAP_WACS_FSM_IDLE             0x00
  35 #define PWRAP_WACS_FSM_REQ              0x02
  36 #define PWRAP_WACS_FSM_WFDLE            0x04
  37 #define PWRAP_WACS_FSM_WFVLDCLR         0x06
  38 #define PWRAP_WACS_INIT_DONE            0x01
  39 #define PWRAP_WACS_WACS_SYNC_IDLE       0x01
  40 #define PWRAP_WACS_SYNC_BUSY            0x00
  41
  42 /* macro for device wrapper default value */
  43 #define PWRAP_DEW_READ_TEST_VAL         0x5aa5
  44 #define PWRAP_DEW_WRITE_TEST_VAL        0xa55a
  45
  46 /* macro for manual command */
  47 #define PWRAP_MAN_CMD_SPI_WRITE_NEW     (1 << 14)
  48 #define PWRAP_MAN_CMD_SPI_WRITE         (1 << 13)
  49 #define PWRAP_MAN_CMD_OP_CSH            (0x0 << 8)
  50 #define PWRAP_MAN_CMD_OP_CSL            (0x1 << 8)
  51 #define PWRAP_MAN_CMD_OP_CK             (0x2 << 8)
  52 #define PWRAP_MAN_CMD_OP_OUTS           (0x8 << 8)
  53 #define PWRAP_MAN_CMD_OP_OUTD           (0x9 << 8)
  54 #define PWRAP_MAN_CMD_OP_OUTQ           (0xa << 8)
  55
  56 /* macro for Watch Dog Timer Source */
  57 #define PWRAP_WDT_SRC_EN_STAUPD_TRIG            (1 << 25)
  58 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE        (1 << 20)
  59 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE        (1 << 6)
  60 #define PWRAP_WDT_SRC_MASK_ALL                  0xffffffff
  61 #define PWRAP_WDT_SRC_MASK_NO_STAUPD    ~(PWRAP_WDT_SRC_EN_STAUPD_TRIG | \
  62                                           PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \
  63                                           PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)
  64
  65 /* Group of bits used for shown slave capability */
  66 #define PWRAP_SLV_CAP_SPI       BIT(0)
  67 #define PWRAP_SLV_CAP_DUALIO    BIT(1)
  68 #define PWRAP_SLV_CAP_SECURITY  BIT(2)
  69 #define HAS_CAP(_c, _x) (((_c) & (_x)) == (_x))
  70
  71 /* Group of bits used for shown pwrap capability */
  72 #define PWRAP_CAP_BRIDGE        BIT(0)
  73 #define PWRAP_CAP_RESET         BIT(1)
  74 #define PWRAP_CAP_DCM           BIT(2)
  75 #define PWRAP_CAP_INT1_EN       BIT(3)
  76 #define PWRAP_CAP_WDT_SRC1      BIT(4)
  77
  78 /* defines for slave device wrapper registers */
  79 enum dew_regs {
  80         PWRAP_DEW_BASE,
  81         PWRAP_DEW_DIO_EN,
  82         PWRAP_DEW_READ_TEST,
  83         PWRAP_DEW_WRITE_TEST,
  84         PWRAP_DEW_CRC_EN,
  85         PWRAP_DEW_CRC_VAL,
  86         PWRAP_DEW_MON_GRP_SEL,
  87         PWRAP_DEW_CIPHER_KEY_SEL,
  88         PWRAP_DEW_CIPHER_IV_SEL,
  89         PWRAP_DEW_CIPHER_RDY,
  90         PWRAP_DEW_CIPHER_MODE,
  91         PWRAP_DEW_CIPHER_SWRST,
  92
  93         /* MT6323 only regs */
  94         PWRAP_DEW_CIPHER_EN,
  95         PWRAP_DEW_RDDMY_NO,
  96
  97         /* MT6358 only regs */
  98         PWRAP_SMT_CON1,
  99         PWRAP_DRV_CON1,
 100         PWRAP_FILTER_CON0,
 101         PWRAP_GPIO_PULLEN0_CLR,
 102         PWRAP_RG_SPI_CON0,
 103         PWRAP_RG_SPI_RECORD0,
 104         PWRAP_RG_SPI_CON2,
 105         PWRAP_RG_SPI_CON3,
 106         PWRAP_RG_SPI_CON4,
 107         PWRAP_RG_SPI_CON5,
 108         PWRAP_RG_SPI_CON6,
 109         PWRAP_RG_SPI_CON7,
 110         PWRAP_RG_SPI_CON8,
 111         PWRAP_RG_SPI_CON13,
 112         PWRAP_SPISLV_KEY,
 113
 114         /* MT6359 only regs */
 115         PWRAP_DEW_CRC_SWRST,
 116         PWRAP_DEW_RG_EN_RECORD,
 117         PWRAP_DEW_RECORD_CMD0,
 118         PWRAP_DEW_RECORD_CMD1,
 119         PWRAP_DEW_RECORD_CMD2,
 120         PWRAP_DEW_RECORD_CMD3,
 121         PWRAP_DEW_RECORD_CMD4,
 122         PWRAP_DEW_RECORD_CMD5,
 123         PWRAP_DEW_RECORD_WDATA0,
 124         PWRAP_DEW_RECORD_WDATA1,
 125         PWRAP_DEW_RECORD_WDATA2,
 126         PWRAP_DEW_RECORD_WDATA3,
 127         PWRAP_DEW_RECORD_WDATA4,
 128         PWRAP_DEW_RECORD_WDATA5,
 129         PWRAP_DEW_RG_ADDR_TARGET,
 130         PWRAP_DEW_RG_ADDR_MASK,
 131         PWRAP_DEW_RG_WDATA_TARGET,
 132         PWRAP_DEW_RG_WDATA_MASK,
 133         PWRAP_DEW_RG_SPI_RECORD_CLR,
 134         PWRAP_DEW_RG_CMD_ALERT_CLR,
 135
 136         /* MT6397 only regs */
 137         PWRAP_DEW_EVENT_OUT_EN,
 138         PWRAP_DEW_EVENT_SRC_EN,
 139         PWRAP_DEW_EVENT_SRC,
 140         PWRAP_DEW_EVENT_FLAG,
 141         PWRAP_DEW_MON_FLAG_SEL,
 142         PWRAP_DEW_EVENT_TEST,
 143         PWRAP_DEW_CIPHER_LOAD,
 144         PWRAP_DEW_CIPHER_START,
 145 };
 146
 147 static const u32 mt6323_regs[] = {
 148         [PWRAP_DEW_BASE] =              0x0000,
 149         [PWRAP_DEW_DIO_EN] =            0x018a,
 150         [PWRAP_DEW_READ_TEST] =         0x018c,
 151         [PWRAP_DEW_WRITE_TEST] =        0x018e,
 152         [PWRAP_DEW_CRC_EN] =            0x0192,
 153         [PWRAP_DEW_CRC_VAL] =           0x0194,
 154         [PWRAP_DEW_MON_GRP_SEL] =       0x0196,
 155         [PWRAP_DEW_CIPHER_KEY_SEL] =    0x0198,
 156         [PWRAP_DEW_CIPHER_IV_SEL] =     0x019a,
 157         [PWRAP_DEW_CIPHER_EN] =         0x019c,
 158         [PWRAP_DEW_CIPHER_RDY] =        0x019e,
 159         [PWRAP_DEW_CIPHER_MODE] =       0x01a0,
 160         [PWRAP_DEW_CIPHER_SWRST] =      0x01a2,
 161         [PWRAP_DEW_RDDMY_NO] =          0x01a4,
 162 };
 163
 164 static const u32 mt6351_regs[] = {
 165         [PWRAP_DEW_DIO_EN] =            0x02F2,
 166         [PWRAP_DEW_READ_TEST] =         0x02F4,
 167         [PWRAP_DEW_WRITE_TEST] =        0x02F6,
 168         [PWRAP_DEW_CRC_EN] =            0x02FA,
 169         [PWRAP_DEW_CRC_VAL] =           0x02FC,
 170         [PWRAP_DEW_CIPHER_KEY_SEL] =    0x0300,
 171         [PWRAP_DEW_CIPHER_IV_SEL] =     0x0302,
 172         [PWRAP_DEW_CIPHER_EN] =         0x0304,
 173         [PWRAP_DEW_CIPHER_RDY] =        0x0306,
 174         [PWRAP_DEW_CIPHER_MODE] =       0x0308,
 175         [PWRAP_DEW_CIPHER_SWRST] =      0x030A,
 176         [PWRAP_DEW_RDDMY_NO] =          0x030C,
 177 };
 178
 179 static const u32 mt6357_regs[] = {
 180         [PWRAP_DEW_DIO_EN] =            0x040A,
 181         [PWRAP_DEW_READ_TEST] =         0x040C,
 182         [PWRAP_DEW_WRITE_TEST] =        0x040E,
 183         [PWRAP_DEW_CRC_EN] =            0x0412,
 184         [PWRAP_DEW_CRC_VAL] =           0x0414,
 185         [PWRAP_DEW_CIPHER_KEY_SEL] =    0x0418,
 186         [PWRAP_DEW_CIPHER_IV_SEL] =     0x041A,
 187         [PWRAP_DEW_CIPHER_EN] =         0x041C,
 188         [PWRAP_DEW_CIPHER_RDY] =        0x041E,
 189         [PWRAP_DEW_CIPHER_MODE] =       0x0420,
 190         [PWRAP_DEW_CIPHER_SWRST] =      0x0422,
 191         [PWRAP_DEW_RDDMY_NO] =          0x0424,
 192 };
 193
 194 static const u32 mt6358_regs[] = {
 195         [PWRAP_SMT_CON1] =              0x0030,
 196         [PWRAP_DRV_CON1] =              0x0038,
 197         [PWRAP_FILTER_CON0] =           0x0040,
 198         [PWRAP_GPIO_PULLEN0_CLR] =      0x0098,
 199         [PWRAP_RG_SPI_CON0] =           0x0408,
 200         [PWRAP_RG_SPI_RECORD0] =        0x040a,
 201         [PWRAP_DEW_DIO_EN] =            0x040c,
 202         [PWRAP_DEW_READ_TEST]   =       0x040e,
 203         [PWRAP_DEW_WRITE_TEST]  =       0x0410,
 204         [PWRAP_DEW_CRC_EN] =            0x0414,
 205         [PWRAP_DEW_CIPHER_KEY_SEL] =    0x041a,
 206         [PWRAP_DEW_CIPHER_IV_SEL] =     0x041c,
 207         [PWRAP_DEW_CIPHER_EN]   =       0x041e,
 208         [PWRAP_DEW_CIPHER_RDY] =        0x0420,
 209         [PWRAP_DEW_CIPHER_MODE] =       0x0422,
 210         [PWRAP_DEW_CIPHER_SWRST] =      0x0424,
 211         [PWRAP_RG_SPI_CON2] =           0x0432,
 212         [PWRAP_RG_SPI_CON3] =           0x0434,
 213         [PWRAP_RG_SPI_CON4] =           0x0436,
 214         [PWRAP_RG_SPI_CON5] =           0x0438,
 215         [PWRAP_RG_SPI_CON6] =           0x043a,
 216         [PWRAP_RG_SPI_CON7] =           0x043c,
 217         [PWRAP_RG_SPI_CON8] =           0x043e,
 218         [PWRAP_RG_SPI_CON13] =          0x0448,
 219         [PWRAP_SPISLV_KEY] =            0x044a,
 220 };
 221
 222 static const u32 mt6359_regs[] = {
 223         [PWRAP_DEW_RG_EN_RECORD] =      0x040a,
 224         [PWRAP_DEW_DIO_EN] =            0x040c,
 225         [PWRAP_DEW_READ_TEST] =         0x040e,
 226         [PWRAP_DEW_WRITE_TEST] =        0x0410,
 227         [PWRAP_DEW_CRC_SWRST] =         0x0412,
 228         [PWRAP_DEW_CRC_EN] =            0x0414,
 229         [PWRAP_DEW_CRC_VAL] =           0x0416,
 230         [PWRAP_DEW_CIPHER_KEY_SEL] =    0x0418,
 231         [PWRAP_DEW_CIPHER_IV_SEL] =     0x041a,
 232         [PWRAP_DEW_CIPHER_EN] =         0x041c,
 233         [PWRAP_DEW_CIPHER_RDY] =        0x041e,
 234         [PWRAP_DEW_CIPHER_MODE] =       0x0420,
 235         [PWRAP_DEW_CIPHER_SWRST] =      0x0422,
 236         [PWRAP_DEW_RDDMY_NO] =          0x0424,
 237         [PWRAP_DEW_RECORD_CMD0] =       0x0428,
 238         [PWRAP_DEW_RECORD_CMD1] =       0x042a,
 239         [PWRAP_DEW_RECORD_CMD2] =       0x042c,
 240         [PWRAP_DEW_RECORD_CMD3] =       0x042e,
 241         [PWRAP_DEW_RECORD_CMD4] =       0x0430,
 242         [PWRAP_DEW_RECORD_CMD5] =       0x0432,
 243         [PWRAP_DEW_RECORD_WDATA0] =     0x0434,
 244         [PWRAP_DEW_RECORD_WDATA1] =     0x0436,
 245         [PWRAP_DEW_RECORD_WDATA2] =     0x0438,
 246         [PWRAP_DEW_RECORD_WDATA3] =     0x043a,
 247         [PWRAP_DEW_RECORD_WDATA4] =     0x043c,
 248         [PWRAP_DEW_RECORD_WDATA5] =     0x043e,
 249         [PWRAP_DEW_RG_ADDR_TARGET] =    0x0440,
 250         [PWRAP_DEW_RG_ADDR_MASK] =      0x0442,
 251         [PWRAP_DEW_RG_WDATA_TARGET] =   0x0444,
 252         [PWRAP_DEW_RG_WDATA_MASK] =     0x0446,
 253         [PWRAP_DEW_RG_SPI_RECORD_CLR] = 0x0448,
 254         [PWRAP_DEW_RG_CMD_ALERT_CLR] =  0x0448,
 255         [PWRAP_SPISLV_KEY] =            0x044a,
 256 };
 257
 258 static const u32 mt6397_regs[] = {
 259         [PWRAP_DEW_BASE] =              0xbc00,
 260         [PWRAP_DEW_EVENT_OUT_EN] =      0xbc00,
 261         [PWRAP_DEW_DIO_EN] =            0xbc02,
 262         [PWRAP_DEW_EVENT_SRC_EN] =      0xbc04,
 263         [PWRAP_DEW_EVENT_SRC] =         0xbc06,
 264         [PWRAP_DEW_EVENT_FLAG] =        0xbc08,
 265         [PWRAP_DEW_READ_TEST] =         0xbc0a,
 266         [PWRAP_DEW_WRITE_TEST] =        0xbc0c,
 267         [PWRAP_DEW_CRC_EN] =            0xbc0e,
 268         [PWRAP_DEW_CRC_VAL] =           0xbc10,
 269         [PWRAP_DEW_MON_GRP_SEL] =       0xbc12,
 270         [PWRAP_DEW_MON_FLAG_SEL] =      0xbc14,
 271         [PWRAP_DEW_EVENT_TEST] =        0xbc16,
 272         [PWRAP_DEW_CIPHER_KEY_SEL] =    0xbc18,
 273         [PWRAP_DEW_CIPHER_IV_SEL] =     0xbc1a,
 274         [PWRAP_DEW_CIPHER_LOAD] =       0xbc1c,
 275         [PWRAP_DEW_CIPHER_START] =      0xbc1e,
 276         [PWRAP_DEW_CIPHER_RDY] =        0xbc20,
 277         [PWRAP_DEW_CIPHER_MODE] =       0xbc22,
 278         [PWRAP_DEW_CIPHER_SWRST] =      0xbc24,
 279 };
 280
 281 enum pwrap_regs {
 282         PWRAP_MUX_SEL,
 283         PWRAP_WRAP_EN,
 284         PWRAP_DIO_EN,
 285         PWRAP_SIDLY,
 286         PWRAP_CSHEXT_WRITE,
 287         PWRAP_CSHEXT_READ,
 288         PWRAP_CSLEXT_START,
 289         PWRAP_CSLEXT_END,
 290         PWRAP_STAUPD_PRD,
 291         PWRAP_STAUPD_GRPEN,
 292         PWRAP_STAUPD_MAN_TRIG,
 293         PWRAP_STAUPD_STA,
 294         PWRAP_WRAP_STA,
 295         PWRAP_HARB_INIT,
 296         PWRAP_HARB_HPRIO,
 297         PWRAP_HIPRIO_ARB_EN,
 298         PWRAP_HARB_STA0,
 299         PWRAP_HARB_STA1,
 300         PWRAP_MAN_EN,
 301         PWRAP_MAN_CMD,
 302         PWRAP_MAN_RDATA,
 303         PWRAP_MAN_VLDCLR,
 304         PWRAP_WACS0_EN,
 305         PWRAP_INIT_DONE0,
 306         PWRAP_WACS0_CMD,
 307         PWRAP_WACS0_RDATA,
 308         PWRAP_WACS0_VLDCLR,
 309         PWRAP_WACS1_EN,
 310         PWRAP_INIT_DONE1,
 311         PWRAP_WACS1_CMD,
 312         PWRAP_WACS1_RDATA,
 313         PWRAP_WACS1_VLDCLR,
 314         PWRAP_WACS2_EN,
 315         PWRAP_INIT_DONE2,
 316         PWRAP_WACS2_CMD,
 317         PWRAP_WACS2_RDATA,
 318         PWRAP_WACS2_VLDCLR,
 319         PWRAP_INT_EN,
 320         PWRAP_INT_FLG_RAW,
 321         PWRAP_INT_FLG,
 322         PWRAP_INT_CLR,
 323         PWRAP_SIG_ADR,
 324         PWRAP_SIG_MODE,
 325         PWRAP_SIG_VALUE,
 326         PWRAP_SIG_ERRVAL,
 327         PWRAP_CRC_EN,
 328         PWRAP_TIMER_EN,
 329         PWRAP_TIMER_STA,
 330         PWRAP_WDT_UNIT,
 331         PWRAP_WDT_SRC_EN,
 332         PWRAP_WDT_FLG,
 333         PWRAP_DEBUG_INT_SEL,
 334         PWRAP_CIPHER_KEY_SEL,
 335         PWRAP_CIPHER_IV_SEL,
 336         PWRAP_CIPHER_RDY,
 337         PWRAP_CIPHER_MODE,
 338         PWRAP_CIPHER_SWRST,
 339         PWRAP_DCM_EN,
 340         PWRAP_DCM_DBC_PRD,
 341         PWRAP_EINT_STA0_ADR,
 342         PWRAP_EINT_STA1_ADR,
 343
 344         /* MT2701 only regs */
 345         PWRAP_ADC_CMD_ADDR,
 346         PWRAP_PWRAP_ADC_CMD,
 347         PWRAP_ADC_RDY_ADDR,
 348         PWRAP_ADC_RDATA_ADDR1,
 349         PWRAP_ADC_RDATA_ADDR2,
 350
 351         /* MT7622 only regs */
 352         PWRAP_STA,
 353         PWRAP_CLR,
 354         PWRAP_DVFS_ADR8,
 355         PWRAP_DVFS_WDATA8,
 356         PWRAP_DVFS_ADR9,
 357         PWRAP_DVFS_WDATA9,
 358         PWRAP_DVFS_ADR10,
 359         PWRAP_DVFS_WDATA10,
 360         PWRAP_DVFS_ADR11,
 361         PWRAP_DVFS_WDATA11,
 362         PWRAP_DVFS_ADR12,
 363         PWRAP_DVFS_WDATA12,
 364         PWRAP_DVFS_ADR13,
 365         PWRAP_DVFS_WDATA13,
 366         PWRAP_DVFS_ADR14,
 367         PWRAP_DVFS_WDATA14,
 368         PWRAP_DVFS_ADR15,
 369         PWRAP_DVFS_WDATA15,
 370         PWRAP_EXT_CK,
 371         PWRAP_ADC_RDATA_ADDR,
 372         PWRAP_GPS_STA,
 373         PWRAP_SW_RST,
 374         PWRAP_DVFS_STEP_CTRL0,
 375         PWRAP_DVFS_STEP_CTRL1,
 376         PWRAP_DVFS_STEP_CTRL2,
 377         PWRAP_SPI2_CTRL,
 378
 379         /* MT8135 only regs */
 380         PWRAP_CSHEXT,
 381         PWRAP_EVENT_IN_EN,
 382         PWRAP_EVENT_DST_EN,
 383         PWRAP_RRARB_INIT,
 384         PWRAP_RRARB_EN,
 385         PWRAP_RRARB_STA0,
 386         PWRAP_RRARB_STA1,
 387         PWRAP_EVENT_STA,
 388         PWRAP_EVENT_STACLR,
 389         PWRAP_CIPHER_LOAD,
 390         PWRAP_CIPHER_START,
 391
 392         /* MT8173 only regs */
 393         PWRAP_RDDMY,
 394         PWRAP_SI_CK_CON,
 395         PWRAP_DVFS_ADR0,
 396         PWRAP_DVFS_WDATA0,
 397         PWRAP_DVFS_ADR1,
 398         PWRAP_DVFS_WDATA1,
 399         PWRAP_DVFS_ADR2,
 400         PWRAP_DVFS_WDATA2,
 401         PWRAP_DVFS_ADR3,
 402         PWRAP_DVFS_WDATA3,
 403         PWRAP_DVFS_ADR4,
 404         PWRAP_DVFS_WDATA4,
 405         PWRAP_DVFS_ADR5,
 406         PWRAP_DVFS_WDATA5,
 407         PWRAP_DVFS_ADR6,
 408         PWRAP_DVFS_WDATA6,
 409         PWRAP_DVFS_ADR7,
 410         PWRAP_DVFS_WDATA7,
 411         PWRAP_SPMINF_STA,
 412         PWRAP_CIPHER_EN,
 413
 414         /* MT8183 only regs */
 415         PWRAP_SI_SAMPLE_CTRL,
 416         PWRAP_CSLEXT_WRITE,
 417         PWRAP_CSLEXT_READ,
 418         PWRAP_EXT_CK_WRITE,
 419         PWRAP_STAUPD_CTRL,
 420         PWRAP_WACS_P2P_EN,
 421         PWRAP_INIT_DONE_P2P,
 422         PWRAP_WACS_MD32_EN,
 423         PWRAP_INIT_DONE_MD32,
 424         PWRAP_INT1_EN,
 425         PWRAP_INT1_FLG,
 426         PWRAP_INT1_CLR,
 427         PWRAP_WDT_SRC_EN_1,
 428         PWRAP_INT_GPS_AUXADC_CMD_ADDR,
 429         PWRAP_INT_GPS_AUXADC_CMD,
 430         PWRAP_INT_GPS_AUXADC_RDATA_ADDR,
 431         PWRAP_EXT_GPS_AUXADC_RDATA_ADDR,
 432         PWRAP_GPSINF_0_STA,
 433         PWRAP_GPSINF_1_STA,
 434
 435         /* MT8516 only regs */
 436         PWRAP_OP_TYPE,
 437         PWRAP_MSB_FIRST,
 438 };
 439
 440 static int mt2701_regs[] = {
 441         [PWRAP_MUX_SEL] =               0x0,
 442         [PWRAP_WRAP_EN] =               0x4,
 443         [PWRAP_DIO_EN] =                0x8,
 444         [PWRAP_SIDLY] =                 0xc,
 445         [PWRAP_RDDMY] =                 0x18,
 446         [PWRAP_SI_CK_CON] =             0x1c,
 447         [PWRAP_CSHEXT_WRITE] =          0x20,
 448         [PWRAP_CSHEXT_READ] =           0x24,
 449         [PWRAP_CSLEXT_START] =          0x28,
 450         [PWRAP_CSLEXT_END] =            0x2c,
 451         [PWRAP_STAUPD_PRD] =            0x30,
 452         [PWRAP_STAUPD_GRPEN] =          0x34,
 453         [PWRAP_STAUPD_MAN_TRIG] =       0x38,
 454         [PWRAP_STAUPD_STA] =            0x3c,
 455         [PWRAP_WRAP_STA] =              0x44,
 456         [PWRAP_HARB_INIT] =             0x48,
 457         [PWRAP_HARB_HPRIO] =            0x4c,
 458         [PWRAP_HIPRIO_ARB_EN] =         0x50,
 459         [PWRAP_HARB_STA0] =             0x54,
 460         [PWRAP_HARB_STA1] =             0x58,
 461         [PWRAP_MAN_EN] =                0x5c,
 462         [PWRAP_MAN_CMD] =               0x60,
 463         [PWRAP_MAN_RDATA] =             0x64,
 464         [PWRAP_MAN_VLDCLR] =            0x68,
 465         [PWRAP_WACS0_EN] =              0x6c,
 466         [PWRAP_INIT_DONE0] =            0x70,
 467         [PWRAP_WACS0_CMD] =             0x74,
 468         [PWRAP_WACS0_RDATA] =           0x78,
 469         [PWRAP_WACS0_VLDCLR] =          0x7c,
 470         [PWRAP_WACS1_EN] =              0x80,
 471         [PWRAP_INIT_DONE1] =            0x84,
 472         [PWRAP_WACS1_CMD] =             0x88,
 473         [PWRAP_WACS1_RDATA] =           0x8c,
 474         [PWRAP_WACS1_VLDCLR] =          0x90,
 475         [PWRAP_WACS2_EN] =              0x94,
 476         [PWRAP_INIT_DONE2] =            0x98,
 477         [PWRAP_WACS2_CMD] =             0x9c,
 478         [PWRAP_WACS2_RDATA] =           0xa0,
 479         [PWRAP_WACS2_VLDCLR] =          0xa4,
 480         [PWRAP_INT_EN] =                0xa8,
 481         [PWRAP_INT_FLG_RAW] =           0xac,
 482         [PWRAP_INT_FLG] =               0xb0,
 483         [PWRAP_INT_CLR] =               0xb4,
 484         [PWRAP_SIG_ADR] =               0xb8,
 485         [PWRAP_SIG_MODE] =              0xbc,
 486         [PWRAP_SIG_VALUE] =             0xc0,
 487         [PWRAP_SIG_ERRVAL] =            0xc4,
 488         [PWRAP_CRC_EN] =                0xc8,
 489         [PWRAP_TIMER_EN] =              0xcc,
 490         [PWRAP_TIMER_STA] =             0xd0,
 491         [PWRAP_WDT_UNIT] =              0xd4,
 492         [PWRAP_WDT_SRC_EN] =            0xd8,
 493         [PWRAP_WDT_FLG] =               0xdc,
 494         [PWRAP_DEBUG_INT_SEL] =         0xe0,
 495         [PWRAP_DVFS_ADR0] =             0xe4,
 496         [PWRAP_DVFS_WDATA0] =           0xe8,
 497         [PWRAP_DVFS_ADR1] =             0xec,
 498         [PWRAP_DVFS_WDATA1] =           0xf0,
 499         [PWRAP_DVFS_ADR2] =             0xf4,
 500         [PWRAP_DVFS_WDATA2] =           0xf8,
 501         [PWRAP_DVFS_ADR3] =             0xfc,
 502         [PWRAP_DVFS_WDATA3] =           0x100,
 503         [PWRAP_DVFS_ADR4] =             0x104,
 504         [PWRAP_DVFS_WDATA4] =           0x108,
 505         [PWRAP_DVFS_ADR5] =             0x10c,
 506         [PWRAP_DVFS_WDATA5] =           0x110,
 507         [PWRAP_DVFS_ADR6] =             0x114,
 508         [PWRAP_DVFS_WDATA6] =           0x118,
 509         [PWRAP_DVFS_ADR7] =             0x11c,
 510         [PWRAP_DVFS_WDATA7] =           0x120,
 511         [PWRAP_CIPHER_KEY_SEL] =        0x124,
 512         [PWRAP_CIPHER_IV_SEL] =         0x128,
 513         [PWRAP_CIPHER_EN] =             0x12c,
 514         [PWRAP_CIPHER_RDY] =            0x130,
 515         [PWRAP_CIPHER_MODE] =           0x134,
 516         [PWRAP_CIPHER_SWRST] =          0x138,
 517         [PWRAP_DCM_EN] =                0x13c,
 518         [PWRAP_DCM_DBC_PRD] =           0x140,
 519         [PWRAP_ADC_CMD_ADDR] =          0x144,
 520         [PWRAP_PWRAP_ADC_CMD] =         0x148,
 521         [PWRAP_ADC_RDY_ADDR] =          0x14c,
 522         [PWRAP_ADC_RDATA_ADDR1] =       0x150,
 523         [PWRAP_ADC_RDATA_ADDR2] =       0x154,
 524 };
 525
 526 static int mt6765_regs[] = {
 527         [PWRAP_MUX_SEL] =               0x0,
 528         [PWRAP_WRAP_EN] =               0x4,
 529         [PWRAP_DIO_EN] =                0x8,
 530         [PWRAP_RDDMY] =                 0x20,
 531         [PWRAP_CSHEXT_WRITE] =          0x24,
 532         [PWRAP_CSHEXT_READ] =           0x28,
 533         [PWRAP_CSLEXT_START] =          0x2C,
 534         [PWRAP_CSLEXT_END] =            0x30,
 535         [PWRAP_STAUPD_PRD] =            0x3C,
 536         [PWRAP_HARB_HPRIO] =            0x68,
 537         [PWRAP_HIPRIO_ARB_EN] =         0x6C,
 538         [PWRAP_MAN_EN] =                0x7C,
 539         [PWRAP_MAN_CMD] =               0x80,
 540         [PWRAP_WACS0_EN] =              0x8C,
 541         [PWRAP_WACS1_EN] =              0x94,
 542         [PWRAP_WACS2_EN] =              0x9C,
 543         [PWRAP_INIT_DONE2] =            0xA0,
 544         [PWRAP_WACS2_CMD] =             0xC20,
 545         [PWRAP_WACS2_RDATA] =           0xC24,
 546         [PWRAP_WACS2_VLDCLR] =          0xC28,
 547         [PWRAP_INT_EN] =                0xB4,
 548         [PWRAP_INT_FLG_RAW] =           0xB8,
 549         [PWRAP_INT_FLG] =               0xBC,
 550         [PWRAP_INT_CLR] =               0xC0,
 551         [PWRAP_TIMER_EN] =              0xE8,
 552         [PWRAP_WDT_UNIT] =              0xF0,
 553         [PWRAP_WDT_SRC_EN] =            0xF4,
 554         [PWRAP_DCM_EN] =                0x1DC,
 555         [PWRAP_DCM_DBC_PRD] =           0x1E0,
 556 };
 557
 558 static int mt6779_regs[] = {
 559         [PWRAP_MUX_SEL] =               0x0,
 560         [PWRAP_WRAP_EN] =               0x4,
 561         [PWRAP_DIO_EN] =                0x8,
 562         [PWRAP_RDDMY] =                 0x20,
 563         [PWRAP_CSHEXT_WRITE] =          0x24,
 564         [PWRAP_CSHEXT_READ] =           0x28,
 565         [PWRAP_CSLEXT_WRITE] =          0x2C,
 566         [PWRAP_CSLEXT_READ] =           0x30,
 567         [PWRAP_EXT_CK_WRITE] =          0x34,
 568         [PWRAP_STAUPD_CTRL] =           0x3C,
 569         [PWRAP_STAUPD_GRPEN] =          0x40,
 570         [PWRAP_EINT_STA0_ADR] =         0x44,
 571         [PWRAP_HARB_HPRIO] =            0x68,
 572         [PWRAP_HIPRIO_ARB_EN] =         0x6C,
 573         [PWRAP_MAN_EN] =                0x7C,
 574         [PWRAP_MAN_CMD] =               0x80,
 575         [PWRAP_WACS0_EN] =              0x8C,
 576         [PWRAP_INIT_DONE0] =            0x90,
 577         [PWRAP_WACS1_EN] =              0x94,
 578         [PWRAP_WACS2_EN] =              0x9C,
 579         [PWRAP_INIT_DONE1] =            0x98,
 580         [PWRAP_INIT_DONE2] =            0xA0,
 581         [PWRAP_INT_EN] =                0xBC,
 582         [PWRAP_INT_FLG_RAW] =           0xC0,
 583         [PWRAP_INT_FLG] =               0xC4,
 584         [PWRAP_INT_CLR] =               0xC8,
 585         [PWRAP_INT1_EN] =               0xCC,
 586         [PWRAP_INT1_FLG] =              0xD4,
 587         [PWRAP_INT1_CLR] =              0xD8,
 588         [PWRAP_TIMER_EN] =              0xF0,
 589         [PWRAP_WDT_UNIT] =              0xF8,
 590         [PWRAP_WDT_SRC_EN] =            0xFC,
 591         [PWRAP_WDT_SRC_EN_1] =          0x100,
 592         [PWRAP_WACS2_CMD] =             0xC20,
 593         [PWRAP_WACS2_RDATA] =           0xC24,
 594         [PWRAP_WACS2_VLDCLR] =          0xC28,
 595 };
 596
 597 static int mt6797_regs[] = {
 598         [PWRAP_MUX_SEL] =               0x0,
 599         [PWRAP_WRAP_EN] =               0x4,
 600         [PWRAP_DIO_EN] =                0x8,
 601         [PWRAP_SIDLY] =                 0xC,
 602         [PWRAP_RDDMY] =                 0x10,
 603         [PWRAP_CSHEXT_WRITE] =          0x18,
 604         [PWRAP_CSHEXT_READ] =           0x1C,
 605         [PWRAP_CSLEXT_START] =          0x20,
 606         [PWRAP_CSLEXT_END] =            0x24,
 607         [PWRAP_STAUPD_PRD] =            0x28,
 608         [PWRAP_HARB_HPRIO] =            0x50,
 609         [PWRAP_HIPRIO_ARB_EN] =         0x54,
 610         [PWRAP_MAN_EN] =                0x60,
 611         [PWRAP_MAN_CMD] =               0x64,
 612         [PWRAP_WACS0_EN] =              0x70,
 613         [PWRAP_WACS1_EN] =              0x84,
 614         [PWRAP_WACS2_EN] =              0x98,
 615         [PWRAP_INIT_DONE2] =            0x9C,
 616         [PWRAP_WACS2_CMD] =             0xA0,
 617         [PWRAP_WACS2_RDATA] =           0xA4,
 618         [PWRAP_WACS2_VLDCLR] =          0xA8,
 619         [PWRAP_INT_EN] =                0xC0,
 620         [PWRAP_INT_FLG_RAW] =           0xC4,
 621         [PWRAP_INT_FLG] =               0xC8,
 622         [PWRAP_INT_CLR] =               0xCC,
 623         [PWRAP_TIMER_EN] =              0xF4,
 624         [PWRAP_WDT_UNIT] =              0xFC,
 625         [PWRAP_WDT_SRC_EN] =            0x100,
 626         [PWRAP_DCM_EN] =                0x1CC,
 627         [PWRAP_DCM_DBC_PRD] =           0x1D4,
 628 };
 629
 630 static int mt7622_regs[] = {
 631         [PWRAP_MUX_SEL] =               0x0,
 632         [PWRAP_WRAP_EN] =               0x4,
 633         [PWRAP_DIO_EN] =                0x8,
 634         [PWRAP_SIDLY] =                 0xC,
 635         [PWRAP_RDDMY] =                 0x10,
 636         [PWRAP_SI_CK_CON] =             0x14,
 637         [PWRAP_CSHEXT_WRITE] =          0x18,
 638         [PWRAP_CSHEXT_READ] =           0x1C,
 639         [PWRAP_CSLEXT_START] =          0x20,
 640         [PWRAP_CSLEXT_END] =            0x24,
 641         [PWRAP_STAUPD_PRD] =            0x28,
 642         [PWRAP_STAUPD_GRPEN] =          0x2C,
 643         [PWRAP_EINT_STA0_ADR] =         0x30,
 644         [PWRAP_EINT_STA1_ADR] =         0x34,
 645         [PWRAP_STA] =                   0x38,
 646         [PWRAP_CLR] =                   0x3C,
 647         [PWRAP_STAUPD_MAN_TRIG] =       0x40,
 648         [PWRAP_STAUPD_STA] =            0x44,
 649         [PWRAP_WRAP_STA] =              0x48,
 650         [PWRAP_HARB_INIT] =             0x4C,
 651         [PWRAP_HARB_HPRIO] =            0x50,
 652         [PWRAP_HIPRIO_ARB_EN] =         0x54,
 653         [PWRAP_HARB_STA0] =             0x58,
 654         [PWRAP_HARB_STA1] =             0x5C,
 655         [PWRAP_MAN_EN] =                0x60,
 656         [PWRAP_MAN_CMD] =               0x64,
 657         [PWRAP_MAN_RDATA] =             0x68,
 658         [PWRAP_MAN_VLDCLR] =            0x6C,
 659         [PWRAP_WACS0_EN] =              0x70,
 660         [PWRAP_INIT_DONE0] =            0x74,
 661         [PWRAP_WACS0_CMD] =             0x78,
 662         [PWRAP_WACS0_RDATA] =           0x7C,
 663         [PWRAP_WACS0_VLDCLR] =          0x80,
 664         [PWRAP_WACS1_EN] =              0x84,
 665         [PWRAP_INIT_DONE1] =            0x88,
 666         [PWRAP_WACS1_CMD] =             0x8C,
 667         [PWRAP_WACS1_RDATA] =           0x90,
 668         [PWRAP_WACS1_VLDCLR] =          0x94,
 669         [PWRAP_WACS2_EN] =              0x98,
 670         [PWRAP_INIT_DONE2] =            0x9C,
 671         [PWRAP_WACS2_CMD] =             0xA0,
 672         [PWRAP_WACS2_RDATA] =           0xA4,
 673         [PWRAP_WACS2_VLDCLR] =          0xA8,
 674         [PWRAP_INT_EN] =                0xAC,
 675         [PWRAP_INT_FLG_RAW] =           0xB0,
 676         [PWRAP_INT_FLG] =               0xB4,
 677         [PWRAP_INT_CLR] =               0xB8,
 678         [PWRAP_SIG_ADR] =               0xBC,
 679         [PWRAP_SIG_MODE] =              0xC0,
 680         [PWRAP_SIG_VALUE] =             0xC4,
 681         [PWRAP_SIG_ERRVAL] =            0xC8,
 682         [PWRAP_CRC_EN] =                0xCC,
 683         [PWRAP_TIMER_EN] =              0xD0,
 684         [PWRAP_TIMER_STA] =             0xD4,
 685         [PWRAP_WDT_UNIT] =              0xD8,
 686         [PWRAP_WDT_SRC_EN] =            0xDC,
 687         [PWRAP_WDT_FLG] =               0xE0,
 688         [PWRAP_DEBUG_INT_SEL] =         0xE4,
 689         [PWRAP_DVFS_ADR0] =             0xE8,
 690         [PWRAP_DVFS_WDATA0] =           0xEC,
 691         [PWRAP_DVFS_ADR1] =             0xF0,
 692         [PWRAP_DVFS_WDATA1] =           0xF4,
 693         [PWRAP_DVFS_ADR2] =             0xF8,
 694         [PWRAP_DVFS_WDATA2] =           0xFC,
 695         [PWRAP_DVFS_ADR3] =             0x100,
 696         [PWRAP_DVFS_WDATA3] =           0x104,
 697         [PWRAP_DVFS_ADR4] =             0x108,
 698         [PWRAP_DVFS_WDATA4] =           0x10C,
 699         [PWRAP_DVFS_ADR5] =             0x110,
 700         [PWRAP_DVFS_WDATA5] =           0x114,
 701         [PWRAP_DVFS_ADR6] =             0x118,
 702         [PWRAP_DVFS_WDATA6] =           0x11C,
 703         [PWRAP_DVFS_ADR7] =             0x120,
 704         [PWRAP_DVFS_WDATA7] =           0x124,
 705         [PWRAP_DVFS_ADR8] =             0x128,
 706         [PWRAP_DVFS_WDATA8] =           0x12C,
 707         [PWRAP_DVFS_ADR9] =             0x130,
 708         [PWRAP_DVFS_WDATA9] =           0x134,
 709         [PWRAP_DVFS_ADR10] =            0x138,
 710         [PWRAP_DVFS_WDATA10] =          0x13C,
 711         [PWRAP_DVFS_ADR11] =            0x140,
 712         [PWRAP_DVFS_WDATA11] =          0x144,
 713         [PWRAP_DVFS_ADR12] =            0x148,
 714         [PWRAP_DVFS_WDATA12] =          0x14C,
 715         [PWRAP_DVFS_ADR13] =            0x150,
 716         [PWRAP_DVFS_WDATA13] =          0x154,
 717         [PWRAP_DVFS_ADR14] =            0x158,
 718         [PWRAP_DVFS_WDATA14] =          0x15C,
 719         [PWRAP_DVFS_ADR15] =            0x160,
 720         [PWRAP_DVFS_WDATA15] =          0x164,
 721         [PWRAP_SPMINF_STA] =            0x168,
 722         [PWRAP_CIPHER_KEY_SEL] =        0x16C,
 723         [PWRAP_CIPHER_IV_SEL] =         0x170,
 724         [PWRAP_CIPHER_EN] =             0x174,
 725         [PWRAP_CIPHER_RDY] =            0x178,
 726         [PWRAP_CIPHER_MODE] =           0x17C,
 727         [PWRAP_CIPHER_SWRST] =          0x180,
 728         [PWRAP_DCM_EN] =                0x184,
 729         [PWRAP_DCM_DBC_PRD] =           0x188,
 730         [PWRAP_EXT_CK] =                0x18C,
 731         [PWRAP_ADC_CMD_ADDR] =          0x190,
 732         [PWRAP_PWRAP_ADC_CMD] =         0x194,
 733         [PWRAP_ADC_RDATA_ADDR] =        0x198,
 734         [PWRAP_GPS_STA] =               0x19C,
 735         [PWRAP_SW_RST] =                0x1A0,
 736         [PWRAP_DVFS_STEP_CTRL0] =       0x238,
 737         [PWRAP_DVFS_STEP_CTRL1] =       0x23C,
 738         [PWRAP_DVFS_STEP_CTRL2] =       0x240,
 739         [PWRAP_SPI2_CTRL] =             0x244,
 740 };
 741
 742 static int mt8135_regs[] = {
 743         [PWRAP_MUX_SEL] =               0x0,
 744         [PWRAP_WRAP_EN] =               0x4,
 745         [PWRAP_DIO_EN] =                0x8,
 746         [PWRAP_SIDLY] =                 0xc,
 747         [PWRAP_CSHEXT] =                0x10,
 748         [PWRAP_CSHEXT_WRITE] =          0x14,
 749         [PWRAP_CSHEXT_READ] =           0x18,
 750         [PWRAP_CSLEXT_START] =          0x1c,
 751         [PWRAP_CSLEXT_END] =            0x20,
 752         [PWRAP_STAUPD_PRD] =            0x24,
 753         [PWRAP_STAUPD_GRPEN] =          0x28,
 754         [PWRAP_STAUPD_MAN_TRIG] =       0x2c,
 755         [PWRAP_STAUPD_STA] =            0x30,
 756         [PWRAP_EVENT_IN_EN] =           0x34,
 757         [PWRAP_EVENT_DST_EN] =          0x38,
 758         [PWRAP_WRAP_STA] =              0x3c,
 759         [PWRAP_RRARB_INIT] =            0x40,
 760         [PWRAP_RRARB_EN] =              0x44,
 761         [PWRAP_RRARB_STA0] =            0x48,
 762         [PWRAP_RRARB_STA1] =            0x4c,
 763         [PWRAP_HARB_INIT] =             0x50,
 764         [PWRAP_HARB_HPRIO] =            0x54,
 765         [PWRAP_HIPRIO_ARB_EN] =         0x58,
 766         [PWRAP_HARB_STA0] =             0x5c,
 767         [PWRAP_HARB_STA1] =             0x60,
 768         [PWRAP_MAN_EN] =                0x64,
 769         [PWRAP_MAN_CMD] =               0x68,
 770         [PWRAP_MAN_RDATA] =             0x6c,
 771         [PWRAP_MAN_VLDCLR] =            0x70,
 772         [PWRAP_WACS0_EN] =              0x74,
 773         [PWRAP_INIT_DONE0] =            0x78,
 774         [PWRAP_WACS0_CMD] =             0x7c,
 775         [PWRAP_WACS0_RDATA] =           0x80,
 776         [PWRAP_WACS0_VLDCLR] =          0x84,
 777         [PWRAP_WACS1_EN] =              0x88,
 778         [PWRAP_INIT_DONE1] =            0x8c,
 779         [PWRAP_WACS1_CMD] =             0x90,
 780         [PWRAP_WACS1_RDATA] =           0x94,
 781         [PWRAP_WACS1_VLDCLR] =          0x98,
 782         [PWRAP_WACS2_EN] =              0x9c,
 783         [PWRAP_INIT_DONE2] =            0xa0,
 784         [PWRAP_WACS2_CMD] =             0xa4,
 785         [PWRAP_WACS2_RDATA] =           0xa8,
 786         [PWRAP_WACS2_VLDCLR] =          0xac,
 787         [PWRAP_INT_EN] =                0xb0,
 788         [PWRAP_INT_FLG_RAW] =           0xb4,
 789         [PWRAP_INT_FLG] =               0xb8,
 790         [PWRAP_INT_CLR] =               0xbc,
 791         [PWRAP_SIG_ADR] =               0xc0,
 792         [PWRAP_SIG_MODE] =              0xc4,
 793         [PWRAP_SIG_VALUE] =             0xc8,
 794         [PWRAP_SIG_ERRVAL] =            0xcc,
 795         [PWRAP_CRC_EN] =                0xd0,
 796         [PWRAP_EVENT_STA] =             0xd4,
 797         [PWRAP_EVENT_STACLR] =          0xd8,
 798         [PWRAP_TIMER_EN] =              0xdc,
 799         [PWRAP_TIMER_STA] =             0xe0,
 800         [PWRAP_WDT_UNIT] =              0xe4,
 801         [PWRAP_WDT_SRC_EN] =            0xe8,
 802         [PWRAP_WDT_FLG] =               0xec,
 803         [PWRAP_DEBUG_INT_SEL] =         0xf0,
 804         [PWRAP_CIPHER_KEY_SEL] =        0x134,
 805         [PWRAP_CIPHER_IV_SEL] =         0x138,
 806         [PWRAP_CIPHER_LOAD] =           0x13c,
 807         [PWRAP_CIPHER_START] =          0x140,
 808         [PWRAP_CIPHER_RDY] =            0x144,
 809         [PWRAP_CIPHER_MODE] =           0x148,
 810         [PWRAP_CIPHER_SWRST] =          0x14c,
 811         [PWRAP_DCM_EN] =                0x15c,
 812         [PWRAP_DCM_DBC_PRD] =           0x160,
 813 };
 814
 815 static int mt8173_regs[] = {
 816         [PWRAP_MUX_SEL] =               0x0,
 817         [PWRAP_WRAP_EN] =               0x4,
 818         [PWRAP_DIO_EN] =                0x8,
 819         [PWRAP_SIDLY] =                 0xc,
 820         [PWRAP_RDDMY] =                 0x10,
 821         [PWRAP_SI_CK_CON] =             0x14,
 822         [PWRAP_CSHEXT_WRITE] =          0x18,
 823         [PWRAP_CSHEXT_READ] =           0x1c,
 824         [PWRAP_CSLEXT_START] =          0x20,
 825         [PWRAP_CSLEXT_END] =            0x24,
 826         [PWRAP_STAUPD_PRD] =            0x28,
 827         [PWRAP_STAUPD_GRPEN] =          0x2c,
 828         [PWRAP_STAUPD_MAN_TRIG] =       0x40,
 829         [PWRAP_STAUPD_STA] =            0x44,
 830         [PWRAP_WRAP_STA] =              0x48,
 831         [PWRAP_HARB_INIT] =             0x4c,
 832         [PWRAP_HARB_HPRIO] =            0x50,
 833         [PWRAP_HIPRIO_ARB_EN] =         0x54,
 834         [PWRAP_HARB_STA0] =             0x58,
 835         [PWRAP_HARB_STA1] =             0x5c,
 836         [PWRAP_MAN_EN] =                0x60,
 837         [PWRAP_MAN_CMD] =               0x64,
 838         [PWRAP_MAN_RDATA] =             0x68,
 839         [PWRAP_MAN_VLDCLR] =            0x6c,
 840         [PWRAP_WACS0_EN] =              0x70,
 841         [PWRAP_INIT_DONE0] =            0x74,
 842         [PWRAP_WACS0_CMD] =             0x78,
 843         [PWRAP_WACS0_RDATA] =           0x7c,
 844         [PWRAP_WACS0_VLDCLR] =          0x80,
 845         [PWRAP_WACS1_EN] =              0x84,
 846         [PWRAP_INIT_DONE1] =            0x88,
 847         [PWRAP_WACS1_CMD] =             0x8c,
 848         [PWRAP_WACS1_RDATA] =           0x90,
 849         [PWRAP_WACS1_VLDCLR] =          0x94,
 850         [PWRAP_WACS2_EN] =              0x98,
 851         [PWRAP_INIT_DONE2] =            0x9c,
 852         [PWRAP_WACS2_CMD] =             0xa0,
 853         [PWRAP_WACS2_RDATA] =           0xa4,
 854         [PWRAP_WACS2_VLDCLR] =          0xa8,
 855         [PWRAP_INT_EN] =                0xac,
 856         [PWRAP_INT_FLG_RAW] =           0xb0,
 857         [PWRAP_INT_FLG] =               0xb4,
 858         [PWRAP_INT_CLR] =               0xb8,
 859         [PWRAP_SIG_ADR] =               0xbc,
 860         [PWRAP_SIG_MODE] =              0xc0,
 861         [PWRAP_SIG_VALUE] =             0xc4,
 862         [PWRAP_SIG_ERRVAL] =            0xc8,
 863         [PWRAP_CRC_EN] =                0xcc,
 864         [PWRAP_TIMER_EN] =              0xd0,
 865         [PWRAP_TIMER_STA] =             0xd4,
 866         [PWRAP_WDT_UNIT] =              0xd8,
 867         [PWRAP_WDT_SRC_EN] =            0xdc,
 868         [PWRAP_WDT_FLG] =               0xe0,
 869         [PWRAP_DEBUG_INT_SEL] =         0xe4,
 870         [PWRAP_DVFS_ADR0] =             0xe8,
 871         [PWRAP_DVFS_WDATA0] =           0xec,
 872         [PWRAP_DVFS_ADR1] =             0xf0,
 873         [PWRAP_DVFS_WDATA1] =           0xf4,
 874         [PWRAP_DVFS_ADR2] =             0xf8,
 875         [PWRAP_DVFS_WDATA2] =           0xfc,
 876         [PWRAP_DVFS_ADR3] =             0x100,
 877         [PWRAP_DVFS_WDATA3] =           0x104,
 878         [PWRAP_DVFS_ADR4] =             0x108,
 879         [PWRAP_DVFS_WDATA4] =           0x10c,
 880         [PWRAP_DVFS_ADR5] =             0x110,
 881         [PWRAP_DVFS_WDATA5] =           0x114,
 882         [PWRAP_DVFS_ADR6] =             0x118,
 883         [PWRAP_DVFS_WDATA6] =           0x11c,
 884         [PWRAP_DVFS_ADR7] =             0x120,
 885         [PWRAP_DVFS_WDATA7] =           0x124,
 886         [PWRAP_SPMINF_STA] =            0x128,
 887         [PWRAP_CIPHER_KEY_SEL] =        0x12c,
 888         [PWRAP_CIPHER_IV_SEL] =         0x130,
 889         [PWRAP_CIPHER_EN] =             0x134,
 890         [PWRAP_CIPHER_RDY] =            0x138,
 891         [PWRAP_CIPHER_MODE] =           0x13c,
 892         [PWRAP_CIPHER_SWRST] =          0x140,
 893         [PWRAP_DCM_EN] =                0x144,
 894         [PWRAP_DCM_DBC_PRD] =           0x148,
 895 };
 896
 897 static int mt8183_regs[] = {
 898         [PWRAP_MUX_SEL] =                       0x0,
 899         [PWRAP_WRAP_EN] =                       0x4,
 900         [PWRAP_DIO_EN] =                        0x8,
 901         [PWRAP_SI_SAMPLE_CTRL] =                0xC,
 902         [PWRAP_RDDMY] =                         0x14,
 903         [PWRAP_CSHEXT_WRITE] =                  0x18,
 904         [PWRAP_CSHEXT_READ] =                   0x1C,
 905         [PWRAP_CSLEXT_WRITE] =                  0x20,
 906         [PWRAP_CSLEXT_READ] =                   0x24,
 907         [PWRAP_EXT_CK_WRITE] =                  0x28,
 908         [PWRAP_STAUPD_CTRL] =                   0x30,
 909         [PWRAP_STAUPD_GRPEN] =                  0x34,
 910         [PWRAP_EINT_STA0_ADR] =                 0x38,
 911         [PWRAP_HARB_HPRIO] =                    0x5C,
 912         [PWRAP_HIPRIO_ARB_EN] =                 0x60,
 913         [PWRAP_MAN_EN] =                        0x70,
 914         [PWRAP_MAN_CMD] =                       0x74,
 915         [PWRAP_WACS0_EN] =                      0x80,
 916         [PWRAP_INIT_DONE0] =                    0x84,
 917         [PWRAP_WACS1_EN] =                      0x88,
 918         [PWRAP_INIT_DONE1] =                    0x8C,
 919         [PWRAP_WACS2_EN] =                      0x90,
 920         [PWRAP_INIT_DONE2] =                    0x94,
 921         [PWRAP_WACS_P2P_EN] =                   0xA0,
 922         [PWRAP_INIT_DONE_P2P] =                 0xA4,
 923         [PWRAP_WACS_MD32_EN] =                  0xA8,
 924         [PWRAP_INIT_DONE_MD32] =                0xAC,
 925         [PWRAP_INT_EN] =                        0xB0,
 926         [PWRAP_INT_FLG] =                       0xB8,
 927         [PWRAP_INT_CLR] =                       0xBC,
 928         [PWRAP_INT1_EN] =                       0xC0,
 929         [PWRAP_INT1_FLG] =                      0xC8,
 930         [PWRAP_INT1_CLR] =                      0xCC,
 931         [PWRAP_SIG_ADR] =                       0xD0,
 932         [PWRAP_CRC_EN] =                        0xE0,
 933         [PWRAP_TIMER_EN] =                      0xE4,
 934         [PWRAP_WDT_UNIT] =                      0xEC,
 935         [PWRAP_WDT_SRC_EN] =                    0xF0,
 936         [PWRAP_WDT_SRC_EN_1] =                  0xF4,
 937         [PWRAP_INT_GPS_AUXADC_CMD_ADDR] =       0x1DC,
 938         [PWRAP_INT_GPS_AUXADC_CMD] =            0x1E0,
 939         [PWRAP_INT_GPS_AUXADC_RDATA_ADDR] =     0x1E4,
 940         [PWRAP_EXT_GPS_AUXADC_RDATA_ADDR] =     0x1E8,
 941         [PWRAP_GPSINF_0_STA] =                  0x1EC,
 942         [PWRAP_GPSINF_1_STA] =                  0x1F0,
 943         [PWRAP_WACS2_CMD] =                     0xC20,
 944         [PWRAP_WACS2_RDATA] =                   0xC24,
 945         [PWRAP_WACS2_VLDCLR] =                  0xC28,
 946 };
 947
 948 static int mt8516_regs[] = {
 949         [PWRAP_MUX_SEL] =               0x0,
 950         [PWRAP_WRAP_EN] =               0x4,
 951         [PWRAP_DIO_EN] =                0x8,
 952         [PWRAP_SIDLY] =                 0xc,
 953         [PWRAP_RDDMY] =                 0x10,
 954         [PWRAP_SI_CK_CON] =             0x14,
 955         [PWRAP_CSHEXT_WRITE] =          0x18,
 956         [PWRAP_CSHEXT_READ] =           0x1c,
 957         [PWRAP_CSLEXT_START] =          0x20,
 958         [PWRAP_CSLEXT_END] =            0x24,
 959         [PWRAP_STAUPD_PRD] =            0x28,
 960         [PWRAP_STAUPD_GRPEN] =          0x2c,
 961         [PWRAP_STAUPD_MAN_TRIG] =       0x40,
 962         [PWRAP_STAUPD_STA] =            0x44,
 963         [PWRAP_WRAP_STA] =              0x48,
 964         [PWRAP_HARB_INIT] =             0x4c,
 965         [PWRAP_HARB_HPRIO] =            0x50,
 966         [PWRAP_HIPRIO_ARB_EN] =         0x54,
 967         [PWRAP_HARB_STA0] =             0x58,
 968         [PWRAP_HARB_STA1] =             0x5c,
 969         [PWRAP_MAN_EN] =                0x60,
 970         [PWRAP_MAN_CMD] =               0x64,
 971         [PWRAP_MAN_RDATA] =             0x68,
 972         [PWRAP_MAN_VLDCLR] =            0x6c,
 973         [PWRAP_WACS0_EN] =              0x70,
 974         [PWRAP_INIT_DONE0] =            0x74,
 975         [PWRAP_WACS0_CMD] =             0x78,
 976         [PWRAP_WACS0_RDATA] =           0x7c,
 977         [PWRAP_WACS0_VLDCLR] =          0x80,
 978         [PWRAP_WACS1_EN] =              0x84,
 979         [PWRAP_INIT_DONE1] =            0x88,
 980         [PWRAP_WACS1_CMD] =             0x8c,
 981         [PWRAP_WACS1_RDATA] =           0x90,
 982         [PWRAP_WACS1_VLDCLR] =          0x94,
 983         [PWRAP_WACS2_EN] =              0x98,
 984         [PWRAP_INIT_DONE2] =            0x9c,
 985         [PWRAP_WACS2_CMD] =             0xa0,
 986         [PWRAP_WACS2_RDATA] =           0xa4,
 987         [PWRAP_WACS2_VLDCLR] =          0xa8,
 988         [PWRAP_INT_EN] =                0xac,
 989         [PWRAP_INT_FLG_RAW] =           0xb0,
 990         [PWRAP_INT_FLG] =               0xb4,
 991         [PWRAP_INT_CLR] =               0xb8,
 992         [PWRAP_SIG_ADR] =               0xbc,
 993         [PWRAP_SIG_MODE] =              0xc0,
 994         [PWRAP_SIG_VALUE] =             0xc4,
 995         [PWRAP_SIG_ERRVAL] =            0xc8,
 996         [PWRAP_CRC_EN] =                0xcc,
 997         [PWRAP_TIMER_EN] =              0xd0,
 998         [PWRAP_TIMER_STA] =             0xd4,
 999         [PWRAP_WDT_UNIT] =              0xd8,
1000         [PWRAP_WDT_SRC_EN] =            0xdc,
1001         [PWRAP_WDT_FLG] =               0xe0,
1002         [PWRAP_DEBUG_INT_SEL] =         0xe4,
1003         [PWRAP_DVFS_ADR0] =             0xe8,
1004         [PWRAP_DVFS_WDATA0] =           0xec,
1005         [PWRAP_DVFS_ADR1] =             0xf0,
1006         [PWRAP_DVFS_WDATA1] =           0xf4,
1007         [PWRAP_DVFS_ADR2] =             0xf8,
1008         [PWRAP_DVFS_WDATA2] =           0xfc,
1009         [PWRAP_DVFS_ADR3] =             0x100,
1010         [PWRAP_DVFS_WDATA3] =           0x104,
1011         [PWRAP_DVFS_ADR4] =             0x108,
1012         [PWRAP_DVFS_WDATA4] =           0x10c,
1013         [PWRAP_DVFS_ADR5] =             0x110,
1014         [PWRAP_DVFS_WDATA5] =           0x114,
1015         [PWRAP_DVFS_ADR6] =             0x118,
1016         [PWRAP_DVFS_WDATA6] =           0x11c,
1017         [PWRAP_DVFS_ADR7] =             0x120,
1018         [PWRAP_DVFS_WDATA7] =           0x124,
1019         [PWRAP_SPMINF_STA] =            0x128,
1020         [PWRAP_CIPHER_KEY_SEL] =        0x12c,
1021         [PWRAP_CIPHER_IV_SEL] =         0x130,
1022         [PWRAP_CIPHER_EN] =             0x134,
1023         [PWRAP_CIPHER_RDY] =            0x138,
1024         [PWRAP_CIPHER_MODE] =           0x13c,
1025         [PWRAP_CIPHER_SWRST] =          0x140,
1026         [PWRAP_DCM_EN] =                0x144,
1027         [PWRAP_DCM_DBC_PRD] =           0x148,
1028         [PWRAP_SW_RST] =                0x168,
1029         [PWRAP_OP_TYPE] =               0x16c,
1030         [PWRAP_MSB_FIRST] =             0x170,
1031 };
1032
1033 enum pmic_type {
1034         PMIC_MT6323,
1035         PMIC_MT6351,
1036         PMIC_MT6357,
1037         PMIC_MT6358,
1038         PMIC_MT6359,
1039         PMIC_MT6380,
1040         PMIC_MT6397,
1041 };
1042
1043 enum pwrap_type {
1044         PWRAP_MT2701,
1045         PWRAP_MT6765,
1046         PWRAP_MT6779,
1047         PWRAP_MT6797,
1048         PWRAP_MT7622,
1049         PWRAP_MT8135,
1050         PWRAP_MT8173,
1051         PWRAP_MT8183,
1052         PWRAP_MT8516,
1053 };
1054
1055 struct pmic_wrapper;
1056 struct pwrap_slv_type {
1057         const u32 *dew_regs;
1058         enum pmic_type type;
1059         const struct regmap_config *regmap;
1060         /* Flags indicating the capability for the target slave */
1061         u32 caps;
1062         /*
1063          * pwrap operations are highly associated with the PMIC types,
1064          * so the pointers added increases flexibility allowing determination
1065          * which type is used by the detection through device tree.
1066          */
1067         int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
1068         int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata);
1069 };
1070
1071 struct pmic_wrapper {
1072         struct device *dev;
1073         void __iomem *base;
1074         struct regmap *regmap;
1075         const struct pmic_wrapper_type *master;
1076         const struct pwrap_slv_type *slave;
1077         struct clk *clk_spi;
1078         struct clk *clk_wrap;
1079         struct reset_control *rstc;
1080
1081         struct reset_control *rstc_bridge;
1082         void __iomem *bridge_base;
1083 };
1084
1085 struct pmic_wrapper_type {
1086         int *regs;
1087         enum pwrap_type type;
1088         u32 arb_en_all;
1089         u32 int_en_all;
1090         u32 int1_en_all;
1091         u32 spi_w;
1092         u32 wdt_src;
1093         /* Flags indicating the capability for the target pwrap */
1094         u32 caps;
1095         int (*init_reg_clock)(struct pmic_wrapper *wrp);
1096         int (*init_soc_specific)(struct pmic_wrapper *wrp);
1097 };
1098
1099 static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)
1100 {
1101         return readl(wrp->base + wrp->master->regs[reg]);
1102 }
1103
1104 static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg)
1105 {
1106         writel(val, wrp->base + wrp->master->regs[reg]);
1107 }
1108
1109 static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
1110 {
1111         u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1112
1113         return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE;
1114 }
1115
1116 static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
1117 {
1118         u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1119
1120         return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR;
1121 }
1122
1123 /*
1124  * Timeout issue sometimes caused by the last read command
1125  * failed because pmic wrap could not got the FSM_VLDCLR
1126  * in time after finishing WACS2_CMD. It made state machine
1127  * still on FSM_VLDCLR and timeout next time.
1128  * Check the status of FSM and clear the vldclr to recovery the
1129  * error.
1130  */
1131 static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp)
1132 {
1133         if (pwrap_is_fsm_vldclr(wrp))
1134                 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1135 }
1136
1137 static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp)
1138 {
1139         return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0;
1140 }
1141
1142 static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp)
1143 {
1144         u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1145
1146         return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) &&
1147                 (val & PWRAP_STATE_SYNC_IDLE0);
1148 }
1149
1150 static int pwrap_wait_for_state(struct pmic_wrapper *wrp,
1151                 bool (*fp)(struct pmic_wrapper *))
1152 {
1153         unsigned long timeout;
1154
1155         timeout = jiffies + usecs_to_jiffies(10000);
1156
1157         do {
1158                 if (time_after(jiffies, timeout))
1159                         return fp(wrp) ? 0 : -ETIMEDOUT;
1160                 if (fp(wrp))
1161                         return 0;
1162         } while (1);
1163 }
1164
1165 static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1166 {
1167         int ret;
1168
1169         ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1170         if (ret) {
1171                 pwrap_leave_fsm_vldclr(wrp);
1172                 return ret;
1173         }
1174
1175         pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD);
1176
1177         ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
1178         if (ret)
1179                 return ret;
1180
1181         *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, PWRAP_WACS2_RDATA));
1182
1183         pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1184
1185         return 0;
1186 }
1187
1188 static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1189 {
1190         int ret, msb;
1191
1192         *rdata = 0;
1193         for (msb = 0; msb < 2; msb++) {
1194                 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1195                 if (ret) {
1196                         pwrap_leave_fsm_vldclr(wrp);
1197                         return ret;
1198                 }
1199
1200                 pwrap_writel(wrp, ((msb << 30) | (adr << 16)),
1201                              PWRAP_WACS2_CMD);
1202
1203                 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
1204                 if (ret)
1205                         return ret;
1206
1207                 *rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp,
1208                            PWRAP_WACS2_RDATA)) << (16 * msb));
1209
1210                 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1211         }
1212
1213         return 0;
1214 }
1215
1216 static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1217 {
1218         return wrp->slave->pwrap_read(wrp, adr, rdata);
1219 }
1220
1221 static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1222 {
1223         int ret;
1224
1225         ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1226         if (ret) {
1227                 pwrap_leave_fsm_vldclr(wrp);
1228                 return ret;
1229         }
1230
1231         pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
1232                      PWRAP_WACS2_CMD);
1233
1234         return 0;
1235 }
1236
1237 static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1238 {
1239         int ret, msb, rdata;
1240
1241         for (msb = 0; msb < 2; msb++) {
1242                 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1243                 if (ret) {
1244                         pwrap_leave_fsm_vldclr(wrp);
1245                         return ret;
1246                 }
1247
1248                 pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) |
1249                              ((wdata >> (msb * 16)) & 0xffff),
1250                              PWRAP_WACS2_CMD);
1251
1252                 /*
1253                  * The pwrap_read operation is the requirement of hardware used
1254                  * for the synchronization between two successive 16-bit
1255                  * pwrap_writel operations composing one 32-bit bus writing.
1256                  * Otherwise, we'll find the result fails on the lower 16-bit
1257                  * pwrap writing.
1258                  */
1259                 if (!msb)
1260                         pwrap_read(wrp, adr, &rdata);
1261         }
1262
1263         return 0;
1264 }
1265
1266 static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1267 {
1268         return wrp->slave->pwrap_write(wrp, adr, wdata);
1269 }
1270
1271 static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
1272 {
1273         return pwrap_read(context, adr, rdata);
1274 }
1275
1276 static int pwrap_regmap_write(void *context, u32 adr, u32 wdata)
1277 {
1278         return pwrap_write(context, adr, wdata);
1279 }
1280
1281 static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
1282 {
1283         int ret, i;
1284
1285         pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN);
1286         pwrap_writel(wrp, 0, PWRAP_WRAP_EN);
1287         pwrap_writel(wrp, 1, PWRAP_MUX_SEL);
1288         pwrap_writel(wrp, 1, PWRAP_MAN_EN);
1289         pwrap_writel(wrp, 0, PWRAP_DIO_EN);
1290
1291         pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL,
1292                         PWRAP_MAN_CMD);
1293         pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
1294                         PWRAP_MAN_CMD);
1295         pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH,
1296                         PWRAP_MAN_CMD);
1297
1298         for (i = 0; i < 4; i++)
1299                 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
1300                                 PWRAP_MAN_CMD);
1301
1302         ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle);
1303         if (ret) {
1304                 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
1305                 return ret;
1306         }
1307
1308         pwrap_writel(wrp, 0, PWRAP_MAN_EN);
1309         pwrap_writel(wrp, 0, PWRAP_MUX_SEL);
1310
1311         return 0;
1312 }
1313
1314 /*
1315  * pwrap_init_sidly - configure serial input delay
1316  *
1317  * This configures the serial input delay. We can configure 0, 2, 4 or 6ns
1318  * delay. Do a read test with all possible values and chose the best delay.
1319  */
1320 static int pwrap_init_sidly(struct pmic_wrapper *wrp)
1321 {
1322         u32 rdata;
1323         u32 i;
1324         u32 pass = 0;
1325         signed char dly[16] = {
1326                 -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1
1327         };
1328
1329         for (i = 0; i < 4; i++) {
1330                 pwrap_writel(wrp, i, PWRAP_SIDLY);
1331                 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST],
1332                            &rdata);
1333                 if (rdata == PWRAP_DEW_READ_TEST_VAL) {
1334                         dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
1335                         pass |= 1 << i;
1336                 }
1337         }
1338
1339         if (dly[pass] < 0) {
1340                 dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n",
1341                                 pass);
1342                 return -EIO;
1343         }
1344
1345         pwrap_writel(wrp, dly[pass], PWRAP_SIDLY);
1346
1347         return 0;
1348 }
1349
1350 static int pwrap_init_dual_io(struct pmic_wrapper *wrp)
1351 {
1352         int ret;
1353         u32 rdata;
1354
1355         /* Enable dual IO mode */
1356         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
1357
1358         /* Check IDLE & INIT_DONE in advance */
1359         ret = pwrap_wait_for_state(wrp,
1360                                    pwrap_is_fsm_idle_and_sync_idle);
1361         if (ret) {
1362                 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
1363                 return ret;
1364         }
1365
1366         pwrap_writel(wrp, 1, PWRAP_DIO_EN);
1367
1368         /* Read Test */
1369         pwrap_read(wrp,
1370                    wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
1371         if (rdata != PWRAP_DEW_READ_TEST_VAL) {
1372                 dev_err(wrp->dev,
1373                         "Read failed on DIO mode: 0x%04x!=0x%04x\n",
1374                         PWRAP_DEW_READ_TEST_VAL, rdata);
1375                 return -EFAULT;
1376         }
1377
1378         return 0;
1379 }
1380
1381 /*
1382  * pwrap_init_chip_select_ext is used to configure CS extension time for each
1383  * phase during data transactions on the pwrap bus.
1384  */
1385 static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
1386                                        u8 hext_read, u8 lext_start,
1387                                        u8 lext_end)
1388 {
1389         /*
1390          * After finishing a write and read transaction, extends CS high time
1391          * to be at least xT of BUS CLK as hext_write and hext_read specifies
1392          * respectively.
1393          */
1394         pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE);
1395         pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ);
1396
1397         /*
1398          * Extends CS low time after CSL and before CSH command to be at
1399          * least xT of BUS CLK as lext_start and lext_end specifies
1400          * respectively.
1401          */
1402         pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START);
1403         pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END);
1404 }
1405
1406 static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
1407 {
1408         switch (wrp->master->type) {
1409         case PWRAP_MT8173:
1410                 pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);
1411                 break;
1412         case PWRAP_MT8135:
1413                 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
1414                 pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0);
1415                 break;
1416         default:
1417                 break;
1418         }
1419
1420         return 0;
1421 }
1422
1423 static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp)
1424 {
1425         switch (wrp->slave->type) {
1426         case PMIC_MT6397:
1427                 pwrap_writel(wrp, 0xc, PWRAP_RDDMY);
1428                 pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2);
1429                 break;
1430
1431         case PMIC_MT6323:
1432                 pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
1433                 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO],
1434                             0x8);
1435                 pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2);
1436                 break;
1437         default:
1438                 break;
1439         }
1440
1441         return 0;
1442 }
1443
1444 static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
1445 {
1446         return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
1447 }
1448
1449 static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
1450 {
1451         u32 rdata;
1452         int ret;
1453
1454         ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY],
1455                          &rdata);
1456         if (ret)
1457                 return false;
1458
1459         return rdata == 1;
1460 }
1461
1462 static int pwrap_init_cipher(struct pmic_wrapper *wrp)
1463 {
1464         int ret;
1465         u32 rdata = 0;
1466
1467         pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST);
1468         pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST);
1469         pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);
1470         pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);
1471
1472         switch (wrp->master->type) {
1473         case PWRAP_MT8135:
1474                 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
1475                 pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
1476                 break;
1477         case PWRAP_MT2701:
1478         case PWRAP_MT6765:
1479         case PWRAP_MT6779:
1480         case PWRAP_MT6797:
1481         case PWRAP_MT8173:
1482         case PWRAP_MT8516:
1483                 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
1484                 break;
1485         case PWRAP_MT7622:
1486                 pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
1487                 break;
1488         case PWRAP_MT8183:
1489                 break;
1490         }
1491
1492         /* Config cipher mode @PMIC */
1493         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1);
1494         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);
1495         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);
1496         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);
1497
1498         switch (wrp->slave->type) {
1499         case PMIC_MT6397:
1500                 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD],
1501                             0x1);
1502                 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START],
1503                             0x1);
1504                 break;
1505         case PMIC_MT6323:
1506         case PMIC_MT6351:
1507         case PMIC_MT6357:
1508                 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
1509                             0x1);
1510                 break;
1511         default:
1512                 break;
1513         }
1514
1515         /* wait for cipher data ready@AP */
1516         ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
1517         if (ret) {
1518                 dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret);
1519                 return ret;
1520         }
1521
1522         /* wait for cipher data ready@PMIC */
1523         ret = pwrap_wait_for_state(wrp, pwrap_is_pmic_cipher_ready);
1524         if (ret) {
1525                 dev_err(wrp->dev,
1526                         "timeout waiting for cipher data ready@PMIC\n");
1527                 return ret;
1528         }
1529
1530         /* wait for cipher mode idle */
1531         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1);
1532         ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
1533         if (ret) {
1534                 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
1535                 return ret;
1536         }
1537
1538         pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
1539
1540         /* Write Test */
1541         if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1542                         PWRAP_DEW_WRITE_TEST_VAL) ||
1543             pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1544                        &rdata) ||
1545             (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
1546                 dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
1547                 return -EFAULT;
1548         }
1549
1550         return 0;
1551 }
1552
1553 static int pwrap_init_security(struct pmic_wrapper *wrp)
1554 {
1555         int ret;
1556
1557         /* Enable encryption */
1558         ret = pwrap_init_cipher(wrp);
1559         if (ret)
1560                 return ret;
1561
1562         /* Signature checking - using CRC */
1563         if (pwrap_write(wrp,
1564                         wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
1565                 return -EFAULT;
1566
1567         pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
1568         pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
1569         pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
1570                      PWRAP_SIG_ADR);
1571         pwrap_writel(wrp,
1572                      wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
1573
1574         return 0;
1575 }
1576
1577 static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
1578 {
1579         /* enable pwrap events and pwrap bridge in AP side */
1580         pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN);
1581         pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN);
1582         writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN);
1583         writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN);
1584         writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN);
1585         writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT);
1586         writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN);
1587         writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN);
1588         writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
1589
1590         /* enable PMIC event out and sources */
1591         if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
1592                         0x1) ||
1593             pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
1594                         0xffff)) {
1595                 dev_err(wrp->dev, "enable dewrap fail\n");
1596                 return -EFAULT;
1597         }
1598
1599         return 0;
1600 }
1601
1602 static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
1603 {
1604         /* PMIC_DEWRAP enables */
1605         if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
1606                         0x1) ||
1607             pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
1608                         0xffff)) {
1609                 dev_err(wrp->dev, "enable dewrap fail\n");
1610                 return -EFAULT;
1611         }
1612
1613         return 0;
1614 }
1615
1616 static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
1617 {
1618         /* GPS_INTF initialization */
1619         switch (wrp->slave->type) {
1620         case PMIC_MT6323:
1621                 pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR);
1622                 pwrap_writel(wrp, 0x8000, PWRAP_PWRAP_ADC_CMD);
1623                 pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR);
1624                 pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1);
1625                 pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2);
1626                 break;
1627         default:
1628                 break;
1629         }
1630
1631         return 0;
1632 }
1633
1634 static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
1635 {
1636         pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);
1637         /* enable 2wire SPI master */
1638         pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL);
1639
1640         return 0;
1641 }
1642
1643 static int pwrap_mt8183_init_soc_specific(struct pmic_wrapper *wrp)
1644 {
1645         pwrap_writel(wrp, 0xf5, PWRAP_STAUPD_GRPEN);
1646
1647         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1);
1648         pwrap_writel(wrp, 1, PWRAP_CRC_EN);
1649         pwrap_writel(wrp, 0x416, PWRAP_SIG_ADR);
1650         pwrap_writel(wrp, 0x42e, PWRAP_EINT_STA0_ADR);
1651
1652         pwrap_writel(wrp, 1, PWRAP_WACS_P2P_EN);
1653         pwrap_writel(wrp, 1, PWRAP_WACS_MD32_EN);
1654         pwrap_writel(wrp, 1, PWRAP_INIT_DONE_P2P);
1655         pwrap_writel(wrp, 1, PWRAP_INIT_DONE_MD32);
1656
1657         return 0;
1658 }
1659
1660 static int pwrap_init(struct pmic_wrapper *wrp)
1661 {
1662         int ret;
1663
1664         if (wrp->rstc)
1665                 reset_control_reset(wrp->rstc);
1666         if (wrp->rstc_bridge)
1667                 reset_control_reset(wrp->rstc_bridge);
1668
1669         if (wrp->master->type == PWRAP_MT8173) {
1670                 /* Enable DCM */
1671                 pwrap_writel(wrp, 3, PWRAP_DCM_EN);
1672                 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
1673         }
1674
1675         if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
1676                 /* Reset SPI slave */
1677                 ret = pwrap_reset_spislave(wrp);
1678                 if (ret)
1679                         return ret;
1680         }
1681
1682         pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
1683
1684         pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
1685
1686         pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
1687
1688         ret = wrp->master->init_reg_clock(wrp);
1689         if (ret)
1690                 return ret;
1691
1692         if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
1693                 /* Setup serial input delay */
1694                 ret = pwrap_init_sidly(wrp);
1695                 if (ret)
1696                         return ret;
1697         }
1698
1699         if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) {
1700                 /* Enable dual I/O mode */
1701                 ret = pwrap_init_dual_io(wrp);
1702                 if (ret)
1703                         return ret;
1704         }
1705
1706         if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) {
1707                 /* Enable security on bus */
1708                 ret = pwrap_init_security(wrp);
1709                 if (ret)
1710                         return ret;
1711         }
1712
1713         if (wrp->master->type == PWRAP_MT8135)
1714                 pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
1715
1716         pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);
1717         pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN);
1718         pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN);
1719         pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);
1720         pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);
1721
1722         if (wrp->master->init_soc_specific) {
1723                 ret = wrp->master->init_soc_specific(wrp);
1724                 if (ret)
1725                         return ret;
1726         }
1727
1728         /* Setup the init done registers */
1729         pwrap_writel(wrp, 1, PWRAP_INIT_DONE2);
1730         pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
1731         pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
1732
1733         if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
1734                 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
1735                 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
1736         }
1737
1738         return 0;
1739 }
1740
1741 static irqreturn_t pwrap_interrupt(int irqno, void *dev_id)
1742 {
1743         u32 rdata;
1744         struct pmic_wrapper *wrp = dev_id;
1745
1746         rdata = pwrap_readl(wrp, PWRAP_INT_FLG);
1747         dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata);
1748         pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR);
1749
1750         if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) {
1751                 rdata = pwrap_readl(wrp, PWRAP_INT1_FLG);
1752                 dev_err(wrp->dev, "unexpected interrupt int1=0x%x\n", rdata);
1753                 pwrap_writel(wrp, 0xffffffff, PWRAP_INT1_CLR);
1754         }
1755
1756         return IRQ_HANDLED;
1757 }
1758
1759 static const struct regmap_config pwrap_regmap_config16 = {
1760         .reg_bits = 16,
1761         .val_bits = 16,
1762         .reg_stride = 2,
1763         .reg_read = pwrap_regmap_read,
1764         .reg_write = pwrap_regmap_write,
1765         .max_register = 0xffff,
1766 };
1767
1768 static const struct regmap_config pwrap_regmap_config32 = {
1769         .reg_bits = 32,
1770         .val_bits = 32,
1771         .reg_stride = 4,
1772         .reg_read = pwrap_regmap_read,
1773         .reg_write = pwrap_regmap_write,
1774         .max_register = 0xffff,
1775 };
1776
1777 static const struct pwrap_slv_type pmic_mt6323 = {
1778         .dew_regs = mt6323_regs,
1779         .type = PMIC_MT6323,
1780         .regmap = &pwrap_regmap_config16,
1781         .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
1782                 PWRAP_SLV_CAP_SECURITY,
1783         .pwrap_read = pwrap_read16,
1784         .pwrap_write = pwrap_write16,
1785 };
1786
1787 static const struct pwrap_slv_type pmic_mt6351 = {
1788         .dew_regs = mt6351_regs,
1789         .type = PMIC_MT6351,
1790         .regmap = &pwrap_regmap_config16,
1791         .caps = 0,
1792         .pwrap_read = pwrap_read16,
1793         .pwrap_write = pwrap_write16,
1794 };
1795
1796 static const struct pwrap_slv_type pmic_mt6357 = {
1797         .dew_regs = mt6357_regs,
1798         .type = PMIC_MT6357,
1799         .regmap = &pwrap_regmap_config16,
1800         .caps = 0,
1801         .pwrap_read = pwrap_read16,
1802         .pwrap_write = pwrap_write16,
1803 };
1804
1805 static const struct pwrap_slv_type pmic_mt6358 = {
1806         .dew_regs = mt6358_regs,
1807         .type = PMIC_MT6358,
1808         .regmap = &pwrap_regmap_config16,
1809         .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO,
1810         .pwrap_read = pwrap_read16,
1811         .pwrap_write = pwrap_write16,
1812 };
1813
1814 static const struct pwrap_slv_type pmic_mt6359 = {
1815         .dew_regs = mt6359_regs,
1816         .type = PMIC_MT6359,
1817         .regmap = &pwrap_regmap_config16,
1818         .caps = PWRAP_SLV_CAP_DUALIO,
1819         .pwrap_read = pwrap_read16,
1820         .pwrap_write = pwrap_write16,
1821 };
1822
1823 static const struct pwrap_slv_type pmic_mt6380 = {
1824         .dew_regs = NULL,
1825         .type = PMIC_MT6380,
1826         .regmap = &pwrap_regmap_config32,
1827         .caps = 0,
1828         .pwrap_read = pwrap_read32,
1829         .pwrap_write = pwrap_write32,
1830 };
1831
1832 static const struct pwrap_slv_type pmic_mt6397 = {
1833         .dew_regs = mt6397_regs,
1834         .type = PMIC_MT6397,
1835         .regmap = &pwrap_regmap_config16,
1836         .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
1837                 PWRAP_SLV_CAP_SECURITY,
1838         .pwrap_read = pwrap_read16,
1839         .pwrap_write = pwrap_write16,
1840 };
1841
1842 static const struct of_device_id of_slave_match_tbl[] = {
1843         {
1844                 .compatible = "mediatek,mt6323",
1845                 .data = &pmic_mt6323,
1846         }, {
1847                 .compatible = "mediatek,mt6351",
1848                 .data = &pmic_mt6351,
1849         }, {
1850                 .compatible = "mediatek,mt6357",
1851                 .data = &pmic_mt6357,
1852         }, {
1853                 .compatible = "mediatek,mt6358",
1854                 .data = &pmic_mt6358,
1855         }, {
1856                 .compatible = "mediatek,mt6359",
1857                 .data = &pmic_mt6359,
1858         }, {
1859                 /* The MT6380 PMIC only implements a regulator, so we bind it
1860                  * directly instead of using a MFD.
1861                  */
1862                 .compatible = "mediatek,mt6380-regulator",
1863                 .data = &pmic_mt6380,
1864         }, {
1865                 .compatible = "mediatek,mt6397",
1866                 .data = &pmic_mt6397,
1867         }, {
1868                 /* sentinel */
1869         }
1870 };
1871 MODULE_DEVICE_TABLE(of, of_slave_match_tbl);
1872
1873 static const struct pmic_wrapper_type pwrap_mt2701 = {
1874         .regs = mt2701_regs,
1875         .type = PWRAP_MT2701,
1876         .arb_en_all = 0x3f,
1877         .int_en_all = ~(u32)(BIT(31) | BIT(2)),
1878         .int1_en_all = 0,
1879         .spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW,
1880         .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1881         .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1882         .init_reg_clock = pwrap_mt2701_init_reg_clock,
1883         .init_soc_specific = pwrap_mt2701_init_soc_specific,
1884 };
1885
1886 static const struct pmic_wrapper_type pwrap_mt6765 = {
1887         .regs = mt6765_regs,
1888         .type = PWRAP_MT6765,
1889         .arb_en_all = 0x3fd35,
1890         .int_en_all = 0xffffffff,
1891         .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1892         .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1893         .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1894         .init_reg_clock = pwrap_common_init_reg_clock,
1895         .init_soc_specific = NULL,
1896 };
1897
1898 static const struct pmic_wrapper_type pwrap_mt6779 = {
1899         .regs = mt6779_regs,
1900         .type = PWRAP_MT6779,
1901         .arb_en_all = 0xfbb7f,
1902         .int_en_all = 0xfffffffe,
1903         .int1_en_all = 0,
1904         .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1905         .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1906         .caps = 0,
1907         .init_reg_clock = pwrap_common_init_reg_clock,
1908         .init_soc_specific = NULL,
1909 };
1910
1911 static const struct pmic_wrapper_type pwrap_mt6797 = {
1912         .regs = mt6797_regs,
1913         .type = PWRAP_MT6797,
1914         .arb_en_all = 0x01fff,
1915         .int_en_all = 0xffffffc6,
1916         .int1_en_all = 0,
1917         .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1918         .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1919         .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1920         .init_reg_clock = pwrap_common_init_reg_clock,
1921         .init_soc_specific = NULL,
1922 };
1923
1924 static const struct pmic_wrapper_type pwrap_mt7622 = {
1925         .regs = mt7622_regs,
1926         .type = PWRAP_MT7622,
1927         .arb_en_all = 0xff,
1928         .int_en_all = ~(u32)BIT(31),
1929         .int1_en_all = 0,
1930         .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1931         .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1932         .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1933         .init_reg_clock = pwrap_common_init_reg_clock,
1934         .init_soc_specific = pwrap_mt7622_init_soc_specific,
1935 };
1936
1937 static const struct pmic_wrapper_type pwrap_mt8135 = {
1938         .regs = mt8135_regs,
1939         .type = PWRAP_MT8135,
1940         .arb_en_all = 0x1ff,
1941         .int_en_all = ~(u32)(BIT(31) | BIT(1)),
1942         .int1_en_all = 0,
1943         .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1944         .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1945         .caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1946         .init_reg_clock = pwrap_common_init_reg_clock,
1947         .init_soc_specific = pwrap_mt8135_init_soc_specific,
1948 };
1949
1950 static const struct pmic_wrapper_type pwrap_mt8173 = {
1951         .regs = mt8173_regs,
1952         .type = PWRAP_MT8173,
1953         .arb_en_all = 0x3f,
1954         .int_en_all = ~(u32)(BIT(31) | BIT(1)),
1955         .int1_en_all = 0,
1956         .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1957         .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
1958         .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1959         .init_reg_clock = pwrap_common_init_reg_clock,
1960         .init_soc_specific = pwrap_mt8173_init_soc_specific,
1961 };
1962
1963 static const struct pmic_wrapper_type pwrap_mt8183 = {
1964         .regs = mt8183_regs,
1965         .type = PWRAP_MT8183,
1966         .arb_en_all = 0x3fa75,
1967         .int_en_all = 0xffffffff,
1968         .int1_en_all = 0xeef7ffff,
1969         .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1970         .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1971         .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1,
1972         .init_reg_clock = pwrap_common_init_reg_clock,
1973         .init_soc_specific = pwrap_mt8183_init_soc_specific,
1974 };
1975
1976 static struct pmic_wrapper_type pwrap_mt8516 = {
1977         .regs = mt8516_regs,
1978         .type = PWRAP_MT8516,
1979         .arb_en_all = 0xff,
1980         .int_en_all = ~(u32)(BIT(31) | BIT(2)),
1981         .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1982         .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1983         .caps = PWRAP_CAP_DCM,
1984         .init_reg_clock = pwrap_mt2701_init_reg_clock,
1985         .init_soc_specific = NULL,
1986 };
1987
1988 static const struct of_device_id of_pwrap_match_tbl[] = {
1989         {
1990                 .compatible = "mediatek,mt2701-pwrap",
1991                 .data = &pwrap_mt2701,
1992         }, {
1993                 .compatible = "mediatek,mt6765-pwrap",
1994                 .data = &pwrap_mt6765,
1995         }, {
1996                 .compatible = "mediatek,mt6779-pwrap",
1997                 .data = &pwrap_mt6779,
1998         }, {
1999                 .compatible = "mediatek,mt6797-pwrap",
2000                 .data = &pwrap_mt6797,
2001         }, {
2002                 .compatible = "mediatek,mt7622-pwrap",
2003                 .data = &pwrap_mt7622,
2004         }, {
2005                 .compatible = "mediatek,mt8135-pwrap",
2006                 .data = &pwrap_mt8135,
2007         }, {
2008                 .compatible = "mediatek,mt8173-pwrap",
2009                 .data = &pwrap_mt8173,
2010         }, {
2011                 .compatible = "mediatek,mt8183-pwrap",
2012                 .data = &pwrap_mt8183,
2013         }, {
2014                 .compatible = "mediatek,mt8516-pwrap",
2015                 .data = &pwrap_mt8516,
2016         }, {
2017                 /* sentinel */
2018         }
2019 };
2020 MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
2021
2022 static int pwrap_probe(struct platform_device *pdev)
2023 {
2024         int ret, irq;
2025         struct pmic_wrapper *wrp;
2026         struct device_node *np = pdev->dev.of_node;
2027         const struct of_device_id *of_slave_id = NULL;
2028         struct resource *res;
2029
2030         if (np->child)
2031                 of_slave_id = of_match_node(of_slave_match_tbl, np->child);
2032
2033         if (!of_slave_id) {
2034                 dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n");
2035                 return -EINVAL;
2036         }
2037
2038         wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
2039         if (!wrp)
2040                 return -ENOMEM;
2041
2042         platform_set_drvdata(pdev, wrp);
2043
2044         wrp->master = of_device_get_match_data(&pdev->dev);
2045         wrp->slave = of_slave_id->data;
2046         wrp->dev = &pdev->dev;
2047
2048         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
2049         wrp->base = devm_ioremap_resource(wrp->dev, res);
2050         if (IS_ERR(wrp->base))
2051                 return PTR_ERR(wrp->base);
2052
2053         if (HAS_CAP(wrp->master->caps, PWRAP_CAP_RESET)) {
2054                 wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
2055                 if (IS_ERR(wrp->rstc)) {
2056                         ret = PTR_ERR(wrp->rstc);
2057                         dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);
2058                         return ret;
2059                 }
2060         }
2061
2062         if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
2063                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2064                                 "pwrap-bridge");
2065                 wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);
2066                 if (IS_ERR(wrp->bridge_base))
2067                         return PTR_ERR(wrp->bridge_base);
2068
2069                 wrp->rstc_bridge = devm_reset_control_get(wrp->dev,
2070                                                           "pwrap-bridge");
2071                 if (IS_ERR(wrp->rstc_bridge)) {
2072                         ret = PTR_ERR(wrp->rstc_bridge);
2073                         dev_dbg(wrp->dev,
2074                                 "cannot get pwrap-bridge reset: %d\n", ret);
2075                         return ret;
2076                 }
2077         }
2078
2079         wrp->clk_spi = devm_clk_get(wrp->dev, "spi");
2080         if (IS_ERR(wrp->clk_spi)) {
2081                 dev_dbg(wrp->dev, "failed to get clock: %ld\n",
2082                         PTR_ERR(wrp->clk_spi));
2083                 return PTR_ERR(wrp->clk_spi);
2084         }
2085
2086         wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap");
2087         if (IS_ERR(wrp->clk_wrap)) {
2088                 dev_dbg(wrp->dev, "failed to get clock: %ld\n",
2089                         PTR_ERR(wrp->clk_wrap));
2090                 return PTR_ERR(wrp->clk_wrap);
2091         }
2092
2093         ret = clk_prepare_enable(wrp->clk_spi);
2094         if (ret)
2095                 return ret;
2096
2097         ret = clk_prepare_enable(wrp->clk_wrap);
2098         if (ret)
2099                 goto err_out1;
2100
2101         /* Enable internal dynamic clock */
2102         if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) {
2103                 pwrap_writel(wrp, 1, PWRAP_DCM_EN);
2104                 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
2105         }
2106
2107         /*
2108          * The PMIC could already be initialized by the bootloader.
2109          * Skip initialization here in this case.
2110          */
2111         if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) {
2112                 ret = pwrap_init(wrp);
2113                 if (ret) {
2114                         dev_dbg(wrp->dev, "init failed with %d\n", ret);
2115                         goto err_out2;
2116                 }
2117         }
2118
2119         if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_INIT_DONE0)) {
2120                 dev_dbg(wrp->dev, "initialization isn't finished\n");
2121                 ret = -ENODEV;
2122                 goto err_out2;
2123         }
2124
2125         /* Initialize watchdog, may not be done by the bootloader */
2126         pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
2127         /*
2128          * Since STAUPD was not used on mt8173 platform,
2129          * so STAUPD of WDT_SRC which should be turned off
2130          */
2131         pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN);
2132         if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1))
2133                 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1);
2134
2135         pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
2136         pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
2137         /*
2138          * We add INT1 interrupt to handle starvation and request exception
2139          * If we support it, we should enable it here.
2140          */
2141         if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN))
2142                 pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN);
2143
2144         irq = platform_get_irq(pdev, 0);
2145         ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt,
2146                                IRQF_TRIGGER_HIGH,
2147                                "mt-pmic-pwrap", wrp);
2148         if (ret)
2149                 goto err_out2;
2150
2151         wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regmap);
2152         if (IS_ERR(wrp->regmap)) {
2153                 ret = PTR_ERR(wrp->regmap);
2154                 goto err_out2;
2155         }
2156
2157         ret = of_platform_populate(np, NULL, NULL, wrp->dev);
2158         if (ret) {
2159                 dev_dbg(wrp->dev, "failed to create child devices at %pOF\n",
2160                                 np);
2161                 goto err_out2;
2162         }
2163
2164         return 0;
2165
2166 err_out2:
2167         clk_disable_unprepare(wrp->clk_wrap);
2168 err_out1:
2169         clk_disable_unprepare(wrp->clk_spi);
2170
2171         return ret;
2172 }
2173
2174 static struct platform_driver pwrap_drv = {
2175         .driver = {
2176                 .name = "mt-pmic-pwrap",
2177                 .of_match_table = of_match_ptr(of_pwrap_match_tbl),
2178         },
2179         .probe = pwrap_probe,
2180 };
2181
2182 module_platform_driver(pwrap_drv);
2183
2184 MODULE_AUTHOR("Flora Fu, MediaTek");
2185 MODULE_DESCRIPTION("MediaTek MT8135 PMIC Wrapper Driver");
2186 MODULE_LICENSE("GPL v2");