1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef __SOC_MEDIATEK_MT8192_PM_DOMAINS_H
4 #define __SOC_MEDIATEK_MT8192_PM_DOMAINS_H
6 #include "mtk-pm-domains.h"
7 #include <dt-bindings/power/mt8192-power.h>
10 * MT8192 power domain support
13 static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
14 [MT8192_POWER_DOMAIN_AUDIO] = {
18 .pwr_sta_offs = 0x016c,
19 .pwr_sta2nd_offs = 0x0170,
20 .sram_pdn_bits = GENMASK(8, 8),
21 .sram_pdn_ack_bits = GENMASK(12, 12),
23 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_AUDIO,
24 MT8192_TOP_AXI_PROT_EN_2_SET,
25 MT8192_TOP_AXI_PROT_EN_2_CLR,
26 MT8192_TOP_AXI_PROT_EN_2_STA1),
29 [MT8192_POWER_DOMAIN_CONN] = {
31 .sta_mask = PWR_STATUS_CONN,
33 .pwr_sta_offs = 0x016c,
34 .pwr_sta2nd_offs = 0x0170,
36 .sram_pdn_ack_bits = 0,
38 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN,
39 MT8192_TOP_AXI_PROT_EN_SET,
40 MT8192_TOP_AXI_PROT_EN_CLR,
41 MT8192_TOP_AXI_PROT_EN_STA1),
42 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN_2ND,
43 MT8192_TOP_AXI_PROT_EN_SET,
44 MT8192_TOP_AXI_PROT_EN_CLR,
45 MT8192_TOP_AXI_PROT_EN_STA1),
46 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CONN,
47 MT8192_TOP_AXI_PROT_EN_1_SET,
48 MT8192_TOP_AXI_PROT_EN_1_CLR,
49 MT8192_TOP_AXI_PROT_EN_1_STA1),
51 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
53 [MT8192_POWER_DOMAIN_MFG0] = {
57 .pwr_sta_offs = 0x016c,
58 .pwr_sta2nd_offs = 0x0170,
59 .sram_pdn_bits = GENMASK(8, 8),
60 .sram_pdn_ack_bits = GENMASK(12, 12),
62 [MT8192_POWER_DOMAIN_MFG1] = {
66 .pwr_sta_offs = 0x016c,
67 .pwr_sta2nd_offs = 0x0170,
68 .sram_pdn_bits = GENMASK(8, 8),
69 .sram_pdn_ack_bits = GENMASK(12, 12),
71 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_MFG1,
72 MT8192_TOP_AXI_PROT_EN_1_SET,
73 MT8192_TOP_AXI_PROT_EN_1_CLR,
74 MT8192_TOP_AXI_PROT_EN_1_STA1),
75 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1,
76 MT8192_TOP_AXI_PROT_EN_2_SET,
77 MT8192_TOP_AXI_PROT_EN_2_CLR,
78 MT8192_TOP_AXI_PROT_EN_2_STA1),
79 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MFG1,
80 MT8192_TOP_AXI_PROT_EN_SET,
81 MT8192_TOP_AXI_PROT_EN_CLR,
82 MT8192_TOP_AXI_PROT_EN_STA1),
83 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND,
84 MT8192_TOP_AXI_PROT_EN_2_SET,
85 MT8192_TOP_AXI_PROT_EN_2_CLR,
86 MT8192_TOP_AXI_PROT_EN_2_STA1),
89 [MT8192_POWER_DOMAIN_MFG2] = {
93 .pwr_sta_offs = 0x016c,
94 .pwr_sta2nd_offs = 0x0170,
95 .sram_pdn_bits = GENMASK(8, 8),
96 .sram_pdn_ack_bits = GENMASK(12, 12),
98 [MT8192_POWER_DOMAIN_MFG3] = {
102 .pwr_sta_offs = 0x016c,
103 .pwr_sta2nd_offs = 0x0170,
104 .sram_pdn_bits = GENMASK(8, 8),
105 .sram_pdn_ack_bits = GENMASK(12, 12),
107 [MT8192_POWER_DOMAIN_MFG4] = {
111 .pwr_sta_offs = 0x016c,
112 .pwr_sta2nd_offs = 0x0170,
113 .sram_pdn_bits = GENMASK(8, 8),
114 .sram_pdn_ack_bits = GENMASK(12, 12),
116 [MT8192_POWER_DOMAIN_MFG5] = {
120 .pwr_sta_offs = 0x016c,
121 .pwr_sta2nd_offs = 0x0170,
122 .sram_pdn_bits = GENMASK(8, 8),
123 .sram_pdn_ack_bits = GENMASK(12, 12),
125 [MT8192_POWER_DOMAIN_MFG6] = {
129 .pwr_sta_offs = 0x016c,
130 .pwr_sta2nd_offs = 0x0170,
131 .sram_pdn_bits = GENMASK(8, 8),
132 .sram_pdn_ack_bits = GENMASK(12, 12),
134 [MT8192_POWER_DOMAIN_DISP] = {
138 .pwr_sta_offs = 0x016c,
139 .pwr_sta2nd_offs = 0x0170,
140 .sram_pdn_bits = GENMASK(8, 8),
141 .sram_pdn_ack_bits = GENMASK(12, 12),
143 BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_DISP,
144 MT8192_TOP_AXI_PROT_EN_MM_SET,
145 MT8192_TOP_AXI_PROT_EN_MM_CLR,
146 MT8192_TOP_AXI_PROT_EN_MM_STA1),
147 BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_2_DISP,
148 MT8192_TOP_AXI_PROT_EN_MM_2_SET,
149 MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
150 MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
151 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_DISP,
152 MT8192_TOP_AXI_PROT_EN_SET,
153 MT8192_TOP_AXI_PROT_EN_CLR,
154 MT8192_TOP_AXI_PROT_EN_STA1),
155 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND,
156 MT8192_TOP_AXI_PROT_EN_MM_SET,
157 MT8192_TOP_AXI_PROT_EN_MM_CLR,
158 MT8192_TOP_AXI_PROT_EN_MM_STA1),
159 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND,
160 MT8192_TOP_AXI_PROT_EN_MM_2_SET,
161 MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
162 MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
165 [MT8192_POWER_DOMAIN_IPE] = {
169 .pwr_sta_offs = 0x016c,
170 .pwr_sta2nd_offs = 0x0170,
171 .sram_pdn_bits = GENMASK(8, 8),
172 .sram_pdn_ack_bits = GENMASK(12, 12),
174 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE,
175 MT8192_TOP_AXI_PROT_EN_MM_SET,
176 MT8192_TOP_AXI_PROT_EN_MM_CLR,
177 MT8192_TOP_AXI_PROT_EN_MM_STA1),
178 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND,
179 MT8192_TOP_AXI_PROT_EN_MM_SET,
180 MT8192_TOP_AXI_PROT_EN_MM_CLR,
181 MT8192_TOP_AXI_PROT_EN_MM_STA1),
184 [MT8192_POWER_DOMAIN_ISP] = {
188 .pwr_sta_offs = 0x016c,
189 .pwr_sta2nd_offs = 0x0170,
190 .sram_pdn_bits = GENMASK(8, 8),
191 .sram_pdn_ack_bits = GENMASK(12, 12),
193 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP,
194 MT8192_TOP_AXI_PROT_EN_MM_2_SET,
195 MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
196 MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
197 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND,
198 MT8192_TOP_AXI_PROT_EN_MM_2_SET,
199 MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
200 MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
203 [MT8192_POWER_DOMAIN_ISP2] = {
207 .pwr_sta_offs = 0x016c,
208 .pwr_sta2nd_offs = 0x0170,
209 .sram_pdn_bits = GENMASK(8, 8),
210 .sram_pdn_ack_bits = GENMASK(12, 12),
212 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2,
213 MT8192_TOP_AXI_PROT_EN_MM_SET,
214 MT8192_TOP_AXI_PROT_EN_MM_CLR,
215 MT8192_TOP_AXI_PROT_EN_MM_STA1),
216 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND,
217 MT8192_TOP_AXI_PROT_EN_MM_SET,
218 MT8192_TOP_AXI_PROT_EN_MM_CLR,
219 MT8192_TOP_AXI_PROT_EN_MM_STA1),
222 [MT8192_POWER_DOMAIN_MDP] = {
226 .pwr_sta_offs = 0x016c,
227 .pwr_sta2nd_offs = 0x0170,
228 .sram_pdn_bits = GENMASK(8, 8),
229 .sram_pdn_ack_bits = GENMASK(12, 12),
231 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP,
232 MT8192_TOP_AXI_PROT_EN_MM_2_SET,
233 MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
234 MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
235 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND,
236 MT8192_TOP_AXI_PROT_EN_MM_2_SET,
237 MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
238 MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
241 [MT8192_POWER_DOMAIN_VENC] = {
245 .pwr_sta_offs = 0x016c,
246 .pwr_sta2nd_offs = 0x0170,
247 .sram_pdn_bits = GENMASK(8, 8),
248 .sram_pdn_ack_bits = GENMASK(12, 12),
250 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC,
251 MT8192_TOP_AXI_PROT_EN_MM_SET,
252 MT8192_TOP_AXI_PROT_EN_MM_CLR,
253 MT8192_TOP_AXI_PROT_EN_MM_STA1),
254 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND,
255 MT8192_TOP_AXI_PROT_EN_MM_SET,
256 MT8192_TOP_AXI_PROT_EN_MM_CLR,
257 MT8192_TOP_AXI_PROT_EN_MM_STA1),
260 [MT8192_POWER_DOMAIN_VDEC] = {
264 .pwr_sta_offs = 0x016c,
265 .pwr_sta2nd_offs = 0x0170,
266 .sram_pdn_bits = GENMASK(8, 8),
267 .sram_pdn_ack_bits = GENMASK(12, 12),
269 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC,
270 MT8192_TOP_AXI_PROT_EN_MM_SET,
271 MT8192_TOP_AXI_PROT_EN_MM_CLR,
272 MT8192_TOP_AXI_PROT_EN_MM_STA1),
273 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND,
274 MT8192_TOP_AXI_PROT_EN_MM_SET,
275 MT8192_TOP_AXI_PROT_EN_MM_CLR,
276 MT8192_TOP_AXI_PROT_EN_MM_STA1),
279 [MT8192_POWER_DOMAIN_VDEC2] = {
283 .pwr_sta_offs = 0x016c,
284 .pwr_sta2nd_offs = 0x0170,
285 .sram_pdn_bits = GENMASK(8, 8),
286 .sram_pdn_ack_bits = GENMASK(12, 12),
288 [MT8192_POWER_DOMAIN_CAM] = {
292 .pwr_sta_offs = 0x016c,
293 .pwr_sta2nd_offs = 0x0170,
294 .sram_pdn_bits = GENMASK(8, 8),
295 .sram_pdn_ack_bits = GENMASK(12, 12),
297 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_CAM,
298 MT8192_TOP_AXI_PROT_EN_2_SET,
299 MT8192_TOP_AXI_PROT_EN_2_CLR,
300 MT8192_TOP_AXI_PROT_EN_2_STA1),
301 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM,
302 MT8192_TOP_AXI_PROT_EN_MM_SET,
303 MT8192_TOP_AXI_PROT_EN_MM_CLR,
304 MT8192_TOP_AXI_PROT_EN_MM_STA1),
305 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CAM,
306 MT8192_TOP_AXI_PROT_EN_1_SET,
307 MT8192_TOP_AXI_PROT_EN_1_CLR,
308 MT8192_TOP_AXI_PROT_EN_1_STA1),
309 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND,
310 MT8192_TOP_AXI_PROT_EN_MM_SET,
311 MT8192_TOP_AXI_PROT_EN_MM_CLR,
312 MT8192_TOP_AXI_PROT_EN_MM_STA1),
313 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_VDNR_CAM,
314 MT8192_TOP_AXI_PROT_EN_VDNR_SET,
315 MT8192_TOP_AXI_PROT_EN_VDNR_CLR,
316 MT8192_TOP_AXI_PROT_EN_VDNR_STA1),
319 [MT8192_POWER_DOMAIN_CAM_RAWA] = {
323 .pwr_sta_offs = 0x016c,
324 .pwr_sta2nd_offs = 0x0170,
325 .sram_pdn_bits = GENMASK(8, 8),
326 .sram_pdn_ack_bits = GENMASK(12, 12),
328 [MT8192_POWER_DOMAIN_CAM_RAWB] = {
332 .pwr_sta_offs = 0x016c,
333 .pwr_sta2nd_offs = 0x0170,
334 .sram_pdn_bits = GENMASK(8, 8),
335 .sram_pdn_ack_bits = GENMASK(12, 12),
337 [MT8192_POWER_DOMAIN_CAM_RAWC] = {
341 .pwr_sta_offs = 0x016c,
342 .pwr_sta2nd_offs = 0x0170,
343 .sram_pdn_bits = GENMASK(8, 8),
344 .sram_pdn_ack_bits = GENMASK(12, 12),
348 static const struct scpsys_soc_data mt8192_scpsys_data = {
349 .domains_data = scpsys_domain_data_mt8192,
350 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8192),
353 #endif /* __SOC_MEDIATEK_MT8192_PM_DOMAINS_H */