drivers/soc/mediatek/mt8192-pm-domains.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef __SOC_MEDIATEK_MT8192_PM_DOMAINS_H
   4 #define __SOC_MEDIATEK_MT8192_PM_DOMAINS_H
   5
   6 #include "mtk-pm-domains.h"
   7 #include <dt-bindings/power/mt8192-power.h>
   8
   9 /*
  10  * MT8192 power domain support
  11  */
  12
  13 static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
  14         [MT8192_POWER_DOMAIN_AUDIO] = {
  15                 .name = "audio",
  16                 .sta_mask = BIT(21),
  17                 .ctl_offs = 0x0354,
  18                 .pwr_sta_offs = 0x016c,
  19                 .pwr_sta2nd_offs = 0x0170,
  20                 .sram_pdn_bits = GENMASK(8, 8),
  21                 .sram_pdn_ack_bits = GENMASK(12, 12),
  22                 .bp_infracfg = {
  23                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_AUDIO,
  24                                     MT8192_TOP_AXI_PROT_EN_2_SET,
  25                                     MT8192_TOP_AXI_PROT_EN_2_CLR,
  26                                     MT8192_TOP_AXI_PROT_EN_2_STA1),
  27                 },
  28         },
  29         [MT8192_POWER_DOMAIN_CONN] = {
  30                 .name = "conn",
  31                 .sta_mask = PWR_STATUS_CONN,
  32                 .ctl_offs = 0x0304,
  33                 .pwr_sta_offs = 0x016c,
  34                 .pwr_sta2nd_offs = 0x0170,
  35                 .sram_pdn_bits = 0,
  36                 .sram_pdn_ack_bits = 0,
  37                 .bp_infracfg = {
  38                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN,
  39                                     MT8192_TOP_AXI_PROT_EN_SET,
  40                                     MT8192_TOP_AXI_PROT_EN_CLR,
  41                                     MT8192_TOP_AXI_PROT_EN_STA1),
  42                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN_2ND,
  43                                     MT8192_TOP_AXI_PROT_EN_SET,
  44                                     MT8192_TOP_AXI_PROT_EN_CLR,
  45                                     MT8192_TOP_AXI_PROT_EN_STA1),
  46                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CONN,
  47                                     MT8192_TOP_AXI_PROT_EN_1_SET,
  48                                     MT8192_TOP_AXI_PROT_EN_1_CLR,
  49                                     MT8192_TOP_AXI_PROT_EN_1_STA1),
  50                 },
  51                 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
  52         },
  53         [MT8192_POWER_DOMAIN_MFG0] = {
  54                 .name = "mfg0",
  55                 .sta_mask = BIT(2),
  56                 .ctl_offs = 0x0308,
  57                 .pwr_sta_offs = 0x016c,
  58                 .pwr_sta2nd_offs = 0x0170,
  59                 .sram_pdn_bits = GENMASK(8, 8),
  60                 .sram_pdn_ack_bits = GENMASK(12, 12),
  61                 .caps = MTK_SCPD_DOMAIN_SUPPLY,
  62         },
  63         [MT8192_POWER_DOMAIN_MFG1] = {
  64                 .name = "mfg1",
  65                 .sta_mask = BIT(3),
  66                 .ctl_offs = 0x030c,
  67                 .pwr_sta_offs = 0x016c,
  68                 .pwr_sta2nd_offs = 0x0170,
  69                 .sram_pdn_bits = GENMASK(8, 8),
  70                 .sram_pdn_ack_bits = GENMASK(12, 12),
  71                 .bp_infracfg = {
  72                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_MFG1,
  73                                     MT8192_TOP_AXI_PROT_EN_1_SET,
  74                                     MT8192_TOP_AXI_PROT_EN_1_CLR,
  75                                     MT8192_TOP_AXI_PROT_EN_1_STA1),
  76                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1,
  77                                     MT8192_TOP_AXI_PROT_EN_2_SET,
  78                                     MT8192_TOP_AXI_PROT_EN_2_CLR,
  79                                     MT8192_TOP_AXI_PROT_EN_2_STA1),
  80                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MFG1,
  81                                     MT8192_TOP_AXI_PROT_EN_SET,
  82                                     MT8192_TOP_AXI_PROT_EN_CLR,
  83                                     MT8192_TOP_AXI_PROT_EN_STA1),
  84                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND,
  85                                     MT8192_TOP_AXI_PROT_EN_2_SET,
  86                                     MT8192_TOP_AXI_PROT_EN_2_CLR,
  87                                     MT8192_TOP_AXI_PROT_EN_2_STA1),
  88                 },
  89                 .caps = MTK_SCPD_DOMAIN_SUPPLY,
  90         },
  91         [MT8192_POWER_DOMAIN_MFG2] = {
  92                 .name = "mfg2",
  93                 .sta_mask = BIT(4),
  94                 .ctl_offs = 0x0310,
  95                 .pwr_sta_offs = 0x016c,
  96                 .pwr_sta2nd_offs = 0x0170,
  97                 .sram_pdn_bits = GENMASK(8, 8),
  98                 .sram_pdn_ack_bits = GENMASK(12, 12),
  99         },
 100         [MT8192_POWER_DOMAIN_MFG3] = {
 101                 .name = "mfg3",
 102                 .sta_mask = BIT(5),
 103                 .ctl_offs = 0x0314,
 104                 .pwr_sta_offs = 0x016c,
 105                 .pwr_sta2nd_offs = 0x0170,
 106                 .sram_pdn_bits = GENMASK(8, 8),
 107                 .sram_pdn_ack_bits = GENMASK(12, 12),
 108         },
 109         [MT8192_POWER_DOMAIN_MFG4] = {
 110                 .name = "mfg4",
 111                 .sta_mask = BIT(6),
 112                 .ctl_offs = 0x0318,
 113                 .pwr_sta_offs = 0x016c,
 114                 .pwr_sta2nd_offs = 0x0170,
 115                 .sram_pdn_bits = GENMASK(8, 8),
 116                 .sram_pdn_ack_bits = GENMASK(12, 12),
 117         },
 118         [MT8192_POWER_DOMAIN_MFG5] = {
 119                 .name = "mfg5",
 120                 .sta_mask = BIT(7),
 121                 .ctl_offs = 0x031c,
 122                 .pwr_sta_offs = 0x016c,
 123                 .pwr_sta2nd_offs = 0x0170,
 124                 .sram_pdn_bits = GENMASK(8, 8),
 125                 .sram_pdn_ack_bits = GENMASK(12, 12),
 126         },
 127         [MT8192_POWER_DOMAIN_MFG6] = {
 128                 .name = "mfg6",
 129                 .sta_mask = BIT(8),
 130                 .ctl_offs = 0x0320,
 131                 .pwr_sta_offs = 0x016c,
 132                 .pwr_sta2nd_offs = 0x0170,
 133                 .sram_pdn_bits = GENMASK(8, 8),
 134                 .sram_pdn_ack_bits = GENMASK(12, 12),
 135         },
 136         [MT8192_POWER_DOMAIN_DISP] = {
 137                 .name = "disp",
 138                 .sta_mask = BIT(20),
 139                 .ctl_offs = 0x0350,
 140                 .pwr_sta_offs = 0x016c,
 141                 .pwr_sta2nd_offs = 0x0170,
 142                 .sram_pdn_bits = GENMASK(8, 8),
 143                 .sram_pdn_ack_bits = GENMASK(12, 12),
 144                 .bp_infracfg = {
 145                         BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_DISP,
 146                                         MT8192_TOP_AXI_PROT_EN_MM_SET,
 147                                         MT8192_TOP_AXI_PROT_EN_MM_CLR,
 148                                         MT8192_TOP_AXI_PROT_EN_MM_STA1),
 149                         BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_2_DISP,
 150                                         MT8192_TOP_AXI_PROT_EN_MM_2_SET,
 151                                         MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
 152                                         MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
 153                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_DISP,
 154                                     MT8192_TOP_AXI_PROT_EN_SET,
 155                                     MT8192_TOP_AXI_PROT_EN_CLR,
 156                                     MT8192_TOP_AXI_PROT_EN_STA1),
 157                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND,
 158                                     MT8192_TOP_AXI_PROT_EN_MM_SET,
 159                                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
 160                                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
 161                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND,
 162                                     MT8192_TOP_AXI_PROT_EN_MM_2_SET,
 163                                     MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
 164                                     MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
 165                 },
 166         },
 167         [MT8192_POWER_DOMAIN_IPE] = {
 168                 .name = "ipe",
 169                 .sta_mask = BIT(14),
 170                 .ctl_offs = 0x0338,
 171                 .pwr_sta_offs = 0x016c,
 172                 .pwr_sta2nd_offs = 0x0170,
 173                 .sram_pdn_bits = GENMASK(8, 8),
 174                 .sram_pdn_ack_bits = GENMASK(12, 12),
 175                 .bp_infracfg = {
 176                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE,
 177                                     MT8192_TOP_AXI_PROT_EN_MM_SET,
 178                                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
 179                                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
 180                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND,
 181                                     MT8192_TOP_AXI_PROT_EN_MM_SET,
 182                                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
 183                                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
 184                 },
 185         },
 186         [MT8192_POWER_DOMAIN_ISP] = {
 187                 .name = "isp",
 188                 .sta_mask = BIT(12),
 189                 .ctl_offs = 0x0330,
 190                 .pwr_sta_offs = 0x016c,
 191                 .pwr_sta2nd_offs = 0x0170,
 192                 .sram_pdn_bits = GENMASK(8, 8),
 193                 .sram_pdn_ack_bits = GENMASK(12, 12),
 194                 .bp_infracfg = {
 195                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP,
 196                                     MT8192_TOP_AXI_PROT_EN_MM_2_SET,
 197                                     MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
 198                                     MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
 199                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND,
 200                                     MT8192_TOP_AXI_PROT_EN_MM_2_SET,
 201                                     MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
 202                                     MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
 203                 },
 204         },
 205         [MT8192_POWER_DOMAIN_ISP2] = {
 206                 .name = "isp2",
 207                 .sta_mask = BIT(13),
 208                 .ctl_offs = 0x0334,
 209                 .pwr_sta_offs = 0x016c,
 210                 .pwr_sta2nd_offs = 0x0170,
 211                 .sram_pdn_bits = GENMASK(8, 8),
 212                 .sram_pdn_ack_bits = GENMASK(12, 12),
 213                 .bp_infracfg = {
 214                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2,
 215                                     MT8192_TOP_AXI_PROT_EN_MM_SET,
 216                                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
 217                                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
 218                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND,
 219                                     MT8192_TOP_AXI_PROT_EN_MM_SET,
 220                                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
 221                                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
 222                 },
 223         },
 224         [MT8192_POWER_DOMAIN_MDP] = {
 225                 .name = "mdp",
 226                 .sta_mask = BIT(19),
 227                 .ctl_offs = 0x034c,
 228                 .pwr_sta_offs = 0x016c,
 229                 .pwr_sta2nd_offs = 0x0170,
 230                 .sram_pdn_bits = GENMASK(8, 8),
 231                 .sram_pdn_ack_bits = GENMASK(12, 12),
 232                 .bp_infracfg = {
 233                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP,
 234                                     MT8192_TOP_AXI_PROT_EN_MM_2_SET,
 235                                     MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
 236                                     MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
 237                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND,
 238                                     MT8192_TOP_AXI_PROT_EN_MM_2_SET,
 239                                     MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
 240                                     MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
 241                 },
 242         },
 243         [MT8192_POWER_DOMAIN_VENC] = {
 244                 .name = "venc",
 245                 .sta_mask = BIT(17),
 246                 .ctl_offs = 0x0344,
 247                 .pwr_sta_offs = 0x016c,
 248                 .pwr_sta2nd_offs = 0x0170,
 249                 .sram_pdn_bits = GENMASK(8, 8),
 250                 .sram_pdn_ack_bits = GENMASK(12, 12),
 251                 .bp_infracfg = {
 252                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC,
 253                                     MT8192_TOP_AXI_PROT_EN_MM_SET,
 254                                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
 255                                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
 256                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND,
 257                                     MT8192_TOP_AXI_PROT_EN_MM_SET,
 258                                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
 259                                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
 260                 },
 261         },
 262         [MT8192_POWER_DOMAIN_VDEC] = {
 263                 .name = "vdec",
 264                 .sta_mask = BIT(15),
 265                 .ctl_offs = 0x033c,
 266                 .pwr_sta_offs = 0x016c,
 267                 .pwr_sta2nd_offs = 0x0170,
 268                 .sram_pdn_bits = GENMASK(8, 8),
 269                 .sram_pdn_ack_bits = GENMASK(12, 12),
 270                 .bp_infracfg = {
 271                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC,
 272                                     MT8192_TOP_AXI_PROT_EN_MM_SET,
 273                                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
 274                                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
 275                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND,
 276                                     MT8192_TOP_AXI_PROT_EN_MM_SET,
 277                                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
 278                                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
 279                 },
 280         },
 281         [MT8192_POWER_DOMAIN_VDEC2] = {
 282                 .name = "vdec2",
 283                 .sta_mask = BIT(16),
 284                 .ctl_offs = 0x0340,
 285                 .pwr_sta_offs = 0x016c,
 286                 .pwr_sta2nd_offs = 0x0170,
 287                 .sram_pdn_bits = GENMASK(8, 8),
 288                 .sram_pdn_ack_bits = GENMASK(12, 12),
 289         },
 290         [MT8192_POWER_DOMAIN_CAM] = {
 291                 .name = "cam",
 292                 .sta_mask = BIT(23),
 293                 .ctl_offs = 0x035c,
 294                 .pwr_sta_offs = 0x016c,
 295                 .pwr_sta2nd_offs = 0x0170,
 296                 .sram_pdn_bits = GENMASK(8, 8),
 297                 .sram_pdn_ack_bits = GENMASK(12, 12),
 298                 .bp_infracfg = {
 299                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_CAM,
 300                                     MT8192_TOP_AXI_PROT_EN_2_SET,
 301                                     MT8192_TOP_AXI_PROT_EN_2_CLR,
 302                                     MT8192_TOP_AXI_PROT_EN_2_STA1),
 303                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM,
 304                                     MT8192_TOP_AXI_PROT_EN_MM_SET,
 305                                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
 306                                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
 307                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CAM,
 308                                     MT8192_TOP_AXI_PROT_EN_1_SET,
 309                                     MT8192_TOP_AXI_PROT_EN_1_CLR,
 310                                     MT8192_TOP_AXI_PROT_EN_1_STA1),
 311                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND,
 312                                     MT8192_TOP_AXI_PROT_EN_MM_SET,
 313                                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
 314                                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
 315                         BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_VDNR_CAM,
 316                                     MT8192_TOP_AXI_PROT_EN_VDNR_SET,
 317                                     MT8192_TOP_AXI_PROT_EN_VDNR_CLR,
 318                                     MT8192_TOP_AXI_PROT_EN_VDNR_STA1),
 319                 },
 320         },
 321         [MT8192_POWER_DOMAIN_CAM_RAWA] = {
 322                 .name = "cam_rawa",
 323                 .sta_mask = BIT(24),
 324                 .ctl_offs = 0x0360,
 325                 .pwr_sta_offs = 0x016c,
 326                 .pwr_sta2nd_offs = 0x0170,
 327                 .sram_pdn_bits = GENMASK(8, 8),
 328                 .sram_pdn_ack_bits = GENMASK(12, 12),
 329         },
 330         [MT8192_POWER_DOMAIN_CAM_RAWB] = {
 331                 .name = "cam_rawb",
 332                 .sta_mask = BIT(25),
 333                 .ctl_offs = 0x0364,
 334                 .pwr_sta_offs = 0x016c,
 335                 .pwr_sta2nd_offs = 0x0170,
 336                 .sram_pdn_bits = GENMASK(8, 8),
 337                 .sram_pdn_ack_bits = GENMASK(12, 12),
 338         },
 339         [MT8192_POWER_DOMAIN_CAM_RAWC] = {
 340                 .name = "cam_rawc",
 341                 .sta_mask = BIT(26),
 342                 .ctl_offs = 0x0368,
 343                 .pwr_sta_offs = 0x016c,
 344                 .pwr_sta2nd_offs = 0x0170,
 345                 .sram_pdn_bits = GENMASK(8, 8),
 346                 .sram_pdn_ack_bits = GENMASK(12, 12),
 347         },
 348 };
 349
 350 static const struct scpsys_soc_data mt8192_scpsys_data = {
 351         .domains_data = scpsys_domain_data_mt8192,
 352         .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8192),
 353 };
 354
 355 #endif /* __SOC_MEDIATEK_MT8192_PM_DOMAINS_H */