1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef __SOC_MEDIATEK_MT8173_PM_DOMAINS_H
4 #define __SOC_MEDIATEK_MT8173_PM_DOMAINS_H
6 #include "mtk-pm-domains.h"
7 #include <dt-bindings/power/mt8173-power.h>
10 * MT8173 power domain support
13 static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
14 [MT8173_POWER_DOMAIN_VDEC] = {
16 .sta_mask = PWR_STATUS_VDEC,
17 .ctl_offs = SPM_VDE_PWR_CON,
18 .sram_pdn_bits = GENMASK(11, 8),
19 .sram_pdn_ack_bits = GENMASK(12, 12),
21 [MT8173_POWER_DOMAIN_VENC] = {
23 .sta_mask = PWR_STATUS_VENC,
24 .ctl_offs = SPM_VEN_PWR_CON,
25 .sram_pdn_bits = GENMASK(11, 8),
26 .sram_pdn_ack_bits = GENMASK(15, 12),
28 [MT8173_POWER_DOMAIN_ISP] = {
30 .sta_mask = PWR_STATUS_ISP,
31 .ctl_offs = SPM_ISP_PWR_CON,
32 .sram_pdn_bits = GENMASK(11, 8),
33 .sram_pdn_ack_bits = GENMASK(13, 12),
35 [MT8173_POWER_DOMAIN_MM] = {
37 .sta_mask = PWR_STATUS_DISP,
38 .ctl_offs = SPM_DIS_PWR_CON,
39 .sram_pdn_bits = GENMASK(11, 8),
40 .sram_pdn_ack_bits = GENMASK(12, 12),
42 BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |
43 MT8173_TOP_AXI_PROT_EN_MM_M1),
46 [MT8173_POWER_DOMAIN_VENC_LT] = {
48 .sta_mask = PWR_STATUS_VENC_LT,
49 .ctl_offs = SPM_VEN2_PWR_CON,
50 .sram_pdn_bits = GENMASK(11, 8),
51 .sram_pdn_ack_bits = GENMASK(15, 12),
53 [MT8173_POWER_DOMAIN_AUDIO] = {
55 .sta_mask = PWR_STATUS_AUDIO,
56 .ctl_offs = SPM_AUDIO_PWR_CON,
57 .sram_pdn_bits = GENMASK(11, 8),
58 .sram_pdn_ack_bits = GENMASK(15, 12),
60 [MT8173_POWER_DOMAIN_USB] = {
62 .sta_mask = PWR_STATUS_USB,
63 .ctl_offs = SPM_USB_PWR_CON,
64 .sram_pdn_bits = GENMASK(11, 8),
65 .sram_pdn_ack_bits = GENMASK(15, 12),
66 .caps = MTK_SCPD_ACTIVE_WAKEUP,
68 [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
70 .sta_mask = PWR_STATUS_MFG_ASYNC,
71 .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
72 .sram_pdn_bits = GENMASK(11, 8),
73 .sram_pdn_ack_bits = 0,
75 [MT8173_POWER_DOMAIN_MFG_2D] = {
77 .sta_mask = PWR_STATUS_MFG_2D,
78 .ctl_offs = SPM_MFG_2D_PWR_CON,
79 .sram_pdn_bits = GENMASK(11, 8),
80 .sram_pdn_ack_bits = GENMASK(13, 12),
82 [MT8173_POWER_DOMAIN_MFG] = {
84 .sta_mask = PWR_STATUS_MFG,
85 .ctl_offs = SPM_MFG_PWR_CON,
86 .sram_pdn_bits = GENMASK(13, 8),
87 .sram_pdn_ack_bits = GENMASK(21, 16),
89 BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |
90 MT8173_TOP_AXI_PROT_EN_MFG_M0 |
91 MT8173_TOP_AXI_PROT_EN_MFG_M1 |
92 MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
97 static const struct scpsys_soc_data mt8173_scpsys_data = {
98 .domains_data = scpsys_domain_data_mt8173,
99 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8173),
100 .pwr_sta_offs = SPM_PWR_STATUS,
101 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
104 #endif /* __SOC_MEDIATEK_MT8173_PM_DOMAINS_H */