drivers/soc/mediatek/mt8167-pm-domains.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef __SOC_MEDIATEK_MT8167_PM_DOMAINS_H
   4 #define __SOC_MEDIATEK_MT8167_PM_DOMAINS_H
   5
   6 #include "mtk-pm-domains.h"
   7 #include <dt-bindings/power/mt8167-power.h>
   8
   9 #define MT8167_PWR_STATUS_MFG_2D        BIT(24)
  10 #define MT8167_PWR_STATUS_MFG_ASYNC     BIT(25)
  11
  12 /*
  13  * MT8167 power domain support
  14  */
  15
  16 static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
  17         [MT8167_POWER_DOMAIN_MM] = {
  18                 .name = "mm",
  19                 .sta_mask = PWR_STATUS_DISP,
  20                 .ctl_offs = SPM_DIS_PWR_CON,
  21                 .sram_pdn_bits = GENMASK(11, 8),
  22                 .sram_pdn_ack_bits = GENMASK(12, 12),
  23                 .bp_infracfg = {
  24                         BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI |
  25                                                MT8167_TOP_AXI_PROT_EN_MCU_MM),
  26                 },
  27                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
  28         },
  29         [MT8167_POWER_DOMAIN_VDEC] = {
  30                 .name = "vdec",
  31                 .sta_mask = PWR_STATUS_VDEC,
  32                 .ctl_offs = SPM_VDE_PWR_CON,
  33                 .sram_pdn_bits = GENMASK(8, 8),
  34                 .sram_pdn_ack_bits = GENMASK(12, 12),
  35                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
  36         },
  37         [MT8167_POWER_DOMAIN_ISP] = {
  38                 .name = "isp",
  39                 .sta_mask = PWR_STATUS_ISP,
  40                 .ctl_offs = SPM_ISP_PWR_CON,
  41                 .sram_pdn_bits = GENMASK(11, 8),
  42                 .sram_pdn_ack_bits = GENMASK(13, 12),
  43                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
  44         },
  45         [MT8167_POWER_DOMAIN_MFG_ASYNC] = {
  46                 .name = "mfg_async",
  47                 .sta_mask = MT8167_PWR_STATUS_MFG_ASYNC,
  48                 .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
  49                 .sram_pdn_bits = 0,
  50                 .sram_pdn_ack_bits = 0,
  51                 .bp_infracfg = {
  52                         BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG |
  53                                                MT8167_TOP_AXI_PROT_EN_MFG_EMI),
  54                 },
  55         },
  56         [MT8167_POWER_DOMAIN_MFG_2D] = {
  57                 .name = "mfg_2d",
  58                 .sta_mask = MT8167_PWR_STATUS_MFG_2D,
  59                 .ctl_offs = SPM_MFG_2D_PWR_CON,
  60                 .sram_pdn_bits = GENMASK(11, 8),
  61                 .sram_pdn_ack_bits = GENMASK(15, 12),
  62         },
  63         [MT8167_POWER_DOMAIN_MFG] = {
  64                 .name = "mfg",
  65                 .sta_mask = PWR_STATUS_MFG,
  66                 .ctl_offs = SPM_MFG_PWR_CON,
  67                 .sram_pdn_bits = GENMASK(11, 8),
  68                 .sram_pdn_ack_bits = GENMASK(15, 12),
  69         },
  70         [MT8167_POWER_DOMAIN_CONN] = {
  71                 .name = "conn",
  72                 .sta_mask = PWR_STATUS_CONN,
  73                 .ctl_offs = SPM_CONN_PWR_CON,
  74                 .sram_pdn_bits = GENMASK(8, 8),
  75                 .sram_pdn_ack_bits = 0,
  76                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
  77                 .bp_infracfg = {
  78                         BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI |
  79                                                MT8167_TOP_AXI_PROT_EN_CONN_MCU |
  80                                                MT8167_TOP_AXI_PROT_EN_MCU_CONN),
  81                 },
  82         },
  83 };
  84
  85 static const struct scpsys_soc_data mt8167_scpsys_data = {
  86         .domains_data = scpsys_domain_data_mt8167,
  87         .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8167),
  88         .pwr_sta_offs = SPM_PWR_STATUS,
  89         .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
  90 };
  91
  92 #endif /* __SOC_MEDIATEK_MT8167_PM_DOMAINS_H */
  93