drivers/soc/imx/gpcv2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017 Impinj, Inc
   4  * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
   5  *
   6  * Based on the code of analogus driver:
   7  *
   8  * Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/of_device.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/pm_domain.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/regmap.h>
  17 #include <linux/regulator/consumer.h>
  18 #include <linux/reset.h>
  19 #include <linux/sizes.h>
  20 #include <dt-bindings/power/imx7-power.h>
  21 #include <dt-bindings/power/imx8mq-power.h>
  22 #include <dt-bindings/power/imx8mm-power.h>
  23 #include <dt-bindings/power/imx8mn-power.h>
  24
  25 #define GPC_LPCR_A_CORE_BSC                     0x000
  26
  27 #define GPC_PGC_CPU_MAPPING             0x0ec
  28
  29 #define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN         BIT(6)
  30 #define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN         BIT(5)
  31 #define IMX7_USB_OTG1_PHY_A_CORE_DOMAIN         BIT(4)
  32 #define IMX7_PCIE_PHY_A_CORE_DOMAIN             BIT(3)
  33 #define IMX7_MIPI_PHY_A_CORE_DOMAIN             BIT(2)
  34
  35 #define IMX8M_PCIE2_A53_DOMAIN                  BIT(15)
  36 #define IMX8M_MIPI_CSI2_A53_DOMAIN              BIT(14)
  37 #define IMX8M_MIPI_CSI1_A53_DOMAIN              BIT(13)
  38 #define IMX8M_DISP_A53_DOMAIN                   BIT(12)
  39 #define IMX8M_HDMI_A53_DOMAIN                   BIT(11)
  40 #define IMX8M_VPU_A53_DOMAIN                    BIT(10)
  41 #define IMX8M_GPU_A53_DOMAIN                    BIT(9)
  42 #define IMX8M_DDR2_A53_DOMAIN                   BIT(8)
  43 #define IMX8M_DDR1_A53_DOMAIN                   BIT(7)
  44 #define IMX8M_OTG2_A53_DOMAIN                   BIT(5)
  45 #define IMX8M_OTG1_A53_DOMAIN                   BIT(4)
  46 #define IMX8M_PCIE1_A53_DOMAIN                  BIT(3)
  47 #define IMX8M_MIPI_A53_DOMAIN                   BIT(2)
  48
  49 #define IMX8MM_VPUH1_A53_DOMAIN                 BIT(15)
  50 #define IMX8MM_VPUG2_A53_DOMAIN                 BIT(14)
  51 #define IMX8MM_VPUG1_A53_DOMAIN                 BIT(13)
  52 #define IMX8MM_DISPMIX_A53_DOMAIN               BIT(12)
  53 #define IMX8MM_VPUMIX_A53_DOMAIN                BIT(10)
  54 #define IMX8MM_GPUMIX_A53_DOMAIN                BIT(9)
  55 #define IMX8MM_GPU_A53_DOMAIN                   (BIT(8) | BIT(11))
  56 #define IMX8MM_DDR1_A53_DOMAIN                  BIT(7)
  57 #define IMX8MM_OTG2_A53_DOMAIN                  BIT(5)
  58 #define IMX8MM_OTG1_A53_DOMAIN                  BIT(4)
  59 #define IMX8MM_PCIE_A53_DOMAIN                  BIT(3)
  60 #define IMX8MM_MIPI_A53_DOMAIN                  BIT(2)
  61
  62 #define IMX8MN_DISPMIX_A53_DOMAIN               BIT(12)
  63 #define IMX8MN_GPUMIX_A53_DOMAIN                BIT(9)
  64 #define IMX8MN_DDR1_A53_DOMAIN          BIT(7)
  65 #define IMX8MN_OTG1_A53_DOMAIN          BIT(4)
  66 #define IMX8MN_MIPI_A53_DOMAIN          BIT(2)
  67
  68 #define GPC_PU_PGC_SW_PUP_REQ           0x0f8
  69 #define GPC_PU_PGC_SW_PDN_REQ           0x104
  70
  71 #define IMX7_USB_HSIC_PHY_SW_Pxx_REQ            BIT(4)
  72 #define IMX7_USB_OTG2_PHY_SW_Pxx_REQ            BIT(3)
  73 #define IMX7_USB_OTG1_PHY_SW_Pxx_REQ            BIT(2)
  74 #define IMX7_PCIE_PHY_SW_Pxx_REQ                BIT(1)
  75 #define IMX7_MIPI_PHY_SW_Pxx_REQ                BIT(0)
  76
  77 #define IMX8M_PCIE2_SW_Pxx_REQ                  BIT(13)
  78 #define IMX8M_MIPI_CSI2_SW_Pxx_REQ              BIT(12)
  79 #define IMX8M_MIPI_CSI1_SW_Pxx_REQ              BIT(11)
  80 #define IMX8M_DISP_SW_Pxx_REQ                   BIT(10)
  81 #define IMX8M_HDMI_SW_Pxx_REQ                   BIT(9)
  82 #define IMX8M_VPU_SW_Pxx_REQ                    BIT(8)
  83 #define IMX8M_GPU_SW_Pxx_REQ                    BIT(7)
  84 #define IMX8M_DDR2_SW_Pxx_REQ                   BIT(6)
  85 #define IMX8M_DDR1_SW_Pxx_REQ                   BIT(5)
  86 #define IMX8M_OTG2_SW_Pxx_REQ                   BIT(3)
  87 #define IMX8M_OTG1_SW_Pxx_REQ                   BIT(2)
  88 #define IMX8M_PCIE1_SW_Pxx_REQ                  BIT(1)
  89 #define IMX8M_MIPI_SW_Pxx_REQ                   BIT(0)
  90
  91 #define IMX8MM_VPUH1_SW_Pxx_REQ                 BIT(13)
  92 #define IMX8MM_VPUG2_SW_Pxx_REQ                 BIT(12)
  93 #define IMX8MM_VPUG1_SW_Pxx_REQ                 BIT(11)
  94 #define IMX8MM_DISPMIX_SW_Pxx_REQ               BIT(10)
  95 #define IMX8MM_VPUMIX_SW_Pxx_REQ                BIT(8)
  96 #define IMX8MM_GPUMIX_SW_Pxx_REQ                BIT(7)
  97 #define IMX8MM_GPU_SW_Pxx_REQ                   (BIT(6) | BIT(9))
  98 #define IMX8MM_DDR1_SW_Pxx_REQ                  BIT(5)
  99 #define IMX8MM_OTG2_SW_Pxx_REQ                  BIT(3)
 100 #define IMX8MM_OTG1_SW_Pxx_REQ                  BIT(2)
 101 #define IMX8MM_PCIE_SW_Pxx_REQ                  BIT(1)
 102 #define IMX8MM_MIPI_SW_Pxx_REQ                  BIT(0)
 103
 104 #define IMX8MN_DISPMIX_SW_Pxx_REQ               BIT(10)
 105 #define IMX8MN_GPUMIX_SW_Pxx_REQ                BIT(7)
 106 #define IMX8MN_DDR1_SW_Pxx_REQ          BIT(5)
 107 #define IMX8MN_OTG1_SW_Pxx_REQ          BIT(2)
 108 #define IMX8MN_MIPI_SW_Pxx_REQ          BIT(0)
 109
 110 #define GPC_M4_PU_PDN_FLG               0x1bc
 111
 112 #define GPC_PU_PWRHSK                   0x1fc
 113
 114 #define IMX8M_GPU_HSK_PWRDNACKN                 BIT(26)
 115 #define IMX8M_VPU_HSK_PWRDNACKN                 BIT(25)
 116 #define IMX8M_DISP_HSK_PWRDNACKN                BIT(24)
 117 #define IMX8M_GPU_HSK_PWRDNREQN                 BIT(6)
 118 #define IMX8M_VPU_HSK_PWRDNREQN                 BIT(5)
 119 #define IMX8M_DISP_HSK_PWRDNREQN                BIT(4)
 120
 121
 122 #define IMX8MM_GPUMIX_HSK_PWRDNACKN             BIT(29)
 123 #define IMX8MM_GPU_HSK_PWRDNACKN                (BIT(27) | BIT(28))
 124 #define IMX8MM_VPUMIX_HSK_PWRDNACKN             BIT(26)
 125 #define IMX8MM_DISPMIX_HSK_PWRDNACKN            BIT(25)
 126 #define IMX8MM_HSIO_HSK_PWRDNACKN               (BIT(23) | BIT(24))
 127 #define IMX8MM_GPUMIX_HSK_PWRDNREQN             BIT(11)
 128 #define IMX8MM_GPU_HSK_PWRDNREQN                (BIT(9) | BIT(10))
 129 #define IMX8MM_VPUMIX_HSK_PWRDNREQN             BIT(8)
 130 #define IMX8MM_DISPMIX_HSK_PWRDNREQN            BIT(7)
 131 #define IMX8MM_HSIO_HSK_PWRDNREQN               (BIT(5) | BIT(6))
 132
 133 #define IMX8MN_GPUMIX_HSK_PWRDNACKN             (BIT(29) | BIT(27))
 134 #define IMX8MN_DISPMIX_HSK_PWRDNACKN            BIT(25)
 135 #define IMX8MN_HSIO_HSK_PWRDNACKN               BIT(23)
 136 #define IMX8MN_GPUMIX_HSK_PWRDNREQN             (BIT(11) | BIT(9))
 137 #define IMX8MN_DISPMIX_HSK_PWRDNREQN            BIT(7)
 138 #define IMX8MN_HSIO_HSK_PWRDNREQN               BIT(5)
 139
 140 /*
 141  * The PGC offset values in Reference Manual
 142  * (Rev. 1, 01/2018 and the older ones) GPC chapter's
 143  * GPC_PGC memory map are incorrect, below offset
 144  * values are from design RTL.
 145  */
 146 #define IMX7_PGC_MIPI                   16
 147 #define IMX7_PGC_PCIE                   17
 148 #define IMX7_PGC_USB_HSIC               20
 149
 150 #define IMX8M_PGC_MIPI                  16
 151 #define IMX8M_PGC_PCIE1                 17
 152 #define IMX8M_PGC_OTG1                  18
 153 #define IMX8M_PGC_OTG2                  19
 154 #define IMX8M_PGC_DDR1                  21
 155 #define IMX8M_PGC_GPU                   23
 156 #define IMX8M_PGC_VPU                   24
 157 #define IMX8M_PGC_DISP                  26
 158 #define IMX8M_PGC_MIPI_CSI1             27
 159 #define IMX8M_PGC_MIPI_CSI2             28
 160 #define IMX8M_PGC_PCIE2                 29
 161
 162 #define IMX8MM_PGC_MIPI                 16
 163 #define IMX8MM_PGC_PCIE                 17
 164 #define IMX8MM_PGC_OTG1                 18
 165 #define IMX8MM_PGC_OTG2                 19
 166 #define IMX8MM_PGC_DDR1                 21
 167 #define IMX8MM_PGC_GPU2D                22
 168 #define IMX8MM_PGC_GPUMIX               23
 169 #define IMX8MM_PGC_VPUMIX               24
 170 #define IMX8MM_PGC_GPU3D                25
 171 #define IMX8MM_PGC_DISPMIX              26
 172 #define IMX8MM_PGC_VPUG1                27
 173 #define IMX8MM_PGC_VPUG2                28
 174 #define IMX8MM_PGC_VPUH1                29
 175
 176 #define IMX8MN_PGC_MIPI         16
 177 #define IMX8MN_PGC_OTG1         18
 178 #define IMX8MN_PGC_DDR1         21
 179 #define IMX8MN_PGC_GPUMIX               23
 180 #define IMX8MN_PGC_DISPMIX              26
 181
 182 #define GPC_PGC_CTRL(n)                 (0x800 + (n) * 0x40)
 183 #define GPC_PGC_SR(n)                   (GPC_PGC_CTRL(n) + 0xc)
 184
 185 #define GPC_PGC_CTRL_PCR                BIT(0)
 186
 187 struct imx_pgc_domain {
 188         struct generic_pm_domain genpd;
 189         struct regmap *regmap;
 190         struct regulator *regulator;
 191         struct reset_control *reset;
 192         struct clk_bulk_data *clks;
 193         int num_clks;
 194
 195         unsigned long pgc;
 196
 197         const struct {
 198                 u32 pxx;
 199                 u32 map;
 200                 u32 hskreq;
 201                 u32 hskack;
 202         } bits;
 203
 204         const int voltage;
 205         const bool keep_clocks;
 206         struct device *dev;
 207 };
 208
 209 struct imx_pgc_domain_data {
 210         const struct imx_pgc_domain *domains;
 211         size_t domains_num;
 212         const struct regmap_access_table *reg_access_table;
 213 };
 214
 215 static inline struct imx_pgc_domain *
 216 to_imx_pgc_domain(struct generic_pm_domain *genpd)
 217 {
 218         return container_of(genpd, struct imx_pgc_domain, genpd);
 219 }
 220
 221 static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 222 {
 223         struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
 224         u32 reg_val, pgc;
 225         int ret;
 226
 227         ret = pm_runtime_get_sync(domain->dev);
 228         if (ret < 0) {
 229                 pm_runtime_put_noidle(domain->dev);
 230                 return ret;
 231         }
 232
 233         if (!IS_ERR(domain->regulator)) {
 234                 ret = regulator_enable(domain->regulator);
 235                 if (ret) {
 236                         dev_err(domain->dev, "failed to enable regulator\n");
 237                         goto out_put_pm;
 238                 }
 239         }
 240
 241         /* Enable reset clocks for all devices in the domain */
 242         ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
 243         if (ret) {
 244                 dev_err(domain->dev, "failed to enable reset clocks\n");
 245                 goto out_regulator_disable;
 246         }
 247
 248         reset_control_assert(domain->reset);
 249
 250         if (domain->bits.pxx) {
 251                 /* request the domain to power up */
 252                 regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
 253                                    domain->bits.pxx, domain->bits.pxx);
 254                 /*
 255                  * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
 256                  * for PUP_REQ/PDN_REQ bit to be cleared
 257                  */
 258                 ret = regmap_read_poll_timeout(domain->regmap,
 259                                                GPC_PU_PGC_SW_PUP_REQ, reg_val,
 260                                                !(reg_val & domain->bits.pxx),
 261                                                0, USEC_PER_MSEC);
 262                 if (ret) {
 263                         dev_err(domain->dev, "failed to command PGC\n");
 264                         goto out_clk_disable;
 265                 }
 266
 267                 /* disable power control */
 268                 for_each_set_bit(pgc, &domain->pgc, 32) {
 269                         regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(pgc),
 270                                           GPC_PGC_CTRL_PCR);
 271                 }
 272         }
 273
 274         /* delay for reset to propagate */
 275         udelay(5);
 276
 277         reset_control_deassert(domain->reset);
 278
 279         /* request the ADB400 to power up */
 280         if (domain->bits.hskreq) {
 281                 regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
 282                                    domain->bits.hskreq, domain->bits.hskreq);
 283
 284                 /*
 285                  * ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK, reg_val,
 286                  *                                (reg_val & domain->bits.hskack), 0,
 287                  *                                USEC_PER_MSEC);
 288                  * Technically we need the commented code to wait handshake. But that needs
 289                  * the BLK-CTL module BUS clk-en bit being set.
 290                  *
 291                  * There is a separate BLK-CTL module and we will have such a driver for it,
 292                  * that driver will set the BUS clk-en bit and handshake will be triggered
 293                  * automatically there. Just add a delay and suppose the handshake finish
 294                  * after that.
 295                  */
 296         }
 297
 298         /* Disable reset clocks for all devices in the domain */
 299         if (!domain->keep_clocks)
 300                 clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
 301
 302         return 0;
 303
 304 out_clk_disable:
 305         clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
 306 out_regulator_disable:
 307         if (!IS_ERR(domain->regulator))
 308                 regulator_disable(domain->regulator);
 309 out_put_pm:
 310         pm_runtime_put(domain->dev);
 311
 312         return ret;
 313 }
 314
 315 static int imx_pgc_power_down(struct generic_pm_domain *genpd)
 316 {
 317         struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
 318         u32 reg_val, pgc;
 319         int ret;
 320
 321         /* Enable reset clocks for all devices in the domain */
 322         if (!domain->keep_clocks) {
 323                 ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
 324                 if (ret) {
 325                         dev_err(domain->dev, "failed to enable reset clocks\n");
 326                         return ret;
 327                 }
 328         }
 329
 330         /* request the ADB400 to power down */
 331         if (domain->bits.hskreq) {
 332                 regmap_clear_bits(domain->regmap, GPC_PU_PWRHSK,
 333                                   domain->bits.hskreq);
 334
 335                 ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK,
 336                                                reg_val,
 337                                                !(reg_val & domain->bits.hskack),
 338                                                0, USEC_PER_MSEC);
 339                 if (ret) {
 340                         dev_err(domain->dev, "failed to power down ADB400\n");
 341                         goto out_clk_disable;
 342                 }
 343         }
 344
 345         if (domain->bits.pxx) {
 346                 /* enable power control */
 347                 for_each_set_bit(pgc, &domain->pgc, 32) {
 348                         regmap_update_bits(domain->regmap, GPC_PGC_CTRL(pgc),
 349                                            GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
 350                 }
 351
 352                 /* request the domain to power down */
 353                 regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
 354                                    domain->bits.pxx, domain->bits.pxx);
 355                 /*
 356                  * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
 357                  * for PUP_REQ/PDN_REQ bit to be cleared
 358                  */
 359                 ret = regmap_read_poll_timeout(domain->regmap,
 360                                                GPC_PU_PGC_SW_PDN_REQ, reg_val,
 361                                                !(reg_val & domain->bits.pxx),
 362                                                0, USEC_PER_MSEC);
 363                 if (ret) {
 364                         dev_err(domain->dev, "failed to command PGC\n");
 365                         goto out_clk_disable;
 366                 }
 367         }
 368
 369         /* Disable reset clocks for all devices in the domain */
 370         clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
 371
 372         if (!IS_ERR(domain->regulator)) {
 373                 ret = regulator_disable(domain->regulator);
 374                 if (ret) {
 375                         dev_err(domain->dev, "failed to disable regulator\n");
 376                         return ret;
 377                 }
 378         }
 379
 380         pm_runtime_put_sync_suspend(domain->dev);
 381
 382         return 0;
 383
 384 out_clk_disable:
 385         clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
 386
 387         return ret;
 388 }
 389
 390 static const struct imx_pgc_domain imx7_pgc_domains[] = {
 391         [IMX7_POWER_DOMAIN_MIPI_PHY] = {
 392                 .genpd = {
 393                         .name      = "mipi-phy",
 394                 },
 395                 .bits  = {
 396                         .pxx = IMX7_MIPI_PHY_SW_Pxx_REQ,
 397                         .map = IMX7_MIPI_PHY_A_CORE_DOMAIN,
 398                 },
 399                 .voltage   = 1000000,
 400                 .pgc       = BIT(IMX7_PGC_MIPI),
 401         },
 402
 403         [IMX7_POWER_DOMAIN_PCIE_PHY] = {
 404                 .genpd = {
 405                         .name      = "pcie-phy",
 406                 },
 407                 .bits  = {
 408                         .pxx = IMX7_PCIE_PHY_SW_Pxx_REQ,
 409                         .map = IMX7_PCIE_PHY_A_CORE_DOMAIN,
 410                 },
 411                 .voltage   = 1000000,
 412                 .pgc       = BIT(IMX7_PGC_PCIE),
 413         },
 414
 415         [IMX7_POWER_DOMAIN_USB_HSIC_PHY] = {
 416                 .genpd = {
 417                         .name      = "usb-hsic-phy",
 418                 },
 419                 .bits  = {
 420                         .pxx = IMX7_USB_HSIC_PHY_SW_Pxx_REQ,
 421                         .map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN,
 422                 },
 423                 .voltage   = 1200000,
 424                 .pgc       = BIT(IMX7_PGC_USB_HSIC),
 425         },
 426 };
 427
 428 static const struct regmap_range imx7_yes_ranges[] = {
 429                 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
 430                                  GPC_M4_PU_PDN_FLG),
 431                 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_MIPI),
 432                                  GPC_PGC_SR(IMX7_PGC_MIPI)),
 433                 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_PCIE),
 434                                  GPC_PGC_SR(IMX7_PGC_PCIE)),
 435                 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_USB_HSIC),
 436                                  GPC_PGC_SR(IMX7_PGC_USB_HSIC)),
 437 };
 438
 439 static const struct regmap_access_table imx7_access_table = {
 440         .yes_ranges     = imx7_yes_ranges,
 441         .n_yes_ranges   = ARRAY_SIZE(imx7_yes_ranges),
 442 };
 443
 444 static const struct imx_pgc_domain_data imx7_pgc_domain_data = {
 445         .domains = imx7_pgc_domains,
 446         .domains_num = ARRAY_SIZE(imx7_pgc_domains),
 447         .reg_access_table = &imx7_access_table,
 448 };
 449
 450 static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 451         [IMX8M_POWER_DOMAIN_MIPI] = {
 452                 .genpd = {
 453                         .name      = "mipi",
 454                 },
 455                 .bits  = {
 456                         .pxx = IMX8M_MIPI_SW_Pxx_REQ,
 457                         .map = IMX8M_MIPI_A53_DOMAIN,
 458                 },
 459                 .pgc       = BIT(IMX8M_PGC_MIPI),
 460         },
 461
 462         [IMX8M_POWER_DOMAIN_PCIE1] = {
 463                 .genpd = {
 464                         .name = "pcie1",
 465                 },
 466                 .bits  = {
 467                         .pxx = IMX8M_PCIE1_SW_Pxx_REQ,
 468                         .map = IMX8M_PCIE1_A53_DOMAIN,
 469                 },
 470                 .pgc   = BIT(IMX8M_PGC_PCIE1),
 471         },
 472
 473         [IMX8M_POWER_DOMAIN_USB_OTG1] = {
 474                 .genpd = {
 475                         .name = "usb-otg1",
 476                 },
 477                 .bits  = {
 478                         .pxx = IMX8M_OTG1_SW_Pxx_REQ,
 479                         .map = IMX8M_OTG1_A53_DOMAIN,
 480                 },
 481                 .pgc   = BIT(IMX8M_PGC_OTG1),
 482         },
 483
 484         [IMX8M_POWER_DOMAIN_USB_OTG2] = {
 485                 .genpd = {
 486                         .name = "usb-otg2",
 487                 },
 488                 .bits  = {
 489                         .pxx = IMX8M_OTG2_SW_Pxx_REQ,
 490                         .map = IMX8M_OTG2_A53_DOMAIN,
 491                 },
 492                 .pgc   = BIT(IMX8M_PGC_OTG2),
 493         },
 494
 495         [IMX8M_POWER_DOMAIN_DDR1] = {
 496                 .genpd = {
 497                         .name = "ddr1",
 498                 },
 499                 .bits  = {
 500                         .pxx = IMX8M_DDR1_SW_Pxx_REQ,
 501                         .map = IMX8M_DDR2_A53_DOMAIN,
 502                 },
 503                 .pgc   = BIT(IMX8M_PGC_DDR1),
 504         },
 505
 506         [IMX8M_POWER_DOMAIN_GPU] = {
 507                 .genpd = {
 508                         .name = "gpu",
 509                 },
 510                 .bits  = {
 511                         .pxx = IMX8M_GPU_SW_Pxx_REQ,
 512                         .map = IMX8M_GPU_A53_DOMAIN,
 513                         .hskreq = IMX8M_GPU_HSK_PWRDNREQN,
 514                         .hskack = IMX8M_GPU_HSK_PWRDNACKN,
 515                 },
 516                 .pgc   = BIT(IMX8M_PGC_GPU),
 517         },
 518
 519         [IMX8M_POWER_DOMAIN_VPU] = {
 520                 .genpd = {
 521                         .name = "vpu",
 522                 },
 523                 .bits  = {
 524                         .pxx = IMX8M_VPU_SW_Pxx_REQ,
 525                         .map = IMX8M_VPU_A53_DOMAIN,
 526                         .hskreq = IMX8M_VPU_HSK_PWRDNREQN,
 527                         .hskack = IMX8M_VPU_HSK_PWRDNACKN,
 528                 },
 529                 .pgc   = BIT(IMX8M_PGC_VPU),
 530                 .keep_clocks = true,
 531         },
 532
 533         [IMX8M_POWER_DOMAIN_DISP] = {
 534                 .genpd = {
 535                         .name = "disp",
 536                 },
 537                 .bits  = {
 538                         .pxx = IMX8M_DISP_SW_Pxx_REQ,
 539                         .map = IMX8M_DISP_A53_DOMAIN,
 540                         .hskreq = IMX8M_DISP_HSK_PWRDNREQN,
 541                         .hskack = IMX8M_DISP_HSK_PWRDNACKN,
 542                 },
 543                 .pgc   = BIT(IMX8M_PGC_DISP),
 544         },
 545
 546         [IMX8M_POWER_DOMAIN_MIPI_CSI1] = {
 547                 .genpd = {
 548                         .name = "mipi-csi1",
 549                 },
 550                 .bits  = {
 551                         .pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ,
 552                         .map = IMX8M_MIPI_CSI1_A53_DOMAIN,
 553                 },
 554                 .pgc   = BIT(IMX8M_PGC_MIPI_CSI1),
 555         },
 556
 557         [IMX8M_POWER_DOMAIN_MIPI_CSI2] = {
 558                 .genpd = {
 559                         .name = "mipi-csi2",
 560                 },
 561                 .bits  = {
 562                         .pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ,
 563                         .map = IMX8M_MIPI_CSI2_A53_DOMAIN,
 564                 },
 565                 .pgc   = BIT(IMX8M_PGC_MIPI_CSI2),
 566         },
 567
 568         [IMX8M_POWER_DOMAIN_PCIE2] = {
 569                 .genpd = {
 570                         .name = "pcie2",
 571                 },
 572                 .bits  = {
 573                         .pxx = IMX8M_PCIE2_SW_Pxx_REQ,
 574                         .map = IMX8M_PCIE2_A53_DOMAIN,
 575                 },
 576                 .pgc   = BIT(IMX8M_PGC_PCIE2),
 577         },
 578 };
 579
 580 static const struct regmap_range imx8m_yes_ranges[] = {
 581                 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
 582                                  GPC_PU_PWRHSK),
 583                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI),
 584                                  GPC_PGC_SR(IMX8M_PGC_MIPI)),
 585                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE1),
 586                                  GPC_PGC_SR(IMX8M_PGC_PCIE1)),
 587                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG1),
 588                                  GPC_PGC_SR(IMX8M_PGC_OTG1)),
 589                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG2),
 590                                  GPC_PGC_SR(IMX8M_PGC_OTG2)),
 591                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DDR1),
 592                                  GPC_PGC_SR(IMX8M_PGC_DDR1)),
 593                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_GPU),
 594                                  GPC_PGC_SR(IMX8M_PGC_GPU)),
 595                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_VPU),
 596                                  GPC_PGC_SR(IMX8M_PGC_VPU)),
 597                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DISP),
 598                                  GPC_PGC_SR(IMX8M_PGC_DISP)),
 599                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI1),
 600                                  GPC_PGC_SR(IMX8M_PGC_MIPI_CSI1)),
 601                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI2),
 602                                  GPC_PGC_SR(IMX8M_PGC_MIPI_CSI2)),
 603                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE2),
 604                                  GPC_PGC_SR(IMX8M_PGC_PCIE2)),
 605 };
 606
 607 static const struct regmap_access_table imx8m_access_table = {
 608         .yes_ranges     = imx8m_yes_ranges,
 609         .n_yes_ranges   = ARRAY_SIZE(imx8m_yes_ranges),
 610 };
 611
 612 static const struct imx_pgc_domain_data imx8m_pgc_domain_data = {
 613         .domains = imx8m_pgc_domains,
 614         .domains_num = ARRAY_SIZE(imx8m_pgc_domains),
 615         .reg_access_table = &imx8m_access_table,
 616 };
 617
 618 static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 619         [IMX8MM_POWER_DOMAIN_HSIOMIX] = {
 620                 .genpd = {
 621                         .name = "hsiomix",
 622                 },
 623                 .bits  = {
 624                         .pxx = 0, /* no power sequence control */
 625                         .map = 0, /* no power sequence control */
 626                         .hskreq = IMX8MM_HSIO_HSK_PWRDNREQN,
 627                         .hskack = IMX8MM_HSIO_HSK_PWRDNACKN,
 628                 },
 629                 .keep_clocks = true,
 630         },
 631
 632         [IMX8MM_POWER_DOMAIN_PCIE] = {
 633                 .genpd = {
 634                         .name = "pcie",
 635                 },
 636                 .bits  = {
 637                         .pxx = IMX8MM_PCIE_SW_Pxx_REQ,
 638                         .map = IMX8MM_PCIE_A53_DOMAIN,
 639                 },
 640                 .pgc   = BIT(IMX8MM_PGC_PCIE),
 641         },
 642
 643         [IMX8MM_POWER_DOMAIN_OTG1] = {
 644                 .genpd = {
 645                         .name = "usb-otg1",
 646                 },
 647                 .bits  = {
 648                         .pxx = IMX8MM_OTG1_SW_Pxx_REQ,
 649                         .map = IMX8MM_OTG1_A53_DOMAIN,
 650                 },
 651                 .pgc   = BIT(IMX8MM_PGC_OTG1),
 652         },
 653
 654         [IMX8MM_POWER_DOMAIN_OTG2] = {
 655                 .genpd = {
 656                         .name = "usb-otg2",
 657                 },
 658                 .bits  = {
 659                         .pxx = IMX8MM_OTG2_SW_Pxx_REQ,
 660                         .map = IMX8MM_OTG2_A53_DOMAIN,
 661                 },
 662                 .pgc   = BIT(IMX8MM_PGC_OTG2),
 663         },
 664
 665         [IMX8MM_POWER_DOMAIN_GPUMIX] = {
 666                 .genpd = {
 667                         .name = "gpumix",
 668                 },
 669                 .bits  = {
 670                         .pxx = IMX8MM_GPUMIX_SW_Pxx_REQ,
 671                         .map = IMX8MM_GPUMIX_A53_DOMAIN,
 672                         .hskreq = IMX8MM_GPUMIX_HSK_PWRDNREQN,
 673                         .hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN,
 674                 },
 675                 .pgc   = BIT(IMX8MM_PGC_GPUMIX),
 676                 .keep_clocks = true,
 677         },
 678
 679         [IMX8MM_POWER_DOMAIN_GPU] = {
 680                 .genpd = {
 681                         .name = "gpu",
 682                 },
 683                 .bits  = {
 684                         .pxx = IMX8MM_GPU_SW_Pxx_REQ,
 685                         .map = IMX8MM_GPU_A53_DOMAIN,
 686                         .hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
 687                         .hskack = IMX8MM_GPU_HSK_PWRDNACKN,
 688                 },
 689                 .pgc   = BIT(IMX8MM_PGC_GPU2D) | BIT(IMX8MM_PGC_GPU3D),
 690         },
 691
 692         [IMX8MM_POWER_DOMAIN_VPUMIX] = {
 693                 .genpd = {
 694                         .name = "vpumix",
 695                 },
 696                 .bits  = {
 697                         .pxx = IMX8MM_VPUMIX_SW_Pxx_REQ,
 698                         .map = IMX8MM_VPUMIX_A53_DOMAIN,
 699                         .hskreq = IMX8MM_VPUMIX_HSK_PWRDNREQN,
 700                         .hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN,
 701                 },
 702                 .pgc   = BIT(IMX8MM_PGC_VPUMIX),
 703                 .keep_clocks = true,
 704         },
 705
 706         [IMX8MM_POWER_DOMAIN_VPUG1] = {
 707                 .genpd = {
 708                         .name = "vpu-g1",
 709                 },
 710                 .bits  = {
 711                         .pxx = IMX8MM_VPUG1_SW_Pxx_REQ,
 712                         .map = IMX8MM_VPUG1_A53_DOMAIN,
 713                 },
 714                 .pgc   = BIT(IMX8MM_PGC_VPUG1),
 715         },
 716
 717         [IMX8MM_POWER_DOMAIN_VPUG2] = {
 718                 .genpd = {
 719                         .name = "vpu-g2",
 720                 },
 721                 .bits  = {
 722                         .pxx = IMX8MM_VPUG2_SW_Pxx_REQ,
 723                         .map = IMX8MM_VPUG2_A53_DOMAIN,
 724                 },
 725                 .pgc   = BIT(IMX8MM_PGC_VPUG2),
 726         },
 727
 728         [IMX8MM_POWER_DOMAIN_VPUH1] = {
 729                 .genpd = {
 730                         .name = "vpu-h1",
 731                 },
 732                 .bits  = {
 733                         .pxx = IMX8MM_VPUH1_SW_Pxx_REQ,
 734                         .map = IMX8MM_VPUH1_A53_DOMAIN,
 735                 },
 736                 .pgc   = BIT(IMX8MM_PGC_VPUH1),
 737                 .keep_clocks = true,
 738         },
 739
 740         [IMX8MM_POWER_DOMAIN_DISPMIX] = {
 741                 .genpd = {
 742                         .name = "dispmix",
 743                 },
 744                 .bits  = {
 745                         .pxx = IMX8MM_DISPMIX_SW_Pxx_REQ,
 746                         .map = IMX8MM_DISPMIX_A53_DOMAIN,
 747                         .hskreq = IMX8MM_DISPMIX_HSK_PWRDNREQN,
 748                         .hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN,
 749                 },
 750                 .pgc   = BIT(IMX8MM_PGC_DISPMIX),
 751                 .keep_clocks = true,
 752         },
 753
 754         [IMX8MM_POWER_DOMAIN_MIPI] = {
 755                 .genpd = {
 756                         .name = "mipi",
 757                 },
 758                 .bits  = {
 759                         .pxx = IMX8MM_MIPI_SW_Pxx_REQ,
 760                         .map = IMX8MM_MIPI_A53_DOMAIN,
 761                 },
 762                 .pgc   = BIT(IMX8MM_PGC_MIPI),
 763         },
 764 };
 765
 766 static const struct regmap_range imx8mm_yes_ranges[] = {
 767                 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
 768                                  GPC_PU_PWRHSK),
 769                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_MIPI),
 770                                  GPC_PGC_SR(IMX8MM_PGC_MIPI)),
 771                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_PCIE),
 772                                  GPC_PGC_SR(IMX8MM_PGC_PCIE)),
 773                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG1),
 774                                  GPC_PGC_SR(IMX8MM_PGC_OTG1)),
 775                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG2),
 776                                  GPC_PGC_SR(IMX8MM_PGC_OTG2)),
 777                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DDR1),
 778                                  GPC_PGC_SR(IMX8MM_PGC_DDR1)),
 779                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU2D),
 780                                  GPC_PGC_SR(IMX8MM_PGC_GPU2D)),
 781                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPUMIX),
 782                                  GPC_PGC_SR(IMX8MM_PGC_GPUMIX)),
 783                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUMIX),
 784                                  GPC_PGC_SR(IMX8MM_PGC_VPUMIX)),
 785                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU3D),
 786                                  GPC_PGC_SR(IMX8MM_PGC_GPU3D)),
 787                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DISPMIX),
 788                                  GPC_PGC_SR(IMX8MM_PGC_DISPMIX)),
 789                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUG1),
 790                                  GPC_PGC_SR(IMX8MM_PGC_VPUG1)),
 791                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUG2),
 792                                  GPC_PGC_SR(IMX8MM_PGC_VPUG2)),
 793                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUH1),
 794                                  GPC_PGC_SR(IMX8MM_PGC_VPUH1)),
 795 };
 796
 797 static const struct regmap_access_table imx8mm_access_table = {
 798         .yes_ranges     = imx8mm_yes_ranges,
 799         .n_yes_ranges   = ARRAY_SIZE(imx8mm_yes_ranges),
 800 };
 801
 802 static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
 803         .domains = imx8mm_pgc_domains,
 804         .domains_num = ARRAY_SIZE(imx8mm_pgc_domains),
 805         .reg_access_table = &imx8mm_access_table,
 806 };
 807
 808 static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
 809         [IMX8MN_POWER_DOMAIN_HSIOMIX] = {
 810                 .genpd = {
 811                         .name = "hsiomix",
 812                 },
 813                 .bits  = {
 814                         .pxx = 0, /* no power sequence control */
 815                         .map = 0, /* no power sequence control */
 816                         .hskreq = IMX8MN_HSIO_HSK_PWRDNREQN,
 817                         .hskack = IMX8MN_HSIO_HSK_PWRDNACKN,
 818                 },
 819                 .keep_clocks = true,
 820         },
 821
 822         [IMX8MN_POWER_DOMAIN_OTG1] = {
 823                 .genpd = {
 824                         .name = "usb-otg1",
 825                 },
 826                 .bits  = {
 827                         .pxx = IMX8MN_OTG1_SW_Pxx_REQ,
 828                         .map = IMX8MN_OTG1_A53_DOMAIN,
 829                 },
 830                 .pgc   = BIT(IMX8MN_PGC_OTG1),
 831         },
 832
 833         [IMX8MN_POWER_DOMAIN_GPUMIX] = {
 834                 .genpd = {
 835                         .name = "gpumix",
 836                 },
 837                 .bits  = {
 838                         .pxx = IMX8MN_GPUMIX_SW_Pxx_REQ,
 839                         .map = IMX8MN_GPUMIX_A53_DOMAIN,
 840                         .hskreq = IMX8MN_GPUMIX_HSK_PWRDNREQN,
 841                         .hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN,
 842                 },
 843                 .pgc   = BIT(IMX8MN_PGC_GPUMIX),
 844                 .keep_clocks = true,
 845         },
 846
 847         [IMX8MN_POWER_DOMAIN_DISPMIX] = {
 848                 .genpd = {
 849                         .name = "dispmix",
 850                 },
 851                         .bits  = {
 852                         .pxx = IMX8MN_DISPMIX_SW_Pxx_REQ,
 853                         .map = IMX8MN_DISPMIX_A53_DOMAIN,
 854                         .hskreq = IMX8MN_DISPMIX_HSK_PWRDNREQN,
 855                         .hskack = IMX8MN_DISPMIX_HSK_PWRDNACKN,
 856                 },
 857                 .pgc   = BIT(IMX8MN_PGC_DISPMIX),
 858                 .keep_clocks = true,
 859         },
 860
 861         [IMX8MN_POWER_DOMAIN_MIPI] = {
 862                 .genpd = {
 863                         .name = "mipi",
 864                 },
 865                         .bits  = {
 866                         .pxx = IMX8MN_MIPI_SW_Pxx_REQ,
 867                         .map = IMX8MN_MIPI_A53_DOMAIN,
 868                 },
 869                 .pgc   = BIT(IMX8MN_PGC_MIPI),
 870         },
 871 };
 872
 873 static const struct regmap_range imx8mn_yes_ranges[] = {
 874         regmap_reg_range(GPC_LPCR_A_CORE_BSC,
 875                          GPC_PU_PWRHSK),
 876         regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_MIPI),
 877                          GPC_PGC_SR(IMX8MN_PGC_MIPI)),
 878         regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_OTG1),
 879                          GPC_PGC_SR(IMX8MN_PGC_OTG1)),
 880         regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DDR1),
 881                          GPC_PGC_SR(IMX8MN_PGC_DDR1)),
 882         regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_GPUMIX),
 883                          GPC_PGC_SR(IMX8MN_PGC_GPUMIX)),
 884         regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DISPMIX),
 885                          GPC_PGC_SR(IMX8MN_PGC_DISPMIX)),
 886 };
 887
 888 static const struct regmap_access_table imx8mn_access_table = {
 889         .yes_ranges     = imx8mn_yes_ranges,
 890         .n_yes_ranges   = ARRAY_SIZE(imx8mn_yes_ranges),
 891 };
 892
 893 static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = {
 894         .domains = imx8mn_pgc_domains,
 895         .domains_num = ARRAY_SIZE(imx8mn_pgc_domains),
 896         .reg_access_table = &imx8mn_access_table,
 897 };
 898
 899 static int imx_pgc_domain_probe(struct platform_device *pdev)
 900 {
 901         struct imx_pgc_domain *domain = pdev->dev.platform_data;
 902         int ret;
 903
 904         domain->dev = &pdev->dev;
 905
 906         domain->regulator = devm_regulator_get_optional(domain->dev, "power");
 907         if (IS_ERR(domain->regulator)) {
 908                 if (PTR_ERR(domain->regulator) != -ENODEV)
 909                         return dev_err_probe(domain->dev, PTR_ERR(domain->regulator),
 910                                              "Failed to get domain's regulator\n");
 911         } else if (domain->voltage) {
 912                 regulator_set_voltage(domain->regulator,
 913                                       domain->voltage, domain->voltage);
 914         }
 915
 916         domain->num_clks = devm_clk_bulk_get_all(domain->dev, &domain->clks);
 917         if (domain->num_clks < 0)
 918                 return dev_err_probe(domain->dev, domain->num_clks,
 919                                      "Failed to get domain's clocks\n");
 920
 921         domain->reset = devm_reset_control_array_get_optional_exclusive(domain->dev);
 922         if (IS_ERR(domain->reset))
 923                 return dev_err_probe(domain->dev, PTR_ERR(domain->reset),
 924                                      "Failed to get domain's resets\n");
 925
 926         pm_runtime_enable(domain->dev);
 927
 928         if (domain->bits.map)
 929                 regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
 930                                    domain->bits.map, domain->bits.map);
 931
 932         ret = pm_genpd_init(&domain->genpd, NULL, true);
 933         if (ret) {
 934                 dev_err(domain->dev, "Failed to init power domain\n");
 935                 goto out_domain_unmap;
 936         }
 937
 938         if (IS_ENABLED(CONFIG_LOCKDEP) &&
 939             of_property_read_bool(domain->dev->of_node, "power-domains"))
 940                 lockdep_set_subclass(&domain->genpd.mlock, 1);
 941
 942         ret = of_genpd_add_provider_simple(domain->dev->of_node,
 943                                            &domain->genpd);
 944         if (ret) {
 945                 dev_err(domain->dev, "Failed to add genpd provider\n");
 946                 goto out_genpd_remove;
 947         }
 948
 949         return 0;
 950
 951 out_genpd_remove:
 952         pm_genpd_remove(&domain->genpd);
 953 out_domain_unmap:
 954         if (domain->bits.map)
 955                 regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
 956                                    domain->bits.map, 0);
 957         pm_runtime_disable(domain->dev);
 958
 959         return ret;
 960 }
 961
 962 static int imx_pgc_domain_remove(struct platform_device *pdev)
 963 {
 964         struct imx_pgc_domain *domain = pdev->dev.platform_data;
 965
 966         of_genpd_del_provider(domain->dev->of_node);
 967         pm_genpd_remove(&domain->genpd);
 968
 969         if (domain->bits.map)
 970                 regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
 971                                    domain->bits.map, 0);
 972
 973         pm_runtime_disable(domain->dev);
 974
 975         return 0;
 976 }
 977
 978 #ifdef CONFIG_PM_SLEEP
 979 static int imx_pgc_domain_suspend(struct device *dev)
 980 {
 981         int ret;
 982
 983         /*
 984          * This may look strange, but is done so the generic PM_SLEEP code
 985          * can power down our domain and more importantly power it up again
 986          * after resume, without tripping over our usage of runtime PM to
 987          * power up/down the nested domains.
 988          */
 989         ret = pm_runtime_get_sync(dev);
 990         if (ret < 0) {
 991                 pm_runtime_put_noidle(dev);
 992                 return ret;
 993         }
 994
 995         return 0;
 996 }
 997
 998 static int imx_pgc_domain_resume(struct device *dev)
 999 {
1000         return pm_runtime_put(dev);
1001 }
1002 #endif
1003
1004 static const struct dev_pm_ops imx_pgc_domain_pm_ops = {
1005         SET_SYSTEM_SLEEP_PM_OPS(imx_pgc_domain_suspend, imx_pgc_domain_resume)
1006 };
1007
1008 static const struct platform_device_id imx_pgc_domain_id[] = {
1009         { "imx-pgc-domain", },
1010         { },
1011 };
1012
1013 static struct platform_driver imx_pgc_domain_driver = {
1014         .driver = {
1015                 .name = "imx-pgc",
1016                 .pm = &imx_pgc_domain_pm_ops,
1017         },
1018         .probe    = imx_pgc_domain_probe,
1019         .remove   = imx_pgc_domain_remove,
1020         .id_table = imx_pgc_domain_id,
1021 };
1022 builtin_platform_driver(imx_pgc_domain_driver)
1023
1024 static int imx_gpcv2_probe(struct platform_device *pdev)
1025 {
1026         const struct imx_pgc_domain_data *domain_data =
1027                         of_device_get_match_data(&pdev->dev);
1028
1029         struct regmap_config regmap_config = {
1030                 .reg_bits       = 32,
1031                 .val_bits       = 32,
1032                 .reg_stride     = 4,
1033                 .rd_table       = domain_data->reg_access_table,
1034                 .wr_table       = domain_data->reg_access_table,
1035                 .max_register   = SZ_4K,
1036         };
1037         struct device *dev = &pdev->dev;
1038         struct device_node *pgc_np, *np;
1039         struct regmap *regmap;
1040         void __iomem *base;
1041         int ret;
1042
1043         pgc_np = of_get_child_by_name(dev->of_node, "pgc");
1044         if (!pgc_np) {
1045                 dev_err(dev, "No power domains specified in DT\n");
1046                 return -EINVAL;
1047         }
1048
1049         base = devm_platform_ioremap_resource(pdev, 0);
1050         if (IS_ERR(base))
1051                 return PTR_ERR(base);
1052
1053         regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
1054         if (IS_ERR(regmap)) {
1055                 ret = PTR_ERR(regmap);
1056                 dev_err(dev, "failed to init regmap (%d)\n", ret);
1057                 return ret;
1058         }
1059
1060         for_each_child_of_node(pgc_np, np) {
1061                 struct platform_device *pd_pdev;
1062                 struct imx_pgc_domain *domain;
1063                 u32 domain_index;
1064
1065                 if (!of_device_is_available(np))
1066                         continue;
1067
1068                 ret = of_property_read_u32(np, "reg", &domain_index);
1069                 if (ret) {
1070                         dev_err(dev, "Failed to read 'reg' property\n");
1071                         of_node_put(np);
1072                         return ret;
1073                 }
1074
1075                 if (domain_index >= domain_data->domains_num) {
1076                         dev_warn(dev,
1077                                  "Domain index %d is out of bounds\n",
1078                                  domain_index);
1079                         continue;
1080                 }
1081
1082                 pd_pdev = platform_device_alloc("imx-pgc-domain",
1083                                                 domain_index);
1084                 if (!pd_pdev) {
1085                         dev_err(dev, "Failed to allocate platform device\n");
1086                         of_node_put(np);
1087                         return -ENOMEM;
1088                 }
1089
1090                 ret = platform_device_add_data(pd_pdev,
1091                                                &domain_data->domains[domain_index],
1092                                                sizeof(domain_data->domains[domain_index]));
1093                 if (ret) {
1094                         platform_device_put(pd_pdev);
1095                         of_node_put(np);
1096                         return ret;
1097                 }
1098
1099                 domain = pd_pdev->dev.platform_data;
1100                 domain->regmap = regmap;
1101                 domain->genpd.power_on  = imx_pgc_power_up;
1102                 domain->genpd.power_off = imx_pgc_power_down;
1103
1104                 pd_pdev->dev.parent = dev;
1105                 pd_pdev->dev.of_node = np;
1106
1107                 ret = platform_device_add(pd_pdev);
1108                 if (ret) {
1109                         platform_device_put(pd_pdev);
1110                         of_node_put(np);
1111                         return ret;
1112                 }
1113         }
1114
1115         return 0;
1116 }
1117
1118 static const struct of_device_id imx_gpcv2_dt_ids[] = {
1119         { .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
1120         { .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, },
1121         { .compatible = "fsl,imx8mn-gpc", .data = &imx8mn_pgc_domain_data, },
1122         { .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
1123         { }
1124 };
1125
1126 static struct platform_driver imx_gpc_driver = {
1127         .driver = {
1128                 .name = "imx-gpcv2",
1129                 .of_match_table = imx_gpcv2_dt_ids,
1130         },
1131         .probe = imx_gpcv2_probe,
1132 };
1133 builtin_platform_driver(imx_gpc_driver)