drivers/soc/fsl/qe/qe_ic.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * arch/powerpc/sysdev/qe_lib/qe_ic.c
   4  *
   5  * Copyright (C) 2006 Freescale Semiconductor, Inc.  All rights reserved.
   6  *
   7  * Author: Li Yang <leoli@freescale.com>
   8  * Based on code from Shlomi Gridish <gridish@freescale.com>
   9  *
  10  * QUICC ENGINE Interrupt Controller
  11  */
  12
  13 #include <linux/of_irq.h>
  14 #include <linux/of_address.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/reboot.h>
  19 #include <linux/slab.h>
  20 #include <linux/stddef.h>
  21 #include <linux/sched.h>
  22 #include <linux/signal.h>
  23 #include <linux/device.h>
  24 #include <linux/spinlock.h>
  25 #include <asm/irq.h>
  26 #include <asm/io.h>
  27 #include <soc/fsl/qe/qe.h>
  28 #include <soc/fsl/qe/qe_ic.h>
  29
  30 #include "qe_ic.h"
  31
  32 static DEFINE_RAW_SPINLOCK(qe_ic_lock);
  33
  34 static struct qe_ic_info qe_ic_info[] = {
  35         [1] = {
  36                .mask = 0x00008000,
  37                .mask_reg = QEIC_CIMR,
  38                .pri_code = 0,
  39                .pri_reg = QEIC_CIPWCC,
  40                },
  41         [2] = {
  42                .mask = 0x00004000,
  43                .mask_reg = QEIC_CIMR,
  44                .pri_code = 1,
  45                .pri_reg = QEIC_CIPWCC,
  46                },
  47         [3] = {
  48                .mask = 0x00002000,
  49                .mask_reg = QEIC_CIMR,
  50                .pri_code = 2,
  51                .pri_reg = QEIC_CIPWCC,
  52                },
  53         [10] = {
  54                 .mask = 0x00000040,
  55                 .mask_reg = QEIC_CIMR,
  56                 .pri_code = 1,
  57                 .pri_reg = QEIC_CIPZCC,
  58                 },
  59         [11] = {
  60                 .mask = 0x00000020,
  61                 .mask_reg = QEIC_CIMR,
  62                 .pri_code = 2,
  63                 .pri_reg = QEIC_CIPZCC,
  64                 },
  65         [12] = {
  66                 .mask = 0x00000010,
  67                 .mask_reg = QEIC_CIMR,
  68                 .pri_code = 3,
  69                 .pri_reg = QEIC_CIPZCC,
  70                 },
  71         [13] = {
  72                 .mask = 0x00000008,
  73                 .mask_reg = QEIC_CIMR,
  74                 .pri_code = 4,
  75                 .pri_reg = QEIC_CIPZCC,
  76                 },
  77         [14] = {
  78                 .mask = 0x00000004,
  79                 .mask_reg = QEIC_CIMR,
  80                 .pri_code = 5,
  81                 .pri_reg = QEIC_CIPZCC,
  82                 },
  83         [15] = {
  84                 .mask = 0x00000002,
  85                 .mask_reg = QEIC_CIMR,
  86                 .pri_code = 6,
  87                 .pri_reg = QEIC_CIPZCC,
  88                 },
  89         [20] = {
  90                 .mask = 0x10000000,
  91                 .mask_reg = QEIC_CRIMR,
  92                 .pri_code = 3,
  93                 .pri_reg = QEIC_CIPRTA,
  94                 },
  95         [25] = {
  96                 .mask = 0x00800000,
  97                 .mask_reg = QEIC_CRIMR,
  98                 .pri_code = 0,
  99                 .pri_reg = QEIC_CIPRTB,
 100                 },
 101         [26] = {
 102                 .mask = 0x00400000,
 103                 .mask_reg = QEIC_CRIMR,
 104                 .pri_code = 1,
 105                 .pri_reg = QEIC_CIPRTB,
 106                 },
 107         [27] = {
 108                 .mask = 0x00200000,
 109                 .mask_reg = QEIC_CRIMR,
 110                 .pri_code = 2,
 111                 .pri_reg = QEIC_CIPRTB,
 112                 },
 113         [28] = {
 114                 .mask = 0x00100000,
 115                 .mask_reg = QEIC_CRIMR,
 116                 .pri_code = 3,
 117                 .pri_reg = QEIC_CIPRTB,
 118                 },
 119         [32] = {
 120                 .mask = 0x80000000,
 121                 .mask_reg = QEIC_CIMR,
 122                 .pri_code = 0,
 123                 .pri_reg = QEIC_CIPXCC,
 124                 },
 125         [33] = {
 126                 .mask = 0x40000000,
 127                 .mask_reg = QEIC_CIMR,
 128                 .pri_code = 1,
 129                 .pri_reg = QEIC_CIPXCC,
 130                 },
 131         [34] = {
 132                 .mask = 0x20000000,
 133                 .mask_reg = QEIC_CIMR,
 134                 .pri_code = 2,
 135                 .pri_reg = QEIC_CIPXCC,
 136                 },
 137         [35] = {
 138                 .mask = 0x10000000,
 139                 .mask_reg = QEIC_CIMR,
 140                 .pri_code = 3,
 141                 .pri_reg = QEIC_CIPXCC,
 142                 },
 143         [36] = {
 144                 .mask = 0x08000000,
 145                 .mask_reg = QEIC_CIMR,
 146                 .pri_code = 4,
 147                 .pri_reg = QEIC_CIPXCC,
 148                 },
 149         [40] = {
 150                 .mask = 0x00800000,
 151                 .mask_reg = QEIC_CIMR,
 152                 .pri_code = 0,
 153                 .pri_reg = QEIC_CIPYCC,
 154                 },
 155         [41] = {
 156                 .mask = 0x00400000,
 157                 .mask_reg = QEIC_CIMR,
 158                 .pri_code = 1,
 159                 .pri_reg = QEIC_CIPYCC,
 160                 },
 161         [42] = {
 162                 .mask = 0x00200000,
 163                 .mask_reg = QEIC_CIMR,
 164                 .pri_code = 2,
 165                 .pri_reg = QEIC_CIPYCC,
 166                 },
 167         [43] = {
 168                 .mask = 0x00100000,
 169                 .mask_reg = QEIC_CIMR,
 170                 .pri_code = 3,
 171                 .pri_reg = QEIC_CIPYCC,
 172                 },
 173 };
 174
 175 static inline u32 qe_ic_read(__be32  __iomem *base, unsigned int reg)
 176 {
 177         return qe_ioread32be(base + (reg >> 2));
 178 }
 179
 180 static inline void qe_ic_write(__be32  __iomem *base, unsigned int reg,
 181                                u32 value)
 182 {
 183         qe_iowrite32be(value, base + (reg >> 2));
 184 }
 185
 186 static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
 187 {
 188         return irq_get_chip_data(virq);
 189 }
 190
 191 static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d)
 192 {
 193         return irq_data_get_irq_chip_data(d);
 194 }
 195
 196 static void qe_ic_unmask_irq(struct irq_data *d)
 197 {
 198         struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
 199         unsigned int src = irqd_to_hwirq(d);
 200         unsigned long flags;
 201         u32 temp;
 202
 203         raw_spin_lock_irqsave(&qe_ic_lock, flags);
 204
 205         temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
 206         qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
 207                     temp | qe_ic_info[src].mask);
 208
 209         raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
 210 }
 211
 212 static void qe_ic_mask_irq(struct irq_data *d)
 213 {
 214         struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
 215         unsigned int src = irqd_to_hwirq(d);
 216         unsigned long flags;
 217         u32 temp;
 218
 219         raw_spin_lock_irqsave(&qe_ic_lock, flags);
 220
 221         temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
 222         qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
 223                     temp & ~qe_ic_info[src].mask);
 224
 225         /* Flush the above write before enabling interrupts; otherwise,
 226          * spurious interrupts will sometimes happen.  To be 100% sure
 227          * that the write has reached the device before interrupts are
 228          * enabled, the mask register would have to be read back; however,
 229          * this is not required for correctness, only to avoid wasting
 230          * time on a large number of spurious interrupts.  In testing,
 231          * a sync reduced the observed spurious interrupts to zero.
 232          */
 233         mb();
 234
 235         raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
 236 }
 237
 238 static struct irq_chip qe_ic_irq_chip = {
 239         .name = "QEIC",
 240         .irq_unmask = qe_ic_unmask_irq,
 241         .irq_mask = qe_ic_mask_irq,
 242         .irq_mask_ack = qe_ic_mask_irq,
 243 };
 244
 245 static int qe_ic_host_match(struct irq_domain *h, struct device_node *node,
 246                             enum irq_domain_bus_token bus_token)
 247 {
 248         /* Exact match, unless qe_ic node is NULL */
 249         struct device_node *of_node = irq_domain_get_of_node(h);
 250         return of_node == NULL || of_node == node;
 251 }
 252
 253 static int qe_ic_host_map(struct irq_domain *h, unsigned int virq,
 254                           irq_hw_number_t hw)
 255 {
 256         struct qe_ic *qe_ic = h->host_data;
 257         struct irq_chip *chip;
 258
 259         if (hw >= ARRAY_SIZE(qe_ic_info)) {
 260                 pr_err("%s: Invalid hw irq number for QEIC\n", __func__);
 261                 return -EINVAL;
 262         }
 263
 264         if (qe_ic_info[hw].mask == 0) {
 265                 printk(KERN_ERR "Can't map reserved IRQ\n");
 266                 return -EINVAL;
 267         }
 268         /* Default chip */
 269         chip = &qe_ic->hc_irq;
 270
 271         irq_set_chip_data(virq, qe_ic);
 272         irq_set_status_flags(virq, IRQ_LEVEL);
 273
 274         irq_set_chip_and_handler(virq, chip, handle_level_irq);
 275
 276         return 0;
 277 }
 278
 279 static const struct irq_domain_ops qe_ic_host_ops = {
 280         .match = qe_ic_host_match,
 281         .map = qe_ic_host_map,
 282         .xlate = irq_domain_xlate_onetwocell,
 283 };
 284
 285 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
 286 unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
 287 {
 288         int irq;
 289
 290         BUG_ON(qe_ic == NULL);
 291
 292         /* get the interrupt source vector. */
 293         irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
 294
 295         if (irq == 0)
 296                 return NO_IRQ;
 297
 298         return irq_linear_revmap(qe_ic->irqhost, irq);
 299 }
 300
 301 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
 302 unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
 303 {
 304         int irq;
 305
 306         BUG_ON(qe_ic == NULL);
 307
 308         /* get the interrupt source vector. */
 309         irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
 310
 311         if (irq == 0)
 312                 return NO_IRQ;
 313
 314         return irq_linear_revmap(qe_ic->irqhost, irq);
 315 }
 316
 317 void __init qe_ic_init(struct device_node *node, unsigned int flags,
 318                        void (*low_handler)(struct irq_desc *desc),
 319                        void (*high_handler)(struct irq_desc *desc))
 320 {
 321         struct qe_ic *qe_ic;
 322         struct resource res;
 323         u32 temp = 0, ret, high_active = 0;
 324
 325         ret = of_address_to_resource(node, 0, &res);
 326         if (ret)
 327                 return;
 328
 329         qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL);
 330         if (qe_ic == NULL)
 331                 return;
 332
 333         qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS,
 334                                                &qe_ic_host_ops, qe_ic);
 335         if (qe_ic->irqhost == NULL) {
 336                 kfree(qe_ic);
 337                 return;
 338         }
 339
 340         qe_ic->regs = ioremap(res.start, resource_size(&res));
 341
 342         qe_ic->hc_irq = qe_ic_irq_chip;
 343
 344         qe_ic->virq_high = irq_of_parse_and_map(node, 0);
 345         qe_ic->virq_low = irq_of_parse_and_map(node, 1);
 346
 347         if (qe_ic->virq_low == NO_IRQ) {
 348                 printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
 349                 kfree(qe_ic);
 350                 return;
 351         }
 352
 353         /* default priority scheme is grouped. If spread mode is    */
 354         /* required, configure cicr accordingly.                    */
 355         if (flags & QE_IC_SPREADMODE_GRP_W)
 356                 temp |= CICR_GWCC;
 357         if (flags & QE_IC_SPREADMODE_GRP_X)
 358                 temp |= CICR_GXCC;
 359         if (flags & QE_IC_SPREADMODE_GRP_Y)
 360                 temp |= CICR_GYCC;
 361         if (flags & QE_IC_SPREADMODE_GRP_Z)
 362                 temp |= CICR_GZCC;
 363         if (flags & QE_IC_SPREADMODE_GRP_RISCA)
 364                 temp |= CICR_GRTA;
 365         if (flags & QE_IC_SPREADMODE_GRP_RISCB)
 366                 temp |= CICR_GRTB;
 367
 368         /* choose destination signal for highest priority interrupt */
 369         if (flags & QE_IC_HIGH_SIGNAL) {
 370                 temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
 371                 high_active = 1;
 372         }
 373
 374         qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
 375
 376         irq_set_handler_data(qe_ic->virq_low, qe_ic);
 377         irq_set_chained_handler(qe_ic->virq_low, low_handler);
 378
 379         if (qe_ic->virq_high != NO_IRQ &&
 380                         qe_ic->virq_high != qe_ic->virq_low) {
 381                 irq_set_handler_data(qe_ic->virq_high, qe_ic);
 382                 irq_set_chained_handler(qe_ic->virq_high, high_handler);
 383         }
 384 }
 385
 386 void qe_ic_set_highest_priority(unsigned int virq, int high)
 387 {
 388         struct qe_ic *qe_ic = qe_ic_from_irq(virq);
 389         unsigned int src = virq_to_hw(virq);
 390         u32 temp = 0;
 391
 392         temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
 393
 394         temp &= ~CICR_HP_MASK;
 395         temp |= src << CICR_HP_SHIFT;
 396
 397         temp &= ~CICR_HPIT_MASK;
 398         temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;
 399
 400         qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
 401 }
 402
 403 /* Set Priority level within its group, from 1 to 8 */
 404 int qe_ic_set_priority(unsigned int virq, unsigned int priority)
 405 {
 406         struct qe_ic *qe_ic = qe_ic_from_irq(virq);
 407         unsigned int src = virq_to_hw(virq);
 408         u32 temp;
 409
 410         if (priority > 8 || priority == 0)
 411                 return -EINVAL;
 412         if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
 413                       "%s: Invalid hw irq number for QEIC\n", __func__))
 414                 return -EINVAL;
 415         if (qe_ic_info[src].pri_reg == 0)
 416                 return -EINVAL;
 417
 418         temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);
 419
 420         if (priority < 4) {
 421                 temp &= ~(0x7 << (32 - priority * 3));
 422                 temp |= qe_ic_info[src].pri_code << (32 - priority * 3);
 423         } else {
 424                 temp &= ~(0x7 << (24 - priority * 3));
 425                 temp |= qe_ic_info[src].pri_code << (24 - priority * 3);
 426         }
 427
 428         qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);
 429
 430         return 0;
 431 }
 432
 433 /* Set a QE priority to use high irq, only priority 1~2 can use high irq */
 434 int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
 435 {
 436         struct qe_ic *qe_ic = qe_ic_from_irq(virq);
 437         unsigned int src = virq_to_hw(virq);
 438         u32 temp, control_reg = QEIC_CICNR, shift = 0;
 439
 440         if (priority > 2 || priority == 0)
 441                 return -EINVAL;
 442         if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
 443                       "%s: Invalid hw irq number for QEIC\n", __func__))
 444                 return -EINVAL;
 445
 446         switch (qe_ic_info[src].pri_reg) {
 447         case QEIC_CIPZCC:
 448                 shift = CICNR_ZCC1T_SHIFT;
 449                 break;
 450         case QEIC_CIPWCC:
 451                 shift = CICNR_WCC1T_SHIFT;
 452                 break;
 453         case QEIC_CIPYCC:
 454                 shift = CICNR_YCC1T_SHIFT;
 455                 break;
 456         case QEIC_CIPXCC:
 457                 shift = CICNR_XCC1T_SHIFT;
 458                 break;
 459         case QEIC_CIPRTA:
 460                 shift = CRICR_RTA1T_SHIFT;
 461                 control_reg = QEIC_CRICR;
 462                 break;
 463         case QEIC_CIPRTB:
 464                 shift = CRICR_RTB1T_SHIFT;
 465                 control_reg = QEIC_CRICR;
 466                 break;
 467         default:
 468                 return -EINVAL;
 469         }
 470
 471         shift += (2 - priority) * 2;
 472         temp = qe_ic_read(qe_ic->regs, control_reg);
 473         temp &= ~(SIGNAL_MASK << shift);
 474         temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
 475         qe_ic_write(qe_ic->regs, control_reg, temp);
 476
 477         return 0;
 478 }
 479
 480 static struct bus_type qe_ic_subsys = {
 481         .name = "qe_ic",
 482         .dev_name = "qe_ic",
 483 };
 484
 485 static struct device device_qe_ic = {
 486         .id = 0,
 487         .bus = &qe_ic_subsys,
 488 };
 489
 490 static int __init init_qe_ic_sysfs(void)
 491 {
 492         int rc;
 493
 494         printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");
 495
 496         rc = subsys_system_register(&qe_ic_subsys, NULL);
 497         if (rc) {
 498                 printk(KERN_ERR "Failed registering qe_ic sys class\n");
 499                 return -ENODEV;
 500         }
 501         rc = device_register(&device_qe_ic);
 502         if (rc) {
 503                 printk(KERN_ERR "Failed registering qe_ic sys device\n");
 504                 return -ENODEV;
 505         }
 506         return 0;
 507 }
 508
 509 subsys_initcall(init_qe_ic_sysfs);