drivers/soc/fsl/qe/qe.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. All rights reserved.
   4  *
   5  * Authors:     Shlomi Gridish <gridish@freescale.com>
   6  *              Li Yang <leoli@freescale.com>
   7  * Based on cpm2_common.c from Dan Malek (dmalek@jlc.net)
   8  *
   9  * Description:
  10  * General Purpose functions for the global management of the
  11  * QUICC Engine (QE).
  12  */
  13 #include <linux/bitmap.h>
  14 #include <linux/errno.h>
  15 #include <linux/sched.h>
  16 #include <linux/kernel.h>
  17 #include <linux/param.h>
  18 #include <linux/string.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/mm.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/delay.h>
  24 #include <linux/ioport.h>
  25 #include <linux/crc32.h>
  26 #include <linux/mod_devicetable.h>
  27 #include <linux/of_platform.h>
  28 #include <asm/irq.h>
  29 #include <asm/page.h>
  30 #include <asm/pgtable.h>
  31 #include <soc/fsl/qe/immap_qe.h>
  32 #include <soc/fsl/qe/qe.h>
  33 #include <asm/prom.h>
  34 #include <asm/rheap.h>
  35
  36 static void qe_snums_init(void);
  37 static int qe_sdma_init(void);
  38
  39 static DEFINE_SPINLOCK(qe_lock);
  40 DEFINE_SPINLOCK(cmxgcr_lock);
  41 EXPORT_SYMBOL(cmxgcr_lock);
  42
  43 /* We allocate this here because it is used almost exclusively for
  44  * the communication processor devices.
  45  */
  46 struct qe_immap __iomem *qe_immr;
  47 EXPORT_SYMBOL(qe_immr);
  48
  49 static u8 snums[QE_NUM_OF_SNUM];        /* Dynamically allocated SNUMs */
  50 static DECLARE_BITMAP(snum_state, QE_NUM_OF_SNUM);
  51 static unsigned int qe_num_of_snum;
  52
  53 static phys_addr_t qebase = -1;
  54
  55 static struct device_node *qe_get_device_node(void)
  56 {
  57         struct device_node *qe;
  58
  59         /*
  60          * Newer device trees have an "fsl,qe" compatible property for the QE
  61          * node, but we still need to support older device trees.
  62          */
  63         qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
  64         if (qe)
  65                 return qe;
  66         return of_find_node_by_type(NULL, "qe");
  67 }
  68
  69 static phys_addr_t get_qe_base(void)
  70 {
  71         struct device_node *qe;
  72         int ret;
  73         struct resource res;
  74
  75         if (qebase != -1)
  76                 return qebase;
  77
  78         qe = qe_get_device_node();
  79         if (!qe)
  80                 return qebase;
  81
  82         ret = of_address_to_resource(qe, 0, &res);
  83         if (!ret)
  84                 qebase = res.start;
  85         of_node_put(qe);
  86
  87         return qebase;
  88 }
  89
  90 void qe_reset(void)
  91 {
  92         if (qe_immr == NULL)
  93                 qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE);
  94
  95         qe_snums_init();
  96
  97         qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
  98                      QE_CR_PROTOCOL_UNSPECIFIED, 0);
  99
 100         /* Reclaim the MURAM memory for our use. */
 101         qe_muram_init();
 102
 103         if (qe_sdma_init())
 104                 panic("sdma init failed!");
 105 }
 106
 107 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
 108 {
 109         unsigned long flags;
 110         u8 mcn_shift = 0, dev_shift = 0;
 111         u32 ret;
 112
 113         spin_lock_irqsave(&qe_lock, flags);
 114         if (cmd == QE_RESET) {
 115                 qe_iowrite32be((u32)(cmd | QE_CR_FLG), &qe_immr->cp.cecr);
 116         } else {
 117                 if (cmd == QE_ASSIGN_PAGE) {
 118                         /* Here device is the SNUM, not sub-block */
 119                         dev_shift = QE_CR_SNUM_SHIFT;
 120                 } else if (cmd == QE_ASSIGN_RISC) {
 121                         /* Here device is the SNUM, and mcnProtocol is
 122                          * e_QeCmdRiscAssignment value */
 123                         dev_shift = QE_CR_SNUM_SHIFT;
 124                         mcn_shift = QE_CR_MCN_RISC_ASSIGN_SHIFT;
 125                 } else {
 126                         if (device == QE_CR_SUBBLOCK_USB)
 127                                 mcn_shift = QE_CR_MCN_USB_SHIFT;
 128                         else
 129                                 mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
 130                 }
 131
 132                 qe_iowrite32be(cmd_input, &qe_immr->cp.cecdr);
 133                 qe_iowrite32be((cmd | QE_CR_FLG | ((u32)device << dev_shift) | (u32)mcn_protocol << mcn_shift),
 134                                &qe_immr->cp.cecr);
 135         }
 136
 137         /* wait for the QE_CR_FLG to clear */
 138         ret = spin_event_timeout((qe_ioread32be(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
 139                                  100, 0);
 140         /* On timeout (e.g. failure), the expression will be false (ret == 0),
 141            otherwise it will be true (ret == 1). */
 142         spin_unlock_irqrestore(&qe_lock, flags);
 143
 144         return ret == 1;
 145 }
 146 EXPORT_SYMBOL(qe_issue_cmd);
 147
 148 /* Set a baud rate generator. This needs lots of work. There are
 149  * 16 BRGs, which can be connected to the QE channels or output
 150  * as clocks. The BRGs are in two different block of internal
 151  * memory mapped space.
 152  * The BRG clock is the QE clock divided by 2.
 153  * It was set up long ago during the initial boot phase and is
 154  * is given to us.
 155  * Baud rate clocks are zero-based in the driver code (as that maps
 156  * to port numbers). Documentation uses 1-based numbering.
 157  */
 158 static unsigned int brg_clk = 0;
 159
 160 #define CLK_GRAN        (1000)
 161 #define CLK_GRAN_LIMIT  (5)
 162
 163 unsigned int qe_get_brg_clk(void)
 164 {
 165         struct device_node *qe;
 166         int size;
 167         const u32 *prop;
 168         unsigned int mod;
 169
 170         if (brg_clk)
 171                 return brg_clk;
 172
 173         qe = qe_get_device_node();
 174         if (!qe)
 175                 return brg_clk;
 176
 177         prop = of_get_property(qe, "brg-frequency", &size);
 178         if (prop && size == sizeof(*prop))
 179                 brg_clk = *prop;
 180
 181         of_node_put(qe);
 182
 183         /* round this if near to a multiple of CLK_GRAN */
 184         mod = brg_clk % CLK_GRAN;
 185         if (mod) {
 186                 if (mod < CLK_GRAN_LIMIT)
 187                         brg_clk -= mod;
 188                 else if (mod > (CLK_GRAN - CLK_GRAN_LIMIT))
 189                         brg_clk += CLK_GRAN - mod;
 190         }
 191
 192         return brg_clk;
 193 }
 194 EXPORT_SYMBOL(qe_get_brg_clk);
 195
 196 #define PVR_VER_836x    0x8083
 197 #define PVR_VER_832x    0x8084
 198
 199 /* Program the BRG to the given sampling rate and multiplier
 200  *
 201  * @brg: the BRG, QE_BRG1 - QE_BRG16
 202  * @rate: the desired sampling rate
 203  * @multiplier: corresponds to the value programmed in GUMR_L[RDCR] or
 204  * GUMR_L[TDCR].  E.g., if this BRG is the RX clock, and GUMR_L[RDCR]=01,
 205  * then 'multiplier' should be 8.
 206  */
 207 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
 208 {
 209         u32 divisor, tempval;
 210         u32 div16 = 0;
 211
 212         if ((brg < QE_BRG1) || (brg > QE_BRG16))
 213                 return -EINVAL;
 214
 215         divisor = qe_get_brg_clk() / (rate * multiplier);
 216
 217         if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
 218                 div16 = QE_BRGC_DIV16;
 219                 divisor /= 16;
 220         }
 221
 222         /* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
 223            that the BRG divisor must be even if you're not using divide-by-16
 224            mode. */
 225         if (pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x))
 226                 if (!div16 && (divisor & 1) && (divisor > 3))
 227                         divisor++;
 228
 229         tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
 230                 QE_BRGC_ENABLE | div16;
 231
 232         qe_iowrite32be(tempval, &qe_immr->brg.brgc[brg - QE_BRG1]);
 233
 234         return 0;
 235 }
 236 EXPORT_SYMBOL(qe_setbrg);
 237
 238 /* Convert a string to a QE clock source enum
 239  *
 240  * This function takes a string, typically from a property in the device
 241  * tree, and returns the corresponding "enum qe_clock" value.
 242 */
 243 enum qe_clock qe_clock_source(const char *source)
 244 {
 245         unsigned int i;
 246
 247         if (strcasecmp(source, "none") == 0)
 248                 return QE_CLK_NONE;
 249
 250         if (strcmp(source, "tsync_pin") == 0)
 251                 return QE_TSYNC_PIN;
 252
 253         if (strcmp(source, "rsync_pin") == 0)
 254                 return QE_RSYNC_PIN;
 255
 256         if (strncasecmp(source, "brg", 3) == 0) {
 257                 i = simple_strtoul(source + 3, NULL, 10);
 258                 if ((i >= 1) && (i <= 16))
 259                         return (QE_BRG1 - 1) + i;
 260                 else
 261                         return QE_CLK_DUMMY;
 262         }
 263
 264         if (strncasecmp(source, "clk", 3) == 0) {
 265                 i = simple_strtoul(source + 3, NULL, 10);
 266                 if ((i >= 1) && (i <= 24))
 267                         return (QE_CLK1 - 1) + i;
 268                 else
 269                         return QE_CLK_DUMMY;
 270         }
 271
 272         return QE_CLK_DUMMY;
 273 }
 274 EXPORT_SYMBOL(qe_clock_source);
 275
 276 /* Initialize SNUMs (thread serial numbers) according to
 277  * QE Module Control chapter, SNUM table
 278  */
 279 static void qe_snums_init(void)
 280 {
 281         static const u8 snum_init_76[] = {
 282                 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
 283                 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
 284                 0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
 285                 0xD8, 0xD9, 0xE8, 0xE9, 0x44, 0x45, 0x4C, 0x4D,
 286                 0x54, 0x55, 0x5C, 0x5D, 0x64, 0x65, 0x6C, 0x6D,
 287                 0x74, 0x75, 0x7C, 0x7D, 0x84, 0x85, 0x8C, 0x8D,
 288                 0x94, 0x95, 0x9C, 0x9D, 0xA4, 0xA5, 0xAC, 0xAD,
 289                 0xB4, 0xB5, 0xBC, 0xBD, 0xC4, 0xC5, 0xCC, 0xCD,
 290                 0xD4, 0xD5, 0xDC, 0xDD, 0xE4, 0xE5, 0xEC, 0xED,
 291                 0xF4, 0xF5, 0xFC, 0xFD,
 292         };
 293         static const u8 snum_init_46[] = {
 294                 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
 295                 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
 296                 0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
 297                 0xD8, 0xD9, 0xE8, 0xE9, 0x08, 0x09, 0x18, 0x19,
 298                 0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59,
 299                 0x68, 0x69, 0x78, 0x79, 0x80, 0x81,
 300         };
 301         struct device_node *qe;
 302         const u8 *snum_init;
 303         int i;
 304
 305         bitmap_zero(snum_state, QE_NUM_OF_SNUM);
 306         qe_num_of_snum = 28; /* The default number of snum for threads is 28 */
 307         qe = qe_get_device_node();
 308         if (qe) {
 309                 i = of_property_read_variable_u8_array(qe, "fsl,qe-snums",
 310                                                        snums, 1, QE_NUM_OF_SNUM);
 311                 if (i > 0) {
 312                         of_node_put(qe);
 313                         qe_num_of_snum = i;
 314                         return;
 315                 }
 316                 /*
 317                  * Fall back to legacy binding of using the value of
 318                  * fsl,qe-num-snums to choose one of the static arrays
 319                  * above.
 320                  */
 321                 of_property_read_u32(qe, "fsl,qe-num-snums", &qe_num_of_snum);
 322                 of_node_put(qe);
 323         }
 324
 325         if (qe_num_of_snum == 76) {
 326                 snum_init = snum_init_76;
 327         } else if (qe_num_of_snum == 28 || qe_num_of_snum == 46) {
 328                 snum_init = snum_init_46;
 329         } else {
 330                 pr_err("QE: unsupported value of fsl,qe-num-snums: %u\n", qe_num_of_snum);
 331                 return;
 332         }
 333         memcpy(snums, snum_init, qe_num_of_snum);
 334 }
 335
 336 int qe_get_snum(void)
 337 {
 338         unsigned long flags;
 339         int snum = -EBUSY;
 340         int i;
 341
 342         spin_lock_irqsave(&qe_lock, flags);
 343         i = find_first_zero_bit(snum_state, qe_num_of_snum);
 344         if (i < qe_num_of_snum) {
 345                 set_bit(i, snum_state);
 346                 snum = snums[i];
 347         }
 348         spin_unlock_irqrestore(&qe_lock, flags);
 349
 350         return snum;
 351 }
 352 EXPORT_SYMBOL(qe_get_snum);
 353
 354 void qe_put_snum(u8 snum)
 355 {
 356         const u8 *p = memchr(snums, snum, qe_num_of_snum);
 357
 358         if (p)
 359                 clear_bit(p - snums, snum_state);
 360 }
 361 EXPORT_SYMBOL(qe_put_snum);
 362
 363 static int qe_sdma_init(void)
 364 {
 365         struct sdma __iomem *sdma = &qe_immr->sdma;
 366         static unsigned long sdma_buf_offset = (unsigned long)-ENOMEM;
 367
 368         if (!sdma)
 369                 return -ENODEV;
 370
 371         /* allocate 2 internal temporary buffers (512 bytes size each) for
 372          * the SDMA */
 373         if (IS_ERR_VALUE(sdma_buf_offset)) {
 374                 sdma_buf_offset = qe_muram_alloc(512 * 2, 4096);
 375                 if (IS_ERR_VALUE(sdma_buf_offset))
 376                         return -ENOMEM;
 377         }
 378
 379         qe_iowrite32be((u32)sdma_buf_offset & QE_SDEBCR_BA_MASK,
 380                        &sdma->sdebcr);
 381         qe_iowrite32be((QE_SDMR_GLB_1_MSK | (0x1 << QE_SDMR_CEN_SHIFT)),
 382                        &sdma->sdmr);
 383
 384         return 0;
 385 }
 386
 387 /* The maximum number of RISCs we support */
 388 #define MAX_QE_RISC     4
 389
 390 /* Firmware information stored here for qe_get_firmware_info() */
 391 static struct qe_firmware_info qe_firmware_info;
 392
 393 /*
 394  * Set to 1 if QE firmware has been uploaded, and therefore
 395  * qe_firmware_info contains valid data.
 396  */
 397 static int qe_firmware_uploaded;
 398
 399 /*
 400  * Upload a QE microcode
 401  *
 402  * This function is a worker function for qe_upload_firmware().  It does
 403  * the actual uploading of the microcode.
 404  */
 405 static void qe_upload_microcode(const void *base,
 406         const struct qe_microcode *ucode)
 407 {
 408         const __be32 *code = base + be32_to_cpu(ucode->code_offset);
 409         unsigned int i;
 410
 411         if (ucode->major || ucode->minor || ucode->revision)
 412                 printk(KERN_INFO "qe-firmware: "
 413                         "uploading microcode '%s' version %u.%u.%u\n",
 414                         ucode->id, ucode->major, ucode->minor, ucode->revision);
 415         else
 416                 printk(KERN_INFO "qe-firmware: "
 417                         "uploading microcode '%s'\n", ucode->id);
 418
 419         /* Use auto-increment */
 420         qe_iowrite32be(be32_to_cpu(ucode->iram_offset) | QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR,
 421                        &qe_immr->iram.iadd);
 422
 423         for (i = 0; i < be32_to_cpu(ucode->count); i++)
 424                 qe_iowrite32be(be32_to_cpu(code[i]), &qe_immr->iram.idata);
 425
 426         /* Set I-RAM Ready Register */
 427         qe_iowrite32be(be32_to_cpu(QE_IRAM_READY), &qe_immr->iram.iready);
 428 }
 429
 430 /*
 431  * Upload a microcode to the I-RAM at a specific address.
 432  *
 433  * See Documentation/powerpc/qe_firmware.rst for information on QE microcode
 434  * uploading.
 435  *
 436  * Currently, only version 1 is supported, so the 'version' field must be
 437  * set to 1.
 438  *
 439  * The SOC model and revision are not validated, they are only displayed for
 440  * informational purposes.
 441  *
 442  * 'calc_size' is the calculated size, in bytes, of the firmware structure and
 443  * all of the microcode structures, minus the CRC.
 444  *
 445  * 'length' is the size that the structure says it is, including the CRC.
 446  */
 447 int qe_upload_firmware(const struct qe_firmware *firmware)
 448 {
 449         unsigned int i;
 450         unsigned int j;
 451         u32 crc;
 452         size_t calc_size = sizeof(struct qe_firmware);
 453         size_t length;
 454         const struct qe_header *hdr;
 455
 456         if (!firmware) {
 457                 printk(KERN_ERR "qe-firmware: invalid pointer\n");
 458                 return -EINVAL;
 459         }
 460
 461         hdr = &firmware->header;
 462         length = be32_to_cpu(hdr->length);
 463
 464         /* Check the magic */
 465         if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
 466             (hdr->magic[2] != 'F')) {
 467                 printk(KERN_ERR "qe-firmware: not a microcode\n");
 468                 return -EPERM;
 469         }
 470
 471         /* Check the version */
 472         if (hdr->version != 1) {
 473                 printk(KERN_ERR "qe-firmware: unsupported version\n");
 474                 return -EPERM;
 475         }
 476
 477         /* Validate some of the fields */
 478         if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
 479                 printk(KERN_ERR "qe-firmware: invalid data\n");
 480                 return -EINVAL;
 481         }
 482
 483         /* Validate the length and check if there's a CRC */
 484         calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
 485
 486         for (i = 0; i < firmware->count; i++)
 487                 /*
 488                  * For situations where the second RISC uses the same microcode
 489                  * as the first, the 'code_offset' and 'count' fields will be
 490                  * zero, so it's okay to add those.
 491                  */
 492                 calc_size += sizeof(__be32) *
 493                         be32_to_cpu(firmware->microcode[i].count);
 494
 495         /* Validate the length */
 496         if (length != calc_size + sizeof(__be32)) {
 497                 printk(KERN_ERR "qe-firmware: invalid length\n");
 498                 return -EPERM;
 499         }
 500
 501         /* Validate the CRC */
 502         crc = be32_to_cpu(*(__be32 *)((void *)firmware + calc_size));
 503         if (crc != crc32(0, firmware, calc_size)) {
 504                 printk(KERN_ERR "qe-firmware: firmware CRC is invalid\n");
 505                 return -EIO;
 506         }
 507
 508         /*
 509          * If the microcode calls for it, split the I-RAM.
 510          */
 511         if (!firmware->split)
 512                 qe_setbits_be16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
 513
 514         if (firmware->soc.model)
 515                 printk(KERN_INFO
 516                         "qe-firmware: firmware '%s' for %u V%u.%u\n",
 517                         firmware->id, be16_to_cpu(firmware->soc.model),
 518                         firmware->soc.major, firmware->soc.minor);
 519         else
 520                 printk(KERN_INFO "qe-firmware: firmware '%s'\n",
 521                         firmware->id);
 522
 523         /*
 524          * The QE only supports one microcode per RISC, so clear out all the
 525          * saved microcode information and put in the new.
 526          */
 527         memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
 528         strlcpy(qe_firmware_info.id, firmware->id, sizeof(qe_firmware_info.id));
 529         qe_firmware_info.extended_modes = firmware->extended_modes;
 530         memcpy(qe_firmware_info.vtraps, firmware->vtraps,
 531                 sizeof(firmware->vtraps));
 532
 533         /* Loop through each microcode. */
 534         for (i = 0; i < firmware->count; i++) {
 535                 const struct qe_microcode *ucode = &firmware->microcode[i];
 536
 537                 /* Upload a microcode if it's present */
 538                 if (ucode->code_offset)
 539                         qe_upload_microcode(firmware, ucode);
 540
 541                 /* Program the traps for this processor */
 542                 for (j = 0; j < 16; j++) {
 543                         u32 trap = be32_to_cpu(ucode->traps[j]);
 544
 545                         if (trap)
 546                                 qe_iowrite32be(trap,
 547                                                &qe_immr->rsp[i].tibcr[j]);
 548                 }
 549
 550                 /* Enable traps */
 551                 qe_iowrite32be(be32_to_cpu(ucode->eccr),
 552                                &qe_immr->rsp[i].eccr);
 553         }
 554
 555         qe_firmware_uploaded = 1;
 556
 557         return 0;
 558 }
 559 EXPORT_SYMBOL(qe_upload_firmware);
 560
 561 /*
 562  * Get info on the currently-loaded firmware
 563  *
 564  * This function also checks the device tree to see if the boot loader has
 565  * uploaded a firmware already.
 566  */
 567 struct qe_firmware_info *qe_get_firmware_info(void)
 568 {
 569         static int initialized;
 570         struct property *prop;
 571         struct device_node *qe;
 572         struct device_node *fw = NULL;
 573         const char *sprop;
 574         unsigned int i;
 575
 576         /*
 577          * If we haven't checked yet, and a driver hasn't uploaded a firmware
 578          * yet, then check the device tree for information.
 579          */
 580         if (qe_firmware_uploaded)
 581                 return &qe_firmware_info;
 582
 583         if (initialized)
 584                 return NULL;
 585
 586         initialized = 1;
 587
 588         qe = qe_get_device_node();
 589         if (!qe)
 590                 return NULL;
 591
 592         /* Find the 'firmware' child node */
 593         fw = of_get_child_by_name(qe, "firmware");
 594         of_node_put(qe);
 595
 596         /* Did we find the 'firmware' node? */
 597         if (!fw)
 598                 return NULL;
 599
 600         qe_firmware_uploaded = 1;
 601
 602         /* Copy the data into qe_firmware_info*/
 603         sprop = of_get_property(fw, "id", NULL);
 604         if (sprop)
 605                 strlcpy(qe_firmware_info.id, sprop,
 606                         sizeof(qe_firmware_info.id));
 607
 608         prop = of_find_property(fw, "extended-modes", NULL);
 609         if (prop && (prop->length == sizeof(u64))) {
 610                 const u64 *iprop = prop->value;
 611
 612                 qe_firmware_info.extended_modes = *iprop;
 613         }
 614
 615         prop = of_find_property(fw, "virtual-traps", NULL);
 616         if (prop && (prop->length == 32)) {
 617                 const u32 *iprop = prop->value;
 618
 619                 for (i = 0; i < ARRAY_SIZE(qe_firmware_info.vtraps); i++)
 620                         qe_firmware_info.vtraps[i] = iprop[i];
 621         }
 622
 623         of_node_put(fw);
 624
 625         return &qe_firmware_info;
 626 }
 627 EXPORT_SYMBOL(qe_get_firmware_info);
 628
 629 unsigned int qe_get_num_of_risc(void)
 630 {
 631         struct device_node *qe;
 632         int size;
 633         unsigned int num_of_risc = 0;
 634         const u32 *prop;
 635
 636         qe = qe_get_device_node();
 637         if (!qe)
 638                 return num_of_risc;
 639
 640         prop = of_get_property(qe, "fsl,qe-num-riscs", &size);
 641         if (prop && size == sizeof(*prop))
 642                 num_of_risc = *prop;
 643
 644         of_node_put(qe);
 645
 646         return num_of_risc;
 647 }
 648 EXPORT_SYMBOL(qe_get_num_of_risc);
 649
 650 unsigned int qe_get_num_of_snums(void)
 651 {
 652         return qe_num_of_snum;
 653 }
 654 EXPORT_SYMBOL(qe_get_num_of_snums);
 655
 656 static int __init qe_init(void)
 657 {
 658         struct device_node *np;
 659
 660         np = of_find_compatible_node(NULL, NULL, "fsl,qe");
 661         if (!np)
 662                 return -ENODEV;
 663         qe_reset();
 664         of_node_put(np);
 665         return 0;
 666 }
 667 subsys_initcall(qe_init);
 668
 669 #if defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx)
 670 static int qe_resume(struct platform_device *ofdev)
 671 {
 672         if (!qe_alive_during_sleep())
 673                 qe_reset();
 674         return 0;
 675 }
 676
 677 static int qe_probe(struct platform_device *ofdev)
 678 {
 679         return 0;
 680 }
 681
 682 static const struct of_device_id qe_ids[] = {
 683         { .compatible = "fsl,qe", },
 684         { },
 685 };
 686
 687 static struct platform_driver qe_driver = {
 688         .driver = {
 689                 .name = "fsl-qe",
 690                 .of_match_table = qe_ids,
 691         },
 692         .probe = qe_probe,
 693         .resume = qe_resume,
 694 };
 695
 696 builtin_platform_driver(qe_driver);
 697 #endif /* defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx) */