2 * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. All rights reserved.
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 * Based on cpm2_common.c from Dan Malek (dmalek@jlc.net)
9 * General Purpose functions for the global management of the
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
17 #include <linux/bitmap.h>
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
21 #include <linux/param.h>
22 #include <linux/string.h>
23 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/module.h>
27 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/crc32.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/of_platform.h>
34 #include <asm/pgtable.h>
35 #include <soc/fsl/qe/immap_qe.h>
36 #include <soc/fsl/qe/qe.h>
38 #include <asm/rheap.h>
40 static void qe_snums_init(void);
41 static int qe_sdma_init(void);
43 static DEFINE_SPINLOCK(qe_lock);
44 DEFINE_SPINLOCK(cmxgcr_lock);
45 EXPORT_SYMBOL(cmxgcr_lock);
47 /* We allocate this here because it is used almost exclusively for
48 * the communication processor devices.
50 struct qe_immap __iomem *qe_immr;
51 EXPORT_SYMBOL(qe_immr);
53 static u8 snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */
54 static DECLARE_BITMAP(snum_state, QE_NUM_OF_SNUM);
55 static unsigned int qe_num_of_snum;
57 static phys_addr_t qebase = -1;
59 static struct device_node *qe_get_device_node(void)
61 struct device_node *qe;
64 * Newer device trees have an "fsl,qe" compatible property for the QE
65 * node, but we still need to support older device trees.
67 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
70 return of_find_node_by_type(NULL, "qe");
73 static phys_addr_t get_qe_base(void)
75 struct device_node *qe;
82 qe = qe_get_device_node();
86 ret = of_address_to_resource(qe, 0, &res);
97 qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE);
101 qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
102 QE_CR_PROTOCOL_UNSPECIFIED, 0);
104 /* Reclaim the MURAM memory for our use. */
108 panic("sdma init failed!");
111 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
114 u8 mcn_shift = 0, dev_shift = 0;
117 spin_lock_irqsave(&qe_lock, flags);
118 if (cmd == QE_RESET) {
119 out_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));
121 if (cmd == QE_ASSIGN_PAGE) {
122 /* Here device is the SNUM, not sub-block */
123 dev_shift = QE_CR_SNUM_SHIFT;
124 } else if (cmd == QE_ASSIGN_RISC) {
125 /* Here device is the SNUM, and mcnProtocol is
126 * e_QeCmdRiscAssignment value */
127 dev_shift = QE_CR_SNUM_SHIFT;
128 mcn_shift = QE_CR_MCN_RISC_ASSIGN_SHIFT;
130 if (device == QE_CR_SUBBLOCK_USB)
131 mcn_shift = QE_CR_MCN_USB_SHIFT;
133 mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
136 out_be32(&qe_immr->cp.cecdr, cmd_input);
137 out_be32(&qe_immr->cp.cecr,
138 (cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)
139 mcn_protocol << mcn_shift));
142 /* wait for the QE_CR_FLG to clear */
143 ret = spin_event_timeout((in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
145 /* On timeout (e.g. failure), the expression will be false (ret == 0),
146 otherwise it will be true (ret == 1). */
147 spin_unlock_irqrestore(&qe_lock, flags);
151 EXPORT_SYMBOL(qe_issue_cmd);
153 /* Set a baud rate generator. This needs lots of work. There are
154 * 16 BRGs, which can be connected to the QE channels or output
155 * as clocks. The BRGs are in two different block of internal
156 * memory mapped space.
157 * The BRG clock is the QE clock divided by 2.
158 * It was set up long ago during the initial boot phase and is
160 * Baud rate clocks are zero-based in the driver code (as that maps
161 * to port numbers). Documentation uses 1-based numbering.
163 static unsigned int brg_clk = 0;
165 #define CLK_GRAN (1000)
166 #define CLK_GRAN_LIMIT (5)
168 unsigned int qe_get_brg_clk(void)
170 struct device_node *qe;
178 qe = qe_get_device_node();
182 prop = of_get_property(qe, "brg-frequency", &size);
183 if (prop && size == sizeof(*prop))
188 /* round this if near to a multiple of CLK_GRAN */
189 mod = brg_clk % CLK_GRAN;
191 if (mod < CLK_GRAN_LIMIT)
193 else if (mod > (CLK_GRAN - CLK_GRAN_LIMIT))
194 brg_clk += CLK_GRAN - mod;
199 EXPORT_SYMBOL(qe_get_brg_clk);
201 #define PVR_VER_836x 0x8083
202 #define PVR_VER_832x 0x8084
204 /* Program the BRG to the given sampling rate and multiplier
206 * @brg: the BRG, QE_BRG1 - QE_BRG16
207 * @rate: the desired sampling rate
208 * @multiplier: corresponds to the value programmed in GUMR_L[RDCR] or
209 * GUMR_L[TDCR]. E.g., if this BRG is the RX clock, and GUMR_L[RDCR]=01,
210 * then 'multiplier' should be 8.
212 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
214 u32 divisor, tempval;
217 if ((brg < QE_BRG1) || (brg > QE_BRG16))
220 divisor = qe_get_brg_clk() / (rate * multiplier);
222 if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
223 div16 = QE_BRGC_DIV16;
227 /* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
228 that the BRG divisor must be even if you're not using divide-by-16
230 if (pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x))
231 if (!div16 && (divisor & 1) && (divisor > 3))
234 tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
235 QE_BRGC_ENABLE | div16;
237 out_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval);
241 EXPORT_SYMBOL(qe_setbrg);
243 /* Convert a string to a QE clock source enum
245 * This function takes a string, typically from a property in the device
246 * tree, and returns the corresponding "enum qe_clock" value.
248 enum qe_clock qe_clock_source(const char *source)
252 if (strcasecmp(source, "none") == 0)
255 if (strcmp(source, "tsync_pin") == 0)
258 if (strcmp(source, "rsync_pin") == 0)
261 if (strncasecmp(source, "brg", 3) == 0) {
262 i = simple_strtoul(source + 3, NULL, 10);
263 if ((i >= 1) && (i <= 16))
264 return (QE_BRG1 - 1) + i;
269 if (strncasecmp(source, "clk", 3) == 0) {
270 i = simple_strtoul(source + 3, NULL, 10);
271 if ((i >= 1) && (i <= 24))
272 return (QE_CLK1 - 1) + i;
279 EXPORT_SYMBOL(qe_clock_source);
281 /* Initialize SNUMs (thread serial numbers) according to
282 * QE Module Control chapter, SNUM table
284 static void qe_snums_init(void)
286 static const u8 snum_init_76[] = {
287 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
288 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
289 0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
290 0xD8, 0xD9, 0xE8, 0xE9, 0x44, 0x45, 0x4C, 0x4D,
291 0x54, 0x55, 0x5C, 0x5D, 0x64, 0x65, 0x6C, 0x6D,
292 0x74, 0x75, 0x7C, 0x7D, 0x84, 0x85, 0x8C, 0x8D,
293 0x94, 0x95, 0x9C, 0x9D, 0xA4, 0xA5, 0xAC, 0xAD,
294 0xB4, 0xB5, 0xBC, 0xBD, 0xC4, 0xC5, 0xCC, 0xCD,
295 0xD4, 0xD5, 0xDC, 0xDD, 0xE4, 0xE5, 0xEC, 0xED,
296 0xF4, 0xF5, 0xFC, 0xFD,
298 static const u8 snum_init_46[] = {
299 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
300 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
301 0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
302 0xD8, 0xD9, 0xE8, 0xE9, 0x08, 0x09, 0x18, 0x19,
303 0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59,
304 0x68, 0x69, 0x78, 0x79, 0x80, 0x81,
306 struct device_node *qe;
310 bitmap_zero(snum_state, QE_NUM_OF_SNUM);
311 qe = qe_get_device_node();
313 i = of_property_read_variable_u8_array(qe, "fsl,qe-snums",
314 snums, 1, QE_NUM_OF_SNUM);
322 qe_num_of_snum = qe_get_num_of_snums();
324 if (qe_num_of_snum == 76)
325 snum_init = snum_init_76;
327 snum_init = snum_init_46;
329 memcpy(snums, snum_init, qe_num_of_snum);
332 int qe_get_snum(void)
338 spin_lock_irqsave(&qe_lock, flags);
339 i = find_first_zero_bit(snum_state, qe_num_of_snum);
340 if (i < qe_num_of_snum) {
341 set_bit(i, snum_state);
344 spin_unlock_irqrestore(&qe_lock, flags);
348 EXPORT_SYMBOL(qe_get_snum);
350 void qe_put_snum(u8 snum)
352 const u8 *p = memchr(snums, snum, qe_num_of_snum);
355 clear_bit(p - snums, snum_state);
357 EXPORT_SYMBOL(qe_put_snum);
359 static int qe_sdma_init(void)
361 struct sdma __iomem *sdma = &qe_immr->sdma;
362 static unsigned long sdma_buf_offset = (unsigned long)-ENOMEM;
367 /* allocate 2 internal temporary buffers (512 bytes size each) for
369 if (IS_ERR_VALUE(sdma_buf_offset)) {
370 sdma_buf_offset = qe_muram_alloc(512 * 2, 4096);
371 if (IS_ERR_VALUE(sdma_buf_offset))
375 out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
376 out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
377 (0x1 << QE_SDMR_CEN_SHIFT)));
382 /* The maximum number of RISCs we support */
383 #define MAX_QE_RISC 4
385 /* Firmware information stored here for qe_get_firmware_info() */
386 static struct qe_firmware_info qe_firmware_info;
389 * Set to 1 if QE firmware has been uploaded, and therefore
390 * qe_firmware_info contains valid data.
392 static int qe_firmware_uploaded;
395 * Upload a QE microcode
397 * This function is a worker function for qe_upload_firmware(). It does
398 * the actual uploading of the microcode.
400 static void qe_upload_microcode(const void *base,
401 const struct qe_microcode *ucode)
403 const __be32 *code = base + be32_to_cpu(ucode->code_offset);
406 if (ucode->major || ucode->minor || ucode->revision)
407 printk(KERN_INFO "qe-firmware: "
408 "uploading microcode '%s' version %u.%u.%u\n",
409 ucode->id, ucode->major, ucode->minor, ucode->revision);
411 printk(KERN_INFO "qe-firmware: "
412 "uploading microcode '%s'\n", ucode->id);
414 /* Use auto-increment */
415 out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
416 QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
418 for (i = 0; i < be32_to_cpu(ucode->count); i++)
419 out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
421 /* Set I-RAM Ready Register */
422 out_be32(&qe_immr->iram.iready, be32_to_cpu(QE_IRAM_READY));
426 * Upload a microcode to the I-RAM at a specific address.
428 * See Documentation/powerpc/qe_firmware.txt for information on QE microcode
431 * Currently, only version 1 is supported, so the 'version' field must be
434 * The SOC model and revision are not validated, they are only displayed for
435 * informational purposes.
437 * 'calc_size' is the calculated size, in bytes, of the firmware structure and
438 * all of the microcode structures, minus the CRC.
440 * 'length' is the size that the structure says it is, including the CRC.
442 int qe_upload_firmware(const struct qe_firmware *firmware)
447 size_t calc_size = sizeof(struct qe_firmware);
449 const struct qe_header *hdr;
452 printk(KERN_ERR "qe-firmware: invalid pointer\n");
456 hdr = &firmware->header;
457 length = be32_to_cpu(hdr->length);
459 /* Check the magic */
460 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
461 (hdr->magic[2] != 'F')) {
462 printk(KERN_ERR "qe-firmware: not a microcode\n");
466 /* Check the version */
467 if (hdr->version != 1) {
468 printk(KERN_ERR "qe-firmware: unsupported version\n");
472 /* Validate some of the fields */
473 if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
474 printk(KERN_ERR "qe-firmware: invalid data\n");
478 /* Validate the length and check if there's a CRC */
479 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
481 for (i = 0; i < firmware->count; i++)
483 * For situations where the second RISC uses the same microcode
484 * as the first, the 'code_offset' and 'count' fields will be
485 * zero, so it's okay to add those.
487 calc_size += sizeof(__be32) *
488 be32_to_cpu(firmware->microcode[i].count);
490 /* Validate the length */
491 if (length != calc_size + sizeof(__be32)) {
492 printk(KERN_ERR "qe-firmware: invalid length\n");
496 /* Validate the CRC */
497 crc = be32_to_cpu(*(__be32 *)((void *)firmware + calc_size));
498 if (crc != crc32(0, firmware, calc_size)) {
499 printk(KERN_ERR "qe-firmware: firmware CRC is invalid\n");
504 * If the microcode calls for it, split the I-RAM.
506 if (!firmware->split)
507 setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
509 if (firmware->soc.model)
511 "qe-firmware: firmware '%s' for %u V%u.%u\n",
512 firmware->id, be16_to_cpu(firmware->soc.model),
513 firmware->soc.major, firmware->soc.minor);
515 printk(KERN_INFO "qe-firmware: firmware '%s'\n",
519 * The QE only supports one microcode per RISC, so clear out all the
520 * saved microcode information and put in the new.
522 memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
523 strlcpy(qe_firmware_info.id, firmware->id, sizeof(qe_firmware_info.id));
524 qe_firmware_info.extended_modes = firmware->extended_modes;
525 memcpy(qe_firmware_info.vtraps, firmware->vtraps,
526 sizeof(firmware->vtraps));
528 /* Loop through each microcode. */
529 for (i = 0; i < firmware->count; i++) {
530 const struct qe_microcode *ucode = &firmware->microcode[i];
532 /* Upload a microcode if it's present */
533 if (ucode->code_offset)
534 qe_upload_microcode(firmware, ucode);
536 /* Program the traps for this processor */
537 for (j = 0; j < 16; j++) {
538 u32 trap = be32_to_cpu(ucode->traps[j]);
541 out_be32(&qe_immr->rsp[i].tibcr[j], trap);
545 out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
548 qe_firmware_uploaded = 1;
552 EXPORT_SYMBOL(qe_upload_firmware);
555 * Get info on the currently-loaded firmware
557 * This function also checks the device tree to see if the boot loader has
558 * uploaded a firmware already.
560 struct qe_firmware_info *qe_get_firmware_info(void)
562 static int initialized;
563 struct property *prop;
564 struct device_node *qe;
565 struct device_node *fw = NULL;
570 * If we haven't checked yet, and a driver hasn't uploaded a firmware
571 * yet, then check the device tree for information.
573 if (qe_firmware_uploaded)
574 return &qe_firmware_info;
581 qe = qe_get_device_node();
585 /* Find the 'firmware' child node */
586 fw = of_get_child_by_name(qe, "firmware");
589 /* Did we find the 'firmware' node? */
593 qe_firmware_uploaded = 1;
595 /* Copy the data into qe_firmware_info*/
596 sprop = of_get_property(fw, "id", NULL);
598 strlcpy(qe_firmware_info.id, sprop,
599 sizeof(qe_firmware_info.id));
601 prop = of_find_property(fw, "extended-modes", NULL);
602 if (prop && (prop->length == sizeof(u64))) {
603 const u64 *iprop = prop->value;
605 qe_firmware_info.extended_modes = *iprop;
608 prop = of_find_property(fw, "virtual-traps", NULL);
609 if (prop && (prop->length == 32)) {
610 const u32 *iprop = prop->value;
612 for (i = 0; i < ARRAY_SIZE(qe_firmware_info.vtraps); i++)
613 qe_firmware_info.vtraps[i] = iprop[i];
618 return &qe_firmware_info;
620 EXPORT_SYMBOL(qe_get_firmware_info);
622 unsigned int qe_get_num_of_risc(void)
624 struct device_node *qe;
626 unsigned int num_of_risc = 0;
629 qe = qe_get_device_node();
633 prop = of_get_property(qe, "fsl,qe-num-riscs", &size);
634 if (prop && size == sizeof(*prop))
641 EXPORT_SYMBOL(qe_get_num_of_risc);
643 unsigned int qe_get_num_of_snums(void)
645 struct device_node *qe;
647 unsigned int num_of_snums;
650 num_of_snums = 28; /* The default number of snum for threads is 28 */
651 qe = qe_get_device_node();
655 prop = of_get_property(qe, "fsl,qe-num-snums", &size);
656 if (prop && size == sizeof(*prop)) {
657 num_of_snums = *prop;
658 if ((num_of_snums < 28) || (num_of_snums > QE_NUM_OF_SNUM)) {
659 /* No QE ever has fewer than 28 SNUMs */
660 pr_err("QE: number of snum is invalid\n");
670 EXPORT_SYMBOL(qe_get_num_of_snums);
672 static int __init qe_init(void)
674 struct device_node *np;
676 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
683 subsys_initcall(qe_init);
685 #if defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx)
686 static int qe_resume(struct platform_device *ofdev)
688 if (!qe_alive_during_sleep())
693 static int qe_probe(struct platform_device *ofdev)
698 static const struct of_device_id qe_ids[] = {
699 { .compatible = "fsl,qe", },
703 static struct platform_driver qe_driver = {
706 .of_match_table = qe_ids,
712 builtin_platform_driver(qe_driver);
713 #endif /* defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx) */