drivers/soc/fsl/qbman/qman.c

   1 /* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
   2  *
   3  * Redistribution and use in source and binary forms, with or without
   4  * modification, are permitted provided that the following conditions are met:
   5  *     * Redistributions of source code must retain the above copyright
   6  *       notice, this list of conditions and the following disclaimer.
   7  *     * Redistributions in binary form must reproduce the above copyright
   8  *       notice, this list of conditions and the following disclaimer in the
   9  *       documentation and/or other materials provided with the distribution.
  10  *     * Neither the name of Freescale Semiconductor nor the
  11  *       names of its contributors may be used to endorse or promote products
  12  *       derived from this software without specific prior written permission.
  13  *
  14  * ALTERNATIVELY, this software may be distributed under the terms of the
  15  * GNU General Public License ("GPL") as published by the Free Software
  16  * Foundation, either version 2 of that License or (at your option) any
  17  * later version.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  20  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  21  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  22  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  23  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  25  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  26  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 #include "qman_priv.h"
  32
  33 #define DQRR_MAXFILL    15
  34 #define EQCR_ITHRESH    4       /* if EQCR congests, interrupt threshold */
  35 #define IRQNAME         "QMan portal %d"
  36 #define MAX_IRQNAME     16      /* big enough for "QMan portal %d" */
  37 #define QMAN_POLL_LIMIT 32
  38 #define QMAN_PIRQ_DQRR_ITHRESH 12
  39 #define QMAN_DQRR_IT_MAX 15
  40 #define QMAN_ITP_MAX 0xFFF
  41 #define QMAN_PIRQ_MR_ITHRESH 4
  42 #define QMAN_PIRQ_IPERIOD 100
  43
  44 /* Portal register assists */
  45
  46 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
  47 /* Cache-inhibited register offsets */
  48 #define QM_REG_EQCR_PI_CINH     0x3000
  49 #define QM_REG_EQCR_CI_CINH     0x3040
  50 #define QM_REG_EQCR_ITR         0x3080
  51 #define QM_REG_DQRR_PI_CINH     0x3100
  52 #define QM_REG_DQRR_CI_CINH     0x3140
  53 #define QM_REG_DQRR_ITR         0x3180
  54 #define QM_REG_DQRR_DCAP        0x31C0
  55 #define QM_REG_DQRR_SDQCR       0x3200
  56 #define QM_REG_DQRR_VDQCR       0x3240
  57 #define QM_REG_DQRR_PDQCR       0x3280
  58 #define QM_REG_MR_PI_CINH       0x3300
  59 #define QM_REG_MR_CI_CINH       0x3340
  60 #define QM_REG_MR_ITR           0x3380
  61 #define QM_REG_CFG              0x3500
  62 #define QM_REG_ISR              0x3600
  63 #define QM_REG_IER              0x3640
  64 #define QM_REG_ISDR             0x3680
  65 #define QM_REG_IIR              0x36C0
  66 #define QM_REG_ITPR             0x3740
  67
  68 /* Cache-enabled register offsets */
  69 #define QM_CL_EQCR              0x0000
  70 #define QM_CL_DQRR              0x1000
  71 #define QM_CL_MR                0x2000
  72 #define QM_CL_EQCR_PI_CENA      0x3000
  73 #define QM_CL_EQCR_CI_CENA      0x3040
  74 #define QM_CL_DQRR_PI_CENA      0x3100
  75 #define QM_CL_DQRR_CI_CENA      0x3140
  76 #define QM_CL_MR_PI_CENA        0x3300
  77 #define QM_CL_MR_CI_CENA        0x3340
  78 #define QM_CL_CR                0x3800
  79 #define QM_CL_RR0               0x3900
  80 #define QM_CL_RR1               0x3940
  81
  82 #else
  83 /* Cache-inhibited register offsets */
  84 #define QM_REG_EQCR_PI_CINH     0x0000
  85 #define QM_REG_EQCR_CI_CINH     0x0004
  86 #define QM_REG_EQCR_ITR         0x0008
  87 #define QM_REG_DQRR_PI_CINH     0x0040
  88 #define QM_REG_DQRR_CI_CINH     0x0044
  89 #define QM_REG_DQRR_ITR         0x0048
  90 #define QM_REG_DQRR_DCAP        0x0050
  91 #define QM_REG_DQRR_SDQCR       0x0054
  92 #define QM_REG_DQRR_VDQCR       0x0058
  93 #define QM_REG_DQRR_PDQCR       0x005c
  94 #define QM_REG_MR_PI_CINH       0x0080
  95 #define QM_REG_MR_CI_CINH       0x0084
  96 #define QM_REG_MR_ITR           0x0088
  97 #define QM_REG_CFG              0x0100
  98 #define QM_REG_ISR              0x0e00
  99 #define QM_REG_IER              0x0e04
 100 #define QM_REG_ISDR             0x0e08
 101 #define QM_REG_IIR              0x0e0c
 102 #define QM_REG_ITPR             0x0e14
 103
 104 /* Cache-enabled register offsets */
 105 #define QM_CL_EQCR              0x0000
 106 #define QM_CL_DQRR              0x1000
 107 #define QM_CL_MR                0x2000
 108 #define QM_CL_EQCR_PI_CENA      0x3000
 109 #define QM_CL_EQCR_CI_CENA      0x3100
 110 #define QM_CL_DQRR_PI_CENA      0x3200
 111 #define QM_CL_DQRR_CI_CENA      0x3300
 112 #define QM_CL_MR_PI_CENA        0x3400
 113 #define QM_CL_MR_CI_CENA        0x3500
 114 #define QM_CL_CR                0x3800
 115 #define QM_CL_RR0               0x3900
 116 #define QM_CL_RR1               0x3940
 117 #endif
 118
 119 /*
 120  * BTW, the drivers (and h/w programming model) already obtain the required
 121  * synchronisation for portal accesses and data-dependencies. Use of barrier()s
 122  * or other order-preserving primitives simply degrade performance. Hence the
 123  * use of the __raw_*() interfaces, which simply ensure that the compiler treats
 124  * the portal registers as volatile
 125  */
 126
 127 /* Cache-enabled ring access */
 128 #define qm_cl(base, idx)        ((void *)base + ((idx) << 6))
 129
 130 /*
 131  * Portal modes.
 132  *   Enum types;
 133  *     pmode == production mode
 134  *     cmode == consumption mode,
 135  *     dmode == h/w dequeue mode.
 136  *   Enum values use 3 letter codes. First letter matches the portal mode,
 137  *   remaining two letters indicate;
 138  *     ci == cache-inhibited portal register
 139  *     ce == cache-enabled portal register
 140  *     vb == in-band valid-bit (cache-enabled)
 141  *     dc == DCA (Discrete Consumption Acknowledgment), DQRR-only
 142  *   As for "enum qm_dqrr_dmode", it should be self-explanatory.
 143  */
 144 enum qm_eqcr_pmode {            /* matches QCSP_CFG::EPM */
 145         qm_eqcr_pci = 0,        /* PI index, cache-inhibited */
 146         qm_eqcr_pce = 1,        /* PI index, cache-enabled */
 147         qm_eqcr_pvb = 2         /* valid-bit */
 148 };
 149 enum qm_dqrr_dmode {            /* matches QCSP_CFG::DP */
 150         qm_dqrr_dpush = 0,      /* SDQCR  + VDQCR */
 151         qm_dqrr_dpull = 1       /* PDQCR */
 152 };
 153 enum qm_dqrr_pmode {            /* s/w-only */
 154         qm_dqrr_pci,            /* reads DQRR_PI_CINH */
 155         qm_dqrr_pce,            /* reads DQRR_PI_CENA */
 156         qm_dqrr_pvb             /* reads valid-bit */
 157 };
 158 enum qm_dqrr_cmode {            /* matches QCSP_CFG::DCM */
 159         qm_dqrr_cci = 0,        /* CI index, cache-inhibited */
 160         qm_dqrr_cce = 1,        /* CI index, cache-enabled */
 161         qm_dqrr_cdc = 2         /* Discrete Consumption Acknowledgment */
 162 };
 163 enum qm_mr_pmode {              /* s/w-only */
 164         qm_mr_pci,              /* reads MR_PI_CINH */
 165         qm_mr_pce,              /* reads MR_PI_CENA */
 166         qm_mr_pvb               /* reads valid-bit */
 167 };
 168 enum qm_mr_cmode {              /* matches QCSP_CFG::MM */
 169         qm_mr_cci = 0,          /* CI index, cache-inhibited */
 170         qm_mr_cce = 1           /* CI index, cache-enabled */
 171 };
 172
 173 /* --- Portal structures --- */
 174
 175 #define QM_EQCR_SIZE            8
 176 #define QM_DQRR_SIZE            16
 177 #define QM_MR_SIZE              8
 178
 179 /* "Enqueue Command" */
 180 struct qm_eqcr_entry {
 181         u8 _ncw_verb; /* writes to this are non-coherent */
 182         u8 dca;
 183         __be16 seqnum;
 184         u8 __reserved[4];
 185         __be32 fqid;    /* 24-bit */
 186         __be32 tag;
 187         struct qm_fd fd;
 188         u8 __reserved3[32];
 189 } __packed;
 190 #define QM_EQCR_VERB_VBIT               0x80
 191 #define QM_EQCR_VERB_CMD_MASK           0x61    /* but only one value; */
 192 #define QM_EQCR_VERB_CMD_ENQUEUE        0x01
 193 #define QM_EQCR_SEQNUM_NESN             0x8000  /* Advance NESN */
 194 #define QM_EQCR_SEQNUM_NLIS             0x4000  /* More fragments to come */
 195 #define QM_EQCR_SEQNUM_SEQMASK          0x3fff  /* sequence number goes here */
 196
 197 struct qm_eqcr {
 198         struct qm_eqcr_entry *ring, *cursor;
 199         u8 ci, available, ithresh, vbit;
 200 #ifdef CONFIG_FSL_DPAA_CHECKING
 201         u32 busy;
 202         enum qm_eqcr_pmode pmode;
 203 #endif
 204 };
 205
 206 struct qm_dqrr {
 207         const struct qm_dqrr_entry *ring, *cursor;
 208         u8 pi, ci, fill, ithresh, vbit;
 209 #ifdef CONFIG_FSL_DPAA_CHECKING
 210         enum qm_dqrr_dmode dmode;
 211         enum qm_dqrr_pmode pmode;
 212         enum qm_dqrr_cmode cmode;
 213 #endif
 214 };
 215
 216 struct qm_mr {
 217         union qm_mr_entry *ring, *cursor;
 218         u8 pi, ci, fill, ithresh, vbit;
 219 #ifdef CONFIG_FSL_DPAA_CHECKING
 220         enum qm_mr_pmode pmode;
 221         enum qm_mr_cmode cmode;
 222 #endif
 223 };
 224
 225 /* MC (Management Command) command */
 226 /* "FQ" command layout */
 227 struct qm_mcc_fq {
 228         u8 _ncw_verb;
 229         u8 __reserved1[3];
 230         __be32 fqid;    /* 24-bit */
 231         u8 __reserved2[56];
 232 } __packed;
 233
 234 /* "CGR" command layout */
 235 struct qm_mcc_cgr {
 236         u8 _ncw_verb;
 237         u8 __reserved1[30];
 238         u8 cgid;
 239         u8 __reserved2[32];
 240 };
 241
 242 #define QM_MCC_VERB_VBIT                0x80
 243 #define QM_MCC_VERB_MASK                0x7f    /* where the verb contains; */
 244 #define QM_MCC_VERB_INITFQ_PARKED       0x40
 245 #define QM_MCC_VERB_INITFQ_SCHED        0x41
 246 #define QM_MCC_VERB_QUERYFQ             0x44
 247 #define QM_MCC_VERB_QUERYFQ_NP          0x45    /* "non-programmable" fields */
 248 #define QM_MCC_VERB_QUERYWQ             0x46
 249 #define QM_MCC_VERB_QUERYWQ_DEDICATED   0x47
 250 #define QM_MCC_VERB_ALTER_SCHED         0x48    /* Schedule FQ */
 251 #define QM_MCC_VERB_ALTER_FE            0x49    /* Force Eligible FQ */
 252 #define QM_MCC_VERB_ALTER_RETIRE        0x4a    /* Retire FQ */
 253 #define QM_MCC_VERB_ALTER_OOS           0x4b    /* Take FQ out of service */
 254 #define QM_MCC_VERB_ALTER_FQXON         0x4d    /* FQ XON */
 255 #define QM_MCC_VERB_ALTER_FQXOFF        0x4e    /* FQ XOFF */
 256 #define QM_MCC_VERB_INITCGR             0x50
 257 #define QM_MCC_VERB_MODIFYCGR           0x51
 258 #define QM_MCC_VERB_CGRTESTWRITE        0x52
 259 #define QM_MCC_VERB_QUERYCGR            0x58
 260 #define QM_MCC_VERB_QUERYCONGESTION     0x59
 261 union qm_mc_command {
 262         struct {
 263                 u8 _ncw_verb; /* writes to this are non-coherent */
 264                 u8 __reserved[63];
 265         };
 266         struct qm_mcc_initfq initfq;
 267         struct qm_mcc_initcgr initcgr;
 268         struct qm_mcc_fq fq;
 269         struct qm_mcc_cgr cgr;
 270 };
 271
 272 /* MC (Management Command) result */
 273 /* "Query FQ" */
 274 struct qm_mcr_queryfq {
 275         u8 verb;
 276         u8 result;
 277         u8 __reserved1[8];
 278         struct qm_fqd fqd;      /* the FQD fields are here */
 279         u8 __reserved2[30];
 280 } __packed;
 281
 282 /* "Alter FQ State Commands" */
 283 struct qm_mcr_alterfq {
 284         u8 verb;
 285         u8 result;
 286         u8 fqs;         /* Frame Queue Status */
 287         u8 __reserved1[61];
 288 };
 289 #define QM_MCR_VERB_RRID                0x80
 290 #define QM_MCR_VERB_MASK                QM_MCC_VERB_MASK
 291 #define QM_MCR_VERB_INITFQ_PARKED       QM_MCC_VERB_INITFQ_PARKED
 292 #define QM_MCR_VERB_INITFQ_SCHED        QM_MCC_VERB_INITFQ_SCHED
 293 #define QM_MCR_VERB_QUERYFQ             QM_MCC_VERB_QUERYFQ
 294 #define QM_MCR_VERB_QUERYFQ_NP          QM_MCC_VERB_QUERYFQ_NP
 295 #define QM_MCR_VERB_QUERYWQ             QM_MCC_VERB_QUERYWQ
 296 #define QM_MCR_VERB_QUERYWQ_DEDICATED   QM_MCC_VERB_QUERYWQ_DEDICATED
 297 #define QM_MCR_VERB_ALTER_SCHED         QM_MCC_VERB_ALTER_SCHED
 298 #define QM_MCR_VERB_ALTER_FE            QM_MCC_VERB_ALTER_FE
 299 #define QM_MCR_VERB_ALTER_RETIRE        QM_MCC_VERB_ALTER_RETIRE
 300 #define QM_MCR_VERB_ALTER_OOS           QM_MCC_VERB_ALTER_OOS
 301 #define QM_MCR_RESULT_NULL              0x00
 302 #define QM_MCR_RESULT_OK                0xf0
 303 #define QM_MCR_RESULT_ERR_FQID          0xf1
 304 #define QM_MCR_RESULT_ERR_FQSTATE       0xf2
 305 #define QM_MCR_RESULT_ERR_NOTEMPTY      0xf3    /* OOS fails if FQ is !empty */
 306 #define QM_MCR_RESULT_ERR_BADCHANNEL    0xf4
 307 #define QM_MCR_RESULT_PENDING           0xf8
 308 #define QM_MCR_RESULT_ERR_BADCOMMAND    0xff
 309 #define QM_MCR_FQS_ORLPRESENT           0x02    /* ORL fragments to come */
 310 #define QM_MCR_FQS_NOTEMPTY             0x01    /* FQ has enqueued frames */
 311 #define QM_MCR_TIMEOUT                  10000   /* us */
 312 union qm_mc_result {
 313         struct {
 314                 u8 verb;
 315                 u8 result;
 316                 u8 __reserved1[62];
 317         };
 318         struct qm_mcr_queryfq queryfq;
 319         struct qm_mcr_alterfq alterfq;
 320         struct qm_mcr_querycgr querycgr;
 321         struct qm_mcr_querycongestion querycongestion;
 322         struct qm_mcr_querywq querywq;
 323         struct qm_mcr_queryfq_np queryfq_np;
 324 };
 325
 326 struct qm_mc {
 327         union qm_mc_command *cr;
 328         union qm_mc_result *rr;
 329         u8 rridx, vbit;
 330 #ifdef CONFIG_FSL_DPAA_CHECKING
 331         enum {
 332                 /* Can be _mc_start()ed */
 333                 qman_mc_idle,
 334                 /* Can be _mc_commit()ed or _mc_abort()ed */
 335                 qman_mc_user,
 336                 /* Can only be _mc_retry()ed */
 337                 qman_mc_hw
 338         } state;
 339 #endif
 340 };
 341
 342 struct qm_addr {
 343         void *ce;               /* cache-enabled */
 344         __be32 *ce_be;          /* same value as above but for direct access */
 345         void __iomem *ci;       /* cache-inhibited */
 346 };
 347
 348 struct qm_portal {
 349         /*
 350          * In the non-CONFIG_FSL_DPAA_CHECKING case, the following stuff up to
 351          * and including 'mc' fits within a cacheline (yay!). The 'config' part
 352          * is setup-only, so isn't a cause for a concern. In other words, don't
 353          * rearrange this structure on a whim, there be dragons ...
 354          */
 355         struct qm_addr addr;
 356         struct qm_eqcr eqcr;
 357         struct qm_dqrr dqrr;
 358         struct qm_mr mr;
 359         struct qm_mc mc;
 360 } ____cacheline_aligned;
 361
 362 /* Cache-inhibited register access. */
 363 static inline u32 qm_in(struct qm_portal *p, u32 offset)
 364 {
 365         return ioread32be(p->addr.ci + offset);
 366 }
 367
 368 static inline void qm_out(struct qm_portal *p, u32 offset, u32 val)
 369 {
 370         iowrite32be(val, p->addr.ci + offset);
 371 }
 372
 373 /* Cache Enabled Portal Access */
 374 static inline void qm_cl_invalidate(struct qm_portal *p, u32 offset)
 375 {
 376         dpaa_invalidate(p->addr.ce + offset);
 377 }
 378
 379 static inline void qm_cl_touch_ro(struct qm_portal *p, u32 offset)
 380 {
 381         dpaa_touch_ro(p->addr.ce + offset);
 382 }
 383
 384 static inline u32 qm_ce_in(struct qm_portal *p, u32 offset)
 385 {
 386         return be32_to_cpu(*(p->addr.ce_be + (offset/4)));
 387 }
 388
 389 /* --- EQCR API --- */
 390
 391 #define EQCR_SHIFT      ilog2(sizeof(struct qm_eqcr_entry))
 392 #define EQCR_CARRY      (uintptr_t)(QM_EQCR_SIZE << EQCR_SHIFT)
 393
 394 /* Bit-wise logic to wrap a ring pointer by clearing the "carry bit" */
 395 static struct qm_eqcr_entry *eqcr_carryclear(struct qm_eqcr_entry *p)
 396 {
 397         uintptr_t addr = (uintptr_t)p;
 398
 399         addr &= ~EQCR_CARRY;
 400
 401         return (struct qm_eqcr_entry *)addr;
 402 }
 403
 404 /* Bit-wise logic to convert a ring pointer to a ring index */
 405 static int eqcr_ptr2idx(struct qm_eqcr_entry *e)
 406 {
 407         return ((uintptr_t)e >> EQCR_SHIFT) & (QM_EQCR_SIZE - 1);
 408 }
 409
 410 /* Increment the 'cursor' ring pointer, taking 'vbit' into account */
 411 static inline void eqcr_inc(struct qm_eqcr *eqcr)
 412 {
 413         /* increment to the next EQCR pointer and handle overflow and 'vbit' */
 414         struct qm_eqcr_entry *partial = eqcr->cursor + 1;
 415
 416         eqcr->cursor = eqcr_carryclear(partial);
 417         if (partial != eqcr->cursor)
 418                 eqcr->vbit ^= QM_EQCR_VERB_VBIT;
 419 }
 420
 421 static inline int qm_eqcr_init(struct qm_portal *portal,
 422                                 enum qm_eqcr_pmode pmode,
 423                                 unsigned int eq_stash_thresh,
 424                                 int eq_stash_prio)
 425 {
 426         struct qm_eqcr *eqcr = &portal->eqcr;
 427         u32 cfg;
 428         u8 pi;
 429
 430         eqcr->ring = portal->addr.ce + QM_CL_EQCR;
 431         eqcr->ci = qm_in(portal, QM_REG_EQCR_CI_CINH) & (QM_EQCR_SIZE - 1);
 432         qm_cl_invalidate(portal, QM_CL_EQCR_CI_CENA);
 433         pi = qm_in(portal, QM_REG_EQCR_PI_CINH) & (QM_EQCR_SIZE - 1);
 434         eqcr->cursor = eqcr->ring + pi;
 435         eqcr->vbit = (qm_in(portal, QM_REG_EQCR_PI_CINH) & QM_EQCR_SIZE) ?
 436                      QM_EQCR_VERB_VBIT : 0;
 437         eqcr->available = QM_EQCR_SIZE - 1 -
 438                           dpaa_cyc_diff(QM_EQCR_SIZE, eqcr->ci, pi);
 439         eqcr->ithresh = qm_in(portal, QM_REG_EQCR_ITR);
 440 #ifdef CONFIG_FSL_DPAA_CHECKING
 441         eqcr->busy = 0;
 442         eqcr->pmode = pmode;
 443 #endif
 444         cfg = (qm_in(portal, QM_REG_CFG) & 0x00ffffff) |
 445               (eq_stash_thresh << 28) | /* QCSP_CFG: EST */
 446               (eq_stash_prio << 26) | /* QCSP_CFG: EP */
 447               ((pmode & 0x3) << 24); /* QCSP_CFG::EPM */
 448         qm_out(portal, QM_REG_CFG, cfg);
 449         return 0;
 450 }
 451
 452 static inline unsigned int qm_eqcr_get_ci_stashing(struct qm_portal *portal)
 453 {
 454         return (qm_in(portal, QM_REG_CFG) >> 28) & 0x7;
 455 }
 456
 457 static inline void qm_eqcr_finish(struct qm_portal *portal)
 458 {
 459         struct qm_eqcr *eqcr = &portal->eqcr;
 460         u8 pi = qm_in(portal, QM_REG_EQCR_PI_CINH) & (QM_EQCR_SIZE - 1);
 461         u8 ci = qm_in(portal, QM_REG_EQCR_CI_CINH) & (QM_EQCR_SIZE - 1);
 462
 463         DPAA_ASSERT(!eqcr->busy);
 464         if (pi != eqcr_ptr2idx(eqcr->cursor))
 465                 pr_crit("losing uncommitted EQCR entries\n");
 466         if (ci != eqcr->ci)
 467                 pr_crit("missing existing EQCR completions\n");
 468         if (eqcr->ci != eqcr_ptr2idx(eqcr->cursor))
 469                 pr_crit("EQCR destroyed unquiesced\n");
 470 }
 471
 472 static inline struct qm_eqcr_entry *qm_eqcr_start_no_stash(struct qm_portal
 473                                                                  *portal)
 474 {
 475         struct qm_eqcr *eqcr = &portal->eqcr;
 476
 477         DPAA_ASSERT(!eqcr->busy);
 478         if (!eqcr->available)
 479                 return NULL;
 480
 481 #ifdef CONFIG_FSL_DPAA_CHECKING
 482         eqcr->busy = 1;
 483 #endif
 484         dpaa_zero(eqcr->cursor);
 485         return eqcr->cursor;
 486 }
 487
 488 static inline struct qm_eqcr_entry *qm_eqcr_start_stash(struct qm_portal
 489                                                                 *portal)
 490 {
 491         struct qm_eqcr *eqcr = &portal->eqcr;
 492         u8 diff, old_ci;
 493
 494         DPAA_ASSERT(!eqcr->busy);
 495         if (!eqcr->available) {
 496                 old_ci = eqcr->ci;
 497                 eqcr->ci = qm_ce_in(portal, QM_CL_EQCR_CI_CENA) &
 498                            (QM_EQCR_SIZE - 1);
 499                 diff = dpaa_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
 500                 eqcr->available += diff;
 501                 if (!diff)
 502                         return NULL;
 503         }
 504 #ifdef CONFIG_FSL_DPAA_CHECKING
 505         eqcr->busy = 1;
 506 #endif
 507         dpaa_zero(eqcr->cursor);
 508         return eqcr->cursor;
 509 }
 510
 511 static inline void eqcr_commit_checks(struct qm_eqcr *eqcr)
 512 {
 513         DPAA_ASSERT(eqcr->busy);
 514         DPAA_ASSERT(!(be32_to_cpu(eqcr->cursor->fqid) & ~QM_FQID_MASK));
 515         DPAA_ASSERT(eqcr->available >= 1);
 516 }
 517
 518 static inline void qm_eqcr_pvb_commit(struct qm_portal *portal, u8 myverb)
 519 {
 520         struct qm_eqcr *eqcr = &portal->eqcr;
 521         struct qm_eqcr_entry *eqcursor;
 522
 523         eqcr_commit_checks(eqcr);
 524         DPAA_ASSERT(eqcr->pmode == qm_eqcr_pvb);
 525         dma_wmb();
 526         eqcursor = eqcr->cursor;
 527         eqcursor->_ncw_verb = myverb | eqcr->vbit;
 528         dpaa_flush(eqcursor);
 529         eqcr_inc(eqcr);
 530         eqcr->available--;
 531 #ifdef CONFIG_FSL_DPAA_CHECKING
 532         eqcr->busy = 0;
 533 #endif
 534 }
 535
 536 static inline void qm_eqcr_cce_prefetch(struct qm_portal *portal)
 537 {
 538         qm_cl_touch_ro(portal, QM_CL_EQCR_CI_CENA);
 539 }
 540
 541 static inline u8 qm_eqcr_cce_update(struct qm_portal *portal)
 542 {
 543         struct qm_eqcr *eqcr = &portal->eqcr;
 544         u8 diff, old_ci = eqcr->ci;
 545
 546         eqcr->ci = qm_ce_in(portal, QM_CL_EQCR_CI_CENA) & (QM_EQCR_SIZE - 1);
 547         qm_cl_invalidate(portal, QM_CL_EQCR_CI_CENA);
 548         diff = dpaa_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
 549         eqcr->available += diff;
 550         return diff;
 551 }
 552
 553 static inline void qm_eqcr_set_ithresh(struct qm_portal *portal, u8 ithresh)
 554 {
 555         struct qm_eqcr *eqcr = &portal->eqcr;
 556
 557         eqcr->ithresh = ithresh;
 558         qm_out(portal, QM_REG_EQCR_ITR, ithresh);
 559 }
 560
 561 static inline u8 qm_eqcr_get_avail(struct qm_portal *portal)
 562 {
 563         struct qm_eqcr *eqcr = &portal->eqcr;
 564
 565         return eqcr->available;
 566 }
 567
 568 static inline u8 qm_eqcr_get_fill(struct qm_portal *portal)
 569 {
 570         struct qm_eqcr *eqcr = &portal->eqcr;
 571
 572         return QM_EQCR_SIZE - 1 - eqcr->available;
 573 }
 574
 575 /* --- DQRR API --- */
 576
 577 #define DQRR_SHIFT      ilog2(sizeof(struct qm_dqrr_entry))
 578 #define DQRR_CARRY      (uintptr_t)(QM_DQRR_SIZE << DQRR_SHIFT)
 579
 580 static const struct qm_dqrr_entry *dqrr_carryclear(
 581                                         const struct qm_dqrr_entry *p)
 582 {
 583         uintptr_t addr = (uintptr_t)p;
 584
 585         addr &= ~DQRR_CARRY;
 586
 587         return (const struct qm_dqrr_entry *)addr;
 588 }
 589
 590 static inline int dqrr_ptr2idx(const struct qm_dqrr_entry *e)
 591 {
 592         return ((uintptr_t)e >> DQRR_SHIFT) & (QM_DQRR_SIZE - 1);
 593 }
 594
 595 static const struct qm_dqrr_entry *dqrr_inc(const struct qm_dqrr_entry *e)
 596 {
 597         return dqrr_carryclear(e + 1);
 598 }
 599
 600 static inline void qm_dqrr_set_maxfill(struct qm_portal *portal, u8 mf)
 601 {
 602         qm_out(portal, QM_REG_CFG, (qm_in(portal, QM_REG_CFG) & 0xff0fffff) |
 603                                    ((mf & (QM_DQRR_SIZE - 1)) << 20));
 604 }
 605
 606 static inline int qm_dqrr_init(struct qm_portal *portal,
 607                                const struct qm_portal_config *config,
 608                                enum qm_dqrr_dmode dmode,
 609                                enum qm_dqrr_pmode pmode,
 610                                enum qm_dqrr_cmode cmode, u8 max_fill)
 611 {
 612         struct qm_dqrr *dqrr = &portal->dqrr;
 613         u32 cfg;
 614
 615         /* Make sure the DQRR will be idle when we enable */
 616         qm_out(portal, QM_REG_DQRR_SDQCR, 0);
 617         qm_out(portal, QM_REG_DQRR_VDQCR, 0);
 618         qm_out(portal, QM_REG_DQRR_PDQCR, 0);
 619         dqrr->ring = portal->addr.ce + QM_CL_DQRR;
 620         dqrr->pi = qm_in(portal, QM_REG_DQRR_PI_CINH) & (QM_DQRR_SIZE - 1);
 621         dqrr->ci = qm_in(portal, QM_REG_DQRR_CI_CINH) & (QM_DQRR_SIZE - 1);
 622         dqrr->cursor = dqrr->ring + dqrr->ci;
 623         dqrr->fill = dpaa_cyc_diff(QM_DQRR_SIZE, dqrr->ci, dqrr->pi);
 624         dqrr->vbit = (qm_in(portal, QM_REG_DQRR_PI_CINH) & QM_DQRR_SIZE) ?
 625                         QM_DQRR_VERB_VBIT : 0;
 626         dqrr->ithresh = qm_in(portal, QM_REG_DQRR_ITR);
 627 #ifdef CONFIG_FSL_DPAA_CHECKING
 628         dqrr->dmode = dmode;
 629         dqrr->pmode = pmode;
 630         dqrr->cmode = cmode;
 631 #endif
 632         /* Invalidate every ring entry before beginning */
 633         for (cfg = 0; cfg < QM_DQRR_SIZE; cfg++)
 634                 dpaa_invalidate(qm_cl(dqrr->ring, cfg));
 635         cfg = (qm_in(portal, QM_REG_CFG) & 0xff000f00) |
 636                 ((max_fill & (QM_DQRR_SIZE - 1)) << 20) | /* DQRR_MF */
 637                 ((dmode & 1) << 18) |                   /* DP */
 638                 ((cmode & 3) << 16) |                   /* DCM */
 639                 0xa0 |                                  /* RE+SE */
 640                 (0 ? 0x40 : 0) |                        /* Ignore RP */
 641                 (0 ? 0x10 : 0);                         /* Ignore SP */
 642         qm_out(portal, QM_REG_CFG, cfg);
 643         qm_dqrr_set_maxfill(portal, max_fill);
 644         return 0;
 645 }
 646
 647 static inline void qm_dqrr_finish(struct qm_portal *portal)
 648 {
 649 #ifdef CONFIG_FSL_DPAA_CHECKING
 650         struct qm_dqrr *dqrr = &portal->dqrr;
 651
 652         if (dqrr->cmode != qm_dqrr_cdc &&
 653             dqrr->ci != dqrr_ptr2idx(dqrr->cursor))
 654                 pr_crit("Ignoring completed DQRR entries\n");
 655 #endif
 656 }
 657
 658 static inline const struct qm_dqrr_entry *qm_dqrr_current(
 659                                                 struct qm_portal *portal)
 660 {
 661         struct qm_dqrr *dqrr = &portal->dqrr;
 662
 663         if (!dqrr->fill)
 664                 return NULL;
 665         return dqrr->cursor;
 666 }
 667
 668 static inline u8 qm_dqrr_next(struct qm_portal *portal)
 669 {
 670         struct qm_dqrr *dqrr = &portal->dqrr;
 671
 672         DPAA_ASSERT(dqrr->fill);
 673         dqrr->cursor = dqrr_inc(dqrr->cursor);
 674         return --dqrr->fill;
 675 }
 676
 677 static inline void qm_dqrr_pvb_update(struct qm_portal *portal)
 678 {
 679         struct qm_dqrr *dqrr = &portal->dqrr;
 680         struct qm_dqrr_entry *res = qm_cl(dqrr->ring, dqrr->pi);
 681
 682         DPAA_ASSERT(dqrr->pmode == qm_dqrr_pvb);
 683 #ifndef CONFIG_FSL_PAMU
 684         /*
 685          * If PAMU is not available we need to invalidate the cache.
 686          * When PAMU is available the cache is updated by stash
 687          */
 688         dpaa_invalidate_touch_ro(res);
 689 #endif
 690         if ((res->verb & QM_DQRR_VERB_VBIT) == dqrr->vbit) {
 691                 dqrr->pi = (dqrr->pi + 1) & (QM_DQRR_SIZE - 1);
 692                 if (!dqrr->pi)
 693                         dqrr->vbit ^= QM_DQRR_VERB_VBIT;
 694                 dqrr->fill++;
 695         }
 696 }
 697
 698 static inline void qm_dqrr_cdc_consume_1ptr(struct qm_portal *portal,
 699                                         const struct qm_dqrr_entry *dq,
 700                                         int park)
 701 {
 702         __maybe_unused struct qm_dqrr *dqrr = &portal->dqrr;
 703         int idx = dqrr_ptr2idx(dq);
 704
 705         DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
 706         DPAA_ASSERT((dqrr->ring + idx) == dq);
 707         DPAA_ASSERT(idx < QM_DQRR_SIZE);
 708         qm_out(portal, QM_REG_DQRR_DCAP, (0 << 8) | /* DQRR_DCAP::S */
 709                ((park ? 1 : 0) << 6) |              /* DQRR_DCAP::PK */
 710                idx);                                /* DQRR_DCAP::DCAP_CI */
 711 }
 712
 713 static inline void qm_dqrr_cdc_consume_n(struct qm_portal *portal, u32 bitmask)
 714 {
 715         __maybe_unused struct qm_dqrr *dqrr = &portal->dqrr;
 716
 717         DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
 718         qm_out(portal, QM_REG_DQRR_DCAP, (1 << 8) | /* DQRR_DCAP::S */
 719                (bitmask << 16));                    /* DQRR_DCAP::DCAP_CI */
 720 }
 721
 722 static inline void qm_dqrr_sdqcr_set(struct qm_portal *portal, u32 sdqcr)
 723 {
 724         qm_out(portal, QM_REG_DQRR_SDQCR, sdqcr);
 725 }
 726
 727 static inline void qm_dqrr_vdqcr_set(struct qm_portal *portal, u32 vdqcr)
 728 {
 729         qm_out(portal, QM_REG_DQRR_VDQCR, vdqcr);
 730 }
 731
 732 static inline int qm_dqrr_set_ithresh(struct qm_portal *portal, u8 ithresh)
 733 {
 734
 735         if (ithresh > QMAN_DQRR_IT_MAX)
 736                 return -EINVAL;
 737
 738         qm_out(portal, QM_REG_DQRR_ITR, ithresh);
 739
 740         return 0;
 741 }
 742
 743 /* --- MR API --- */
 744
 745 #define MR_SHIFT        ilog2(sizeof(union qm_mr_entry))
 746 #define MR_CARRY        (uintptr_t)(QM_MR_SIZE << MR_SHIFT)
 747
 748 static union qm_mr_entry *mr_carryclear(union qm_mr_entry *p)
 749 {
 750         uintptr_t addr = (uintptr_t)p;
 751
 752         addr &= ~MR_CARRY;
 753
 754         return (union qm_mr_entry *)addr;
 755 }
 756
 757 static inline int mr_ptr2idx(const union qm_mr_entry *e)
 758 {
 759         return ((uintptr_t)e >> MR_SHIFT) & (QM_MR_SIZE - 1);
 760 }
 761
 762 static inline union qm_mr_entry *mr_inc(union qm_mr_entry *e)
 763 {
 764         return mr_carryclear(e + 1);
 765 }
 766
 767 static inline int qm_mr_init(struct qm_portal *portal, enum qm_mr_pmode pmode,
 768                              enum qm_mr_cmode cmode)
 769 {
 770         struct qm_mr *mr = &portal->mr;
 771         u32 cfg;
 772
 773         mr->ring = portal->addr.ce + QM_CL_MR;
 774         mr->pi = qm_in(portal, QM_REG_MR_PI_CINH) & (QM_MR_SIZE - 1);
 775         mr->ci = qm_in(portal, QM_REG_MR_CI_CINH) & (QM_MR_SIZE - 1);
 776         mr->cursor = mr->ring + mr->ci;
 777         mr->fill = dpaa_cyc_diff(QM_MR_SIZE, mr->ci, mr->pi);
 778         mr->vbit = (qm_in(portal, QM_REG_MR_PI_CINH) & QM_MR_SIZE)
 779                 ? QM_MR_VERB_VBIT : 0;
 780         mr->ithresh = qm_in(portal, QM_REG_MR_ITR);
 781 #ifdef CONFIG_FSL_DPAA_CHECKING
 782         mr->pmode = pmode;
 783         mr->cmode = cmode;
 784 #endif
 785         cfg = (qm_in(portal, QM_REG_CFG) & 0xfffff0ff) |
 786               ((cmode & 1) << 8);       /* QCSP_CFG:MM */
 787         qm_out(portal, QM_REG_CFG, cfg);
 788         return 0;
 789 }
 790
 791 static inline void qm_mr_finish(struct qm_portal *portal)
 792 {
 793         struct qm_mr *mr = &portal->mr;
 794
 795         if (mr->ci != mr_ptr2idx(mr->cursor))
 796                 pr_crit("Ignoring completed MR entries\n");
 797 }
 798
 799 static inline const union qm_mr_entry *qm_mr_current(struct qm_portal *portal)
 800 {
 801         struct qm_mr *mr = &portal->mr;
 802
 803         if (!mr->fill)
 804                 return NULL;
 805         return mr->cursor;
 806 }
 807
 808 static inline int qm_mr_next(struct qm_portal *portal)
 809 {
 810         struct qm_mr *mr = &portal->mr;
 811
 812         DPAA_ASSERT(mr->fill);
 813         mr->cursor = mr_inc(mr->cursor);
 814         return --mr->fill;
 815 }
 816
 817 static inline void qm_mr_pvb_update(struct qm_portal *portal)
 818 {
 819         struct qm_mr *mr = &portal->mr;
 820         union qm_mr_entry *res = qm_cl(mr->ring, mr->pi);
 821
 822         DPAA_ASSERT(mr->pmode == qm_mr_pvb);
 823
 824         if ((res->verb & QM_MR_VERB_VBIT) == mr->vbit) {
 825                 mr->pi = (mr->pi + 1) & (QM_MR_SIZE - 1);
 826                 if (!mr->pi)
 827                         mr->vbit ^= QM_MR_VERB_VBIT;
 828                 mr->fill++;
 829                 res = mr_inc(res);
 830         }
 831         dpaa_invalidate_touch_ro(res);
 832 }
 833
 834 static inline void qm_mr_cci_consume(struct qm_portal *portal, u8 num)
 835 {
 836         struct qm_mr *mr = &portal->mr;
 837
 838         DPAA_ASSERT(mr->cmode == qm_mr_cci);
 839         mr->ci = (mr->ci + num) & (QM_MR_SIZE - 1);
 840         qm_out(portal, QM_REG_MR_CI_CINH, mr->ci);
 841 }
 842
 843 static inline void qm_mr_cci_consume_to_current(struct qm_portal *portal)
 844 {
 845         struct qm_mr *mr = &portal->mr;
 846
 847         DPAA_ASSERT(mr->cmode == qm_mr_cci);
 848         mr->ci = mr_ptr2idx(mr->cursor);
 849         qm_out(portal, QM_REG_MR_CI_CINH, mr->ci);
 850 }
 851
 852 static inline void qm_mr_set_ithresh(struct qm_portal *portal, u8 ithresh)
 853 {
 854         qm_out(portal, QM_REG_MR_ITR, ithresh);
 855 }
 856
 857 /* --- Management command API --- */
 858
 859 static inline int qm_mc_init(struct qm_portal *portal)
 860 {
 861         u8 rr0, rr1;
 862         struct qm_mc *mc = &portal->mc;
 863
 864         mc->cr = portal->addr.ce + QM_CL_CR;
 865         mc->rr = portal->addr.ce + QM_CL_RR0;
 866         /*
 867          * The expected valid bit polarity for the next CR command is 0
 868          * if RR1 contains a valid response, and is 1 if RR0 contains a
 869          * valid response. If both RR contain all 0, this indicates either
 870          * that no command has been executed since reset (in which case the
 871          * expected valid bit polarity is 1)
 872          */
 873         rr0 = mc->rr->verb;
 874         rr1 = (mc->rr+1)->verb;
 875         if ((rr0 == 0 && rr1 == 0) || rr0 != 0)
 876                 mc->rridx = 1;
 877         else
 878                 mc->rridx = 0;
 879         mc->vbit = mc->rridx ? QM_MCC_VERB_VBIT : 0;
 880 #ifdef CONFIG_FSL_DPAA_CHECKING
 881         mc->state = qman_mc_idle;
 882 #endif
 883         return 0;
 884 }
 885
 886 static inline void qm_mc_finish(struct qm_portal *portal)
 887 {
 888 #ifdef CONFIG_FSL_DPAA_CHECKING
 889         struct qm_mc *mc = &portal->mc;
 890
 891         DPAA_ASSERT(mc->state == qman_mc_idle);
 892         if (mc->state != qman_mc_idle)
 893                 pr_crit("Losing incomplete MC command\n");
 894 #endif
 895 }
 896
 897 static inline union qm_mc_command *qm_mc_start(struct qm_portal *portal)
 898 {
 899         struct qm_mc *mc = &portal->mc;
 900
 901         DPAA_ASSERT(mc->state == qman_mc_idle);
 902 #ifdef CONFIG_FSL_DPAA_CHECKING
 903         mc->state = qman_mc_user;
 904 #endif
 905         dpaa_zero(mc->cr);
 906         return mc->cr;
 907 }
 908
 909 static inline void qm_mc_commit(struct qm_portal *portal, u8 myverb)
 910 {
 911         struct qm_mc *mc = &portal->mc;
 912         union qm_mc_result *rr = mc->rr + mc->rridx;
 913
 914         DPAA_ASSERT(mc->state == qman_mc_user);
 915         dma_wmb();
 916         mc->cr->_ncw_verb = myverb | mc->vbit;
 917         dpaa_flush(mc->cr);
 918         dpaa_invalidate_touch_ro(rr);
 919 #ifdef CONFIG_FSL_DPAA_CHECKING
 920         mc->state = qman_mc_hw;
 921 #endif
 922 }
 923
 924 static inline union qm_mc_result *qm_mc_result(struct qm_portal *portal)
 925 {
 926         struct qm_mc *mc = &portal->mc;
 927         union qm_mc_result *rr = mc->rr + mc->rridx;
 928
 929         DPAA_ASSERT(mc->state == qman_mc_hw);
 930         /*
 931          *  The inactive response register's verb byte always returns zero until
 932          * its command is submitted and completed. This includes the valid-bit,
 933          * in case you were wondering...
 934          */
 935         if (!rr->verb) {
 936                 dpaa_invalidate_touch_ro(rr);
 937                 return NULL;
 938         }
 939         mc->rridx ^= 1;
 940         mc->vbit ^= QM_MCC_VERB_VBIT;
 941 #ifdef CONFIG_FSL_DPAA_CHECKING
 942         mc->state = qman_mc_idle;
 943 #endif
 944         return rr;
 945 }
 946
 947 static inline int qm_mc_result_timeout(struct qm_portal *portal,
 948                                        union qm_mc_result **mcr)
 949 {
 950         int timeout = QM_MCR_TIMEOUT;
 951
 952         do {
 953                 *mcr = qm_mc_result(portal);
 954                 if (*mcr)
 955                         break;
 956                 udelay(1);
 957         } while (--timeout);
 958
 959         return timeout;
 960 }
 961
 962 static inline void fq_set(struct qman_fq *fq, u32 mask)
 963 {
 964         fq->flags |= mask;
 965 }
 966
 967 static inline void fq_clear(struct qman_fq *fq, u32 mask)
 968 {
 969         fq->flags &= ~mask;
 970 }
 971
 972 static inline int fq_isset(struct qman_fq *fq, u32 mask)
 973 {
 974         return fq->flags & mask;
 975 }
 976
 977 static inline int fq_isclear(struct qman_fq *fq, u32 mask)
 978 {
 979         return !(fq->flags & mask);
 980 }
 981
 982 struct qman_portal {
 983         struct qm_portal p;
 984         /* PORTAL_BITS_*** - dynamic, strictly internal */
 985         unsigned long bits;
 986         /* interrupt sources processed by portal_isr(), configurable */
 987         unsigned long irq_sources;
 988         u32 use_eqcr_ci_stashing;
 989         /* only 1 volatile dequeue at a time */
 990         struct qman_fq *vdqcr_owned;
 991         u32 sdqcr;
 992         /* probing time config params for cpu-affine portals */
 993         const struct qm_portal_config *config;
 994         /* 2-element array. cgrs[0] is mask, cgrs[1] is snapshot. */
 995         struct qman_cgrs *cgrs;
 996         /* linked-list of CSCN handlers. */
 997         struct list_head cgr_cbs;
 998         /* list lock */
 999         spinlock_t cgr_lock;
1000         struct work_struct congestion_work;
1001         struct work_struct mr_work;
1002         char irqname[MAX_IRQNAME];
1003 };
1004
1005 static cpumask_t affine_mask;
1006 static DEFINE_SPINLOCK(affine_mask_lock);
1007 static u16 affine_channels[NR_CPUS];
1008 static DEFINE_PER_CPU(struct qman_portal, qman_affine_portal);
1009 struct qman_portal *affine_portals[NR_CPUS];
1010
1011 static inline struct qman_portal *get_affine_portal(void)
1012 {
1013         return &get_cpu_var(qman_affine_portal);
1014 }
1015
1016 static inline void put_affine_portal(void)
1017 {
1018         put_cpu_var(qman_affine_portal);
1019 }
1020
1021 static struct workqueue_struct *qm_portal_wq;
1022
1023 int qman_dqrr_set_ithresh(struct qman_portal *portal, u8 ithresh)
1024 {
1025         int res;
1026
1027         if (!portal)
1028                 return -EINVAL;
1029
1030         res = qm_dqrr_set_ithresh(&portal->p, ithresh);
1031         if (res)
1032                 return res;
1033
1034         portal->p.dqrr.ithresh = ithresh;
1035
1036         return 0;
1037 }
1038 EXPORT_SYMBOL(qman_dqrr_set_ithresh);
1039
1040 void qman_dqrr_get_ithresh(struct qman_portal *portal, u8 *ithresh)
1041 {
1042         if (portal && ithresh)
1043                 *ithresh = qm_in(&portal->p, QM_REG_DQRR_ITR);
1044 }
1045 EXPORT_SYMBOL(qman_dqrr_get_ithresh);
1046
1047 void qman_portal_get_iperiod(struct qman_portal *portal, u32 *iperiod)
1048 {
1049         if (portal && iperiod)
1050                 *iperiod = qm_in(&portal->p, QM_REG_ITPR);
1051 }
1052 EXPORT_SYMBOL(qman_portal_get_iperiod);
1053
1054 int qman_portal_set_iperiod(struct qman_portal *portal, u32 iperiod)
1055 {
1056         if (!portal || iperiod > QMAN_ITP_MAX)
1057                 return -EINVAL;
1058
1059         qm_out(&portal->p, QM_REG_ITPR, iperiod);
1060
1061         return 0;
1062 }
1063 EXPORT_SYMBOL(qman_portal_set_iperiod);
1064
1065 int qman_wq_alloc(void)
1066 {
1067         qm_portal_wq = alloc_workqueue("qman_portal_wq", 0, 1);
1068         if (!qm_portal_wq)
1069                 return -ENOMEM;
1070         return 0;
1071 }
1072
1073 /*
1074  * This is what everything can wait on, even if it migrates to a different cpu
1075  * to the one whose affine portal it is waiting on.
1076  */
1077 static DECLARE_WAIT_QUEUE_HEAD(affine_queue);
1078
1079 static struct qman_fq **fq_table;
1080 static u32 num_fqids;
1081
1082 int qman_alloc_fq_table(u32 _num_fqids)
1083 {
1084         num_fqids = _num_fqids;
1085
1086         fq_table = vzalloc(array3_size(sizeof(struct qman_fq *),
1087                                        num_fqids, 2));
1088         if (!fq_table)
1089                 return -ENOMEM;
1090
1091         pr_debug("Allocated fq lookup table at %p, entry count %u\n",
1092                  fq_table, num_fqids * 2);
1093         return 0;
1094 }
1095
1096 static struct qman_fq *idx_to_fq(u32 idx)
1097 {
1098         struct qman_fq *fq;
1099
1100 #ifdef CONFIG_FSL_DPAA_CHECKING
1101         if (WARN_ON(idx >= num_fqids * 2))
1102                 return NULL;
1103 #endif
1104         fq = fq_table[idx];
1105         DPAA_ASSERT(!fq || idx == fq->idx);
1106
1107         return fq;
1108 }
1109
1110 /*
1111  * Only returns full-service fq objects, not enqueue-only
1112  * references (QMAN_FQ_FLAG_NO_MODIFY).
1113  */
1114 static struct qman_fq *fqid_to_fq(u32 fqid)
1115 {
1116         return idx_to_fq(fqid * 2);
1117 }
1118
1119 static struct qman_fq *tag_to_fq(u32 tag)
1120 {
1121 #if BITS_PER_LONG == 64
1122         return idx_to_fq(tag);
1123 #else
1124         return (struct qman_fq *)tag;
1125 #endif
1126 }
1127
1128 static u32 fq_to_tag(struct qman_fq *fq)
1129 {
1130 #if BITS_PER_LONG == 64
1131         return fq->idx;
1132 #else
1133         return (u32)fq;
1134 #endif
1135 }
1136
1137 static u32 __poll_portal_slow(struct qman_portal *p, u32 is);
1138 static inline unsigned int __poll_portal_fast(struct qman_portal *p,
1139                                         unsigned int poll_limit);
1140 static void qm_congestion_task(struct work_struct *work);
1141 static void qm_mr_process_task(struct work_struct *work);
1142
1143 static irqreturn_t portal_isr(int irq, void *ptr)
1144 {
1145         struct qman_portal *p = ptr;
1146
1147         u32 clear = QM_DQAVAIL_MASK | p->irq_sources;
1148         u32 is = qm_in(&p->p, QM_REG_ISR) & p->irq_sources;
1149
1150         if (unlikely(!is))
1151                 return IRQ_NONE;
1152
1153         /* DQRR-handling if it's interrupt-driven */
1154         if (is & QM_PIRQ_DQRI)
1155                 __poll_portal_fast(p, QMAN_POLL_LIMIT);
1156         /* Handling of anything else that's interrupt-driven */
1157         clear |= __poll_portal_slow(p, is);
1158         qm_out(&p->p, QM_REG_ISR, clear);
1159         return IRQ_HANDLED;
1160 }
1161
1162 static int drain_mr_fqrni(struct qm_portal *p)
1163 {
1164         const union qm_mr_entry *msg;
1165 loop:
1166         msg = qm_mr_current(p);
1167         if (!msg) {
1168                 /*
1169                  * if MR was full and h/w had other FQRNI entries to produce, we
1170                  * need to allow it time to produce those entries once the
1171                  * existing entries are consumed. A worst-case situation
1172                  * (fully-loaded system) means h/w sequencers may have to do 3-4
1173                  * other things before servicing the portal's MR pump, each of
1174                  * which (if slow) may take ~50 qman cycles (which is ~200
1175                  * processor cycles). So rounding up and then multiplying this
1176                  * worst-case estimate by a factor of 10, just to be
1177                  * ultra-paranoid, goes as high as 10,000 cycles. NB, we consume
1178                  * one entry at a time, so h/w has an opportunity to produce new
1179                  * entries well before the ring has been fully consumed, so
1180                  * we're being *really* paranoid here.
1181                  */
1182                 msleep(1);
1183                 msg = qm_mr_current(p);
1184                 if (!msg)
1185                         return 0;
1186         }
1187         if ((msg->verb & QM_MR_VERB_TYPE_MASK) != QM_MR_VERB_FQRNI) {
1188                 /* We aren't draining anything but FQRNIs */
1189                 pr_err("Found verb 0x%x in MR\n", msg->verb);
1190                 return -1;
1191         }
1192         qm_mr_next(p);
1193         qm_mr_cci_consume(p, 1);
1194         goto loop;
1195 }
1196
1197 static int qman_create_portal(struct qman_portal *portal,
1198                               const struct qm_portal_config *c,
1199                               const struct qman_cgrs *cgrs)
1200 {
1201         struct qm_portal *p;
1202         int ret;
1203         u32 isdr;
1204
1205         p = &portal->p;
1206
1207 #ifdef CONFIG_FSL_PAMU
1208         /* PAMU is required for stashing */
1209         portal->use_eqcr_ci_stashing = ((qman_ip_rev >= QMAN_REV30) ? 1 : 0);
1210 #else
1211         portal->use_eqcr_ci_stashing = 0;
1212 #endif
1213         /*
1214          * prep the low-level portal struct with the mapped addresses from the
1215          * config, everything that follows depends on it and "config" is more
1216          * for (de)reference
1217          */
1218         p->addr.ce = c->addr_virt_ce;
1219         p->addr.ce_be = c->addr_virt_ce;
1220         p->addr.ci = c->addr_virt_ci;
1221         /*
1222          * If CI-stashing is used, the current defaults use a threshold of 3,
1223          * and stash with high-than-DQRR priority.
1224          */
1225         if (qm_eqcr_init(p, qm_eqcr_pvb,
1226                         portal->use_eqcr_ci_stashing ? 3 : 0, 1)) {
1227                 dev_err(c->dev, "EQCR initialisation failed\n");
1228                 goto fail_eqcr;
1229         }
1230         if (qm_dqrr_init(p, c, qm_dqrr_dpush, qm_dqrr_pvb,
1231                         qm_dqrr_cdc, DQRR_MAXFILL)) {
1232                 dev_err(c->dev, "DQRR initialisation failed\n");
1233                 goto fail_dqrr;
1234         }
1235         if (qm_mr_init(p, qm_mr_pvb, qm_mr_cci)) {
1236                 dev_err(c->dev, "MR initialisation failed\n");
1237                 goto fail_mr;
1238         }
1239         if (qm_mc_init(p)) {
1240                 dev_err(c->dev, "MC initialisation failed\n");
1241                 goto fail_mc;
1242         }
1243         /* static interrupt-gating controls */
1244         qm_dqrr_set_ithresh(p, QMAN_PIRQ_DQRR_ITHRESH);
1245         qm_mr_set_ithresh(p, QMAN_PIRQ_MR_ITHRESH);
1246         qm_out(p, QM_REG_ITPR, QMAN_PIRQ_IPERIOD);
1247         portal->cgrs = kmalloc_array(2, sizeof(*cgrs), GFP_KERNEL);
1248         if (!portal->cgrs)
1249                 goto fail_cgrs;
1250         /* initial snapshot is no-depletion */
1251         qman_cgrs_init(&portal->cgrs[1]);
1252         if (cgrs)
1253                 portal->cgrs[0] = *cgrs;
1254         else
1255                 /* if the given mask is NULL, assume all CGRs can be seen */
1256                 qman_cgrs_fill(&portal->cgrs[0]);
1257         INIT_LIST_HEAD(&portal->cgr_cbs);
1258         spin_lock_init(&portal->cgr_lock);
1259         INIT_WORK(&portal->congestion_work, qm_congestion_task);
1260         INIT_WORK(&portal->mr_work, qm_mr_process_task);
1261         portal->bits = 0;
1262         portal->sdqcr = QM_SDQCR_SOURCE_CHANNELS | QM_SDQCR_COUNT_UPTO3 |
1263                         QM_SDQCR_DEDICATED_PRECEDENCE | QM_SDQCR_TYPE_PRIO_QOS |
1264                         QM_SDQCR_TOKEN_SET(0xab) | QM_SDQCR_CHANNELS_DEDICATED;
1265         isdr = 0xffffffff;
1266         qm_out(p, QM_REG_ISDR, isdr);
1267         portal->irq_sources = 0;
1268         qm_out(p, QM_REG_IER, 0);
1269         qm_out(p, QM_REG_ISR, 0xffffffff);
1270         snprintf(portal->irqname, MAX_IRQNAME, IRQNAME, c->cpu);
1271         if (request_irq(c->irq, portal_isr, 0, portal->irqname, portal)) {
1272                 dev_err(c->dev, "request_irq() failed\n");
1273                 goto fail_irq;
1274         }
1275
1276         if (dpaa_set_portal_irq_affinity(c->dev, c->irq, c->cpu))
1277                 goto fail_affinity;
1278
1279         /* Need EQCR to be empty before continuing */
1280         isdr &= ~QM_PIRQ_EQCI;
1281         qm_out(p, QM_REG_ISDR, isdr);
1282         ret = qm_eqcr_get_fill(p);
1283         if (ret) {
1284                 dev_err(c->dev, "EQCR unclean\n");
1285                 goto fail_eqcr_empty;
1286         }
1287         isdr &= ~(QM_PIRQ_DQRI | QM_PIRQ_MRI);
1288         qm_out(p, QM_REG_ISDR, isdr);
1289         if (qm_dqrr_current(p)) {
1290                 dev_err(c->dev, "DQRR unclean\n");
1291                 qm_dqrr_cdc_consume_n(p, 0xffff);
1292         }
1293         if (qm_mr_current(p) && drain_mr_fqrni(p)) {
1294                 /* special handling, drain just in case it's a few FQRNIs */
1295                 const union qm_mr_entry *e = qm_mr_current(p);
1296
1297                 dev_err(c->dev, "MR dirty, VB 0x%x, rc 0x%x, addr 0x%llx\n",
1298                         e->verb, e->ern.rc, qm_fd_addr_get64(&e->ern.fd));
1299                 goto fail_dqrr_mr_empty;
1300         }
1301         /* Success */
1302         portal->config = c;
1303         qm_out(p, QM_REG_ISDR, 0);
1304         qm_out(p, QM_REG_IIR, 0);
1305         /* Write a sane SDQCR */
1306         qm_dqrr_sdqcr_set(p, portal->sdqcr);
1307         return 0;
1308
1309 fail_dqrr_mr_empty:
1310 fail_eqcr_empty:
1311 fail_affinity:
1312         free_irq(c->irq, portal);
1313 fail_irq:
1314         kfree(portal->cgrs);
1315 fail_cgrs:
1316         qm_mc_finish(p);
1317 fail_mc:
1318         qm_mr_finish(p);
1319 fail_mr:
1320         qm_dqrr_finish(p);
1321 fail_dqrr:
1322         qm_eqcr_finish(p);
1323 fail_eqcr:
1324         return -EIO;
1325 }
1326
1327 struct qman_portal *qman_create_affine_portal(const struct qm_portal_config *c,
1328                                               const struct qman_cgrs *cgrs)
1329 {
1330         struct qman_portal *portal;
1331         int err;
1332
1333         portal = &per_cpu(qman_affine_portal, c->cpu);
1334         err = qman_create_portal(portal, c, cgrs);
1335         if (err)
1336                 return NULL;
1337
1338         spin_lock(&affine_mask_lock);
1339         cpumask_set_cpu(c->cpu, &affine_mask);
1340         affine_channels[c->cpu] = c->channel;
1341         affine_portals[c->cpu] = portal;
1342         spin_unlock(&affine_mask_lock);
1343
1344         return portal;
1345 }
1346
1347 static void qman_destroy_portal(struct qman_portal *qm)
1348 {
1349         const struct qm_portal_config *pcfg;
1350
1351         /* Stop dequeues on the portal */
1352         qm_dqrr_sdqcr_set(&qm->p, 0);
1353
1354         /*
1355          * NB we do this to "quiesce" EQCR. If we add enqueue-completions or
1356          * something related to QM_PIRQ_EQCI, this may need fixing.
1357          * Also, due to the prefetching model used for CI updates in the enqueue
1358          * path, this update will only invalidate the CI cacheline *after*
1359          * working on it, so we need to call this twice to ensure a full update
1360          * irrespective of where the enqueue processing was at when the teardown
1361          * began.
1362          */
1363         qm_eqcr_cce_update(&qm->p);
1364         qm_eqcr_cce_update(&qm->p);
1365         pcfg = qm->config;
1366
1367         free_irq(pcfg->irq, qm);
1368
1369         kfree(qm->cgrs);
1370         qm_mc_finish(&qm->p);
1371         qm_mr_finish(&qm->p);
1372         qm_dqrr_finish(&qm->p);
1373         qm_eqcr_finish(&qm->p);
1374
1375         qm->config = NULL;
1376 }
1377
1378 const struct qm_portal_config *qman_destroy_affine_portal(void)
1379 {
1380         struct qman_portal *qm = get_affine_portal();
1381         const struct qm_portal_config *pcfg;
1382         int cpu;
1383
1384         pcfg = qm->config;
1385         cpu = pcfg->cpu;
1386
1387         qman_destroy_portal(qm);
1388
1389         spin_lock(&affine_mask_lock);
1390         cpumask_clear_cpu(cpu, &affine_mask);
1391         spin_unlock(&affine_mask_lock);
1392         put_affine_portal();
1393         return pcfg;
1394 }
1395
1396 /* Inline helper to reduce nesting in __poll_portal_slow() */
1397 static inline void fq_state_change(struct qman_portal *p, struct qman_fq *fq,
1398                                    const union qm_mr_entry *msg, u8 verb)
1399 {
1400         switch (verb) {
1401         case QM_MR_VERB_FQRL:
1402                 DPAA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_ORL));
1403                 fq_clear(fq, QMAN_FQ_STATE_ORL);
1404                 break;
1405         case QM_MR_VERB_FQRN:
1406                 DPAA_ASSERT(fq->state == qman_fq_state_parked ||
1407                             fq->state == qman_fq_state_sched);
1408                 DPAA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_CHANGING));
1409                 fq_clear(fq, QMAN_FQ_STATE_CHANGING);
1410                 if (msg->fq.fqs & QM_MR_FQS_NOTEMPTY)
1411                         fq_set(fq, QMAN_FQ_STATE_NE);
1412                 if (msg->fq.fqs & QM_MR_FQS_ORLPRESENT)
1413                         fq_set(fq, QMAN_FQ_STATE_ORL);
1414                 fq->state = qman_fq_state_retired;
1415                 break;
1416         case QM_MR_VERB_FQPN:
1417                 DPAA_ASSERT(fq->state == qman_fq_state_sched);
1418                 DPAA_ASSERT(fq_isclear(fq, QMAN_FQ_STATE_CHANGING));
1419                 fq->state = qman_fq_state_parked;
1420         }
1421 }
1422
1423 static void qm_congestion_task(struct work_struct *work)
1424 {
1425         struct qman_portal *p = container_of(work, struct qman_portal,
1426                                              congestion_work);
1427         struct qman_cgrs rr, c;
1428         union qm_mc_result *mcr;
1429         struct qman_cgr *cgr;
1430
1431         spin_lock(&p->cgr_lock);
1432         qm_mc_start(&p->p);
1433         qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCONGESTION);
1434         if (!qm_mc_result_timeout(&p->p, &mcr)) {
1435                 spin_unlock(&p->cgr_lock);
1436                 dev_crit(p->config->dev, "QUERYCONGESTION timeout\n");
1437                 qman_p_irqsource_add(p, QM_PIRQ_CSCI);
1438                 return;
1439         }
1440         /* mask out the ones I'm not interested in */
1441         qman_cgrs_and(&rr, (struct qman_cgrs *)&mcr->querycongestion.state,
1442                       &p->cgrs[0]);
1443         /* check previous snapshot for delta, enter/exit congestion */
1444         qman_cgrs_xor(&c, &rr, &p->cgrs[1]);
1445         /* update snapshot */
1446         qman_cgrs_cp(&p->cgrs[1], &rr);
1447         /* Invoke callback */
1448         list_for_each_entry(cgr, &p->cgr_cbs, node)
1449                 if (cgr->cb && qman_cgrs_get(&c, cgr->cgrid))
1450                         cgr->cb(p, cgr, qman_cgrs_get(&rr, cgr->cgrid));
1451         spin_unlock(&p->cgr_lock);
1452         qman_p_irqsource_add(p, QM_PIRQ_CSCI);
1453 }
1454
1455 static void qm_mr_process_task(struct work_struct *work)
1456 {
1457         struct qman_portal *p = container_of(work, struct qman_portal,
1458                                              mr_work);
1459         const union qm_mr_entry *msg;
1460         struct qman_fq *fq;
1461         u8 verb, num = 0;
1462
1463         preempt_disable();
1464
1465         while (1) {
1466                 qm_mr_pvb_update(&p->p);
1467                 msg = qm_mr_current(&p->p);
1468                 if (!msg)
1469                         break;
1470
1471                 verb = msg->verb & QM_MR_VERB_TYPE_MASK;
1472                 /* The message is a software ERN iff the 0x20 bit is clear */
1473                 if (verb & 0x20) {
1474                         switch (verb) {
1475                         case QM_MR_VERB_FQRNI:
1476                                 /* nada, we drop FQRNIs on the floor */
1477                                 break;
1478                         case QM_MR_VERB_FQRN:
1479                         case QM_MR_VERB_FQRL:
1480                                 /* Lookup in the retirement table */
1481                                 fq = fqid_to_fq(qm_fqid_get(&msg->fq));
1482                                 if (WARN_ON(!fq))
1483                                         break;
1484                                 fq_state_change(p, fq, msg, verb);
1485                                 if (fq->cb.fqs)
1486                                         fq->cb.fqs(p, fq, msg);
1487                                 break;
1488                         case QM_MR_VERB_FQPN:
1489                                 /* Parked */
1490                                 fq = tag_to_fq(be32_to_cpu(msg->fq.context_b));
1491                                 fq_state_change(p, fq, msg, verb);
1492                                 if (fq->cb.fqs)
1493                                         fq->cb.fqs(p, fq, msg);
1494                                 break;
1495                         case QM_MR_VERB_DC_ERN:
1496                                 /* DCP ERN */
1497                                 pr_crit_once("Leaking DCP ERNs!\n");
1498                                 break;
1499                         default:
1500                                 pr_crit("Invalid MR verb 0x%02x\n", verb);
1501                         }
1502                 } else {
1503                         /* Its a software ERN */
1504                         fq = tag_to_fq(be32_to_cpu(msg->ern.tag));
1505                         fq->cb.ern(p, fq, msg);
1506                 }
1507                 num++;
1508                 qm_mr_next(&p->p);
1509         }
1510
1511         qm_mr_cci_consume(&p->p, num);
1512         qman_p_irqsource_add(p, QM_PIRQ_MRI);
1513         preempt_enable();
1514 }
1515
1516 static u32 __poll_portal_slow(struct qman_portal *p, u32 is)
1517 {
1518         if (is & QM_PIRQ_CSCI) {
1519                 qman_p_irqsource_remove(p, QM_PIRQ_CSCI);
1520                 queue_work_on(smp_processor_id(), qm_portal_wq,
1521                               &p->congestion_work);
1522         }
1523
1524         if (is & QM_PIRQ_EQRI) {
1525                 qm_eqcr_cce_update(&p->p);
1526                 qm_eqcr_set_ithresh(&p->p, 0);
1527                 wake_up(&affine_queue);
1528         }
1529
1530         if (is & QM_PIRQ_MRI) {
1531                 qman_p_irqsource_remove(p, QM_PIRQ_MRI);
1532                 queue_work_on(smp_processor_id(), qm_portal_wq,
1533                               &p->mr_work);
1534         }
1535
1536         return is;
1537 }
1538
1539 /*
1540  * remove some slowish-path stuff from the "fast path" and make sure it isn't
1541  * inlined.
1542  */
1543 static noinline void clear_vdqcr(struct qman_portal *p, struct qman_fq *fq)
1544 {
1545         p->vdqcr_owned = NULL;
1546         fq_clear(fq, QMAN_FQ_STATE_VDQCR);
1547         wake_up(&affine_queue);
1548 }
1549
1550 /*
1551  * The only states that would conflict with other things if they ran at the
1552  * same time on the same cpu are:
1553  *
1554  *   (i) setting/clearing vdqcr_owned, and
1555  *  (ii) clearing the NE (Not Empty) flag.
1556  *
1557  * Both are safe. Because;
1558  *
1559  *   (i) this clearing can only occur after qman_volatile_dequeue() has set the
1560  *       vdqcr_owned field (which it does before setting VDQCR), and
1561  *       qman_volatile_dequeue() blocks interrupts and preemption while this is
1562  *       done so that we can't interfere.
1563  *  (ii) the NE flag is only cleared after qman_retire_fq() has set it, and as
1564  *       with (i) that API prevents us from interfering until it's safe.
1565  *
1566  * The good thing is that qman_volatile_dequeue() and qman_retire_fq() run far
1567  * less frequently (ie. per-FQ) than __poll_portal_fast() does, so the nett
1568  * advantage comes from this function not having to "lock" anything at all.
1569  *
1570  * Note also that the callbacks are invoked at points which are safe against the
1571  * above potential conflicts, but that this function itself is not re-entrant
1572  * (this is because the function tracks one end of each FIFO in the portal and
1573  * we do *not* want to lock that). So the consequence is that it is safe for
1574  * user callbacks to call into any QMan API.
1575  */
1576 static inline unsigned int __poll_portal_fast(struct qman_portal *p,
1577                                         unsigned int poll_limit)
1578 {
1579         const struct qm_dqrr_entry *dq;
1580         struct qman_fq *fq;
1581         enum qman_cb_dqrr_result res;
1582         unsigned int limit = 0;
1583
1584         do {
1585                 qm_dqrr_pvb_update(&p->p);
1586                 dq = qm_dqrr_current(&p->p);
1587                 if (!dq)
1588                         break;
1589
1590                 if (dq->stat & QM_DQRR_STAT_UNSCHEDULED) {
1591                         /*
1592                          * VDQCR: don't trust context_b as the FQ may have
1593                          * been configured for h/w consumption and we're
1594                          * draining it post-retirement.
1595                          */
1596                         fq = p->vdqcr_owned;
1597                         /*
1598                          * We only set QMAN_FQ_STATE_NE when retiring, so we
1599                          * only need to check for clearing it when doing
1600                          * volatile dequeues.  It's one less thing to check
1601                          * in the critical path (SDQCR).
1602                          */
1603                         if (dq->stat & QM_DQRR_STAT_FQ_EMPTY)
1604                                 fq_clear(fq, QMAN_FQ_STATE_NE);
1605                         /*
1606                          * This is duplicated from the SDQCR code, but we
1607                          * have stuff to do before *and* after this callback,
1608                          * and we don't want multiple if()s in the critical
1609                          * path (SDQCR).
1610                          */
1611                         res = fq->cb.dqrr(p, fq, dq);
1612                         if (res == qman_cb_dqrr_stop)
1613                                 break;
1614                         /* Check for VDQCR completion */
1615                         if (dq->stat & QM_DQRR_STAT_DQCR_EXPIRED)
1616                                 clear_vdqcr(p, fq);
1617                 } else {
1618                         /* SDQCR: context_b points to the FQ */
1619                         fq = tag_to_fq(be32_to_cpu(dq->context_b));
1620                         /* Now let the callback do its stuff */
1621                         res = fq->cb.dqrr(p, fq, dq);
1622                         /*
1623                          * The callback can request that we exit without
1624                          * consuming this entry nor advancing;
1625                          */
1626                         if (res == qman_cb_dqrr_stop)
1627                                 break;
1628                 }
1629                 /* Interpret 'dq' from a driver perspective. */
1630                 /*
1631                  * Parking isn't possible unless HELDACTIVE was set. NB,
1632                  * FORCEELIGIBLE implies HELDACTIVE, so we only need to
1633                  * check for HELDACTIVE to cover both.
1634                  */
1635                 DPAA_ASSERT((dq->stat & QM_DQRR_STAT_FQ_HELDACTIVE) ||
1636                             (res != qman_cb_dqrr_park));
1637                 /* just means "skip it, I'll consume it myself later on" */
1638                 if (res != qman_cb_dqrr_defer)
1639                         qm_dqrr_cdc_consume_1ptr(&p->p, dq,
1640                                                  res == qman_cb_dqrr_park);
1641                 /* Move forward */
1642                 qm_dqrr_next(&p->p);
1643                 /*
1644                  * Entry processed and consumed, increment our counter.  The
1645                  * callback can request that we exit after consuming the
1646                  * entry, and we also exit if we reach our processing limit,
1647                  * so loop back only if neither of these conditions is met.
1648                  */
1649         } while (++limit < poll_limit && res != qman_cb_dqrr_consume_stop);
1650
1651         return limit;
1652 }
1653
1654 void qman_p_irqsource_add(struct qman_portal *p, u32 bits)
1655 {
1656         unsigned long irqflags;
1657
1658         local_irq_save(irqflags);
1659         p->irq_sources |= bits & QM_PIRQ_VISIBLE;
1660         qm_out(&p->p, QM_REG_IER, p->irq_sources);
1661         local_irq_restore(irqflags);
1662 }
1663 EXPORT_SYMBOL(qman_p_irqsource_add);
1664
1665 void qman_p_irqsource_remove(struct qman_portal *p, u32 bits)
1666 {
1667         unsigned long irqflags;
1668         u32 ier;
1669
1670         /*
1671          * Our interrupt handler only processes+clears status register bits that
1672          * are in p->irq_sources. As we're trimming that mask, if one of them
1673          * were to assert in the status register just before we remove it from
1674          * the enable register, there would be an interrupt-storm when we
1675          * release the IRQ lock. So we wait for the enable register update to
1676          * take effect in h/w (by reading it back) and then clear all other bits
1677          * in the status register. Ie. we clear them from ISR once it's certain
1678          * IER won't allow them to reassert.
1679          */
1680         local_irq_save(irqflags);
1681         bits &= QM_PIRQ_VISIBLE;
1682         p->irq_sources &= ~bits;
1683         qm_out(&p->p, QM_REG_IER, p->irq_sources);
1684         ier = qm_in(&p->p, QM_REG_IER);
1685         /*
1686          * Using "~ier" (rather than "bits" or "~p->irq_sources") creates a
1687          * data-dependency, ie. to protect against re-ordering.
1688          */
1689         qm_out(&p->p, QM_REG_ISR, ~ier);
1690         local_irq_restore(irqflags);
1691 }
1692 EXPORT_SYMBOL(qman_p_irqsource_remove);
1693
1694 const cpumask_t *qman_affine_cpus(void)
1695 {
1696         return &affine_mask;
1697 }
1698 EXPORT_SYMBOL(qman_affine_cpus);
1699
1700 u16 qman_affine_channel(int cpu)
1701 {
1702         if (cpu < 0) {
1703                 struct qman_portal *portal = get_affine_portal();
1704
1705                 cpu = portal->config->cpu;
1706                 put_affine_portal();
1707         }
1708         WARN_ON(!cpumask_test_cpu(cpu, &affine_mask));
1709         return affine_channels[cpu];
1710 }
1711 EXPORT_SYMBOL(qman_affine_channel);
1712
1713 struct qman_portal *qman_get_affine_portal(int cpu)
1714 {
1715         return affine_portals[cpu];
1716 }
1717 EXPORT_SYMBOL(qman_get_affine_portal);
1718
1719 int qman_p_poll_dqrr(struct qman_portal *p, unsigned int limit)
1720 {
1721         return __poll_portal_fast(p, limit);
1722 }
1723 EXPORT_SYMBOL(qman_p_poll_dqrr);
1724
1725 void qman_p_static_dequeue_add(struct qman_portal *p, u32 pools)
1726 {
1727         unsigned long irqflags;
1728
1729         local_irq_save(irqflags);
1730         pools &= p->config->pools;
1731         p->sdqcr |= pools;
1732         qm_dqrr_sdqcr_set(&p->p, p->sdqcr);
1733         local_irq_restore(irqflags);
1734 }
1735 EXPORT_SYMBOL(qman_p_static_dequeue_add);
1736
1737 /* Frame queue API */
1738
1739 static const char *mcr_result_str(u8 result)
1740 {
1741         switch (result) {
1742         case QM_MCR_RESULT_NULL:
1743                 return "QM_MCR_RESULT_NULL";
1744         case QM_MCR_RESULT_OK:
1745                 return "QM_MCR_RESULT_OK";
1746         case QM_MCR_RESULT_ERR_FQID:
1747                 return "QM_MCR_RESULT_ERR_FQID";
1748         case QM_MCR_RESULT_ERR_FQSTATE:
1749                 return "QM_MCR_RESULT_ERR_FQSTATE";
1750         case QM_MCR_RESULT_ERR_NOTEMPTY:
1751                 return "QM_MCR_RESULT_ERR_NOTEMPTY";
1752         case QM_MCR_RESULT_PENDING:
1753                 return "QM_MCR_RESULT_PENDING";
1754         case QM_MCR_RESULT_ERR_BADCOMMAND:
1755                 return "QM_MCR_RESULT_ERR_BADCOMMAND";
1756         }
1757         return "<unknown MCR result>";
1758 }
1759
1760 int qman_create_fq(u32 fqid, u32 flags, struct qman_fq *fq)
1761 {
1762         if (flags & QMAN_FQ_FLAG_DYNAMIC_FQID) {
1763                 int ret = qman_alloc_fqid(&fqid);
1764
1765                 if (ret)
1766                         return ret;
1767         }
1768         fq->fqid = fqid;
1769         fq->flags = flags;
1770         fq->state = qman_fq_state_oos;
1771         fq->cgr_groupid = 0;
1772
1773         /* A context_b of 0 is allegedly special, so don't use that fqid */
1774         if (fqid == 0 || fqid >= num_fqids) {
1775                 WARN(1, "bad fqid %d\n", fqid);
1776                 return -EINVAL;
1777         }
1778
1779         fq->idx = fqid * 2;
1780         if (flags & QMAN_FQ_FLAG_NO_MODIFY)
1781                 fq->idx++;
1782
1783         WARN_ON(fq_table[fq->idx]);
1784         fq_table[fq->idx] = fq;
1785
1786         return 0;
1787 }
1788 EXPORT_SYMBOL(qman_create_fq);
1789
1790 void qman_destroy_fq(struct qman_fq *fq)
1791 {
1792         /*
1793          * We don't need to lock the FQ as it is a pre-condition that the FQ be
1794          * quiesced. Instead, run some checks.
1795          */
1796         switch (fq->state) {
1797         case qman_fq_state_parked:
1798         case qman_fq_state_oos:
1799                 if (fq_isset(fq, QMAN_FQ_FLAG_DYNAMIC_FQID))
1800                         qman_release_fqid(fq->fqid);
1801
1802                 DPAA_ASSERT(fq_table[fq->idx]);
1803                 fq_table[fq->idx] = NULL;
1804                 return;
1805         default:
1806                 break;
1807         }
1808         DPAA_ASSERT(NULL == "qman_free_fq() on unquiesced FQ!");
1809 }
1810 EXPORT_SYMBOL(qman_destroy_fq);
1811
1812 u32 qman_fq_fqid(struct qman_fq *fq)
1813 {
1814         return fq->fqid;
1815 }
1816 EXPORT_SYMBOL(qman_fq_fqid);
1817
1818 int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts)
1819 {
1820         union qm_mc_command *mcc;
1821         union qm_mc_result *mcr;
1822         struct qman_portal *p;
1823         u8 res, myverb;
1824         int ret = 0;
1825
1826         myverb = (flags & QMAN_INITFQ_FLAG_SCHED)
1827                 ? QM_MCC_VERB_INITFQ_SCHED : QM_MCC_VERB_INITFQ_PARKED;
1828
1829         if (fq->state != qman_fq_state_oos &&
1830             fq->state != qman_fq_state_parked)
1831                 return -EINVAL;
1832 #ifdef CONFIG_FSL_DPAA_CHECKING
1833         if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1834                 return -EINVAL;
1835 #endif
1836         if (opts && (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_OAC)) {
1837                 /* And can't be set at the same time as TDTHRESH */
1838                 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_TDTHRESH)
1839                         return -EINVAL;
1840         }
1841         /* Issue an INITFQ_[PARKED|SCHED] management command */
1842         p = get_affine_portal();
1843         if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) ||
1844             (fq->state != qman_fq_state_oos &&
1845              fq->state != qman_fq_state_parked)) {
1846                 ret = -EBUSY;
1847                 goto out;
1848         }
1849         mcc = qm_mc_start(&p->p);
1850         if (opts)
1851                 mcc->initfq = *opts;
1852         qm_fqid_set(&mcc->fq, fq->fqid);
1853         mcc->initfq.count = 0;
1854         /*
1855          * If the FQ does *not* have the TO_DCPORTAL flag, context_b is set as a
1856          * demux pointer. Otherwise, the caller-provided value is allowed to
1857          * stand, don't overwrite it.
1858          */
1859         if (fq_isclear(fq, QMAN_FQ_FLAG_TO_DCPORTAL)) {
1860                 dma_addr_t phys_fq;
1861
1862                 mcc->initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CONTEXTB);
1863                 mcc->initfq.fqd.context_b = cpu_to_be32(fq_to_tag(fq));
1864                 /*
1865                  *  and the physical address - NB, if the user wasn't trying to
1866                  * set CONTEXTA, clear the stashing settings.
1867                  */
1868                 if (!(be16_to_cpu(mcc->initfq.we_mask) &
1869                                   QM_INITFQ_WE_CONTEXTA)) {
1870                         mcc->initfq.we_mask |=
1871                                 cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
1872                         memset(&mcc->initfq.fqd.context_a, 0,
1873                                 sizeof(mcc->initfq.fqd.context_a));
1874                 } else {
1875                         struct qman_portal *p = qman_dma_portal;
1876
1877                         phys_fq = dma_map_single(p->config->dev, fq,
1878                                                  sizeof(*fq), DMA_TO_DEVICE);
1879                         if (dma_mapping_error(p->config->dev, phys_fq)) {
1880                                 dev_err(p->config->dev, "dma_mapping failed\n");
1881                                 ret = -EIO;
1882                                 goto out;
1883                         }
1884
1885                         qm_fqd_stashing_set64(&mcc->initfq.fqd, phys_fq);
1886                 }
1887         }
1888         if (flags & QMAN_INITFQ_FLAG_LOCAL) {
1889                 int wq = 0;
1890
1891                 if (!(be16_to_cpu(mcc->initfq.we_mask) &
1892                                   QM_INITFQ_WE_DESTWQ)) {
1893                         mcc->initfq.we_mask |=
1894                                 cpu_to_be16(QM_INITFQ_WE_DESTWQ);
1895                         wq = 4;
1896                 }
1897                 qm_fqd_set_destwq(&mcc->initfq.fqd, p->config->channel, wq);
1898         }
1899         qm_mc_commit(&p->p, myverb);
1900         if (!qm_mc_result_timeout(&p->p, &mcr)) {
1901                 dev_err(p->config->dev, "MCR timeout\n");
1902                 ret = -ETIMEDOUT;
1903                 goto out;
1904         }
1905
1906         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == myverb);
1907         res = mcr->result;
1908         if (res != QM_MCR_RESULT_OK) {
1909                 ret = -EIO;
1910                 goto out;
1911         }
1912         if (opts) {
1913                 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_FQCTRL) {
1914                         if (be16_to_cpu(opts->fqd.fq_ctrl) & QM_FQCTRL_CGE)
1915                                 fq_set(fq, QMAN_FQ_STATE_CGR_EN);
1916                         else
1917                                 fq_clear(fq, QMAN_FQ_STATE_CGR_EN);
1918                 }
1919                 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_CGID)
1920                         fq->cgr_groupid = opts->fqd.cgid;
1921         }
1922         fq->state = (flags & QMAN_INITFQ_FLAG_SCHED) ?
1923                 qman_fq_state_sched : qman_fq_state_parked;
1924
1925 out:
1926         put_affine_portal();
1927         return ret;
1928 }
1929 EXPORT_SYMBOL(qman_init_fq);
1930
1931 int qman_schedule_fq(struct qman_fq *fq)
1932 {
1933         union qm_mc_command *mcc;
1934         union qm_mc_result *mcr;
1935         struct qman_portal *p;
1936         int ret = 0;
1937
1938         if (fq->state != qman_fq_state_parked)
1939                 return -EINVAL;
1940 #ifdef CONFIG_FSL_DPAA_CHECKING
1941         if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1942                 return -EINVAL;
1943 #endif
1944         /* Issue a ALTERFQ_SCHED management command */
1945         p = get_affine_portal();
1946         if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) ||
1947             fq->state != qman_fq_state_parked) {
1948                 ret = -EBUSY;
1949                 goto out;
1950         }
1951         mcc = qm_mc_start(&p->p);
1952         qm_fqid_set(&mcc->fq, fq->fqid);
1953         qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_SCHED);
1954         if (!qm_mc_result_timeout(&p->p, &mcr)) {
1955                 dev_err(p->config->dev, "ALTER_SCHED timeout\n");
1956                 ret = -ETIMEDOUT;
1957                 goto out;
1958         }
1959
1960         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_SCHED);
1961         if (mcr->result != QM_MCR_RESULT_OK) {
1962                 ret = -EIO;
1963                 goto out;
1964         }
1965         fq->state = qman_fq_state_sched;
1966 out:
1967         put_affine_portal();
1968         return ret;
1969 }
1970 EXPORT_SYMBOL(qman_schedule_fq);
1971
1972 int qman_retire_fq(struct qman_fq *fq, u32 *flags)
1973 {
1974         union qm_mc_command *mcc;
1975         union qm_mc_result *mcr;
1976         struct qman_portal *p;
1977         int ret;
1978         u8 res;
1979
1980         if (fq->state != qman_fq_state_parked &&
1981             fq->state != qman_fq_state_sched)
1982                 return -EINVAL;
1983 #ifdef CONFIG_FSL_DPAA_CHECKING
1984         if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1985                 return -EINVAL;
1986 #endif
1987         p = get_affine_portal();
1988         if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) ||
1989             fq->state == qman_fq_state_retired ||
1990             fq->state == qman_fq_state_oos) {
1991                 ret = -EBUSY;
1992                 goto out;
1993         }
1994         mcc = qm_mc_start(&p->p);
1995         qm_fqid_set(&mcc->fq, fq->fqid);
1996         qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_RETIRE);
1997         if (!qm_mc_result_timeout(&p->p, &mcr)) {
1998                 dev_crit(p->config->dev, "ALTER_RETIRE timeout\n");
1999                 ret = -ETIMEDOUT;
2000                 goto out;
2001         }
2002
2003         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_RETIRE);
2004         res = mcr->result;
2005         /*
2006          * "Elegant" would be to treat OK/PENDING the same way; set CHANGING,
2007          * and defer the flags until FQRNI or FQRN (respectively) show up. But
2008          * "Friendly" is to process OK immediately, and not set CHANGING. We do
2009          * friendly, otherwise the caller doesn't necessarily have a fully
2010          * "retired" FQ on return even if the retirement was immediate. However
2011          * this does mean some code duplication between here and
2012          * fq_state_change().
2013          */
2014         if (res == QM_MCR_RESULT_OK) {
2015                 ret = 0;
2016                 /* Process 'fq' right away, we'll ignore FQRNI */
2017                 if (mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY)
2018                         fq_set(fq, QMAN_FQ_STATE_NE);
2019                 if (mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)
2020                         fq_set(fq, QMAN_FQ_STATE_ORL);
2021                 if (flags)
2022                         *flags = fq->flags;
2023                 fq->state = qman_fq_state_retired;
2024                 if (fq->cb.fqs) {
2025                         /*
2026                          * Another issue with supporting "immediate" retirement
2027                          * is that we're forced to drop FQRNIs, because by the
2028                          * time they're seen it may already be "too late" (the
2029                          * fq may have been OOS'd and free()'d already). But if
2030                          * the upper layer wants a callback whether it's
2031                          * immediate or not, we have to fake a "MR" entry to
2032                          * look like an FQRNI...
2033                          */
2034                         union qm_mr_entry msg;
2035
2036                         msg.verb = QM_MR_VERB_FQRNI;
2037                         msg.fq.fqs = mcr->alterfq.fqs;
2038                         qm_fqid_set(&msg.fq, fq->fqid);
2039                         msg.fq.context_b = cpu_to_be32(fq_to_tag(fq));
2040                         fq->cb.fqs(p, fq, &msg);
2041                 }
2042         } else if (res == QM_MCR_RESULT_PENDING) {
2043                 ret = 1;
2044                 fq_set(fq, QMAN_FQ_STATE_CHANGING);
2045         } else {
2046                 ret = -EIO;
2047         }
2048 out:
2049         put_affine_portal();
2050         return ret;
2051 }
2052 EXPORT_SYMBOL(qman_retire_fq);
2053
2054 int qman_oos_fq(struct qman_fq *fq)
2055 {
2056         union qm_mc_command *mcc;
2057         union qm_mc_result *mcr;
2058         struct qman_portal *p;
2059         int ret = 0;
2060
2061         if (fq->state != qman_fq_state_retired)
2062                 return -EINVAL;
2063 #ifdef CONFIG_FSL_DPAA_CHECKING
2064         if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
2065                 return -EINVAL;
2066 #endif
2067         p = get_affine_portal();
2068         if (fq_isset(fq, QMAN_FQ_STATE_BLOCKOOS) ||
2069             fq->state != qman_fq_state_retired) {
2070                 ret = -EBUSY;
2071                 goto out;
2072         }
2073         mcc = qm_mc_start(&p->p);
2074         qm_fqid_set(&mcc->fq, fq->fqid);
2075         qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
2076         if (!qm_mc_result_timeout(&p->p, &mcr)) {
2077                 ret = -ETIMEDOUT;
2078                 goto out;
2079         }
2080         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_OOS);
2081         if (mcr->result != QM_MCR_RESULT_OK) {
2082                 ret = -EIO;
2083                 goto out;
2084         }
2085         fq->state = qman_fq_state_oos;
2086 out:
2087         put_affine_portal();
2088         return ret;
2089 }
2090 EXPORT_SYMBOL(qman_oos_fq);
2091
2092 int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd)
2093 {
2094         union qm_mc_command *mcc;
2095         union qm_mc_result *mcr;
2096         struct qman_portal *p = get_affine_portal();
2097         int ret = 0;
2098
2099         mcc = qm_mc_start(&p->p);
2100         qm_fqid_set(&mcc->fq, fq->fqid);
2101         qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ);
2102         if (!qm_mc_result_timeout(&p->p, &mcr)) {
2103                 ret = -ETIMEDOUT;
2104                 goto out;
2105         }
2106
2107         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ);
2108         if (mcr->result == QM_MCR_RESULT_OK)
2109                 *fqd = mcr->queryfq.fqd;
2110         else
2111                 ret = -EIO;
2112 out:
2113         put_affine_portal();
2114         return ret;
2115 }
2116
2117 int qman_query_fq_np(struct qman_fq *fq, struct qm_mcr_queryfq_np *np)
2118 {
2119         union qm_mc_command *mcc;
2120         union qm_mc_result *mcr;
2121         struct qman_portal *p = get_affine_portal();
2122         int ret = 0;
2123
2124         mcc = qm_mc_start(&p->p);
2125         qm_fqid_set(&mcc->fq, fq->fqid);
2126         qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP);
2127         if (!qm_mc_result_timeout(&p->p, &mcr)) {
2128                 ret = -ETIMEDOUT;
2129                 goto out;
2130         }
2131
2132         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP);
2133         if (mcr->result == QM_MCR_RESULT_OK)
2134                 *np = mcr->queryfq_np;
2135         else if (mcr->result == QM_MCR_RESULT_ERR_FQID)
2136                 ret = -ERANGE;
2137         else
2138                 ret = -EIO;
2139 out:
2140         put_affine_portal();
2141         return ret;
2142 }
2143 EXPORT_SYMBOL(qman_query_fq_np);
2144
2145 static int qman_query_cgr(struct qman_cgr *cgr,
2146                           struct qm_mcr_querycgr *cgrd)
2147 {
2148         union qm_mc_command *mcc;
2149         union qm_mc_result *mcr;
2150         struct qman_portal *p = get_affine_portal();
2151         int ret = 0;
2152
2153         mcc = qm_mc_start(&p->p);
2154         mcc->cgr.cgid = cgr->cgrid;
2155         qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCGR);
2156         if (!qm_mc_result_timeout(&p->p, &mcr)) {
2157                 ret = -ETIMEDOUT;
2158                 goto out;
2159         }
2160         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_QUERYCGR);
2161         if (mcr->result == QM_MCR_RESULT_OK)
2162                 *cgrd = mcr->querycgr;
2163         else {
2164                 dev_err(p->config->dev, "QUERY_CGR failed: %s\n",
2165                         mcr_result_str(mcr->result));
2166                 ret = -EIO;
2167         }
2168 out:
2169         put_affine_portal();
2170         return ret;
2171 }
2172
2173 int qman_query_cgr_congested(struct qman_cgr *cgr, bool *result)
2174 {
2175         struct qm_mcr_querycgr query_cgr;
2176         int err;
2177
2178         err = qman_query_cgr(cgr, &query_cgr);
2179         if (err)
2180                 return err;
2181
2182         *result = !!query_cgr.cgr.cs;
2183         return 0;
2184 }
2185 EXPORT_SYMBOL(qman_query_cgr_congested);
2186
2187 /* internal function used as a wait_event() expression */
2188 static int set_p_vdqcr(struct qman_portal *p, struct qman_fq *fq, u32 vdqcr)
2189 {
2190         unsigned long irqflags;
2191         int ret = -EBUSY;
2192
2193         local_irq_save(irqflags);
2194         if (p->vdqcr_owned)
2195                 goto out;
2196         if (fq_isset(fq, QMAN_FQ_STATE_VDQCR))
2197                 goto out;
2198
2199         fq_set(fq, QMAN_FQ_STATE_VDQCR);
2200         p->vdqcr_owned = fq;
2201         qm_dqrr_vdqcr_set(&p->p, vdqcr);
2202         ret = 0;
2203 out:
2204         local_irq_restore(irqflags);
2205         return ret;
2206 }
2207
2208 static int set_vdqcr(struct qman_portal **p, struct qman_fq *fq, u32 vdqcr)
2209 {
2210         int ret;
2211
2212         *p = get_affine_portal();
2213         ret = set_p_vdqcr(*p, fq, vdqcr);
2214         put_affine_portal();
2215         return ret;
2216 }
2217
2218 static int wait_vdqcr_start(struct qman_portal **p, struct qman_fq *fq,
2219                                 u32 vdqcr, u32 flags)
2220 {
2221         int ret = 0;
2222
2223         if (flags & QMAN_VOLATILE_FLAG_WAIT_INT)
2224                 ret = wait_event_interruptible(affine_queue,
2225                                 !set_vdqcr(p, fq, vdqcr));
2226         else
2227                 wait_event(affine_queue, !set_vdqcr(p, fq, vdqcr));
2228         return ret;
2229 }
2230
2231 int qman_volatile_dequeue(struct qman_fq *fq, u32 flags, u32 vdqcr)
2232 {
2233         struct qman_portal *p;
2234         int ret;
2235
2236         if (fq->state != qman_fq_state_parked &&
2237             fq->state != qman_fq_state_retired)
2238                 return -EINVAL;
2239         if (vdqcr & QM_VDQCR_FQID_MASK)
2240                 return -EINVAL;
2241         if (fq_isset(fq, QMAN_FQ_STATE_VDQCR))
2242                 return -EBUSY;
2243         vdqcr = (vdqcr & ~QM_VDQCR_FQID_MASK) | fq->fqid;
2244         if (flags & QMAN_VOLATILE_FLAG_WAIT)
2245                 ret = wait_vdqcr_start(&p, fq, vdqcr, flags);
2246         else
2247                 ret = set_vdqcr(&p, fq, vdqcr);
2248         if (ret)
2249                 return ret;
2250         /* VDQCR is set */
2251         if (flags & QMAN_VOLATILE_FLAG_FINISH) {
2252                 if (flags & QMAN_VOLATILE_FLAG_WAIT_INT)
2253                         /*
2254                          * NB: don't propagate any error - the caller wouldn't
2255                          * know whether the VDQCR was issued or not. A signal
2256                          * could arrive after returning anyway, so the caller
2257                          * can check signal_pending() if that's an issue.
2258                          */
2259                         wait_event_interruptible(affine_queue,
2260                                 !fq_isset(fq, QMAN_FQ_STATE_VDQCR));
2261                 else
2262                         wait_event(affine_queue,
2263                                 !fq_isset(fq, QMAN_FQ_STATE_VDQCR));
2264         }
2265         return 0;
2266 }
2267 EXPORT_SYMBOL(qman_volatile_dequeue);
2268
2269 static void update_eqcr_ci(struct qman_portal *p, u8 avail)
2270 {
2271         if (avail)
2272                 qm_eqcr_cce_prefetch(&p->p);
2273         else
2274                 qm_eqcr_cce_update(&p->p);
2275 }
2276
2277 int qman_enqueue(struct qman_fq *fq, const struct qm_fd *fd)
2278 {
2279         struct qman_portal *p;
2280         struct qm_eqcr_entry *eq;
2281         unsigned long irqflags;
2282         u8 avail;
2283
2284         p = get_affine_portal();
2285         local_irq_save(irqflags);
2286
2287         if (p->use_eqcr_ci_stashing) {
2288                 /*
2289                  * The stashing case is easy, only update if we need to in
2290                  * order to try and liberate ring entries.
2291                  */
2292                 eq = qm_eqcr_start_stash(&p->p);
2293         } else {
2294                 /*
2295                  * The non-stashing case is harder, need to prefetch ahead of
2296                  * time.
2297                  */
2298                 avail = qm_eqcr_get_avail(&p->p);
2299                 if (avail < 2)
2300                         update_eqcr_ci(p, avail);
2301                 eq = qm_eqcr_start_no_stash(&p->p);
2302         }
2303
2304         if (unlikely(!eq))
2305                 goto out;
2306
2307         qm_fqid_set(eq, fq->fqid);
2308         eq->tag = cpu_to_be32(fq_to_tag(fq));
2309         eq->fd = *fd;
2310
2311         qm_eqcr_pvb_commit(&p->p, QM_EQCR_VERB_CMD_ENQUEUE);
2312 out:
2313         local_irq_restore(irqflags);
2314         put_affine_portal();
2315         return 0;
2316 }
2317 EXPORT_SYMBOL(qman_enqueue);
2318
2319 static int qm_modify_cgr(struct qman_cgr *cgr, u32 flags,
2320                          struct qm_mcc_initcgr *opts)
2321 {
2322         union qm_mc_command *mcc;
2323         union qm_mc_result *mcr;
2324         struct qman_portal *p = get_affine_portal();
2325         u8 verb = QM_MCC_VERB_MODIFYCGR;
2326         int ret = 0;
2327
2328         mcc = qm_mc_start(&p->p);
2329         if (opts)
2330                 mcc->initcgr = *opts;
2331         mcc->initcgr.cgid = cgr->cgrid;
2332         if (flags & QMAN_CGR_FLAG_USE_INIT)
2333                 verb = QM_MCC_VERB_INITCGR;
2334         qm_mc_commit(&p->p, verb);
2335         if (!qm_mc_result_timeout(&p->p, &mcr)) {
2336                 ret = -ETIMEDOUT;
2337                 goto out;
2338         }
2339
2340         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == verb);
2341         if (mcr->result != QM_MCR_RESULT_OK)
2342                 ret = -EIO;
2343
2344 out:
2345         put_affine_portal();
2346         return ret;
2347 }
2348
2349 #define PORTAL_IDX(n)   (n->config->channel - QM_CHANNEL_SWPORTAL0)
2350
2351 /* congestion state change notification target update control */
2352 static void qm_cgr_cscn_targ_set(struct __qm_mc_cgr *cgr, int pi, u32 val)
2353 {
2354         if (qman_ip_rev >= QMAN_REV30)
2355                 cgr->cscn_targ_upd_ctrl = cpu_to_be16(pi |
2356                                         QM_CGR_TARG_UDP_CTRL_WRITE_BIT);
2357         else
2358                 cgr->cscn_targ = cpu_to_be32(val | QM_CGR_TARG_PORTAL(pi));
2359 }
2360
2361 static void qm_cgr_cscn_targ_clear(struct __qm_mc_cgr *cgr, int pi, u32 val)
2362 {
2363         if (qman_ip_rev >= QMAN_REV30)
2364                 cgr->cscn_targ_upd_ctrl = cpu_to_be16(pi);
2365         else
2366                 cgr->cscn_targ = cpu_to_be32(val & ~QM_CGR_TARG_PORTAL(pi));
2367 }
2368
2369 static u8 qman_cgr_cpus[CGR_NUM];
2370
2371 void qman_init_cgr_all(void)
2372 {
2373         struct qman_cgr cgr;
2374         int err_cnt = 0;
2375
2376         for (cgr.cgrid = 0; cgr.cgrid < CGR_NUM; cgr.cgrid++) {
2377                 if (qm_modify_cgr(&cgr, QMAN_CGR_FLAG_USE_INIT, NULL))
2378                         err_cnt++;
2379         }
2380
2381         if (err_cnt)
2382                 pr_err("Warning: %d error%s while initialising CGR h/w\n",
2383                        err_cnt, (err_cnt > 1) ? "s" : "");
2384 }
2385
2386 int qman_create_cgr(struct qman_cgr *cgr, u32 flags,
2387                     struct qm_mcc_initcgr *opts)
2388 {
2389         struct qm_mcr_querycgr cgr_state;
2390         int ret;
2391         struct qman_portal *p;
2392
2393         /*
2394          * We have to check that the provided CGRID is within the limits of the
2395          * data-structures, for obvious reasons. However we'll let h/w take
2396          * care of determining whether it's within the limits of what exists on
2397          * the SoC.
2398          */
2399         if (cgr->cgrid >= CGR_NUM)
2400                 return -EINVAL;
2401
2402         preempt_disable();
2403         p = get_affine_portal();
2404         qman_cgr_cpus[cgr->cgrid] = smp_processor_id();
2405         preempt_enable();
2406
2407         cgr->chan = p->config->channel;
2408         spin_lock(&p->cgr_lock);
2409
2410         if (opts) {
2411                 struct qm_mcc_initcgr local_opts = *opts;
2412
2413                 ret = qman_query_cgr(cgr, &cgr_state);
2414                 if (ret)
2415                         goto out;
2416
2417                 qm_cgr_cscn_targ_set(&local_opts.cgr, PORTAL_IDX(p),
2418                                      be32_to_cpu(cgr_state.cgr.cscn_targ));
2419                 local_opts.we_mask |= cpu_to_be16(QM_CGR_WE_CSCN_TARG);
2420
2421                 /* send init if flags indicate so */
2422                 if (flags & QMAN_CGR_FLAG_USE_INIT)
2423                         ret = qm_modify_cgr(cgr, QMAN_CGR_FLAG_USE_INIT,
2424                                             &local_opts);
2425                 else
2426                         ret = qm_modify_cgr(cgr, 0, &local_opts);
2427                 if (ret)
2428                         goto out;
2429         }
2430
2431         list_add(&cgr->node, &p->cgr_cbs);
2432
2433         /* Determine if newly added object requires its callback to be called */
2434         ret = qman_query_cgr(cgr, &cgr_state);
2435         if (ret) {
2436                 /* we can't go back, so proceed and return success */
2437                 dev_err(p->config->dev, "CGR HW state partially modified\n");
2438                 ret = 0;
2439                 goto out;
2440         }
2441         if (cgr->cb && cgr_state.cgr.cscn_en &&
2442             qman_cgrs_get(&p->cgrs[1], cgr->cgrid))
2443                 cgr->cb(p, cgr, 1);
2444 out:
2445         spin_unlock(&p->cgr_lock);
2446         put_affine_portal();
2447         return ret;
2448 }
2449 EXPORT_SYMBOL(qman_create_cgr);
2450
2451 int qman_delete_cgr(struct qman_cgr *cgr)
2452 {
2453         unsigned long irqflags;
2454         struct qm_mcr_querycgr cgr_state;
2455         struct qm_mcc_initcgr local_opts;
2456         int ret = 0;
2457         struct qman_cgr *i;
2458         struct qman_portal *p = get_affine_portal();
2459
2460         if (cgr->chan != p->config->channel) {
2461                 /* attempt to delete from other portal than creator */
2462                 dev_err(p->config->dev, "CGR not owned by current portal");
2463                 dev_dbg(p->config->dev, " create 0x%x, delete 0x%x\n",
2464                         cgr->chan, p->config->channel);
2465
2466                 ret = -EINVAL;
2467                 goto put_portal;
2468         }
2469         memset(&local_opts, 0, sizeof(struct qm_mcc_initcgr));
2470         spin_lock_irqsave(&p->cgr_lock, irqflags);
2471         list_del(&cgr->node);
2472         /*
2473          * If there are no other CGR objects for this CGRID in the list,
2474          * update CSCN_TARG accordingly
2475          */
2476         list_for_each_entry(i, &p->cgr_cbs, node)
2477                 if (i->cgrid == cgr->cgrid && i->cb)
2478                         goto release_lock;
2479         ret = qman_query_cgr(cgr, &cgr_state);
2480         if (ret)  {
2481                 /* add back to the list */
2482                 list_add(&cgr->node, &p->cgr_cbs);
2483                 goto release_lock;
2484         }
2485
2486         local_opts.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_TARG);
2487         qm_cgr_cscn_targ_clear(&local_opts.cgr, PORTAL_IDX(p),
2488                                be32_to_cpu(cgr_state.cgr.cscn_targ));
2489
2490         ret = qm_modify_cgr(cgr, 0, &local_opts);
2491         if (ret)
2492                 /* add back to the list */
2493                 list_add(&cgr->node, &p->cgr_cbs);
2494 release_lock:
2495         spin_unlock_irqrestore(&p->cgr_lock, irqflags);
2496 put_portal:
2497         put_affine_portal();
2498         return ret;
2499 }
2500 EXPORT_SYMBOL(qman_delete_cgr);
2501
2502 struct cgr_comp {
2503         struct qman_cgr *cgr;
2504         struct completion completion;
2505 };
2506
2507 static void qman_delete_cgr_smp_call(void *p)
2508 {
2509         qman_delete_cgr((struct qman_cgr *)p);
2510 }
2511
2512 void qman_delete_cgr_safe(struct qman_cgr *cgr)
2513 {
2514         preempt_disable();
2515         if (qman_cgr_cpus[cgr->cgrid] != smp_processor_id()) {
2516                 smp_call_function_single(qman_cgr_cpus[cgr->cgrid],
2517                                          qman_delete_cgr_smp_call, cgr, true);
2518                 preempt_enable();
2519                 return;
2520         }
2521
2522         qman_delete_cgr(cgr);
2523         preempt_enable();
2524 }
2525 EXPORT_SYMBOL(qman_delete_cgr_safe);
2526
2527 /* Cleanup FQs */
2528
2529 static int _qm_mr_consume_and_match_verb(struct qm_portal *p, int v)
2530 {
2531         const union qm_mr_entry *msg;
2532         int found = 0;
2533
2534         qm_mr_pvb_update(p);
2535         msg = qm_mr_current(p);
2536         while (msg) {
2537                 if ((msg->verb & QM_MR_VERB_TYPE_MASK) == v)
2538                         found = 1;
2539                 qm_mr_next(p);
2540                 qm_mr_cci_consume_to_current(p);
2541                 qm_mr_pvb_update(p);
2542                 msg = qm_mr_current(p);
2543         }
2544         return found;
2545 }
2546
2547 static int _qm_dqrr_consume_and_match(struct qm_portal *p, u32 fqid, int s,
2548                                       bool wait)
2549 {
2550         const struct qm_dqrr_entry *dqrr;
2551         int found = 0;
2552
2553         do {
2554                 qm_dqrr_pvb_update(p);
2555                 dqrr = qm_dqrr_current(p);
2556                 if (!dqrr)
2557                         cpu_relax();
2558         } while (wait && !dqrr);
2559
2560         while (dqrr) {
2561                 if (qm_fqid_get(dqrr) == fqid && (dqrr->stat & s))
2562                         found = 1;
2563                 qm_dqrr_cdc_consume_1ptr(p, dqrr, 0);
2564                 qm_dqrr_pvb_update(p);
2565                 qm_dqrr_next(p);
2566                 dqrr = qm_dqrr_current(p);
2567         }
2568         return found;
2569 }
2570
2571 #define qm_mr_drain(p, V) \
2572         _qm_mr_consume_and_match_verb(p, QM_MR_VERB_##V)
2573
2574 #define qm_dqrr_drain(p, f, S) \
2575         _qm_dqrr_consume_and_match(p, f, QM_DQRR_STAT_##S, false)
2576
2577 #define qm_dqrr_drain_wait(p, f, S) \
2578         _qm_dqrr_consume_and_match(p, f, QM_DQRR_STAT_##S, true)
2579
2580 #define qm_dqrr_drain_nomatch(p) \
2581         _qm_dqrr_consume_and_match(p, 0, 0, false)
2582
2583 static int qman_shutdown_fq(u32 fqid)
2584 {
2585         struct qman_portal *p;
2586         struct device *dev;
2587         union qm_mc_command *mcc;
2588         union qm_mc_result *mcr;
2589         int orl_empty, drain = 0, ret = 0;
2590         u32 channel, wq, res;
2591         u8 state;
2592
2593         p = get_affine_portal();
2594         dev = p->config->dev;
2595         /* Determine the state of the FQID */
2596         mcc = qm_mc_start(&p->p);
2597         qm_fqid_set(&mcc->fq, fqid);
2598         qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP);
2599         if (!qm_mc_result_timeout(&p->p, &mcr)) {
2600                 dev_err(dev, "QUERYFQ_NP timeout\n");
2601                 ret = -ETIMEDOUT;
2602                 goto out;
2603         }
2604
2605         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP);
2606         state = mcr->queryfq_np.state & QM_MCR_NP_STATE_MASK;
2607         if (state == QM_MCR_NP_STATE_OOS)
2608                 goto out; /* Already OOS, no need to do anymore checks */
2609
2610         /* Query which channel the FQ is using */
2611         mcc = qm_mc_start(&p->p);
2612         qm_fqid_set(&mcc->fq, fqid);
2613         qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ);
2614         if (!qm_mc_result_timeout(&p->p, &mcr)) {
2615                 dev_err(dev, "QUERYFQ timeout\n");
2616                 ret = -ETIMEDOUT;
2617                 goto out;
2618         }
2619
2620         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ);
2621         /* Need to store these since the MCR gets reused */
2622         channel = qm_fqd_get_chan(&mcr->queryfq.fqd);
2623         wq = qm_fqd_get_wq(&mcr->queryfq.fqd);
2624
2625         switch (state) {
2626         case QM_MCR_NP_STATE_TEN_SCHED:
2627         case QM_MCR_NP_STATE_TRU_SCHED:
2628         case QM_MCR_NP_STATE_ACTIVE:
2629         case QM_MCR_NP_STATE_PARKED:
2630                 orl_empty = 0;
2631                 mcc = qm_mc_start(&p->p);
2632                 qm_fqid_set(&mcc->fq, fqid);
2633                 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_RETIRE);
2634                 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2635                         dev_err(dev, "QUERYFQ_NP timeout\n");
2636                         ret = -ETIMEDOUT;
2637                         goto out;
2638                 }
2639                 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2640                             QM_MCR_VERB_ALTER_RETIRE);
2641                 res = mcr->result; /* Make a copy as we reuse MCR below */
2642
2643                 if (res == QM_MCR_RESULT_PENDING) {
2644                         /*
2645                          * Need to wait for the FQRN in the message ring, which
2646                          * will only occur once the FQ has been drained.  In
2647                          * order for the FQ to drain the portal needs to be set
2648                          * to dequeue from the channel the FQ is scheduled on
2649                          */
2650                         int found_fqrn = 0;
2651                         u16 dequeue_wq = 0;
2652
2653                         /* Flag that we need to drain FQ */
2654                         drain = 1;
2655
2656                         if (channel >= qm_channel_pool1 &&
2657                             channel < qm_channel_pool1 + 15) {
2658                                 /* Pool channel, enable the bit in the portal */
2659                                 dequeue_wq = (channel -
2660                                               qm_channel_pool1 + 1)<<4 | wq;
2661                         } else if (channel < qm_channel_pool1) {
2662                                 /* Dedicated channel */
2663                                 dequeue_wq = wq;
2664                         } else {
2665                                 dev_err(dev, "Can't recover FQ 0x%x, ch: 0x%x",
2666                                         fqid, channel);
2667                                 ret = -EBUSY;
2668                                 goto out;
2669                         }
2670                         /* Set the sdqcr to drain this channel */
2671                         if (channel < qm_channel_pool1)
2672                                 qm_dqrr_sdqcr_set(&p->p,
2673                                                   QM_SDQCR_TYPE_ACTIVE |
2674                                                   QM_SDQCR_CHANNELS_DEDICATED);
2675                         else
2676                                 qm_dqrr_sdqcr_set(&p->p,
2677                                                   QM_SDQCR_TYPE_ACTIVE |
2678                                                   QM_SDQCR_CHANNELS_POOL_CONV
2679                                                   (channel));
2680                         do {
2681                                 /* Keep draining DQRR while checking the MR*/
2682                                 qm_dqrr_drain_nomatch(&p->p);
2683                                 /* Process message ring too */
2684                                 found_fqrn = qm_mr_drain(&p->p, FQRN);
2685                                 cpu_relax();
2686                         } while (!found_fqrn);
2687
2688                 }
2689                 if (res != QM_MCR_RESULT_OK &&
2690                     res != QM_MCR_RESULT_PENDING) {
2691                         dev_err(dev, "retire_fq failed: FQ 0x%x, res=0x%x\n",
2692                                 fqid, res);
2693                         ret = -EIO;
2694                         goto out;
2695                 }
2696                 if (!(mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)) {
2697                         /*
2698                          * ORL had no entries, no need to wait until the
2699                          * ERNs come in
2700                          */
2701                         orl_empty = 1;
2702                 }
2703                 /*
2704                  * Retirement succeeded, check to see if FQ needs
2705                  * to be drained
2706                  */
2707                 if (drain || mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY) {
2708                         /* FQ is Not Empty, drain using volatile DQ commands */
2709                         do {
2710                                 u32 vdqcr = fqid | QM_VDQCR_NUMFRAMES_SET(3);
2711
2712                                 qm_dqrr_vdqcr_set(&p->p, vdqcr);
2713                                 /*
2714                                  * Wait for a dequeue and process the dequeues,
2715                                  * making sure to empty the ring completely
2716                                  */
2717                         } while (qm_dqrr_drain_wait(&p->p, fqid, FQ_EMPTY));
2718                 }
2719                 qm_dqrr_sdqcr_set(&p->p, 0);
2720
2721                 while (!orl_empty) {
2722                         /* Wait for the ORL to have been completely drained */
2723                         orl_empty = qm_mr_drain(&p->p, FQRL);
2724                         cpu_relax();
2725                 }
2726                 mcc = qm_mc_start(&p->p);
2727                 qm_fqid_set(&mcc->fq, fqid);
2728                 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
2729                 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2730                         ret = -ETIMEDOUT;
2731                         goto out;
2732                 }
2733
2734                 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2735                             QM_MCR_VERB_ALTER_OOS);
2736                 if (mcr->result != QM_MCR_RESULT_OK) {
2737                         dev_err(dev, "OOS after drain fail: FQ 0x%x (0x%x)\n",
2738                                 fqid, mcr->result);
2739                         ret = -EIO;
2740                         goto out;
2741                 }
2742                 break;
2743
2744         case QM_MCR_NP_STATE_RETIRED:
2745                 /* Send OOS Command */
2746                 mcc = qm_mc_start(&p->p);
2747                 qm_fqid_set(&mcc->fq, fqid);
2748                 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
2749                 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2750                         ret = -ETIMEDOUT;
2751                         goto out;
2752                 }
2753
2754                 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2755                             QM_MCR_VERB_ALTER_OOS);
2756                 if (mcr->result) {
2757                         dev_err(dev, "OOS fail: FQ 0x%x (0x%x)\n",
2758                                 fqid, mcr->result);
2759                         ret = -EIO;
2760                         goto out;
2761                 }
2762                 break;
2763
2764         case QM_MCR_NP_STATE_OOS:
2765                 /*  Done */
2766                 break;
2767
2768         default:
2769                 ret = -EIO;
2770         }
2771
2772 out:
2773         put_affine_portal();
2774         return ret;
2775 }
2776
2777 const struct qm_portal_config *qman_get_qm_portal_config(
2778                                                 struct qman_portal *portal)
2779 {
2780         return portal->config;
2781 }
2782 EXPORT_SYMBOL(qman_get_qm_portal_config);
2783
2784 struct gen_pool *qm_fqalloc; /* FQID allocator */
2785 struct gen_pool *qm_qpalloc; /* pool-channel allocator */
2786 struct gen_pool *qm_cgralloc; /* CGR ID allocator */
2787
2788 static int qman_alloc_range(struct gen_pool *p, u32 *result, u32 cnt)
2789 {
2790         unsigned long addr;
2791
2792         if (!p)
2793                 return -ENODEV;
2794
2795         addr = gen_pool_alloc(p, cnt);
2796         if (!addr)
2797                 return -ENOMEM;
2798
2799         *result = addr & ~DPAA_GENALLOC_OFF;
2800
2801         return 0;
2802 }
2803
2804 int qman_alloc_fqid_range(u32 *result, u32 count)
2805 {
2806         return qman_alloc_range(qm_fqalloc, result, count);
2807 }
2808 EXPORT_SYMBOL(qman_alloc_fqid_range);
2809
2810 int qman_alloc_pool_range(u32 *result, u32 count)
2811 {
2812         return qman_alloc_range(qm_qpalloc, result, count);
2813 }
2814 EXPORT_SYMBOL(qman_alloc_pool_range);
2815
2816 int qman_alloc_cgrid_range(u32 *result, u32 count)
2817 {
2818         return qman_alloc_range(qm_cgralloc, result, count);
2819 }
2820 EXPORT_SYMBOL(qman_alloc_cgrid_range);
2821
2822 int qman_release_fqid(u32 fqid)
2823 {
2824         int ret = qman_shutdown_fq(fqid);
2825
2826         if (ret) {
2827                 pr_debug("FQID %d leaked\n", fqid);
2828                 return ret;
2829         }
2830
2831         gen_pool_free(qm_fqalloc, fqid | DPAA_GENALLOC_OFF, 1);
2832         return 0;
2833 }
2834 EXPORT_SYMBOL(qman_release_fqid);
2835
2836 static int qpool_cleanup(u32 qp)
2837 {
2838         /*
2839          * We query all FQDs starting from
2840          * FQID 1 until we get an "invalid FQID" error, looking for non-OOS FQDs
2841          * whose destination channel is the pool-channel being released.
2842          * When a non-OOS FQD is found we attempt to clean it up
2843          */
2844         struct qman_fq fq = {
2845                 .fqid = QM_FQID_RANGE_START
2846         };
2847         int err;
2848
2849         do {
2850                 struct qm_mcr_queryfq_np np;
2851
2852                 err = qman_query_fq_np(&fq, &np);
2853                 if (err == -ERANGE)
2854                         /* FQID range exceeded, found no problems */
2855                         return 0;
2856                 else if (WARN_ON(err))
2857                         return err;
2858
2859                 if ((np.state & QM_MCR_NP_STATE_MASK) != QM_MCR_NP_STATE_OOS) {
2860                         struct qm_fqd fqd;
2861
2862                         err = qman_query_fq(&fq, &fqd);
2863                         if (WARN_ON(err))
2864                                 return err;
2865                         if (qm_fqd_get_chan(&fqd) == qp) {
2866                                 /* The channel is the FQ's target, clean it */
2867                                 err = qman_shutdown_fq(fq.fqid);
2868                                 if (err)
2869                                         /*
2870                                          * Couldn't shut down the FQ
2871                                          * so the pool must be leaked
2872                                          */
2873                                         return err;
2874                         }
2875                 }
2876                 /* Move to the next FQID */
2877                 fq.fqid++;
2878         } while (1);
2879 }
2880
2881 int qman_release_pool(u32 qp)
2882 {
2883         int ret;
2884
2885         ret = qpool_cleanup(qp);
2886         if (ret) {
2887                 pr_debug("CHID %d leaked\n", qp);
2888                 return ret;
2889         }
2890
2891         gen_pool_free(qm_qpalloc, qp | DPAA_GENALLOC_OFF, 1);
2892         return 0;
2893 }
2894 EXPORT_SYMBOL(qman_release_pool);
2895
2896 static int cgr_cleanup(u32 cgrid)
2897 {
2898         /*
2899          * query all FQDs starting from FQID 1 until we get an "invalid FQID"
2900          * error, looking for non-OOS FQDs whose CGR is the CGR being released
2901          */
2902         struct qman_fq fq = {
2903                 .fqid = QM_FQID_RANGE_START
2904         };
2905         int err;
2906
2907         do {
2908                 struct qm_mcr_queryfq_np np;
2909
2910                 err = qman_query_fq_np(&fq, &np);
2911                 if (err == -ERANGE)
2912                         /* FQID range exceeded, found no problems */
2913                         return 0;
2914                 else if (WARN_ON(err))
2915                         return err;
2916
2917                 if ((np.state & QM_MCR_NP_STATE_MASK) != QM_MCR_NP_STATE_OOS) {
2918                         struct qm_fqd fqd;
2919
2920                         err = qman_query_fq(&fq, &fqd);
2921                         if (WARN_ON(err))
2922                                 return err;
2923                         if (be16_to_cpu(fqd.fq_ctrl) & QM_FQCTRL_CGE &&
2924                             fqd.cgid == cgrid) {
2925                                 pr_err("CRGID 0x%x is being used by FQID 0x%x, CGR will be leaked\n",
2926                                        cgrid, fq.fqid);
2927                                 return -EIO;
2928                         }
2929                 }
2930                 /* Move to the next FQID */
2931                 fq.fqid++;
2932         } while (1);
2933 }
2934
2935 int qman_release_cgrid(u32 cgrid)
2936 {
2937         int ret;
2938
2939         ret = cgr_cleanup(cgrid);
2940         if (ret) {
2941                 pr_debug("CGRID %d leaked\n", cgrid);
2942                 return ret;
2943         }
2944
2945         gen_pool_free(qm_cgralloc, cgrid | DPAA_GENALLOC_OFF, 1);
2946         return 0;
2947 }
2948 EXPORT_SYMBOL(qman_release_cgrid);