drivers/soc/aspeed/aspeed-lpc-ctrl.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2017 IBM Corporation
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/log2.h>
   8 #include <linux/mfd/syscon.h>
   9 #include <linux/miscdevice.h>
  10 #include <linux/mm.h>
  11 #include <linux/module.h>
  12 #include <linux/of_address.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/poll.h>
  15 #include <linux/regmap.h>
  16
  17 #include <linux/aspeed-lpc-ctrl.h>
  18
  19 #define DEVICE_NAME     "aspeed-lpc-ctrl"
  20
  21 #define HICR5 0x80
  22 #define HICR5_ENL2H     BIT(8)
  23 #define HICR5_ENFWH     BIT(10)
  24
  25 #define HICR6 0x84
  26 #define SW_FWH2AHB      BIT(17)
  27
  28 #define HICR7 0x88
  29 #define HICR8 0x8c
  30
  31 struct aspeed_lpc_ctrl {
  32         struct miscdevice       miscdev;
  33         struct regmap           *regmap;
  34         struct clk              *clk;
  35         phys_addr_t             mem_base;
  36         resource_size_t         mem_size;
  37         u32                     pnor_size;
  38         u32                     pnor_base;
  39         bool                    fwh2ahb;
  40 };
  41
  42 static struct aspeed_lpc_ctrl *file_aspeed_lpc_ctrl(struct file *file)
  43 {
  44         return container_of(file->private_data, struct aspeed_lpc_ctrl,
  45                         miscdev);
  46 }
  47
  48 static int aspeed_lpc_ctrl_mmap(struct file *file, struct vm_area_struct *vma)
  49 {
  50         struct aspeed_lpc_ctrl *lpc_ctrl = file_aspeed_lpc_ctrl(file);
  51         unsigned long vsize = vma->vm_end - vma->vm_start;
  52         pgprot_t prot = vma->vm_page_prot;
  53
  54         if (vma->vm_pgoff + vsize > lpc_ctrl->mem_base + lpc_ctrl->mem_size)
  55                 return -EINVAL;
  56
  57         /* ast2400/2500 AHB accesses are not cache coherent */
  58         prot = pgprot_noncached(prot);
  59
  60         if (remap_pfn_range(vma, vma->vm_start,
  61                 (lpc_ctrl->mem_base >> PAGE_SHIFT) + vma->vm_pgoff,
  62                 vsize, prot))
  63                 return -EAGAIN;
  64
  65         return 0;
  66 }
  67
  68 static long aspeed_lpc_ctrl_ioctl(struct file *file, unsigned int cmd,
  69                 unsigned long param)
  70 {
  71         struct aspeed_lpc_ctrl *lpc_ctrl = file_aspeed_lpc_ctrl(file);
  72         struct device *dev = file->private_data;
  73         void __user *p = (void __user *)param;
  74         struct aspeed_lpc_ctrl_mapping map;
  75         u32 addr;
  76         u32 size;
  77         long rc;
  78
  79         if (copy_from_user(&map, p, sizeof(map)))
  80                 return -EFAULT;
  81
  82         if (map.flags != 0)
  83                 return -EINVAL;
  84
  85         switch (cmd) {
  86         case ASPEED_LPC_CTRL_IOCTL_GET_SIZE:
  87                 /* The flash windows don't report their size */
  88                 if (map.window_type != ASPEED_LPC_CTRL_WINDOW_MEMORY)
  89                         return -EINVAL;
  90
  91                 /* Support more than one window id in the future */
  92                 if (map.window_id != 0)
  93                         return -EINVAL;
  94
  95                 /* If memory-region is not described in device tree */
  96                 if (!lpc_ctrl->mem_size) {
  97                         dev_dbg(dev, "Didn't find reserved memory\n");
  98                         return -ENXIO;
  99                 }
 100
 101                 map.size = lpc_ctrl->mem_size;
 102
 103                 return copy_to_user(p, &map, sizeof(map)) ? -EFAULT : 0;
 104         case ASPEED_LPC_CTRL_IOCTL_MAP:
 105
 106                 /*
 107                  * The top half of HICR7 is the MSB of the BMC address of the
 108                  * mapping.
 109                  * The bottom half of HICR7 is the MSB of the HOST LPC
 110                  * firmware space address of the mapping.
 111                  *
 112                  * The 1 bits in the top of half of HICR8 represent the bits
 113                  * (in the requested address) that should be ignored and
 114                  * replaced with those from the top half of HICR7.
 115                  * The 1 bits in the bottom half of HICR8 represent the bits
 116                  * (in the requested address) that should be kept and pass
 117                  * into the BMC address space.
 118                  */
 119
 120                 /*
 121                  * It doesn't make sense to talk about a size or offset with
 122                  * low 16 bits set. Both HICR7 and HICR8 talk about the top 16
 123                  * bits of addresses and sizes.
 124                  */
 125
 126                 if ((map.size & 0x0000ffff) || (map.offset & 0x0000ffff))
 127                         return -EINVAL;
 128
 129                 /*
 130                  * Because of the way the masks work in HICR8 offset has to
 131                  * be a multiple of size.
 132                  */
 133                 if (map.offset & (map.size - 1))
 134                         return -EINVAL;
 135
 136                 if (map.window_type == ASPEED_LPC_CTRL_WINDOW_FLASH) {
 137                         if (!lpc_ctrl->pnor_size) {
 138                                 dev_dbg(dev, "Didn't find host pnor flash\n");
 139                                 return -ENXIO;
 140                         }
 141                         addr = lpc_ctrl->pnor_base;
 142                         size = lpc_ctrl->pnor_size;
 143                 } else if (map.window_type == ASPEED_LPC_CTRL_WINDOW_MEMORY) {
 144                         /* If memory-region is not described in device tree */
 145                         if (!lpc_ctrl->mem_size) {
 146                                 dev_dbg(dev, "Didn't find reserved memory\n");
 147                                 return -ENXIO;
 148                         }
 149                         addr = lpc_ctrl->mem_base;
 150                         size = lpc_ctrl->mem_size;
 151                 } else {
 152                         return -EINVAL;
 153                 }
 154
 155                 /* Check overflow first! */
 156                 if (map.offset + map.size < map.offset ||
 157                         map.offset + map.size > size)
 158                         return -EINVAL;
 159
 160                 if (map.size == 0 || map.size > size)
 161                         return -EINVAL;
 162
 163                 addr += map.offset;
 164
 165                 /*
 166                  * addr (host lpc address) is safe regardless of values. This
 167                  * simply changes the address the host has to request on its
 168                  * side of the LPC bus. This cannot impact the hosts own
 169                  * memory space by surprise as LPC specific accessors are
 170                  * required. The only strange thing that could be done is
 171                  * setting the lower 16 bits but the shift takes care of that.
 172                  */
 173
 174                 rc = regmap_write(lpc_ctrl->regmap, HICR7,
 175                                 (addr | (map.addr >> 16)));
 176                 if (rc)
 177                         return rc;
 178
 179                 rc = regmap_write(lpc_ctrl->regmap, HICR8,
 180                                 (~(map.size - 1)) | ((map.size >> 16) - 1));
 181                 if (rc)
 182                         return rc;
 183
 184                 /*
 185                  * Switch to FWH2AHB mode, AST2600 only.
 186                  *
 187                  * The other bits in this register are interrupt status bits
 188                  * that are cleared by writing 1. As we don't want to clear
 189                  * them, set only the bit of interest.
 190                  */
 191                 if (lpc_ctrl->fwh2ahb)
 192                         regmap_write(lpc_ctrl->regmap, HICR6, SW_FWH2AHB);
 193
 194                 /*
 195                  * Enable LPC FHW cycles. This is required for the host to
 196                  * access the regions specified.
 197                  */
 198                 return regmap_update_bits(lpc_ctrl->regmap, HICR5,
 199                                 HICR5_ENFWH | HICR5_ENL2H,
 200                                 HICR5_ENFWH | HICR5_ENL2H);
 201         }
 202
 203         return -EINVAL;
 204 }
 205
 206 static const struct file_operations aspeed_lpc_ctrl_fops = {
 207         .owner          = THIS_MODULE,
 208         .mmap           = aspeed_lpc_ctrl_mmap,
 209         .unlocked_ioctl = aspeed_lpc_ctrl_ioctl,
 210 };
 211
 212 static int aspeed_lpc_ctrl_probe(struct platform_device *pdev)
 213 {
 214         struct aspeed_lpc_ctrl *lpc_ctrl;
 215         struct device_node *node;
 216         struct resource resm;
 217         struct device *dev;
 218         struct device_node *np;
 219         int rc;
 220
 221         dev = &pdev->dev;
 222
 223         lpc_ctrl = devm_kzalloc(dev, sizeof(*lpc_ctrl), GFP_KERNEL);
 224         if (!lpc_ctrl)
 225                 return -ENOMEM;
 226
 227         /* If flash is described in device tree then store */
 228         node = of_parse_phandle(dev->of_node, "flash", 0);
 229         if (!node) {
 230                 dev_dbg(dev, "Didn't find host pnor flash node\n");
 231         } else {
 232                 rc = of_address_to_resource(node, 1, &resm);
 233                 of_node_put(node);
 234                 if (rc) {
 235                         dev_err(dev, "Couldn't address to resource for flash\n");
 236                         return rc;
 237                 }
 238
 239                 lpc_ctrl->pnor_size = resource_size(&resm);
 240                 lpc_ctrl->pnor_base = resm.start;
 241         }
 242
 243
 244         dev_set_drvdata(&pdev->dev, lpc_ctrl);
 245
 246         /* If memory-region is described in device tree then store */
 247         node = of_parse_phandle(dev->of_node, "memory-region", 0);
 248         if (!node) {
 249                 dev_dbg(dev, "Didn't find reserved memory\n");
 250         } else {
 251                 rc = of_address_to_resource(node, 0, &resm);
 252                 of_node_put(node);
 253                 if (rc) {
 254                         dev_err(dev, "Couldn't address to resource for reserved memory\n");
 255                         return -ENXIO;
 256                 }
 257
 258                 lpc_ctrl->mem_size = resource_size(&resm);
 259                 lpc_ctrl->mem_base = resm.start;
 260
 261                 if (!is_power_of_2(lpc_ctrl->mem_size)) {
 262                         dev_err(dev, "Reserved memory size must be a power of 2, got %u\n",
 263                                (unsigned int)lpc_ctrl->mem_size);
 264                         return -EINVAL;
 265                 }
 266
 267                 if (!IS_ALIGNED(lpc_ctrl->mem_base, lpc_ctrl->mem_size)) {
 268                         dev_err(dev, "Reserved memory must be naturally aligned for size %u\n",
 269                                (unsigned int)lpc_ctrl->mem_size);
 270                         return -EINVAL;
 271                 }
 272         }
 273
 274         np = pdev->dev.parent->of_node;
 275         if (!of_device_is_compatible(np, "aspeed,ast2400-lpc-v2") &&
 276             !of_device_is_compatible(np, "aspeed,ast2500-lpc-v2") &&
 277             !of_device_is_compatible(np, "aspeed,ast2600-lpc-v2")) {
 278                 dev_err(dev, "unsupported LPC device binding\n");
 279                 return -ENODEV;
 280         }
 281
 282         lpc_ctrl->regmap = syscon_node_to_regmap(np);
 283         if (IS_ERR(lpc_ctrl->regmap)) {
 284                 dev_err(dev, "Couldn't get regmap\n");
 285                 return -ENODEV;
 286         }
 287
 288         lpc_ctrl->clk = devm_clk_get(dev, NULL);
 289         if (IS_ERR(lpc_ctrl->clk)) {
 290                 dev_err(dev, "couldn't get clock\n");
 291                 return PTR_ERR(lpc_ctrl->clk);
 292         }
 293         rc = clk_prepare_enable(lpc_ctrl->clk);
 294         if (rc) {
 295                 dev_err(dev, "couldn't enable clock\n");
 296                 return rc;
 297         }
 298
 299         if (of_device_is_compatible(dev->of_node, "aspeed,ast2600-lpc-ctrl"))
 300                 lpc_ctrl->fwh2ahb = true;
 301
 302         lpc_ctrl->miscdev.minor = MISC_DYNAMIC_MINOR;
 303         lpc_ctrl->miscdev.name = DEVICE_NAME;
 304         lpc_ctrl->miscdev.fops = &aspeed_lpc_ctrl_fops;
 305         lpc_ctrl->miscdev.parent = dev;
 306         rc = misc_register(&lpc_ctrl->miscdev);
 307         if (rc) {
 308                 dev_err(dev, "Unable to register device\n");
 309                 goto err;
 310         }
 311
 312         return 0;
 313
 314 err:
 315         clk_disable_unprepare(lpc_ctrl->clk);
 316         return rc;
 317 }
 318
 319 static int aspeed_lpc_ctrl_remove(struct platform_device *pdev)
 320 {
 321         struct aspeed_lpc_ctrl *lpc_ctrl = dev_get_drvdata(&pdev->dev);
 322
 323         misc_deregister(&lpc_ctrl->miscdev);
 324         clk_disable_unprepare(lpc_ctrl->clk);
 325
 326         return 0;
 327 }
 328
 329 static const struct of_device_id aspeed_lpc_ctrl_match[] = {
 330         { .compatible = "aspeed,ast2400-lpc-ctrl" },
 331         { .compatible = "aspeed,ast2500-lpc-ctrl" },
 332         { .compatible = "aspeed,ast2600-lpc-ctrl" },
 333         { },
 334 };
 335
 336 static struct platform_driver aspeed_lpc_ctrl_driver = {
 337         .driver = {
 338                 .name           = DEVICE_NAME,
 339                 .of_match_table = aspeed_lpc_ctrl_match,
 340         },
 341         .probe = aspeed_lpc_ctrl_probe,
 342         .remove = aspeed_lpc_ctrl_remove,
 343 };
 344
 345 module_platform_driver(aspeed_lpc_ctrl_driver);
 346
 347 MODULE_DEVICE_TABLE(of, aspeed_lpc_ctrl_match);
 348 MODULE_LICENSE("GPL");
 349 MODULE_AUTHOR("Cyril Bur <cyrilbur@gmail.com>");
 350 MODULE_DESCRIPTION("Control for ASPEED LPC HOST to BMC mappings");